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| 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 1 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator g eneral d escription the ICS9DB306 is a high performance 1-to-6 differential-to lvpecl jitter attenuator designed for use in pci express? systems. in some pci express? systems, such as those found in desktop pcs, the pci express? clocks are generated from a low bandwidth, high phase noise pll frequency synthesizer. in these systems, a zero delay buffer may be required to attenuate high frequency random and deterministic jitter components from the pll synthesizer and from the system board. the ICS9DB306 has 2 pll bandwidth modes. in low bandwidth mode, the pll loop bw is about 500khz and this setting will attenuate much of the jitter from the reference clock input while being high enough to pass a triangular input spread spectrum profile. there is also a high bandwidth mode which sets the pll bandwidth at 1mhz which will pass more spread spectrum modulation. for serdes which have x30 reference multipliers instead of x25 multipliers, 5 of the 6 pci express? outputs (pciex1:5) can be set for 125mhz instead of 100mhz by configuring the appropri- ate frequency select pins (fs0:1). output pciex0 will always run at the reference clock frequency (usually 100mhz) in desk- top pc pci express? applications. features ? six differential lvpecl output pairs ? 1 differential clock input ? clk and nclk supports the following input types: lvpecl, lvds, lvhstl, sstl, hcsl ? maximum output frequency: 140mhz ? output skew: 135ps (maximum) ? cycle-to-cycle jitter: 25ps (maximum) ? rms phase jitter @ 100mhz, (1.5mhz - 22mhz): 3ps (typical) ? 3.3v operating supply ? 0c to 70c ambient operating temperature ? lead-free package fully rohs compliant ? industrial temperature information available upon request hiperclocks? ics p in a ssignment noe0 clk nclk bypass noe1 pciext0 npciexc0 pciext1 npciexc1 pciext2 npciexc2 pciext3 npciexc3 pciext4 npciexc4 pciext5 npciexc5 b lock d iagram ICS9DB306 28-lead tssop, 173-mil 4.4mm x 9.7mm x 0.92mm body package l package top view v ee pciext1 pciexc1 pciext2 pciexc2 v cc noe0 noe1 v cc pciexc3 pciext3 pciexc4 pciext4 v ee v cc pciexc0 pciext0 fs0 nclk clk pll_bw v cca v ee bypass fs1 pciext5 pciexc5 v cc ICS9DB306 28-lead, 209-mil ssop 5.3mm x 10.2mm x 1.75mm body package f package top view phase detector vco loop filter 1 disabled 0 enabled 1 disabled 0 enabled 5 0 4 1 5 0 5 1 4 fs0 fs1 internal feedback 5 0 1 0 1 0 1 buffer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 4 .com u datasheet
9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 2 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator t able 2. p in c haracteristics t able 3a. r atio of o utput f requency to i nput f requency f unction t able , fs0 l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k s t u p n is t u p t u o 0 s f0 x e i c p1 x e i c p2 x e i c p 01 4 / 54 / 5 1111 t able 3c. o utput e nable f unction t able , noe0 t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 0 2 , 4 1 , 1v e e r e w o p. s n i p y l p p u s e v i t a g e n 3 , 2 , 1 t x e i c p 1 c x e i c p t u p t u o. s l e v e l e c a f r e t n i l c e p v l . s r i a p t u p t u o l a i t n e r e f f i d 5 , 4 , 2 t x e i c p 2 c x e i c p t u p t u o. s l e v e l e c a f r e t n i l c e p v l . s r i a p t u p t u o l a i t n e r e f f i d 8 2 , 5 1 , 9 , 6v c c r e w o p. s n i p y l p p u s e r o c 8 , 71 e o n , 0 e o nt u p n in w o d l l u p o g o t ) x t x e i c p ( s t u p t u o e u r t s e c r o f , h g i h n e h w . e l b a n e t u p t u o , w o l n e h w . h g i h o g o t ) x c x e i c p ( s t u p t u o d e t r e v n i e h t d n a w o l . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e e r a s t u p t u o 1 1 , 0 1 , 3 c x e i c p 3 t x e i c p t u p t u o. s l e v e l e c a f r e t n i l c e p v l . s r i a p t u p t u o l a i t n e r e f f i d 3 1 , 2 1 , 4 c x e i c p 4 t x e i c p t u p t u o. s l e v e l e c a f r e t n i l c e p v l . s r i a p t u p t u o l a i t n e r e f f i d 7 1 , 6 1 , 5 c x e i c p 5 t x e i c p t u p t u o. s l e v e l e c a f r e t n i l c e p v l . s r i a p t u p t u o l a i t n e r e f f i d 8 11 s fn w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s y c n e u q e r f 9 1s s a p y bt u p n in w o d l l u p e h t d n a , e d o m s s a p y b n i s i l l p e h t , h g i h n e h w . n i p t c e l e s s s a p y b . s l e v e l e c a f r e t n i l t t v l / s o m c v l . r e f f u b 6 : 1 a s a n o i t c n u f n a c e c i v e d 1 2v a c c r e w o p4 2 s e r i u q e r . n i p y l p p u s g o l a n a . r o t s i s e r s e i r e s 2 2w b _ l l pt u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i h t d i w d n a b l l p s t c e l e s 3 2k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 4 2k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i c c . g n i t a o l f t f e l n e h w t l u a f e d 2 / 5 20 s ft u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s y c n e u q e r f 7 2 , 6 2 , 0 t x e i c p 0 c x e i c p t u p t u o. s l e v e l e c a f r e t n i l c e p v l . s r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 3b. r atio of o utput f requency to i nput f requency f unction t able , fs1 s t u p n is t u p t u o 1 s f3 x e i c p4 x e i c p5 x e i c p 0111 14 / 54 / 54 / 5 s t u p n is t u p t u o 0 e o n2 : 0 x e i c p 0d e l b a n e 1d e l b a s i d t able 3d. o utput e nable f unction t able , noe1 s t u p n is t u p t u o 1 e o n5 : 3 x e i c p 0d e l b a n e 1d e l b a s i d t able 3e. pll b andwidth f unction t able s t u p n i h t d i w d n a b w b _ l l p 0z h k 0 0 5 1z h m 1 t able 3f. pll m ode f unction t able s t u p n i e d o m l l p s s a p y b 1d e l b a s i d 0d e l b a n e 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 3 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator t able 4c. d ifferential dc c haracteristics , v cc = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n ik l c n , k l cv c c v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n ik l c n , k l cv c c v , v 5 6 4 . 3 = n i v 0 =0 5 1a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o cv e e 5 . 0 +v c c 5 8 . 0 -v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i k l c n , k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n c c . v 3 . 0 + t able 4a. p ower s upply dc c haracteristics , v cc = 3.3v5%, t a = 0c to 70c t able 4b. lvcmos / lvttl dc c haracteristics , v cc = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v i c c t n e r r u c y l p p u s r e w o p 5 3 1a m i a c c t n e r r u c y l p p u s g o l a n a 5 2a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v c c 3 . 0 +v m v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v m i h i t n e r r u c h g i h t u p n i , 1 s f , 1 e o n , 0 e o n s s a p y b v c c v = n i v 5 6 4 . 3 =0 5 1a w b _ l l p , 0 s f 5a i l i t n e r r u c w o l t u p n i , 1 s f , 1 e o n , 0 e o n s s a p y b v c c v , v 5 6 4 . 3 = n i v 0 =5 -a w b _ l l p , 0 s f0 5 1 -a a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 49.8c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 4 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator t able 5. ac c haracteristics , v cc = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 4 1z h m t ) o ( k s2 , 1 e t o n ; w e k s t u p t u o 5 55 3 1s p t ) c c ( t i j2 e t o n , r e t t i j e l c y c - o t - e l c y c 5 2s p t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 3 e t o n : e g n a r n o i t a r g e t n i z h m 2 2 - z h m 5 . 1 3s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 7s p c d oe l c y c y t u d t u p t u o 8 42 5% . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 1 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 2 e t o n . n o i t c e s s i h t g n i w o l l o f t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 3 e t o n t able 4d. lvpecl dc c haracteristics , v cc = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t c c . v 2 - 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 5 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator t ypical p hase n oise at 100mh z 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1m 10m 100m 100mhz rms phase jitter (random) 1.5mhz to 22mhz = 3ps (typical) o ffset f requency (h z ) n oise p ower dbc hz ? ? ? phase noise result by adding pci express? filter to raw data pci express? filter the illustrated phase noise plot was taken using a low phase noise signal generator, the noise floor of the signal generator is less than that of the device under test. using this configuration allows one to see the true spectral pu- rity or phase noise performance of the pll in the device under test. due to the tracking ability of a pll, it will track the input signal up to its loop bandwidth. therefore, if the input phase noise is greater than that of the vco, it will increase the output phase noise performance of the device. it is recommended that the phase noise performance of the input is verified in order to achieve the above phase noise performance. raw phase noise data 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 6 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator p arameter m easurement i nformation scope qx nqx lvpecl o utput s kew d ifferential i nput l evel 3.3v o utput l oad ac t est c ircuit -1.3v 0.165v c ycle - to -c ycle j itter o utput d uty c ycle /p ulse w idth p eriod 2v v cmr cross points v pp v ee clk nclk v cc t sk(o) pciexc0:5x clock outputs 20% 80% 80% 20% t r t f v sw i n g pciext0:5x pciexc0:5y pciext0:5y o utput r ise /f all t ime pulse width t period t pw t period odc = pciext0:5 pciexc0:5 v cc v ee ? ? ? ? pciext0:5 pciexc0:5 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t cycle n t cycle n+1 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 7 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator a pplication i nformation figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 2. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ICS9DB306 provides separate power supplies to isolate any high switching noise from the out- puts to the internal pll. v cc and v cca should be individually con- nected to the power supply plane through vias, and bypass ca- pacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illus- trates how a 24 resistor along with a 10 f and a .01 f by- pass capacitor should be connected to each v cca pin. f igure 1. p ower s upply f iltering 24 v cca 10 f .01 f 3.3v .01 f v cc v_ref r1 1k c1 0.1u r2 1k single ended clock input clkx nclkx vcc 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 8 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 9 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator f igure 4c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 4b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 4d. h i p er c lock s clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4d show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 4a. h i p er c lock s clk/nclk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 4a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 10 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator s chematic e xample figure 5 shows an example of ICS9DB306 application schematic. in this example, the device is operated at v cc = 3.3v. the decoupling capacitor should be located as close as pos- sible to the power pin. the input is driven by a hcsl driver. for f igure 5. e xample of ICS9DB306 s chematic lvpecl output drivers, one of terminations approaches is shown in this schematic. for additional termination approaches, please refer to the lvpecl termination application note. c3 0.1uf c1 0.1uf (u1-6) vcc r14 50 r15 50 zo = 50 lvpecl + - vcc=3.3v (u1-15) r13 33 r8 1k vcc r9 1k u1 ICS9DB306 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 28 27 26 25 vee pciext1 pciexc1 pciext2 pciexc2 vcc noe0 noe1 vcc pciexc3 pciext3 pciexc4 pciext4 vee vcc pciexc5 pciext5 fs1 by pass vee vcca pll_bw clk nclk vcc pciexc0 pciext0 fs0 hcsl c3 0.1uf vcca c11 0.1uf zo = 50 r16 50 (u1-9) c2 0.1uf r1 50 r11 1k zo = 50 c16 10uf vcc zo = 50 vcc r12 33 zo = 50 r7 24 r10 1k r6 50 r2 50 lvpecl + - vcc vcc r5 50 r4 50 zo = 50 (u1-28) 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 11 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS9DB306. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS9DB306 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 135ma = 467.8mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 6 * 30mw = 180mw total power _max (3.465v, with all outputs switching) = 467.8mw + 180mw = 647.8mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.9c/w per table 6 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.648w * 43.9c/w = 98.4c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 82. 9c/w 68.7c/w 60.5c/w multi-layer pcb, jedec standard test boards 49. 8c/w 43.9c/w 41.2c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6. t hermal r esistance ja for 28- pin tssop, f orced c onvection 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 12 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 5. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 5. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 13 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator r eliability i nformation t ransistor c ount the transistor count for ICS9DB306 is: 2190 t able 7a. ja vs . a ir f low t able f or 28 l ead tssop p ackage ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 82.9c/w 68.7c/w 60.5c/w multi-layer pcb, jedec standard test boards 49.8c/w 43.9c/w 41.2c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 7b. ja vs . a ir f low t able f or 28 l ead ssop p ackage ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 49c/w 36c/w 30c/w 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 14 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator p ackage o utline - f s uffix for 28 l ead ssop t able 8b. p ackage d imensions reference document: jedec publication 95, mo-150 p ackage o utline - l s uffix for 28 l ead tssop t able 8a. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 2 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 6 . 90 8 . 9 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 2 a0 0 . 2 1 a5 0 . 0 2 a5 6 . 15 8 . 1 b2 2 . 08 3 . 0 c9 0 . 05 2 . 0 d0 9 . 90 5 . 0 1 e0 4 . 70 2 . 8 1 e0 0 . 50 6 . 5 ec i s a b 5 6 . 0 l5 5 . 05 9 . 0 0 8 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 15 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t l b 6 0 3 b d 9 s c il b 6 0 3 b d 9 s c ip o s s t d a e l 8 2e b u t r e p 8 4c 0 7 o t c 0 t l b 6 0 3 b d 9 s c il b 6 0 3 b d 9 s c il e e r d n a e p a t n o p o s s t d a e l 8 20 0 0 1c 0 7 o t c 0 f l l b 6 0 3 b d 9 s c if l l b 6 0 3 b d 9 s c ip o s s t " e e r f - d a e l " d a e l 8 2e b u t r e p 8 4c 0 7 o t c 0 t f l l b 6 0 3 b d 9 s c if l l b 6 0 3 b d 9 s c i n o p o s s t " e e r f - d a e l " d a e l 8 2 l e e r d n a e p a t 0 0 0 1c 0 7 o t c 0 f b 6 0 3 b d 9 s c if b 6 0 3 b d 9 s c ip o s s d a e l 8 2e b u t r e p 6 4c 0 7 o t c 0 t f b 6 0 3 b d 9 s c if b 6 0 3 b d 9 s c il e e r d n a e p a t n o p o s s d a e l 8 20 0 0 1c 0 7 o t c 0 s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n . t n a i l p m o c the aforementioned trademark, hiperclocks? is a trademark of integrated circuit systems, inc. or its subsidiaries in the unite d states and/or other countries. 4 .com u datasheet 9db306bl www.icst.com/products/hiperclocks.html rev. a april 7, 2005 16 integrated circuit systems, inc. ICS9DB306 pci e xpress , j itter a ttenuator t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d af 32 . e l b a t n o i t c n u f e d o m l l p d e d d a 5 0 / 7 / 4 4 .com u datasheet |
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