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LH540235/45 2048 18 / 4096 18 synchronous fifos features fast cycle times: 20/25/35 ns pin-compatible drop-in replacements for idt72235b/45b fifos choice of idt-compatible or enhanced operating mode; selected by an input control signal device comes up into one of two known default states at reset depending on the state of the emode control input: programming is allowed, but is not required internal memory array architecture based on cmos dual-port sram technology, 2048 18 or 4096 18 synchronous enable-plus-clock control at both input port and output port independently-synchronized operation of input port and output port control inputs sampled on rising clock edge most control signals assertive-low for noise immunity may be cascaded for increased depth, or paralleled for increased width 16 ma-iol high-drive three-state outputs five status flags: full, almost-full, half-full, almost-empty, and empty; almost flags are programmable in enhanced operating mode, almost-full, half-full, and almost-empty flags can be made completely synchronous in enhanced operating mode, duplicate enables for interlocked paralleled fifo operation, for 36-bit data width, when selected and appropriately connected in enhanced operating mode, disabling three-state outputs may be made to suppress reading data retransmit function ttl/cmos-compatible i/o space-saving 68-pin plcc package; even-smaller 64-pin tqfp package reset logic input port rs input port control logic read pointer write pointer dedicated and programmable status flags fifo memory array 2048 x 18/4096 x 18 output port control logic ff paf wxo/hf rxo /ef 2 pae d 0 - d 17 wen wck q 0 - q 17 rck output port ren oe programmable registers expansion logic wxi/ wen 2 fl/ rt wxo/hf rxi/ ren 2 rxo/ ef 2 ld 540235-1 wxi/ wen 2 rxi/ ren 2 bold italic = enhanced operating mode. emode ef figure 1. LH540235/45 block diagram bold italic = enhanced operating mode 1
functional description note: throughout this data sheet, a bold italic type font is used for all references to enhanced operating mode features which do not function in idt-compatible operating mode; and also for all references to the re- transmit facility (which is not an idt72235b/45b fifo feature), even though it may be used C subject to some restrictions C in either of these two operating modes. thus, readers interested only in using the LH540235/45 fifos in idt-compatible operating mode may skip over bold italic sections, if they wish. the LH540235/45 parts are fifo (first-in, first-out) memory devices, based on fully-static cmos dual-port sram technology, capable of containing up to 2048 or 4096 18-bit words respectively. they can replace two or more byte-wide fifos in many applications, for microprocessor- to-microprocessor or microprocessor-to-bus communica- tion. their architecture supports synchronous operation, tied to two independent free-running clocks at the input and output ports respectively. however, these clocks also may be aperiodic, asynchronous demand signals. almost all control-input signals and status-output signals are synchro- nized to these clocks, to simplify system design. the input and output ports operate altogether inde- pendently of each other, unless the fifo becomes either totally full or else totally empty. data flow is initiated at a port by the rising edge of its corresponding clock, and is gated by the appropriate edge-sampled enable signals. the following fifo status flags monitor the extent to which the internal memory has been filled: full, almost- full, half-full, almost-empty, and empty. the almost-full and almost-empty flag offsets are programmable over the entire fifo depth; but, during a reset operation, each of these is initialized to a default offset value of 12710 fifo-memory words, from the respective fifo boundary. if this default offset value is satisfactory, no further pro- gramming is required. after a reset operation during which the emode control input was not asserted (was high), these fifos operate in the idt-compatible operating mode. in this mode, each part is pin-compatible and functionally-compatible with the idt72235b/45b part of similar depth and speed grade; and the control register is not even accessible or visible to the external-system logic which is controlling the fifo, although it still performs the same control functions. however, assertion of the emode control input during a reset operation leaves control register bits 00-05 set, and causes the fifo to operate in the enhanced operating mode. in essence, asserting emode chooses a different default state for the con- trol register. the system optionally then may pro- gram the control register in any desired manner to activate or deactivate any or all of the enhanced-op- erating-mode features which it can control, including selectable-clock-edge flag synchronization, and read inhibition when the data outputs are disabled. whenever emode is being asserted, interlocked- operation paralleling also is available, by appropriate interconnection of the fifos expansion inputs. the retransmit facility is available during standalone operation, in either idt-compatible operating mode or enhanced operating mode (see tables 1 and 2). it is inoperative if the fl/ rt input signal is grounded. it is not an idt72235b/45b feature. the retransmit control signal causes the internal fifo read-address pointer to be set back to zero, without affecting the internal fifo write-address pointer. thus, the retransmit control signal also provides a mechanism whereby a block of data delimited by the zero physical address and the current write-address-pointer address may be read out repeatedly, an arbitrary number of times. the only restrictions are that neither the read-ad- dress pointer nor the write-address pointer may wrap around during this entire process, and that the retransmit facility is not available during depth-cas- caded operation, either in idt-compatible operating mode or in enhanced operating mode (see tables 1 and 2). also, the flags behave differently for a short time after a retransmit operation. otherwise, the re- transmit facility is available during standalone opera- tion, in either idt-compatible operating mode or enhanced operating mode. note that, when fl/rt is being used as rt, rt is an assertive-high signal, rather than assertive-low as it is in most other fifos having a retransmit facility. programming the programmable-flag offsets, the tim- ing synchronization of the various status flags, the optional read-suppression functionality of oe, and the behavior of the pointers which access the offset- value registers and the control register may be indi- vidually controlled by asserting the signal ld, without any reset operation. when ld is being asserted, and writing is being enabled by asserting wen, some portion of the input bus word d 0 C d 17 is used at the next rising edge of wclk to program one or more of the programmable registers on successive write clocks. likewise, the values programmed into these programmable registers may be read out for verification by asserting ld and ren, with the outputs q 0 C q 17 enabled. reading out these pro- grammable registers should not be initiated while they are being written into. table 3 defines the possible modes of operation for loading and reading out the contents of programmable registers. bold italic = enhanced operating mode LH540235/45 2048 x 18/4096 x 18 synchronous fifos 2
in the enhanced operating mode, coordinated op- eration of two 18-bit fifos as one 36-bit fifo may be ensured by interlocked crosscoupling of the status- flag outputs from each fifo to the expansion inputs of the other one; that is, ff to wxi/wen 2 , and ef to rxi/ren 2 , in both directions between two paralleled fifos. this interlocked operation takes effect automatically, if two paralleled fifos are crosscon- nected in this manner, with the emode control input being asserted (low) (see tables 1 and 2, also fig- ures 28 and 31). idt-compatible depth cascading no longer is available when operating in this inter- locked-paralleled mode; however, pipelined depth cascading remains available. top view 540235-2 3 2 1 6867666564636261 9876 54 q 17 q 16 q 15 ld oe v cc ef v cc d 15 d 16 d 17 rclk ren rs 16 17 18 19 20 23 24 21 22 26 15 11 12 13 14 10 25 d 2 d 0 d 13 d 14 d 11 d 12 d 9 d 10 d 8 v cc d 7 d 5 d 6 d 3 d 4 d 1 55 54 53 52 51 48 47 50 49 46 44 60 59 58 57 56 45 q 11 v cc q 10 q 9 q 8 q 7 emode q 6 q 5 q 4 v cc q 14 q 13 q 12 33 34 35 36 37 38 39 40 41 42 43 27 28 29 30 31 32 q 2 q 3 wxo/hf q 0 q 1 v cc v cc fl/ rt wclk rxo/ ef 2 ff rxi/ ren 2 paf wxi/ wen 2 wen pae v ss v ss v ss v ss v ss v ss v ss v ss bold italic = enhanced operating mode. figure 2. pin connections for plcc package bold italic = enhanced operating mode 2048 x 18/4096 x 18 synchronous fifos LH540235/45 3
top view 540235-34 58 57 56 55 54 53 52 51 50 49 64 63 62 61 60 59 q 17 q 16 ld oe v cc ef v cc d 16 d 17 ren rs 7 8 9 10 11 14 15 12 13 6 2 3 4 5 1 16 d 2 d 0 d 13 d 15 d 11 d 12 d 9 d 10 d 8 d 7 d 5 d 6 d 3 d 4 d 1 rclk note: bold italic = enhanced operating mode. d 14 43 42 41 40 39 36 35 38 37 44 48 47 46 45 34 q 14 q 11 q 12 q 10 q 9 q 7 q 8 q 5 q 6 q 4 q 13 33 q 15 23 24 25 26 27 28 29 30 31 32 17 18 19 20 21 22 q 0 q 1 paf ff pae fl/ rt wclk wxi/ wen 2 wxo/hf wen q 2 v cc q 3 64-pin tqfp v cc v ss v ss v ss v ss v ss emode v ss rxo/ ef 2 rxi/ ren 2 v ss figure 3. pin connections for thin quad flat package summary of signals/pins pin name d 0 C d 17 data inputs rs reset emode enhanced operating mode wclk write clock wen write enable rclk read clock ren read enable oe output enable ld load fl /rt first load/ retransmit rxi /ren 2 read expansion input/ read enable 2 pin name wxi /wen 2 write expansion input/ write enable 2 ff full flag paf programmable almost-full flag wxo/ hf write expansion output/half-full flag pae programmable almost-empty flag ef empty flag rxo/ ef 2 read expansion output /empty flag 2 q 0 C q 17 data outputs v cc power v ss ground bold italic = enhanced operating mode LH540235/45 2048 x 18/4096 x 18 synchronous fifos 4
pin list signal name plcc pin no. tqfp pin no. rs 157 oe 258 ld 359 ren 460 rclk 561 d 17 763 d 16 864 d 15 91 d 14 10 2 d 13 11 3 d 12 12 4 d 11 13 5 d 10 14 6 d 9 15 7 d 8 17 8 d 7 19 9 d 6 20 10 d 5 21 11 d 4 22 12 d 3 23 13 d 2 24 14 d 1 25 15 d 0 26 16 pae 27 17 ft/ rt 28 18 wclk 29 19 wen 30 20 wxi/ wen 2 31 21 paf 33 23 rxi/ ren 2 34 24 ff 35 25 wxo/ hf 36 26 rxo/ ef 2 37 27 q 0 38 28 signal name plcc pin no. tqfp pin no. q 1 39 29 q 2 41 31 q 3 42 32 q 4 44 34 q 5 46 36 q 6 47 37 emode 48 33 q 7 49 38 q 8 50 39 q 9 52 41 q 10 53 42 q 11 55 44 q 12 56 45 q 13 58 47 q 14 59 48 q 15 61 50 q 16 63 52 q 17 64 53 ef 66 54 v ss 662 v cc 16 nc v ss 18 nc v cc 32 22 v ss 40 30 v cc 43 nc v ss 45 35 v ss 51 40 v cc 54 43 v ss 57 46 v cc 60 49 v ss 62 51 v cc 65 nc v ss 67 55 v cc 68 56 bold italic = enhanced operating mode 2048 x 18/4096 x 18 synchronous fifos LH540235/45 5
pin descriptions pin name pin type 1 description d 0 C d 17 data inputs i data inputs from an 18-bit bus. rs reset i when rs is taken low, the fifos internal read and write pointers are set to address the first physical location of the ram array; ff, paf, and hf go high; and pae and ef go low. the programmable-flag-offset registers and the control register are set to their default values. (but see the description of emode , below.) a reset operation is required before an initial read or write operation after power-up. emode enhanced operating mode i when emode is tied low, the default setting for control register bits 00- 05 after a reset operation changes to high rather than low, thus enabling all control-register-controllable enhanced operating mode features, and allowing access to the control register for reprogramming or readback (see tables 1, 2, and 5). if this behavior is desired, emode may be grounded; however, control register bits 00-06 still may be individually programmed to selectively enable or disable certain of the enhanced mode features, even though those features associated with interlocked-paralleled operation always are enabled whenever emode is being asserted (see table 2). alternatively, emode may be tied to v cc, so that the fifo is functionally idt-compatible, and the control register is not accessible or visible, and all of its bits remain low. controlling emode dynamically during system operation is not recommended. wclk write clock i data is written into the fifo on a low-to-high transition of wclk, whenever wen (write enable) is being asserted (low), and ld is high. if ld is low, a programmable register rather than the internal fifo memory is written into. in the enhanced operating mode, whenever control register bit 06 is high, wen 2 is anded with wen to produce an effective internal write-enable signal. 2 wen write enable i when wen is low and ld is high, an 18-bit data word is written into the fifo on every low-to-high transition of wclk. when wen is high, the fifo internal memory continues to hold the previous data (see table 3). data will not be written into the fifo if ff is low. in the enhanced operating mode, whenever control register bit 06 is high, wen 2 is anded with wen to produce an effective internal write-enable signal. 2 rclk read clock i data is read from the fifo on a low-to-high transition of rclk whenever ren (read enable) is being asserted (low), and ld is high. if ld is low, a programmable register rather than the internal fifo memory is read from. in the enhanced operating mode, whenever control register bit 06 is high, ren 2 is anded with ren (and whenever control register bit 05 is high, also with oe) to produce an effective internal read-enable signal. 2 ren read enable i when ren is low and ld is high, an 18-bit data word is read from the fifo on every low-to-high transition of rclk. when ren is high, and/or also when ef is low, the fifos output register continues to hold the previous data word, whether or not q 0 C q 17 (the data outputs) are enabled (see table 3). in the enhanced operating mode, whenever control register bit 06 is high, ren 2 is anded with ren (and whenever control register bit 05 is high, also with oe) to produce an effective internal read-enable signal. 2 oe output enable i when oe is low, the fifos data outputs drive the bus to which they are connected. if oe is high, the fifos outputs are in high-z (high-impedance) state. in the enhanced operating mode, oe not only continues to control the outputs in this same manner, but also can function as an additional anding input to the combined effective read-enable signal, along with ren and ren 2 , whenever control register bit 05 is high (see table 5). 2 bold italic = enhanced operating mode LH540235/45 2048 x 18/4096 x 18 synchronous fifos 6
pin descriptions (contd) pin name pin type 1 description ld load i when ld is low, the data word on d 0 C d 17 (the data inputs) is written into a programmable-flag-offset register, or into the control register (when in the enhanced operating mode), on the low-to-high transition of wclk, whenever wen is low (see table 3). also, when ld is low, a word is read to q 0 C q 17 (the data outputs) from the offset registers and/or the control register (when in the enhanced operating mode) on the low-to-high transition of rclk, whenever ren is low (see again table 3, and particularly the notes following this table). when ld is high, normal fifo write and read operations are enabled. wen 2 write enable 2 i tie low in standard mode, cascading is not supported. in the enhanded operating mode, whenever control register bit06 is high, wxi/wen 2 functions as a second write-enable signal, wen 2 , which is anded with wen to produce an effective internal write-enable signal. ren 2 read enable 2 i tie low in standard mode. in the enhanced operating mode, whenever control register bit06 is high, rxi/ ren 2 functions as a second read-enable signal, ren 2 , which is anded with ren to produce an effective internal read- enable signal. ff full flag o when ff is low, the fifo is full; further advancement of its internal write-address pointer, and further data writes through its data inputs into its internal memory array, are inhibited. when ff is high, the fifo is not full. ff is synchronized to wclk. paf programmable almost-full flag o when paf is low, the fifo is almost full, based on the almost-full-offset value programmed into the fifos almost-full offset register. the default value of this offset at reset is 127 10 , measured from full (see table 4). in the idt-compatible operating mode, paf is asynchronous. in the enhanced operating mode, paf is synchronized to wclk after a reset operation, according to the state of control register bit 04 (see table 5). hf half-full flag o in the standalone or paralleled configuration, whenever hf is low the device is more than half full. in idt-compatible operating mode, hf is asynchronous; in the enhanced operating mode, hf may be synchronized either to wclk or to rclk after a reset operation, according to the state of control register bits 02 and 03 (see table 5). pae programmable almost-empty flag o when pae is low, the fifo is almost empty, based on the almost-empty-offset value programmed into the fifos almost-empty offset register. the default value of this offset at reset is 127 10 , measured from empty (see table 4). in idt- compatible operating mode, pae is asynchronous. in the enhanced operating mode, pae is synchronized to rclk after a reset operation, according to the state of control register bit 01. (see table 5.) ef empty flag o when ef is low, the fifo is empty; further advancement of its internal read- address pointer, and further readout of data words from its internal memory array to its data outputs, are inhibited. when ef is high, the fifo is not empty. ef is synchronized to rclk. ef 2 empty flag 2 o in the enhanced operating mode, control register bit 06 is high, ef 2 behaves as an exact duplicate of ef, but delayed by one full cycle of rclk with respect to ef. q 0 C q 17 data outputs o/z data outputs to drive an 18-bit bus. v cc power v +3.3 v power-supply pins. v ss ground v 0 v ground pins. notes: 1 i = input, o = output, z = high-impedance, v = power voltage level 2 the ostensible differences in signal assertiveness are reconciled before anding. bold italic = enhanced operating mode 2048 x 18/4096 x 18 synchronous fifos LH540235/45 7
absolute maximum ratings parameter rating supply voltage to v ss potential C0.5 v to 7 v signal pin voltage to v ss potential C0.5 v to v cc + 0.5 v dc output current 1 75 ma temperature range with power applied 2 C55 c to 125 c storage temperature range C65 c to 150 c power dissipation (plcc pack- age limit) 2 w notes: 1. only one output may be shorted at a time, for a period not exceeding 30 seconds. 2. measured with clocks idle. operating range symbol parameter min. max. unit t a temperature, ambient 070c v cc supply voltage 4.5 5.5 v v ss supply voltage 00v v il logic low input voltage C0.5 0.8 v v ih logic high input voltage 2.0 v cc + 0.5 v dc electrical characteristics (over operating range) symbol parameter test conditions min. max. unit i li input leakage v cc = 5.5 v, v in = 0 v to v cc C10 10 m a i lo i/o leakage oe 3 v ih , 0 v v out v cc C10 10 m a v oh output high voltage i oh = C8.0 ma 2.4 v v ol output low voltage i ol = 16.0 ma 0.4 v i cc average operating supply current 1,2 measured at f cc = 50 mhz 245 ma i cc2 average standby supply current 2 all inputs = v ihmin (clocks idle) 25 ma i cc3 power-down supply current 2 all inputs = v cc C 0.2 v (clocks idle) 1 ma i cc4 power-down supply current 2 all inputs = v cc C 0.2 v (clocks at 50 mhz) 1 ma notes: 1. output load is disconnected. 2. i cc , i cc2 , and i cc3 are dependent upon actual output loading, and i cc and i cc4 are also dependent on cycle rates. specified values are with outputs open; and, for i cc and i cc4 , operating at minimum cycle times. ac test conditions parameter rating input pulse levels v ss to 3 v input rise and fall times (10% to 90%) 3 ns input timing reference levels 1.5 v output timing reference levels 1.5 v output load, timing tests (figure 5) r 1 (top resistor) 1.1k w r 2 (bottom resistor) 680 w c l (load capacitance) 30 pf 540235-3 device under test +5 v 30 pf 1.1 k w 680 w includes jig and scope capacitances * * figure 4. output load circuit capacitance parameter rating c in (input capacitance) v in = 0 v 9 pf c out (output capacitance) v out = 0 v 9 pf bold italic = enhanced operating mode LH540235/45 2048 x 18/4096 x 18 synchronous fifos 8
ac electrical characteristics symbol parameter C20 C25 -35 min. max. min. max. min. max. f cc clock cycle frequency 50 40 28.6 t a data access time 2 12 3 15 3 20 t clk clock cycle time 20 25 35 t clkh clock high time 8 10 14 t clkl clock low time 81014 t ds data setup time 5 6 7 t dh data hold time 2 2 2 t ens enable setup time 567 t enh enable hold time 2 2 2 t rs reset pulse width 1 20 25 35 t rss reset setup time 2 12 15 20 t rsr reset recovery time 2 12 15 20 t rsf reset to flag and output time 30 35 40 t olz output enable to output in low-z 2 000 t oe output enable to output valid 91215 t ohz output enable to output in high-z 2 19112115 t wff write clock to full flag 12 15 20 t ref read clock to empty flag 12 15 20 t paf clock to programmable almost-full flag (idt-compatible operating mode) 14 17 23 t pae clock to programmable almost-empty flag (idt-compatible operating mode) 14 17 23 t hf clock to half-full flag (idt-compatible operating mode) 14 17 23 t pafs clock to programmable almost-full flag (enhanced operating mode) 14 17 23 t paes clock to programmable almost-empty flag (enhanced operating mode) 14 17 23 t hfs clock to half-full flag (enhanced operating mode) 14 17 23 t xo clock to expansion-out 12 15 20 t xi expansion-in pulse width 8913 t xis expansion-in setup time 8 9 14 t skew1 skew time between read clock and write clock for full flag 3 91116 t skew2 skew time between write clock and read clock for empty flag 4 91116 notes: 1. pulse widths less than the stated minimum values may cause incorrect operation. 2. values are guaranteed by design; not currently tested. 3. these times also apply to the programmable-almost-full and half-full flags when they are synchronized to wclk. 4. these times also apply to the half-full and programmable-almost-empty flags when they are synchronized to rclk. rev. b, 8/8/96 bold italic = enhanced operating mode 2048 x 18/4096 x 18 synchronous fifos LH540235/45 9
table 1. grouping-mode determination during a reset operation 5 emode wxi/ wen 2 rxi/ ren 2 fl/ rt mode wxo/ hf usage wxi/ wen 2 usage rxi/ ren 2 usage fl/ rt usage rxo / ef 2 usage h 1 hhh cascaded slave 2 wxo wxi rxi fl rxo h 1 hhl cascaded master 2 wxo wxi rxi fl rxo h hlx (reserved) CC CCC h lhx (reserved) CC CCC h ll h 3 (not allowed during reset) ( hf) (none) (none) (rt) (none) h ll l 3 standalone hf (none) (none) rt (none) lx x h 3 (not allowed during reset) ( hf) (wen 2 )(ren 2 )(rt) ( ef 2 ) lx x l 3 interlocked paralleled 4 hf wen 2 ren 2 rt ef 2 notes: 1. in idt-compatible cascading, a reset operation forces wxo/ hf and rxo/ ef 2 high for the nth fifo, thus forcing wxi/ wen 2 and rxi/ ren 2 high for the (n + 1)st fifo. 2. the terms master and slave refer to idt-compatible cascading. in pipelined cascading 4 , there is no such distinction. 3. once grouping mode has been determined during a reset operation, fl/rt then may go high to activate a retransmit operation. 4. emode must be asserted for access to the control register to be enabled. also, fifos being used in a pipelined-cascading configuration should be in interlocked paralleled mode. 5. setup-time and recovery-time specifications apply during a reset operation. table 2. expansion-pin usage according to grouping mode i/o pin idt-compatible operating mode enhanced operating mode depth-cascaded master depth-cascaded slave standalone interlocked paralleled i wxi / wen 2 from wxo ((n-1)st fifo) from wxo ((n-1)st fifo) grounded from ff (other fifo) o wxo/ hf to wxi ((n+1)st fifo) to wxi ((n+1)st fifo) becomes hf becomes hf i rxi/ ren 2 from rxo ((n-1)st fifo) from rxo ((n-1)st fifo) grounded from ef (other fifo) o rxo / ef 2 to rxi ((n+1)st fifo) to rxi ((n+1)st fifo) unused becomes ef 2 i fl/ rt grounded (logic low) logic high becomes rt 1 becomes rt 1 note: 1. fl/ rt may be grounded if the retransmit facility is not being used. description of signals and operating sequences bold italic = enhanced operating mode LH540235/45 2048 x 18/4096 x 18 synchronous fifos 10
table 3. selection of read and write operations ld wen 3,4 ren 3,4 wclk rclk action l x x C C no operation. ll l illegal combination, which will cause errors. ll h x write to a programmable register. 1 lh h x hold present value of programmable-register write counter, and do not write. 2 lh l x read from a programmable register. 1 lh h x hold present value of programmable-register read counter, and do not read. 2 hl x x normal fifo write operation. hx l x normal fifo read operation. hl x C x no write operation. hh x x x no write operation. h x l x C no read operation. hx h x x no read operation. hl l C C no operation. h h h x x no operation. key: h = logic high; l = logic low; x = dont-care (logic high, logic low, or any transition); = a low-to-high transition; C = any condition except a low-to-high transition. notes: 1. the selection of a programmable register to be written or read is controlled by two simple state machines. one state machine controls the se- lection for writing; the other state machine controls the selection for reading. these two state machines operate independently of each other. both state machines are reset to point to word 0 by a reset operation. in the enhanced operating mode, if control register bit 00 is set, both state machines are also reset to point to word 0 by deassertion of ld after ld has been asserted (that is, by a rising edge of ld), followed by a valid memory array write cycle for the writing-control state machine and/or by a valid memory array read cyc le for the reading-control state machine. 2. the order of the two programmable registers which are accessible in idt-compatible operating mode, as selected by either stat e machine, is always: word 0: almost-empty offset register word 1: almost-full offset register word 0: almost-empty offset register ... (repeats indefinitely) ... the order of the three programmable registers which are accessible in enhanced operating mode, as selected by either state machine, is always: word 0: almost-empty offset register word 1: almost-full offset register word 2: control register word 0: almost-empty offset register ? ? (repeats indefinitely) ? ? note that, in idt-compatible operating mode, word 2 is not accessed; word 0 and word 1 alternate. 3. after normal fifo operation has begun, writing new contents into either of the offset registers should only be done when the fifo is empty. 4. wen 2 , ren 2 , and oe may be anded terms in the enabling of read and write operations, according to the state of the emode control input and of control register bit 05. bold italic = enhanced operating mode 2048 x 18/4096 x 18 synchronous fifos LH540235/45 11
table 4. status flags number of unread data words present within fifo 1, 2 full flag middle flags empty flag 2048 18 fifo 4096 18 fifo ff paf hf pae ef 0 0 hhhl l 1 to q 1 to q h h h l h (q + 1) to 1024 (q + 1) to 2048 hhhhh 1025 to (2048 C (p + 1)) 2049 to (4096 C (p + 1)) h h l h h (2048 C p) to 2047 (4096 C p) to 4095 h l l h h 2048 4096 l l l h h notes: 1. q = programmable-almost-empty offset value. (default value: q = 127.) 2. p = programmable-almost-full offset value. (default value: p = 127.) 3. only 11 (2048 18), or all 12 (4096 18), of the 12 offset-value-register bits should be programmed. the unneeded most-significant-end 2048 18 bit should be low (zero). 4. the flag output is delayed by one full clock cycle in enhanced operating mode, when synchronous operation is specified for in termediate flags. bold italic = enhanced operating mode LH540235/45 2048 x 18/4096 x 18 synchronous fifos 12
table 5. control-register format command register bits code value after reset flag affected, if any description notes emode = h emode = l 00 l lh C deassertion of ld does not reset the programmable- register write pointer and read pointer. idt-compatible addressing of programmable registers. h deassertion of ld resets the programmable-register write pointer and read pointer to address word 0, the programmable-almost- empty-flag-offset register. the change takes effect after a valid write operation or a valid read operation, respectively, to the memory array. non-ambiguous addressing of programmable registers. 01 l lh pae set by - rclk, reset by - wclk. asynchronous flag clocking. h set and reset by - rclk. synchronous flag clocking. 03, 02 ll ll hh hf set by - wclk, reset by - rclk. asynchronous flag clocking. lh set and reset by - rclk. synchronous flag clocking at output port. hl, set and reset by - wclk. synchronous flag clocking at input port. hh 04 l l h paf set by - wclk, reset by - rclk. asynchronous flag clocking. h set and reset by - wclk. synchronous flag clocking. 05 l lh C oe has no effect on an internal read operation, apart from disabling the outputs. allows the read-address pointer to advance even when q 0 C q 17 are not driving the output bus. h deassertion of oe inhibits a read operation; whenever the data outputs q 0 C q 17 are in the high-z state, the read pointer does not advance. inhibits the read-address pointer from advancing when q 0 C q 17 are not driving the output bus; thus, guards against data loss. 06 l ll C reserved. future use to control depth cascading and interlocked paralleling. h 11, 10, 09, 08, 07 lllll lllll lllll C reserved. reserved. notes: 1. when emode is high, and control register bits 00-05 are low, the fifo behaves in a manner functionally equivalent to the idt72235b/45b fifo of similar depth and speed grade. under these conditions, the control register is not visible or accessible to the ex- ternal system which includes the fifo. 2. if emode is not asserted (is high), control register bits 00-05 remain low after a reset operation. however, if emode is asserted (is low) during a reset operation, control register bits 00-05 are forced high, and remain high until changed. control register bit s 06-11 are unaffected by emode. description of signals and operating sequences (contd) bold italic = enhanced operating mode 2048 x 18/4096 x 18 synchronous fifos LH540235/45 13
data inputs data in (d 0 C d 17 ) data, programmable-flag-offset values, and control- register codes are input to the fifo as 18-bit words on d 0 C d 17 . unused bit positions in offset-value and con- trol-register words should be zero-filled. control inputs reset ( rs) the fifo is reset whenever the asynchronous reset ( rs) input is taken to a low state. a reset operation is required after power-up, before the first write operation may occur. the state of the fifo is fully defined after a reset operation. if the default values which are entered into the programmable-flag-offset-value registers and the control register by a reset operation are accept- able, then no device programming is required. a reset operation initializes the fifos internal read-address and write-address pointers to the fifos first physical memory location. the five status flags, ff, paf, hf, pae, and ef, are updated to indicate that the fifo is completely empty; thus, the first three of these are reset to high, and the last two are reset to low. the flag-offset values for paf and pae each are initialized to 127 10 . if emode is not being asserted (i.e., if emode is high), all control register bits are initialized to low, to configure the fifo to operate in the idt72235b/45b-compatible operating mode. until a write operation occurs, the data outputs d 0 C d 17 all are low whenever oe is low. enhanced operating mode ( emode) whenever emode is asserted during a reset op- eration, control register bits 00-05 remain high rather than low after the completion of the reset operation. thus, emode has the effect of activating all of the enhanced-operating-mode features during a reset operation. subsequently, they may be indi- vidually disabled or re-enabled by changing the set- ting of control-register bits. the behavior of these enhanced-operating-mode features is described in table 5. for permanent enhanced-operating-mode operation, emode must be grounded; dynamic con- trol of emode during system operation is not recom- mended. asserting emode during a reset operation also causes wxi/wen 2 to be configured as wen 2 , and rxi/ren 2 to be configured as ren 2 , to support inter- locked-paralleled operation of two fifos side by side (see figure 28). additionally, rxo/ ef 2 is config- ured as ef 2 , which duplicates the ef signal with one extra rck cycle delay, in order to provide proper timing for pipelined cascaded operation. write clock (wclk) a rising edge (low-to-high transition) of wclk initi- ates a fifo write cycle if ld is high, or a programma- ble-register write cycle if ld is low. the 18 data inputs, and all input-side synchronous control inputs, must meet setup and hold times with respect to the rising edge of wclk. the input-side status flags are meaningful after specified time intervals, following a rising edge of wclk. conceptually, the wclk input receives a free-running, periodic clock waveform, which is used to control other signals which are edge-sensitive. however, there actually is not any absolute requirement that the wclk waveform must be periodic. an asynchronous mode of operation is in fact possible, if wen is continuously asserted (that is, is continuously held low), and wclk receives ape- riodic clock pulses of suitable duration. there likewise is no requirement that wclk must have any particular synchronization relation to the read clock rclk. these two clock inputs may in fact receive the same clock signal; or they may receive totally-different signals, which are not synchronized to each other in any way. write enable ( wen) whenever wen is being asserted (is low) and ld is high, and the fifo is not full, an 18-bit data word is loaded into the effective input register for the memory array at every wclk rising edge (low-to-high transi- tion). data words are stored into the two-port memory array sequentially, regardless of any ongoing read opera- tion. whenever wen is not being asserted (is high), the input register retains whatever data word it contained previously, and no new data word gets loaded into the memory array. to prevent overrunning the internal fifo boundaries, further write operations are inhibited whenever the full flag ( ff) is being asserted (is low). if a valid read operation then occurs, upon the completion of that read cycle ff again goes high after a time t wff , and another write operation is allowed to begin whenever wclk makes another low-to-high transition. effectively, wen is overridden by ff; thus, during normal fifo operation, wen has no effect when the fifo is full. in the enhanced operating mode, wxi/wen 2 func- tions as wen 2 , an additional duplicate (albeit asser- tive-high) write-enable input, in order to provide aninterlocking mechanism for reliable synchro- nization of two paralleled fifos. to control writing, wen 2 is anded with wen; this logic-and function ( wen wen 2 ) then behaves like wen in the forego- ing description. bold italic = enhanced operating mode LH540235/45 2048 x 18/4096 x 18 synchronous fifos 14
read clock (rclk) a rising edge (low-to-high transition) of rclk initi- ates a fifo read cycle if ld is high, or a programma- ble-register read cycle if ld is low. all output-side synchronous control inputs must meet setup and hold times with respect to the rising edge of rclk. the 18 data outputs, and the output-side status flags, are meaningful after specified time intervals, following a rising edge of rclk. conceptually, the rclk input receives a free-running, periodic clock waveform, which is used to control other signals which are edge-sensitive. however, there actually is not any absolute requirement that the rclk waveform must be periodic. an asynchronous mode of operation is in fact possible, if ren is continuously asserted (that is, is continuously held low), and rclk receives aperi- odic clock pulses of suitable duration. there likewise is no requirement that rclk must have any particular synchronization relation to the write clock wclk. these two clock inputs may in fact receive the same clock signal; or they may receive totally-different signals, which are not synchronized to each other in any way. read enable ( ren) whenever ren is being asserted (is low), and the fifo is not empty, an 18-bit data word is loaded into the output register from the memory array at every rclk rising edge (low-to-high transition). data words are read from the two-port memory array sequentially, regard- less of any ongoing write operation. whenever ren is not being asserted (is high), the output register retains whatever data word it contained previously, and no new data word gets loaded into it from the memory array. to prevent underrunning the internal fifo boundaries, further read operations are inhibited whenever the empty flag ( ef) is being asserted (is low). if a valid write operation then occurs, upon the completion of that write cycle ef again goes high after a time t ref , and another read operation is allowed to begin whenever rclk makes another low-to-high transition. effectively, ren is overridden by ef; thus, during normal fifo operation, ren has no effect when the fifo is empty. in the enhanced operating mode, one (or, some- times two) additional read-enable inputs may be anded with ren to control reading, depending on the state of control-register bit 05. the additional read-enable input(s) are ren 2 (and oe). also in the enhanced operating mode, rxi/ren 2 functions as ren 2 , an additional duplicate (albeit assertive-high) read-enable input, in order to pro- vide an interlocking mechanism for reliable synchronization of two paralleled fifos. also, if control register bit 05 is high, oe takes on the extra role of serving as yet another duplicate read-enable input, in addition to its usual function of controlling the fifos data outputs, in order to inhibit further read operations whenever the fifos data outputs are disabled, and thereby to prevent data loss under some circumstances. output enable ( oe) oe is an assertive-low, asynchronous, output enable. in the idt-compatible operating mode, oe has only the effect of enabling or disabling the data outputs q 0 C q 17 . that is, disabling q 0 C q 17 does not inhibit a read operation, for data being transmitted to the output register; the same data will remain available later, when the outputs are again enabled, unless subsequently over- written. when q 0 C q 17 are enabled, each of these 18 data outputs is in a normal high or low state, according to the bit pattern of the data word in the output register. when q 0 C q 17 are disabled, each of these outputs is in the high-z (high-impedance) state. in the enhanced operating mode, if control reg- ister bit 05 is high, oe behaves as an additional read-enable control input, as well as enabling and disabling the data outputs q 0 C q 17 . under these circumstances, incrementing the read-address pointer is inhibited whenever q 0 C q 17 are in the high-z state. thus, reading successive words which fail ever to reach the outputs is prevented, as a safeguard against data loss. load ( ld ) the sharp LH540235/45 fifos contain three 18-bit programmable registers. the contents of these three registers may be loaded with data from the data inputs d 0 C d 17 , or read out onto the data outputs q 0 C q 17 . the first two registers are the programmable-flag-offset- value registers, for the programmable almost-empty flag ( pae) and the programmable almost-full flag ( paf) respectively. the third register is the control register, which includes several configuration-control bits for selectively enabling and disabling sharps enhanced-operating-mode features. description of signals and operating sequences (contd) bold italic = enhanced operating mode 2048 x 18/4096 x 18 synchronous fifos LH540235/45 15
none of these three registers makes use of all of its available 18 bits. figure 6 shows which bit positions of each register are operational. the two programmable- flag-offset-value registers each contain an offset value in bits 0-10 (LH540235) or bits 0-11 (lh540245); bits 11-17 (LH540235) or bits 12-17 (lh540245) are unused. the default values for both offsets are 127 10 . the control register configuration is shown in fig- ure 6 and in table 5. for the control register , in the idt-compatible operating mode, with emode deas- serted (high), the default value for all control-register bits is zero (low). in the enhanced operating mode, with emode asserted (low), the default value for bits 00-05 is high, and the default value for bits 06-11 is low. whenever ld and wen are simultaneously being asserted (are both low), the 18-bit data word from the data inputs d 0 C d 17 is written into the programmable- almost-empty-flag-offset-value register at the first ris- ing edge (low-to-high transition) of the write clock (wclk). (see table 3.) if ld and wen continue to be simultaneously asserted, another 18-bit data word from the data inputs d 0 C d 17 is written into the programma- ble-almost-full-flag-offset-value register at the second rising edge of wclk. 540235-4 programmable-almost-empty-flag-offset value 1, 2 0 11 12 17 0 17 programmable-almost-full-flag-offset value 1, 2 word 0 control register 4, 5 1 2 3 4 5 6 17 word 1 word 2 5 2 3 future use to control depth cascading and interlocked paralleling. enables suppressing reading whenever data outputs are disabled. makes paf synchronous. makes hf synchronous. (see the control-register format table for the encoding of bits 02-03.) makes pae synchronous. selects reinitialized addressing of the programmable registers. 6 5 3 6 bold italic = enhanced operating mode. 1 0 = reserved. do not load with non-zero information. 1 0 2 0 11 4 control-register bits: 4 reserved for future use. 12 7 10 3 3 notes: 1. default offset values all are 127 10 = 7f 16 . 2. bits 11-17 (LH540235) or bits 12-17 (lh540245) of both offset-value registers should in all cases be programmed low (zero). 3. this bit position is used for offset values in the lh540245 only. in the LH540235, it always should be programmed low. 4. see the control-register format table for the default states of the control register, for emode = high (idt-compatible operating mode) and for emode = low (enhanced operating mode). the control register is not accessible or visible in idt-compatible operating mode. 5. the assertion of emode (low) forces control register bits 00-05 high during a reset operation. after that, these bits may be programmed at will. see table 5 for a more complete description of these effects. 11 12 10 figure 5. programmable registers bold italic = enhanced operating mode LH540235/45 2048 x 18/4096 x 18 synchronous fifos 16
what happens next is determined by the state of the emode control input. if it is deasserted (high), the next 18-bit word from the data inputs d 0 C d 17 is written back into the programmable-almost-empty-flag-offset-value register again. but, if emode is asserted (low), then still another 18-bit data word from the data inputs d 0 C d 17 is written into the control register at the third rising edge of wclk. at the fourth rising edge of wclk, writing again occurs to the programmable-almost- empty-flag-offset-value register; and the same three-step writing sequence gets repeated on sub- sequent wclk rising edges. the lower 11 bits of these offset-value words are made use of by the 2048-word LH540235, and the lower 12 bits by the 4096-word lh540245. six active bits are used for the control register, by both the LH540235 and the lh540245 . there is no restriction on the values which may occur in these offset-value and control-register fields. however, reserved bit positions must be encoded low, in order to maintain forward compatibility. writing contents to these two or three programmable registers does not have to occur all at one time, or to be effected by one single sequence of steps. whenever ld is being asserted (is low) but wen is not being asserted (is high), the fifos internal programmable-register- write-address pointer maintains its present value, without any writing actually taking place at each rising edge of wclk (see table 3). thus, for instance, one or two programmable registers may be written, after which the fifo may be returned to normal fifo-array-read/write operation by deasserting ld (to high). likewise, whenever ld and ren are simultaneously being asserted (are both low) the 18-bit data word (zero-filled as necessary) from the programmable-al- most-empty-flag-offset-value register is read to the data outputs q 0 C q 17 at the first rising edge (low-to- high transition) of the read clock (rclk) (see table 3). if ld and ren continue to be simultaneously asserted, another 18-bit data word from the programmable-almost- full-flag-offset-value register is read to the data outputs q 0 C q 17 at the second rising edge of rclk. what happens next is determined by the state of the emode control input. if it is deasserted (high), the next 18-bit word again comes from the programmable-almost- empty-flag-offset-value register; it is read to the data outputs q 0 C q 17 . but, if emode is asserted (low), then the next 18-bit data word instead comes from the control register; it is read to the data outputs q 0 C q 17 at the third rising edge of rclk. at the fourth rising edge of rclk, reading again occurs from the programma- ble-almost-empty-flag-offset-value register; and the same three-step reading sequence gets repeated on subsequent rclk rising edges. reading contents from these two or three program- mable registers does not have to occur all at one time, or to be effected by one single sequence of steps. whenever ld is being asserted (is low) but ren is not being asserted (is high), the fifos internal programmable- register-read-address pointer maintains its present value, without any reading actually taking place at each rising edge of rclk. (see table 3.) thus, for instance, one or two programmable registers may be read, after which the fifo may be returned to normal fifo-array-read/write operation by deasserting ld (to high). to ensure correct operation, the simultaneous reading and writing of a register should be avoided. first load/ retransmit ( fl /rt) fl /rt is a dual-purpose signal. it is one of four input signals which select the grouping mode in which the fifo operates after being reset; the other three of these input signals are wxi / wen 2 , rxi / ren 2, and emode. there are four possible grouping modes: standalone, inter- locked paralleled , cascaded master or first-load, and cascaded slave. the designations master and slave pertain to idt-compatible depth cascading. tables 1 and 2 show the signal encodings which select each grouping mode. in standalone or paralleled operation, the fl/ rt pin should be grounded for strict idt72235b/45b-compatible operation. however, if it is taken high, regardless of the state of the emode control input, the fifos internal read-address pointer is reset to address the fifos first physical memory location, without the other usual reset actions being taken; in particular, the fifos internal write-address pointer is unaf- fected. subsequent read operations may then again read out the same block of data, delimited by the fifos first physical memory location and the current value of the write pointer, as was read out previously. there is no limit on the number of times that a block of data may be retransmitted. the only restrictions are that neither the read-address pointer nor the write-address pointer may wrap around and address the fifos first physical memory location a second time during the retransmission process, and that the retransmit facility is unavailable during cascaded opera- tion. in idt-compatible cascaded operation, fl/ rt is grounded for the master or first-load fifo, to distinguish it from the other slave fifos in the cascade, which must all have their fl/ rt inputs high during a reset operation (see again tables 1 and 2). the cascade will not operate correctly either without any master fifo, or with more than one master fifo. description of signals and operating sequences (contd) bold italic = enhanced operating mode 2048 x 18/4096 x 18 synchronous fifos LH540235/45 17
write expansion input/ write enable 2 ( wxi/ wen 2 ) wxi /wen 2 is a dual-purpose signal. it is one of four input signals which select the grouping mode in which the fifo operates after being reset; the other three of these input signals are fl/ rt , rxi/ ren 2 , and emode . there are four possible grouping modes: standalone, inter- locked paralleled , cascaded master or first-load, and cascaded slave. the designations master and slave pertain to idt-compatible depth cascading. tables 1 and 2 show the signal encodings which select each grouping mode. in standalone operation, wxi/ wen 2 and rxi/ ren 2 both must be grounded so that the fifo comes up in the standalone grouping mode after a reset operation. in interlocked-paralleled operation, wxi/wen 2 is tied to ff of the other paralleled fifo, and rxi/ren 2 is tied to ef of that same other fifo. this interconnection scheme ensures that both fifos will operate together, and remain coordinated, regardless of tim- ing skews. in cascaded operation, wxi/ wen 2 is connected to the wxo (write expansion output; actually wxo/ hf) output of the previous fifo in the cascade. rxi/ ren 2 is likewise connected to the rxo (read expansion output; actually rxo/ ef 2 ) output of that previous fifo. a reset operation forces wxo/ hf and rxo/ ef 2 high for each fifo; consequently, all fifos with their wxi/ wen 2 and rxi/ ren 2 inputs thus connected come up in one of the two cascaded grouping modes, according to whether their fl/ rt inputs are grounded or tied high (see tables 1 and 2). read expansion input/ read enable 2 ( rxi/ ren 2 ) rxi /ren 2 is a dual-purpose signal. it is one of four input signals which select the grouping mode in which the fifo operates after being reset; the other three of these input signals are fl/ rt , wxi/ wen 2 , and emode . there are four possible grouping modes: standalone, inter- locked-paralleled , cascaded master or first-load, and cascaded slave. the designations master and slave pertain to idt-compatible depth cascading. tables 1 and 2 show the signal encodings which select each grouping mode. in standalone operation, wxi/ wen 2 and rxi/ ren 2 both must be grounded, so that the fifo comes up in the standalone grouping mode after a reset operation. in interlocked-paralleled operation, wxi/wen 2 is tied to ff of the other paralleled fifo, and rxi/ren 2 is tied to ef of that same other fifo. this interconnection scheme ensures that both fifos will operate to- gether, and remain coordinated, regardless of timing skews. in cascaded operation, rxi/ ren 2 is connected to rxo (read expansion output; actually rxo/ ef 2 )) of the previous fifo in the cascade. wxi/ wen 2 is likewise connected to wxo (write expansion output; actually wxo/ hf) output of that previous fifo. a reset operation forces rxo/ ef 2 and wxo/ hf high for each fifo; consequently, all fifos with their rxi/ ren 2 and wxi/ wen 2 inputs thus connected come up in one of the two idt-compatible cascaded grouping modes, accord- ing to whether their fl/ rt inputs are grounded or tied high (see again tables 1 and 2). data outputs data out (q 0 C q 17 ) data, programmable-flag-offset values, and control- register codes are output from the fifo as 18-bit words on q 0 C q 17 . unused bit positions in offset-value words and control-register words are zero-filled. control/status outputs full flag ( ff) ff goes low whenever the fifo is completely full. that is, whenever the fifos internal write pointer has completely caught up with its internal read pointer; so that, if another word were to be written, it would have to overwrite the unread word which is now in position for reading out by the next requested read operation. under these conditions, the fifo is filled to its nominal capacity, which is 2048 18-bit words for the LH540235 or 4096 18-bit words for the lh540245 respectively. write opera- tions are inhibited whenever ff is low, regardless of the assertion or deassertion of write enable ( wen). if the fifo has been reset by asserting rs (low), ff initially is high. but, whenever no read operations have been performed since the completion of the reset opera- tion, ff goes low after 2048 write operations for the LH540235, or after 4096 write operations for the lh540245 (see table 4). ff gets updated after a low-to-high transition of the write clock (wclk). programmable almost-full flag ( paf) paf goes low whenever the fifo is almost full; that is, whenever subtracting the value of the fifos internal read pointer from the value of its internal write pointer yields a difference which is less than the value of the programmable-almost-full-flag offset p. the subtrac- tion is performed using modular arithmetic, modulo the total nominal number of 18-bit words in the fifos physi- cal memory, which is 2048 for the LH540235 or 4096 for the lh540245 respectively. bold italic = enhanced operating mode LH540235/45 2048 x 18/4096 x 18 synchronous fifos 18
the default value of p after the completion of a reset operation is 127 10 . however, p may be set to any value which does not exceed this total nominal number of words for the device, as explained in the description of load ( ld). if the fifo has been reset by asserting rs (low), and no read operations have been performed since the completion of the reset operation, paf goes low after (2048-p) write operations for the LH540235, or after (4096-p) write operations for the lh540245 (see table 4). if p is still at its default value, paf is low whenever the fifo is from seven-eighths full to completely full. in the idt-compatible operating mode, paf changes from high to low only after a low-to-high transition of the write clock wclk, and from low to high only after a low-to-high transition of the read clock rclk. thus, in this operating mode, paf behaves as an asyn- chronous flag. in the enhanced operating mode, on the other hand, paf gets updated only after a low-to-high transition of the write clock wclk, and thus behaves as a synchronous flag, whenever control register bit 04 is high (see table 5). write expansion out/half-full flag ( wxo/ hf) wxo/ hf is a dual-purpose signal. in standalone operation, it behaves as a half-full flag ( hf), in accord- ance with table 4. in idt-compatible cascaded opera- tion, it behaves as a write expansion output ( wxo) signal to coordinate writing operations with the next fifo in the cascade. under these same conditions, also, the dual-purpose wxi/ wen 2 and rxi/ ren 2 inputs behave as write expansion input ( wxi) and read expansion input ( rxi) signals respectively. when two or more LH540235 or lh540245 fifos are cascaded to operate as a deeper effective fifo, in an idt-style daisy-chain ring configuration, the write ex- pansion input ( wxi) of each fifo is connected to wxo of the previous fifo in the ring, with wxi of the first-load or master fifo being connected to wxo of the last fifo so as to complete the ring. similar connections are made for each fifo in the ring, parallel to these wxo-to- wxi connections, for read expansion input ( rxi) and read expansion output ( rxo/ ef 2 , when it is behaving as rxo). when the last physical location has been written in a fifo operating in cascaded mode, a low-going pulse is emitted by that fifo on its wxo output, and the fifo is deactivated for writing at the next valid wclk; and the next fifo in the ring is simultaneously activated for writing. otherwise, wxo remains constantly high when- ever the fifo is operating in cascaded mode. this low- going wxo pulse serves as a write token in the token-passing fifo-cascading scheme; it is passed on to the next fifo in the ring via its wxi input. when this next fifo receives the write token, it is activated for writing at the next valid wclk. the foregoing description applies both to the first-load or master fifo in the ring, and to any and all slave fifos in the ring. however, wxo has no necessary function for fifos operating in the standalone mode. consequently, in that mode, the same output pin is used for hf; it follows that hf is not available as an output from any fifo which is operating in the idt-compatible cas- caded mode. a fifo is initialized into cascaded master mode, into cascaded slave mode, into interlocked-par- alleled mode , or into standalone mode according to the state of its wxi/ wen 2 , rxi/ ren 2 , and fl/ rt control inputs during a reset operation, and of emode (see table 1, table 2, and table 5). in standalone or interlocked-paralleled operation, hf goes low whenever the fifo is more than half full; that is, whenever subtracting the value of the fifos internal read pointer from the value of its internal write pointer yields a difference which is less than half of the total nominal number of 18-bit words in the fifos physi- cal memory, which is 1024 for the LH540235 or 2048 for the lh540245 respectively (see table 4). the subtraction is performed using modular arithmetic, modulo this total nominal number of words, which is 2048 for the LH540235 or 4096 for the lh540245 respectively. if the fifo has been reset by asserting rs (low), and it is operating in standalone mode or in interlocked-par- alleled mode, and no read operations have been per- formed since the completion of the reset operation, hf goes low after 1025 write operations for the LH540235, or after 2049 write operations for the lh540245 (see again table 4). in the idt-compatible operating mode, hf changes from high to low only after a low-to-high transition of the write clock wclk, and from low to high only after a low-to-high transition of the read clock rclk. thus, in this operating mode, hf behaves as an asyn- chronous flag. in the enhanced operating mode, on the other hand, hf gets updated only after a low-to-high transition of the read clock rclk, or else after a low-to-high transition of the write clock wclk, according to the setting of bits 03 and 02 of the control register (see table 5). thus, in this mode hf behaves as a synchronous flag, and may be syn- chronized either to the input side of the fifo (i.e., to wclk), or to the output side of the fifo (i.e., to rclk). description of signals and operating sequences (contd) bold italic = enhanced operating mode 2048 x 18/4096 x 18 synchronous fifos LH540235/45 19
programmable almost-empty flag ( pae) pae goes low whenever the fifo is almost empty; that is, whenever subtracting the value of the fifos internal write pointer from the value of its internal read pointer yields a difference which is less than q + 1, where q is the value of the programmable-almost-empty-flag offset. the subtraction is performed using modular arith- metic, modulo the total nominal number of 18-bit words in the fifos physical memory, which is 2048 for the LH540235 or 4096 for the lh540245 respectively. the default value of q after the completion of a reset operation is 127 10 . however, q may be set to any value which does not exceed this total nominal number of words for the device, as explained in the description of load ( ld). if the fifo has been reset by asserting rs (low), and no write operations have been performed since the com- pletion of the reset operation, then pae is low (see table 4). if q is still at its default value, pae is low whenever the fifo is from one-eighth full to completely empty. in the idt-compatible operating mode, pae changes from high to low only after a low-to-high transition of the read clock rclk, and from low to high only after a low-to-high transition of the write clock wclk. thus, in this operating mode, pae behaves as an asyn- chronous flag. in the enhanced operating mode, on the other hand, pae gets updated only after a low-to-high transition of the read clock rclk, and thus behaves as a synchronous flag, whenever control register bit 01 is high (see table 5). empty flag ( ef) ef goes low whenever the fifo is completely empty. that is, whenever the fifos internal read pointer has completely caught up with its internal write pointer; so that, if another word were to be read out, it would have to come from the physical memory location which is now in position to be written into by the next requested write operation. read operations are inhibited whenever ef is low, regardless of the assertion or deassertion of read enable ( ren). if the fifo has been reset by asserting rs (low), and no write operations have been performed since the completion of the reset operation, then ef is low. (see table 4.) ef gets updated after a low-to-high transition of the read clock rclk. read expansion out/ empty flag 2 ( rxo/ ef 2 ) rxo/ ef 2 is a dual-purpose signal. in standalone operation, it has no function. in idt-compatible cas- caded operation, it behaves as a read expansion output ( rxo) signal to coordinate writing operations with the next fifo in the cascade. under these same conditions, also, the dual purpose rxi/ ren 2 and wxi/ wen 2 inputs behave as read expansion input ( rxi) and write expan- sion input ( wxi) signals respectively. when two or more LH540235 or lh540245 fifos are operating in idt-compatible cascaded mode as a deeper effective fifo, the dual-purpose rxi/ ren 2 and wxi/ wen 2 inputs behave as read expansion input ( rxi) and write expansion input ( wxi) signals respectively. an idt-style cascade of these fifo devices has a daisy- chain ring configuration; the read expansion input ( rxi) of each fifo is connected to rxo ( rxo/ ef 2 , behaving as rxo) of the previous fifo in the ring, with rxi of the first-load or master fifo being connected to rxo of the last fifo so as to complete the ring. similar connec- tions are made for each fifo in the ring, parallel to these rxo-to- rxi connections, for write expansion input ( wxi) and write expansion output ( wxo). when the last physical location has been read in a fifo operating in idt-style cascaded mode, a low-go- ing pulse is emitted by that fifo on its rxo output; otherwise, rxo remains constantly high. this low-go- ing rxo pulse serves as a read token in the token-pass- ing fifo-cascading scheme; it is passed on to the next fifo in the ring via its rxi input. when this next fifo receives the read token, it is activated for reading at the next valid rclk. after a fifo emits an rxo pulse, the fifo is deacti- vated for reading at the next valid rclk. also, its data outputs go into high-z state, regardless of the assertion or deassertion of its output enable ( oe) control input, until it again receives the token. simultaneously, the next fifo in the ring is activated for reading. the foregoing description applies both to the first-load or master fifo in the ring, and to any and all slave fifos in the ring. however, rxo has no necessary function for a fifo which is operating in standalone mode. consequently, in that mode, rxo is never as- serted, and remains constantly high. a fifo is initialized into standalone mode, into cascaded master mode, or into cascaded slave mode according to the state of its wxi/ wen 2 , rxi/ ren 2 , and fl/ rt control inputs during a reset operation. it also may be forced into inter- locked-paralleled mode by emode (see table 1, ta- ble 2, and table 5). in the enhanced operating mode, rxo/ ef 2 be- haves as a second empty flag ef 2 . ef 2 is an exact duplicate of the main empty flag ef, except that it is delayed with respect to ef by one full cycle of the read clock rclk. bold italic = enhanced operating mode LH540235/45 2048 x 18/4096 x 18 synchronous fifos 20
timing diagrams t rs t rsr t rsf t rsf t rsf q 0 - q 17 ff, paf, hf ef, pae ren, wen, ld rs oe = high 1 oe = low 540235-5 notes: 1. after reset, the outputs will be low if oe = low, and in a high-impedance state if oe = high. 2. the clocks (rclk, wclk) may be free-running during a reset operation. t rss figure 6. reset timing t ds no operation t ens t wff t skew1 (1) t clkh t clk t clkl t dh t enh t wff wclk d 0 - d 17 wen ff rclk ren 540235-6 note: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge for ff to change predictably during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then it is not guaranteed that ff will change state until the next following wclk edge. valid data in figure 7. synchronous write operation 2048 x 18/4096 x 18 synchronous fifos LH540235/45 21
t clkh t clk t clkl wclk q 0 - q 17 ren rclk ef valid data out t ens t enh no operation t ref t ref t a t oe t olz t ohz t skew2 (1) oe wen 540235-7 note: 1. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge for ef to change predictably during the current clock cycle. if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then it is not guaranteed that ef will change state until the next following rclk edge. figure 8. synchronous read operation timing diagrams (contd) LH540235/45 2048 x 18/4096 x 18 synchronous fifos 22
t ds t ens q 0 - q 17 ren rclk ef oe wen 540235-8 d 0 (first valid wrte) d 1 d 2 d 3 d 4 d 0 d 1 t frl (2) t skew2 (1) t ref t a (3) t a t olz t oe d 0 - d 17 wclk notes: 1. t skew2 is the minimum time between a rising rclk edge and a rising wclk edge for ff to change predictably during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew2 , then it is not guaranteed that ff will change state until the next following wclk edge. 2. t frl (first-read latency) is the minimum time between a rising wclk edge and a rising rclk edge to assure a correct readout of the first data word d 0 in response to the next rclk edge. thus, t frl = t clk + t skew2 . if t frl is not met, d 0 may be available either at t clk + t skew2 , or after one more clock cycle delay at 2 t clk + t skew2 . the first-read latency timing restrictions apply only when the fifo has been empty (ef = low). 3. ef may be used to determine when the first data word d 0 may be read. d 0 always is available on the next cycle after ef has gone high. figure 9. latency for the first data word after a reset operation, with simultaneous read and write timing diagrams (contd) 2048 x 18/4096 x 18 synchronous fifos LH540235/45 23
timing diagrams (contd) 540235-9 q 0 - q 17 ren rclk ff oe wen d 0 - d 17 wclk data write data write data read low data in output register next data read no write no write t skew1 1 t ds t ds t skew1 1 t wff t wff t wff t ens t enh t ens t enh t a t a note: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge for ff to change predictably during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then it is not guaranteed that ff will change state until the next following wclk edge. figure 10. full-flag timing LH540235/45 2048 x 18/4096 x 18 synchronous fifos 24
timing diagrams (contd) 540235-10 q 0 - q 17 ren rclk ef oe wen d 0 - d 17 wclk data read t ds data in output register t ds data write 1 data write 2 t ens t enh t enh t ens t frl (2) t skew2 (1) t skew2 (1) t ref t ref t ref t a t frl (2) notes: 1. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge for ef to change predictably during the current clock cycle. if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then it is not guaranteed that ef will change state until the next following rclk edge. 2. t frl (first-read latency) is the minimum time between a rising wclk edge and a rising rclk edge to assure a correct readout of the first data word d 0 in response to the next rclk edge. thus, t frl = t clk + t skew2 . if t frl is not met, d 0 may be available either at t clk + t skew2 , or after one more clock cycle delay at 2 t clk + t skew2 . the first-read latency timing restrictions apply only when the fifo has been empty (ef = low). 3. ef may be used to determine when the first data word d 0 may be read. d 0 always is available on the next cycle after ef has gone high. low bold italic = enhanced operating mode. ef 2 t ref t ref figure 11. empty-flag timing 2048 x 18/4096 x 18 synchronous fifos LH540235/45 25
wclk clkl t clkh t clk t t ens t enh t ens t ds t dh pae offset paf offset control register ld wen d 0 - d 15 540235-11 figure 12. programmable-register write operation rclk clkl t clkh t clk t t ens t enh t ens t a control register ld ren q 0 - q 15 unknown pae offset paf offset 540235-12 figure 13. programmable-register read operation timing diagrams (contd) LH540235/45 2048 x 18/4096 x 18 synchronous fifos 26
540235-13 wclk wen q + 1 words in fifo q words in fifo ren rclk pae note: 1. pae offset = q. also, number of data words written into fifo already = q. t clkh t clkl t ens t enh t ens t pae t pae figure 14. programmable-almost-empty flag timing, idt-compatible operating mode timing diagrams (contd) 2048 x 18/4096 x 18 synchronous fifos LH540235/45 27
540235-23 q 0 - q 17 ren rclk pae oe wen d 0 - d 17 wclk data read t ds data in output register t ds data write 1 data write 2 t ens t enh t enh t ens t skew2 (1) t skew2 (1) t paes t paes t paes t a low notes: 1. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge for pae to change predictably during the current clock cycle. if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then it is not guaranteed that pae will change state until the next following rclk edge. 2. pae offset = q. also, number of data words written into fifo already = q. 3. the internal state of the fifo: at , q+1 words. at , q words. at , q+1 words again. enhanced operating mode timing diagram b a c a b c figure 15. programmable-almost-empty flag timing, when synchronous (enhanced operating mode ) timing diagrams (contd) LH540235/45 2048 x 18/4096 x 18 synchronous fifos 28
timing diagrams (contd) 540235-14 wclk t ens (1) wen 2048 - p words in fifo (2) 2047 - p words in fifo (3) ren rclk paf notes: 1. paf offset = p. number of data words written into fifo already = 2047 - p for the LH540235 and 4095 - p for the lh540245. 2. 2048 - p words in fifo for LH540235. 4096 - p words in fifo for lh540245. 3. 2047 - p words in fifo for LH540235. 4095 - p words in fifo for lh540245. t ens t paf t paf t enh t clkh t clkl figure 16. programmable almost-full-flag timing, idt-compatible operating mode 2048 x 18/4096 x 18 synchronous fifos LH540235/45 29
540235-24 q 0 - q 17 ren rclk paf oe wen d 0 - d 17 wclk data write data write data read low data in output register next data read no write t skew1 (1) t ds t ds t skew1 (1) t pafs t pafs t pafs t ens t enh t ens t enh t a t a no write notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge for paf to change predictably during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then it is not guaranteed that paf will change state until the next following wclk edge. 2. paf offset = p. number of data words written into fifo already = 2047 - p for the LH540235 and 4095 - p for the lh540245. 3. the internal state of the fifo: at , 2047 - p words in fifo for LH540235 and 4095 - p words in fifo for lh540245. enhanced operating mode timing diagram a b c a c b at , 2048 - p words in fifo for LH540235 and 4096 - p words in fifo for lh540245. at , again 2047 - p words in fifo for LH540235 and 4095 - p words in fifo for lh540245. figure 17. programmable-almost-full-flag timing, when synchronous (enhanced operating mode ) timing diagrams (contd) LH540235/45 2048 x 18/4096 x 18 synchronous fifos 30
540235-15 wclk t clkh wen half full +1 or more half full or less ren rclk hf t clkl t ens t enh t hf t hf t ens half full or less figure 18. half-full-flag timing, idt-compatible operating mode timing diagrams (contd) 2048 x 18/4096 x 18 synchronous fifos LH540235/45 31
540235-25 q 0 - q 17 ren rclk hf oe wen d 0 - d 17 wclk data write data write data read low data in output register next data read t skew1 1 t ds t ds t skew1 1 t hfs t hfs t hfs t ens t enh t ens t enh t a t a notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge for hf to change predictably during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then it is not guaranteed that hf will change state until the next following wclk edge. 2. the internal state of the fifo: at , exactly half full. at , half+1 words. at , exactly half full again. enhanced operating mode timing diagram no write no write a b c a b c figure 19. half-full-flag timing, when synchronized to input port (enhanced operating mode) timing diagrams (contd) LH540235/45 2048 x 18/4096 x 18 synchronous fifos 32
540235-26 q 0 - q 17 ren rclk hf oe wen d 0 - d 17 wclk data read t ds data in output register t ds data write 1 data write 2 t ens t enh t enh t ens t skew2 (1) t skew2 (1) t hfs t hfs t hfs t a note: 1. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge for hf to change predictably during the current clock cycle. if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then it is not guaranteed that hf will change state until the next following rclk edge. 2. the internal state of the fifo: at , half+1 words. at , exactly half full. at , half+1 words again. low enhanced operating mode timing diagram a b c a b c t ens t enh figure 20. half-full-flag timing, when synchronized to output port (enhanced operating mode) timing diagrams (contd) 2048 x 18/4096 x 18 synchronous fifos LH540235/45 33
q [17:0] rclk fl/rt ff paf hf pae ef ren 1 540235-28 d r1 t ens t rsf d rt1 2 d rt2 notes: 1. it is not necessary for ren to be low for the device to recognize a retransmit request. 2. in order to actually read data words from the memory arrary, in idt-compatible operating mode, ren = low; in enhanced operating mode, also ren 2 = high (and oe = low, if control register bit 05 = high). in any case, ld = high. 3. d rt1 is the data item in physical location zero of the fifo memory array. 4. the asynchronous intermediate flags (corresponding to low control-register bits) will show correct status three rclk cycles after a retransmit operation, as is shown above. (rt 3 , in the above rclk waveform.) 5. the intermediate flags which have been synchronized to rclk, by setting the appropriate control-register bits to high will show correct status after , four rclk cycles after a retransmit operation. (rt 4 , in the above rclk waveform.) 6. the intermediate flags which have been synchronized to wclk, by setting the appropriate control-register bits high, will show correct status on the second wclk rising edge after , assuming that t skew1 was satisfied at ; otherwise the flags will become valid on the third wclk rising edge after . 7. immediately after a reset operation, before any write operations have taken place, a retransmit operation is a 'no-op', and does not change the state of any fifo registers or flags. 8. in the special case that the fifo memory array contains only one valid data item, the status of hf and paf should be ignored on a retransmit. t ens t enh d r2 t a t a t paf r 1 r 2 rt 1 rt 2 rt 3 rt 4 t wff t hf t pae t ref new valid ff new valid paf new valid hf new valid pae new valid ef unknown unknown unknown previous valid ff previous valid paf previous valid hf previous valid pae previous valid ef ab a b t a t a a a figure 21. retransmit timing, idt-compatible operating mode timing diagrams (contd) LH540235/45 2048 x 18/4096 x 18 synchronous fifos 34
wclk wxo wen (note) note: write to last physical location. 540235-16 t xo t xo t clkh t ens figure 22. write-expansion-out timing, idt-compatible operating mode rclk rxo ren (note) note: read from last physical location. 540235-17 t xo t xo t clkh t ens figure 23. read-expansion-out timing, idt-compatible operating mode wxi wclk 540235-18 t xi t xis figure 24. write-expansion-in timing, timing diagrams (contd) 2048 x 18/4096 x 18 synchronous fifos LH540235/45 35
applications information standalone configuration when depth cascading is not required for a given application, the LH540235/45 is placed in standalone mode by tying the two expansion in pins wxi/ wen 2 and rxi/ ren 2 to ground, while also holding the first load/retransmit pin fl/ rt low for the duration of any reset operation. (see table 1.) subsequently, fl/ rt may be taken high at will, whenever a retransmit operation is desired. if not being used, fl/rt also may be tied to ground, as shown in figure 27. width expansion word-width expansion is implemented by placing mul- tiple LH540235/45 devices in parallel. each device should be configured for standalone mode, unless the depth of one single fifo is not adequate for the application. in this event, word-width expansion may in principle be used with either of the two depth-cascading schemes sup- ported by the LH540235/45 architecture. in practice, the reliability benefits of interlocked-paralleled operation are available only with the pipelining scheme, making it the preferred alternative. (refer to discussion in a later sec- tion.) rxi rclk 540235-19 t xi t xis figure 25. read-expansion-in timing, idt-compatible operating mode write enable (wen) write clock (wclk) load (ld) data in full flag (ff) programmable almost-empty flag (pae) half-full flag (wxo/hf) read clock (rclk) read enable (ren) output enable (oe) data out empty flag (ef) programmable almost-full flag (paf) write expansion in (wxi/ wen 2 ) first load (fl/ rt ) (must be low during a reset operation) 540235-21 LH540235/45 reset (rs) enhanced mode (emode) bold italic = enhanced operating mode. read expansion in (rxi/ ren 2 ) d[17:0] q[17:0] 18 18 figure 26. standalone fifo (2048 18 / 4096 18) timing diagrams (contd) bold italic = enhanced operating mode LH540235/45 2048 x 18/4096 x 18 synchronous fifos 36
when standalone-mode LH540235/45 devices are paralleled, the behavior of the status flags is identical for all devices; so, in principle, a representative value for each of these flags could be derived from any one device. in practice, it is better to derive composite flag values using external logic, since there may be minor speed variations between different actual devices. after writing or reading have been in a disabled state, the process of re-enabling should be gated by the slowest fifo. for m paralleled fifos, the form of this external composite-flag logic may be an or gate with m asser- tive-low inputs and an assertive-low output. in keep- ing with demorgans theorem, such a gate may be implemented as an and gate with m assertive-high inputs and an assertive-high output. figure 28 illustrates the case m = 2. the LH540235/45 architecture supports two very dif- ferent methods of depth cascading: token passing, which follows the scheme used in the pin-compatible and functionally-compatible integrated device technology idt72205b/15b/25b/35b/45b fifos, which the LH540235/45 can directly replace. pipelining, which follows the scheme used in the texas instruments sn74act7801/11/81/82/84 fifos, and also in the sharp lh543620 1024 36 fifo. the sn74act7801/11/81/82/84 pinout closely resembles the LH540235/45 pinout, but is not identical. depth cascading using token passing using the token-passing approach, depth cascading is implemented by configuring the required number of LH540235/45s in a circular ring fashion, with the expan- sion out outputs ( wxo/ hf and rxo/ ef 2 ) of each device tied to the expansion in inputs ( wxi/ wen 2 and rxi/ ren 2 ) of the next device (see figure 29). because a reset operation forces the wxo/ hf and rxo/ ef 2 outputs high for each device, the wxi/ wen 2 and rxi/ ren 2 inputs for the next device are high during the reset operation; thus, these two inputs are high for all devices in the ring. (see tables 1 and 2, and also figure 29.) all devices in the cascade must be in the idt-com- patible operating mode; thus, their emode inputs must be tied to vcc. one fifo in the cascade must be designated as the first-load device, by tying its first load input ( fl/ rt ) to ground. all other devices must have their fl/ rt inputs tied high. under these circumstances, the retransmit function is not available for use. in this mode, the control inputs which govern writing (wclk and wen) and the control inputs which govern reading (rclk and ren) are shared by all devices, while logic within each LH540235/45 governs the steering of data. the common data inputs of all devices are tied together; but only one LH540235/45 is enabled during any given write cycle. likewise, the common three-state data outputs of all devices are wire-ored together; but only one LH540235/45 is enabled, including its three- state outputs, during any given read cycle. a data word is handled only by one device as it passes through the cascade of fifos, regardless of how many fifos are being cascaded together. in the token-passing depth-cascaded mode, external logic should be used to generate a composite full flag and a composite empty flag, by anding the ff outputs of all LH540235/45 devices together and by anding the ef outputs of all devices together, using and gates with assertive-low inputs and an assertive-low output. here, the meaning of these composite flags is direct: the cascade of fifos is full, if and only if all k fifos belonging to the cascade are individually full; and similarly for empty. in keeping with demorgans theorem, these k-input as- sertive-low and gates are implemented physically as k-input assertive-high or gates. figure 29 illustrates the case k = 3. similar external logic also may be used to generate a composite programmable almost-full flag and a com- posite programmable almost-empty flag, by anding the paf outputs of all LH540235/45 devices together and by anding the pae outputs of all devices together. here, however, some careful analysis is required, to determine exactly what the resulting composite flags mean. their significance may vary widely, depending on the number of fifos in the cascade, and on the offset values which are present in the offset registers for these fifos. more complex logical combinations of paf outputs with ff outputs, and of pae outputs with ef outputs, may be found useful in particular applications. in any case, the half-full flag and the retransmit function are not available for devices being used in token- passing depth-cascaded mode. bold italic = enhanced operating mode 2048 x 18/4096 x 18 synchronous fifos LH540235/45 37
hf wclk wen ld rs paf ff ef 2 fl/rt rclk ren oe pae ef ren 2 wen 2 emode hf wclk wen ld rs paf ff ef 2 rclk ren oe pae ef ren 2 wen 2 emode fl/rt read clock read enable output enable efc data out paec write clock write enable load ffc data in reset pafc retransmit (must be low during a reset operation hfc d[17:0] q[17:0] 540235-32 d[17:0] q[17:0] 18 18 18 18 36 36 note: bold italic = enhanced operating mode. figure 27. interlocked-paralleled word-width expansion LH540235/45 2048 x 18/4096 x 18 synchronous fifos 38
540235-27 write clock write enable reset read clock read enable output enable data in ef pae first load data out ff paf load write-token pulse (composite flags) (composite flags) read-token pulse notes: grounding fl designates the 'first-load' fifo ('master' fifo). the remaining fifos are 'slave' fifos. v cc wxo wclk wen ld rs paf ff rxo fl rclk ren oe pae ef rxi wxi emode d[17:0] q[17:0] wxo wclk wen ld rs paf ff rxo fl rclk ren oe pae ef rxi wxi emode d[17:0] q[17:0] wxo wclk wen ld rs paf ff rxo fl rclk ren oe pae ef rxi wxi emode d[17:0] q[17:0] v cc v cc v cc v cc 18 18 18 18 18 18 18 18 bold italic = enhanced operating mode. figure 28. synchronous-fifo depth-cascading using idt-compatible token-passing scheme 2048 x 18/4096 x 18 synchronous fifos LH540235/45 39
depth cascading using pipelining using the pipelining approach, depth cascading is implemented by connecting the required number of LH540235/45s in series. within the cascade, the data outputs of each device are connected to the data inputs of the next device. (see figure 30.) all devices in the cascade must be in the enhanced operating mode ; thus, their emode inputs must be grounded. successive devices in the cascade are crosscoupled; they control each other, using a handclasp scheme for crossconnecting their control inputs and their status out- puts. (see again figure 30.) the input side of the first device, and the output side of the last device, are not crosscoupled to other devices. their control/status and clock pins are connected to the external system. for the fifo devices within the cascade, transferring data from each device to the next device is governed by a clock. preferably, the same clock should be used at every fifo-to-fifo data-transfer interface boundary within the cascade. this transfer clock may be either the external write clock, or the external read clock. if both of these two clocks are periodic and free-running, the faster of the two is the obvious choice for the transfer clock. of course, in principle, the transfer clock may even be some other, totally-different clock. the empty flag of each device is used to govern writing into the next device, and the full flag of each device is used to govern reading from the preceding device. since the standard empty flag ef occurs one rclk cycle too early to properly enable/disable the next device, the duplicate empty flag ef 2 is used instead; ef 2 is an exact copy of ef, except that it is delayed by one full rclk cycle with respect to ef. also, since the usual enable signals wen and ren have the wrong polarity to function properly in this hand- clasp mode, they are grounded for all devices within the cascade. the duplicate but inverted signals wen 2 and ren 2 are used instead. ef 2 , wen 2 , and ren 2 are available only in en- hanced operating mode. they share the same pins which in idt-compatible operating mode are used respectively for rxo, wxi, and rxi. hence, for pipe- lined operation, all devices in the cascade must be in the enhanced operating mode; their emode control inputs must be grounded. when all of the foregoing conditions have been met in the interconnection of the pipelined array, then: at each device-to-device interface boundary within the array, a data word is transferred from the upstream device to the downstream device after every transfer-clock rising edge, as long as the upstream device is not empty and the downstream device is not full. width expansion along with depth cascading in principle, width expansion may be used with either of the two possible depth-cascading schemes. however, when using the token-passing depth-cas- cading scheme, width expansion reduces simply to plac- ing two or more cascades in parallel. in this mode of interconnection, no architectural support is available for interlocked-paralleled operation. composite-flag logic may, of course, be designed to fit any complete array configuration, to determine meaningful full and empty indications for the entire array. this logic may, for in- stance, or the ff and ef signals from the devices at the same relative position in each of the paralleled cascades, and then and all of the rank- ff signals together; and likewise for all of the rank- ef signals. then, the entire array is indicated to be full, if all ranks of devices (across the paralleled cascades) are individually full; and, similarly for empty. when using the pipelined depth-cascading scheme, on the other hand, the first rank of devices (the one which receives input data words from the external system) and the last rank of devices (the one which provides output data words to the external system) may be operated in an interlocked-paralleled manner. figure 31 shows a sug- gested interconnection scheme for two paralleled cas- cades, each three devices deep. the entire array of figure 31 would comprise a 12288 36 effective fifo, if implemented with 4096 18 lh540245 devices. when- ever the number of paralleled cascades exceeds two, a small amount of external logic is necessary to implement the interlocking. bold italic = enhanced operating mode LH540235/45 2048 x 18/4096 x 18 synchronous fifos 40
write clock write enable load data in full v cc reset v cc v cc v cc transfer clock read clock read enable data out hf wclk wen ld rs paf ff ef 2 fl rclk ren oe pae ef ren 2 wen 2 hf wclk wen ld rs paf ff ef 2 rclk ren pae ef ren 2 wen 2 hf wclk wen ld rs paf ff ef 2 rclk ren pae ef ren 2 wen 2 fl fl emode oe emode oe emode d[17:0] q[17:0] d[17:0] q[17:0] d[17:0] q[17:0] almost full almost empty empty output enable the transfer clock may be any free-running clock. however, it is recommended that the faster of the write clock and the read clock be used, if both of these are free-running clocks. 540235-30 18 18 18 18 bold italic = enhanced operating mode. notes: figure 29. ti-style pipelined depth-cascading 2048 x 18/4096 x 18 synchronous fifos LH540235/45 41
write clock write enable load v cc v cc transfer clock hf wclk wen ld rs paf ff ef 2 fl rclk ren oe pae ef ren 2 wen 2 hf wclk wen ld rs paf ff ef 2 rclk ren pae ef ren 2 wen 2 hf wclk wen ld rs paf ff ef 2 rclk ren pae ef ren 2 wen 2 fl fl emode oe emode oe emode reset v cc v cc hf wclk wen ld rs paf ff ef 2 fl rclk ren oe pae ef ren 2 wen 2 hf wclk wen ld rs paf ff ef 2 rclk ren pae ef ren 2 wen 2 hf wclk wen ld rs paf ff ef 2 rclk ren pae ef ren 2 wen 2 fl fl emode oe emode oe emode 540235-33 the transfer clock may be any free-running clock. however, it is recommended that the faster of the write clock and the read clock be used, if both of these are free-running clocks. 18 18 18 18 efc read enab le read clock 36 data out 18 ffc 36 18 18 18 d[17:0] q[17:0] d[17:0] q[17:0] d[17:0] q[17:0] d[17:0] q[17:0] d[17:0] q[17:0] d[17:0] q[17:0] data in bold italic = enhanced operating mode. notes: figure 30. interlocked paralleling used together with pipelined depth-cascading LH540235/45 2048 x 18/4096 x 18 synchronous fifos 42
package diagrams 25.27 [0.995] 25.02 [0.985] 24.23 [0.954] 24.13 [0.950] 24.23 [0.954] 24.13 [0.950] 25.27 [0.995] 25.02 [0.985] 23.62 [0.930] 22.61 [0.890] maximum limit minimum limit dimensions in mm [inches] 1.27 [0.050] bsc 0.53 [0.021] 0.33 [0.013] 0.051 [0.020] min 3.91 [0.154] 3.71 [0.146] 0.10 [0.004] 4.57 [0.180] 4.19 [0.165] 68plcc-1 68plcc (plcc68-p-950) 68-pin plcc 2048 x 18/4096 x 18 synchronous fifos LH540235/45 43
64tqfp dimensions in mm [inches] maximum limit minimum limit 0.20 [0.008] 0.09 [0.004] 0.15 [0.006] 0.05 [0.002] 16.0 [0.630] basic 14.0 [0.551] basic 0.45 [0.018] 0.30 [0.012] 1.45 [0.057] 1.35 [0.53] 1.60 [0.063] max. 0.80 [0.031] basic 14.0 [0.551] basic 16.0 [0.630] basic 0.75 [0.030] 0.45 [0.018] 0.10 [0.004] 64tqfp (tqfp-64-p-1414) detail 64-pin tqfp LH540235/45 2048 x 18/4096 x 18 synchronous fifos 44
ordering information 20 25 35 cycle time (ns) u 68-pin plastic leaded chip carrier (plcc68-p-s950) m 64-pin thin quad flat package LH540235/45 device type x package - ## speed 540235md 2048 x 18/4096 x 18 synchronous fifo example: lh540245u-20 (4096 x 18 sychronous fifo, 20 ns, 68-pin plcc) 2048 x 18/4096 x 18 synchronous fifos LH540235/45 45
bold italic = enhanced operating mode LH540235/45 2048 x 18/4096 x 18 synchronous fifos 46

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