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x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n march 2010 rev. 1.0.0 exar corporation www.exar.com 48720 kato road, fremont ca 94538, usa tel. +1 510 668-7000 ? fax. +1 510 668-7001 general description the XRP6142 is a synchronous step down switching controller for over 15 amps point-of- loads converters and optimized to generate and support ddr i, ii and iii memory voltages requirements. optimized to operate from standard 3.3v and 5v rails, the XRP6142 supports conversions down to 0.5v from an input voltage as low as 1v and can reach efficiencies of up to 96%. based on a constant on-time control scheme and operating at a constant switching frequency over the whole input voltage range, it provides excellent load transient response while requiring no external compensation components. three select able on-time options allow for further switching frequency, solution footprint and efficiency optimization. dedicated support for ddr i, ii and ii memories is also provided. the XRP6142 easily generates v ddq (v dd ) or v tt voltages while an on board buffer provides the buffered v tt reference voltage. under-voltage lock out, short-circuit and over-current and over-temperature protection insure safe operations under abnormal operating conditions. the XRP6142 is available in a compact rohs compliant ?green?/halogen free 16-pin qfn package. applications ? high-power point-of-loads converters ? audio-video equipments ? fpga and dsp power supplies ? ddr memory based embedded systems features ? over 15a point-of-load capable ? down to 0.5v output voltage conversion ? up to 96% efficiency ? wide 1.0v-5.5v input voltage range conversions ? single input 3.3v and 5v rails operations ? constant on-time operations ? constant frequency operations ? no external compensation ? ddr i, ii & iii termination support ? v ddq /v dd or v tt voltages generation ? buffered v tt ref. voltage generation ? soft-start and enable functions ? uvlo, short circuit and over current protection ? rohs compliant ?green?/halogen free 3mm x 3mm 16-pin qfn package typical application diagram figure. 1: XRP6142 as a step-down converter or a ddr supply agnd v in v out r1 r2 l1 pgnd v cc en v ref refin v in bst fb thermal pad vttref vddq/2 sw ilim gl cs gnd gh XRP6142 cff c out qb qt c in 3v-5.5v sp2996b vtt v in gnd acntl ref en vout vddq vref operation as ddr supply r3 r4 rlim
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 2 of 17 rev. 1.0.0 absolute maximum ratings these are stress ratings only, and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v cc ...................................................................... 7.0v v in ....................................................................... 7.0v bst .................................................................... 13.5v sw ............................................................. -1v to 7.0v bst-sw ...................................................... -0.3v to 6v all other pins ..................................... -0.3v to v cc +0.3v storage temperatur e .............................. - 65c to 150c power dissipat ion ................................ internal ly limited lead temperature (sol dering, 10 se c) ................... 300c esd rating (hbm - huma n body mode l) .................... 2kv esd rating (mm - machine model) ........................... 500v operating ratings input voltage range v cc .............................. 3.0v to 5.5v input voltage range v in ............................... 1.0v to 5.5v junction temperature range .................... -40c to 125c thermal resistance ja ................................... 33.3c/w electrical specifications specifications are for an operat ing junction temperature of t j = 25c; limits applying over the full operating junction temperature range are denoted by a ???. minimum and maximum limits are guaranteed through test, design, or statistical correlation. typical values represent th e most likely parametric norm at t j = 25c, and are provided for reference purposes only. unless otherwise indicated, v cc = v in = 3.3v. parameter min. typ. max. units conditions v ref , reference voltage 0.495 0.5 0.505 v 0.492 0.5 0.508 v ? v fb offset 7 mv v refin = v ref v refin , voltage range vref 1.3 v v ddq/2 , input impedance 60 m ? v ttref , output error -1.25 +1.25 % ? v ddq/2 = 0.75v, i vttr =0ma v ttref current limit 20 40 65 ma ? sourcing: v ttref =0, v ddq/2 =v ref sinking: v ttref =2v i q , operating quiescent current 400 600 a not switching, v fb =v refin +0.1v i off , shutdown current 0.1 a en=0v t on , switch on-time 0.4 0.5 0.6 s ? xr6142el0-5-f (t on =500ns) 0.8 1.0 1.2 ? xr6142el1-0-f (t on =1000ns) 1.6 2.0 2.4 ? xr6142el2-0-f (t on =2000ns) t off_min , minimum off-time 300 400 ns ? all t on options t d , gate drive dead-time 50 ns v ih_en , en pin rising threshold 1.15 1.2 1.25 v ? v en_hys , en pin hysteresis 50 200 mv i fb , feedback pin bias current 50 na v fb =2.0v v ccuvlo , under-voltage lockout 2.8 3.0 v ? v cc rising edge v ccuvlo_hys , under-voltage lock out hysteresis 500 mv v sc_th , feedback pin short circuit latch threshold 55 65 75 % ? % of vrefin ilim pin source current 42.5 50 57.5 a ilim current temperature coefficient 0.3 %/c v ilim current limit trip level -20 0 +20 mv ? current limit blanking 130 ns gl rising > 1.0v
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 3 of 17 rev. 1.0.0 parameter min. typ. max. units conditions hiccup timeout 110 ms 0.5 s, 1 s and 2 s option, v out =1v soft start time 3 5 10 ms r ds(on)1 , gh fet driver pull-up on resistance 2.5 ? i gh =20 ma r ds(on)2 , gh fet driver pull-down on resistance 2 ? i gh =20 ma r ds(on)3 , gl fet driver pull-up on resistance 2.5 ? i gl =20 ma r ds(on)4 , gl fet driver pull-down on resistance 2 ? i gl =20 ma block diagram figure. 2: XRP6142 block diagram
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 4 of 17 rev. 1.0.0 pin assignment figure. 3: XRP6142 pin assignment pin description name pin number description agnd 1 analog ground vttref 2 buffered output of vddq/2 v tt reference voltage for ddr applications. vddq/2 3 buffer input voltage. voltage used for the input to the v ttref buffer v ref 4 precision reference output refin 5 reference input to the switching-regulator feedback comparator fb 6 feedback input to feedback comparator csgnd 7 current-sense ground ilim 8 connect a resistor between this pin and the low-side current-sense element in order to set the current-limit-trip threshold. see applications section for instructions on how to set this resistor pgnd 9 gate driver gnd. gl 10 low-side n-channel mosfet driver sw 11 switch node for floating-high-side gate drive gh 12 high-side n-channel mosfet driver bst 13 bootstrap capacitor to drive the high-side gate driver, gh v in 14 input voltage for the power train vcc 15 input voltage for the XRP6142 internal circuitry and gate drives. v in and v cc can be tied together when v in 3.0v en 16 precision enable pin. pulling this pin above 1.2v will turn the part on thermal pad - internally connected to agnd
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 5 of 17 rev. 1.0.0 ordering information part number temperature range marking package packing quantity note 1 note 2 XRP6142el0-5-f -40c t j +125c 6142e yyww05 x 16-pin qfn bulk rohs compliant halogen free 0.5s on time XRP6142eltr0-5-f -40c t j +125c 6142e yyww05 x 16-pin qfn 3k/tape & reel rohs compliant halogen free 0.5s on time XRP6142el1-0-f -40c t j +125c 6142e yyww10 x 16-pin qfn bulk rohs compliant halogen free 1.0s on time XRP6142eltr1-0-f -40c t j +125c 6142e yyww10 x 16-pin qfn 3k/tape & reel rohs compliant halogen free 1.0s on time XRP6142el2-0-f -40c t j +125c 6142e yyww20 x 16-pin qfn bulk rohs compliant halogen free 2.0s on time XRP6142eltr2-0-f -40c t j +125c 6142e yyww20 x 16-pin qfn 3k/tape & reel rohs compliant halogen free 2.0s on time XRP6142evb XRP6142 evaluation board ? XRP6142el2-0-f based ?yy? = year ? ?ww? = work week ? ?x? = lot number
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 6 of 17 rev. 1.0.0 typical performance characteristics all data taken at v in = 3v to 5.5v, t j = t a = 25c, unless otherwise specified - schematic and bom from application information section of this datasheet. fig. 4: t on versus v in fig. 5: t on versus v in fig. 6: efficiency versus i out fig. 7: load regulation fig. 8: line regulation fig. 9: frequency versus i out 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 123456 v in (v) t on ( s) v cc =5v i o =0a 0.2 0.4 0.6 0.8 1.0 1.2 123456 v in (v) t on ( s) v cc =5v i o =0a 80 85 90 95 100 0 5 10 15 20 i out (a) efficiency (%) v in =v cc =5v v out =2.5v 2.480 2.490 2.500 2.510 2.520 0 5 10 15 20 i out (a) v out (v) v in =v cc =5v 2.450 2.475 2.500 2.525 2.550 3.5 4.0 4.5 5.0 5.5 v in (v) v out (v) io=0a io=10a v cc =5v 300 350 400 450 500 0 5 10 15 20 i out (a) f (khz) v in =v cc =5v XRP6142el2.0-f XRP6142el2.0-f XRP6142el2.0-f XRP6142el2.0-f XRP6142el2.0-f XRP6142el1.0-f XRP6142el0.5-f
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 7 of 17 rev. 1.0.0 fig. 10: frequency versus v in fig. 11: iocp versus rlim fig. 12: power-up into a 15a load, v in =5v, v out =2.5v fig. 13: power-down from a 15a load, v in =5v, v out =2.5v fig. 14: steady state, output ripple is 30mv p-p, v out =2.5v fig. 15: transient response, 250mv p-p, 15a load step 300 350 400 450 500 3.54.04.55.05.5 v in (v) f (khz) v cc =5v i out =15a 0 5 10 15 20 25 0.8 1.2 1.6 2.0 rlim (k ) iocp (a) tested iocp calculated iocp XRP6142el2.0-f XRP6142el2.0-f XRP6142el2.0-f XRP6142el2.0-f XRP6142el2.0-f XRP6142el2.0-f v in 5v/div v out 2v/div v sw 5v/div i out 2v/div v in 5v/div v out 2v/div v sw 5v/div i out 2v/div 2ms/div 2ms/div 2 s/div 100 s/div v sw 5v/div v out 20mv/div ac coupled i l 10a/div i out 10a/div v out 100mv/div ac coupled
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 8 of 17 rev. 1.0.0 theory of operation the XRP6142 synchronous buck controller utilizes the constant-on-time principle. the on- time is internally set and is available in three different set points to allow for different frequency options. the XRP6142 automatically adjusts the on-time during operation inversely with the input voltage v in , to maintain a constant frequency. th erefore, the switching frequency is independent of the inductor and capacitor size, unlike hysteretic controllers. at the beginning of the cycle, the XRP6142 turns on the high-side fet for a fixed duration. the on time is internally set and adjusted by v in . at the end of the on time, the high-side fet is turned off, for a predetermined minimum off time (nom inally 300ns). after t off-min has expired, the high-side fet will stay off until the feedback comparator trip point of 0.5v has been reached. then the high-side fet turns on again and the cycle repeats. the operation of the low-side fet is complementary to the high-side fet. a short dead-time prevents shoot-through from occurring. t iming o ptions three versions of XRP6142 (timing options) are identified by their on times at v in =3.3v. for each version, t on is inversely proportional to v in . the constant of proportionality k, is shown in the table below. variation of t on versus v in is shown graphically in figures 4 and 5. part number t on at v in =3.3v k=t on xv in ( s.v) XRP6142el0.5-f 0.5 s 1.65 XRP6142el1.0-f 1.0 s 3.3 XRP6142el2.0-f 2.0 s 6.6 note that for a buck converter the switching frequency is given by: on in out t v v f = since for each xrp61 42 timing option, the product of v in and t on is a constant, then frequency is determined by v out as shown in the following table. v out f(khz) for each timing option 0.5 s 1.0 s 2.0 s 0.8 485 242 121 1.0 606 303 152 1.2 727 364 182 1.5 909 455 227 1.8 1091 545 273 2.5 --- 758 379 3.3 --- --- 500 i nternal s oft -s tart soft-start time is internally set at 5ms (nominal). this removes the need for external components associated with soft-start function, and helps save cost and reduce pcb space. e nable a precision enable function is provided (1.20v 0.05v). en should be tied to v cc in applications that do not require this function. i nternal r eference v oltage a high-precision 0.5v internal reference is provided at the v ref pin. this is normally tied to the refin pin, thus setting the threshold of the voltage comparator. i nternal b ootstrap d iode XRP6142 includes an inte rnal low-vf bootstrap diode. place a 0.1uf capacitor between bst and sw pins to provide drive voltage for the high-side fet. u nder -v oltage l ockout uvlo monitors v cc and ensures adequate voltage exists before starting to switch the fets. s hort c ircuit p rotection an internal short-circui t comparator monitors the feedback voltage. if feedback voltage falls below 65% of reference voltage (this is equivalent to output voltage falling below 65% of nominal value) the ic will latch off. v cc has
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 9 of 17 rev. 1.0.0 to be recycled in order for ic to resume operation. o vercurrent p rotection (ocp) ocp function is implemented by monitoring the voltage across the low- side fet when it is on. ocp is programmed via a resistor rlim connected between ilim and sw pins. an internal constant-current source ilim (50ua nominal) establishes a voltage across rlim. this voltage sets the trip point of the ocp comparator. if the ocp comparator is triggered for eight consecutive switching cycles, then a hiccup timeout, as described in the next section, is initiated. calculate rlim from: a mv r il iocp rlim on ds 5 . 42 20 2 ) ( + ? ? ? ? ? ? ? ? ? ? ? ? + = where: iocp is the output current at which overcurrent protection is activated (usually set 20% above maximum i out ) ? il is inductor current ripple nominally set at 30% of i out r ds(on) is the maximum rated on resistance of the fet 20mv is the ocp comparator offset spec 42.5 a is the minimum spec of the ilim source the actual iocp is 50% to 100% higher than expected iocp as seen in figure 11. this is because rlim in the above equation is calculated based on worst case parameters. a temperature coefficient of 0.3%/c has been designed into ilim. this useful feature nulls out the positive temperature coefficient of the fet r ds(on) to a first order. thus iocp should be largely independent of operating temperature. h iccup t imeout when an over current condition is detected, the internal fet drivers are turned off for 110ms, following which, a soft-start is attempted. if the ocp condition is still present, then the timeout and soft-start cycle repeat. this is referred to as hiccup timeout. p rogramming v out a pair of output resistors is used to set the output voltage v out . calculate r1 from: ? ? ? ? ? ? ? ? ? = 1 2 1 ref out v v r r where: r2 is nominally set at 10k (bottom resistor) v ref is reference voltage (0.5v) note that v out must contain some voltage ripple in order for XRP6142 to regulate the output. since XRP6142 regulates the bottom of the output ripple the average value will be higher (see figure 16). fig. 16: v out voltage ripple v out can be programmed more precisely from: () ? ? ? ? ? ? ? ? ? ? = 1 , 5 . 0 2 1 ref out out v ripple v v r r where: esr il ripple v out = , esr is the output capacitor?s equivalent series resistance. o utput c apacitor c out is the most critical component for proper operation, since the XRP6142 relies on v out
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 10 of 17 rev. 1.0.0 voltage ripple for regulating the output. to ensure stable operation two constraints must be met: first the c out must have sufficient esr in order to get enough voltage ripple at feedback pin. it is recommended that XRP6142 be operated with at least 25mv ripple at feedback pin. assuming majority of output voltage ripple is from esr, we get: il mv esr 25 ????. (1) where ? il is inductor current ripple nominally set at 30% of i out . note that v out ripple, is attenuated by the resistor divider r1/r2, and a smaller ripple is seen at fb pin. for example if v out ripple is 25mv and r1=r2=10k, then the voltage ripple at fb is only 12.5mv. one solution to this problem is to increase the output ripple accordingly, such that ripple at fb is 25mv. a more desirable solution is to provide a high- frequency/low-impedance path for the output ripple to be transmitted to fb without attenuation. this can be done by placing a small feed-forward capacitor cff in parallel with r1. as a starting point calculate cff from: fs r cff = 1 2 10 where fs is the switching frequency in general, a cff of 1nf should provide satisfactory feed-forward for most applications based on the XRP6142. the second constraint for stability establishes a relation between esr and c out . out c ton esr ????. (2) once esr is calculated from equation (1), equation (2) can be used to calculate c out . the aforementioned are in addition to the usual requirements for c out for a buck converter. the usual constraint in order to meet load step transient requirement is given by: 2 2 2 1 2 2 out out v vos i i c ? ? where: i 2 is load step high-level current i 1 is load step low-level current v out is output voltage including transient (nominally this is set 3% higher than v out ) in general, the best capacitors are the ones with known and consistent esr across operating temperature range. examples include poscaps, tantalums and certain aluminum electrolytics. o utput i nductor select the output inductor for inductance and current rating. as a rule of thumb the dc current rating and saturation current should be at least 50% higher than maximum output current. calculate the inductance from: () fs il d v v l out in ? = where: d is duty cycle fs is switching frequency ? il is inductor current ripple nominally set at 30% of i out . i nput c apacitor select the input capacitor for capacitance, voltage rating and rms current rating. as a rule of thumb, the voltage rating should be twice the maximum input voltage of the converter. rms current rating can be approximated from: () d d i i out rms ? = 1 calculate c in such that input voltage ripple does not exceed 2% of v in . ceramic input capacitors are recommended. this choice minimizes input voltage ripple due to esl and esr. thus a simplified expression for c in can be written:
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 11 of 17 rev. 1.0.0 () 2 , 02 . 0 in in out in out max out in v v fs v v v i c ? = s ynchronous fet (l ow - side fet) select the synchronous fet for voltage rating bv dss , on resistance rating r ds(on) and gate drive rating v gs . as a rule of thumb, voltage rating should be at least twice the converter input voltage. fets with voltage rating of up to 30v should provide satisfactory performance. drive voltage of 4.5v is sufficient for applications with minimum input voltage of 4.5v. for applications with a lower input voltage a fet with 2.5v gate drive should be selected. switching losses of the synchronous fet are negligible in comparison to its conduction losses. r ds(on) is calculated based on conduction losses from: () 2 ) ( 1 out conduction on ds i d p r ? it is common practice to allocate 50% of the total fet losses to the synchronous fet. as an example, consider a 10w buck converter with a target efficiency of 90%. therefore, the target total power loss is 1.1w. assume that the only significant non-fet loss is the inductor loss estimated at 0.1w. thus the maximum conduction loss of the synchronous fet should not exceed 0.5w. by using this value in the above equation r ds(on) can be calculated and a suitable fet selected. s witching fet (h igh - side fet) select the switching fet for voltage rating bv dss , on-resistance rating r ds(on) , gate drive rating v gs , rise time t r and fall time t f . bv dss and v gs selection guidelines are the same as synchronous fet. the switching fet incurs switching (i.e., transitional) as well as conduction losses. r ds(on) is calculated based on conduction losses from: 2 ) ( out conduction on ds i d p r it is common practice to allocate 50% of the total high-side fet losses to conduction. proceeding with the example from previous section the total target loss is 0.5w, and thus target conduction loss equals 0.25w. by using this value in the above equation r ds(on) can be calculated. rise and fall time can be approximated from: s out in switching f r f i v p t t = + since the allotted switching loss budget is 0.25w, t r and t f can be calculated from the above equation. for a detailed explanat ion of fet losses and fet selection procedure refer to exar application note anp-20. r-c s nubber (o ptional ) an r-c snubber placed across the synchronous fet eliminates the ringing and reduces the amplitude of overshoot at sw node. use surface-mount componen ts and place them close to the fet drain-source. calculate the value of snubber capacitor csnb from: coss csnb = 3 coss is the output capacitance of the synchronous fet corresponding to v in . calculate the value of the snubber resistor rsnb from: out out i v rsnb = 2 ddr memory power applications XRP6142 can be used to generate the required v ddq (v dd ) or v tt reference voltages for ddr i, ii and iii memories and provides a 40ma buffered v tt reference voltage. when used in conjunction with exar ?s sp2996 ddr memory termination, the XRP6142 provides a complete ddr power management solution. a cost- effective ddr2 solution is shown on page 15. XRP6142 provides the vddq and vttref voltages. sp2996 provides the vtt voltage. please note that the current output of vddq can be increased up to 10a by using a larger qt/qb mosfet and scaling the l1 and c3 accordingly.
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 12 of 17 rev. 1.0.0 pcb l ayout g uidelines the following guidelines will help attain stable operation and reduce jitter: 1- place all the power components; c in , qt, qb, l1 and c out on the same side of the board if possible. 2- make the loop between c in , qt and qb as small as possible and use low- impedance traces. 3- make the loop between qb, l1 and c out as small as possible and use low- impedance traces. 4- place the source of qt, drain of qb and input connection of l1 as close as possible and use low-impedance traces. 5- use a short trace and connect agnd to the thermal pad. this forms the signal ground. 6- use a short trace and connect pgnd to agnd. 7- use a low-impedance trace and connect the pgnd pin to the c out . 8- place cff, r1 and r2 close to the ic, and connect r2 to signal ground. use a short trace and connect r1 to c out . 9- bypass the v cc pin to signal ground with a ceramic capacitor(s) as close to the ic as possible. connect the v cc pin to v in or an independent v cc source through a 10 resistor. this will help filter out noise from v cc .
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 13 of 17 rev. 1.0.0 design examples 5v s tep -d own c onverter note: the data shown in figures 6 trough 15 was collected using this circuit. c5 220uf gnd vin=4.5v-5.5v gnd vout=2.5v, 0-15a u1 XRP6142el2.0-f agnd 1 vttref 2 vddq/2 3 vref 4 refin 5 fb 6 csgnd 7 ilim 8 pgnd 9 gl 10 sw 11 gh 12 bst 13 vin 14 vcc 15 en 16 t. pad qb vishay si4164dy 8 7 6 5 4 1 2 3 l1, wurth elektronik 0.82uh, 27a, 0.9 mohm 1 2 rlim 2.2k cvcc1 0.1uf c1-c3 ceramic, 10v c5-c6 sany o poscap 6tpe220mi, 6.3v, 18mohm snubber components are optional cff 1nf csnb 3.9nf rsnb 0.2 ohm rvcc 10 ohm qt vishay si4164dy 8 7 6 5 4 1 2 3 c6 220uf c1 47uf c2 47uf c3 47uf cbst 0.1uf c4 0.1uf cvcc 4.7uf r1 39.2k (1%) r2 10k (1%)
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 14 of 17 rev. 1.0.0 3.3v s tep -d own c onverter snubber components are optional c5 220uf gnd t poi n t s gnd t poi n t s vin=3v-3.6v t poi n t s vout=1.2v, 0-10a t poi n t s u1 XRP6142el1.0-f agnd 1 vttref 2 vddq/2 3 vref 4 refin 5 fb 6 csgnd 7 ilim 8 pgnd 9 gl 10 sw 11 gh 12 bst 13 vin 14 vcc 15 en 16 t. pad qb fairchild fds6570 8 7 6 5 4 1 2 3 l1, wurth elektronik1 0.72uh, 22a, 1.65 mohm 1 2 rlim 3.65k cvcc1 0.1uf c5-c6 sany o poscap 6tpe220mi, 6.3v, 18mohm c1-c3 ceramic, 10v cff 1nf csnb 3.9nf rsnb 0.2 ohm rvcc 10 ohm qt fairchild fds6570 8 7 6 5 4 1 2 3 c6 220uf c1 47uf c2 47uf c3 47uf cbst 0.1uf c4 0.1uf cvcc 4.7uf r1 14k (1%) r2 10k (1%)
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 15 of 17 rev. 1.0.0 ddr2 memory solution qb vishay , si2312bds 1 2 3 vref c4 47uf, ceramic, 6.3v r3 10k (1%) r4 10k (1%) c5 1uf c3 150uf gnd gnd vin=3.3v or 5v vddq=1.8v, 0-3a u1 XRP6142el1.0-f agnd 1 vttref 2 vddq/2 3 vref 4 refin 5 fb 6 csgnd 7 ilim 8 pgnd 9 gl 10 sw 11 gh 12 bst 13 vin 14 vcc 15 en 16 t. pad l1, vishay ihlp-2525cz 1.5uh, 9a, 15 mohm 1 2 rlim 3.65k cvcc 1uf c3 sany o poscap 4tpe150mazb, 4v, 35mohm cff 1nf rvcc 10 ohm qt vishay , si2312bds 1 2 3 c1 47uf, ceramic, 10v cbst 0.1uf c2 0.1uf r1 25.5k (1%) r2 10k (1%) q1 ces7002a vref/vtt enable vtt=0.9v, 1a peak, 0.5adc u2 sp2996b vcntl 8 vcntl 7 vout 4 vcntl 5 gnd 2 refen 3 vin 1 vcntl 6
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 16 of 17 rev. 1.0.0 package specification 16-p in qfn
x x r r p p 6 6 1 1 4 4 2 2 s s y y n n c c h h r r o o n n o o u u s s s s t t e e p p - - d d o o w w n n c c o o n n t t r r o o l l l l e e r r w w i i t t h h d d d d r r m m e e m m o o r r y y t t e e r r m m i i n n a a t t i i o o n n ? 2010 exar corporation page 17 of 17 rev. 1.0.0 revision history revision date description 1.0.0 03/24/2010 initial release of datasheet for further assistance email: customersupport@exar.com exar technical documentation: http://www.exar.com/techdoc/default.aspx? e xar c orporation h eadquarters and s ales o ffices 48720 kato road fremont, ca 94538 ? usa tel.: +1 (510) 668-7000 fax: +1 (510) 668-7030 www.exar.com notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and make s no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustr ation purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the us e of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause fa ilure of the life support system or to significantly affect it s safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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