; even- or odd-number ed parity by uartcr1) are added to the transfer data. the transfer data formats are shown as follows. figure 14-2 tran sfer data format figure 14-3 caution on c hanging transfer data format note: in order to switch the transfer data format, perfor m transmit operations in the above figure 14-3 sequence except for the initial setting. start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit
page 139 TMP86CS64AFG 14.4 infrared (irda) da ta format transfer mode infrared data format (irda) output is available by se tting irda output control register (irdacr) through txd1 pin. figure 14-4 example of infrared data format (compariso n of normal outpu t and irda output) irda output control register irdacr (001ah) 76543210 irda sel (initial value: **** ***0) irdasel irda output / uart output select 0: 1: uart output irda output r/w uart output irda output start bit stop bit d0 d1 d2 d7 3/16 bit width
page 140 14. asynchronous serial interface (uart ) 14.5 transfer rate TMP86CS64AFG 14.5 transfer rate the baud rate of uart is set of uartcr1. th e example of the baud rate are shown as follows. when tc4 is used as the uart transfer rate (when uartcr1 = ?110?), the tr ansfer clock and transfer rate are determined as follows: transfer clock [hz] = tc4 source clock [hz] / ttreg4 setting value transfer rate [baud] = transfer clock [hz] / 16 14.6 data sampling method the uart receiver keeps sampling input using the cloc k selected by uartcr1 until a start bit is detected in rxd1 pin input. rt clock starts detecting ?l? level of the rxd1 pin. once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sample d at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to major- ity rule (the data are the same tw ice or more out of three samplings). figure 14-5 data sampling method table 14-1 transfer rate (example) brg source clock 16 mhz 8 mhz 4 mhz 000 76800 [baud] 38400 [baud] 19200 [baud] 001 38400 19200 9600 010 19200 9600 4800 011 9600 4800 2400 100 4800 2400 1200 101 2400 1200 600 rt0 1 2 3 4 5 6 7 8 9101112 1314 15  01234567891011 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9101112 1314 15  01234567891011 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd1 pin rxd1 pin
page 141 TMP86CS64AFG 14.7 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcr1. 14.8 parity set parity / no parity by uartcr1 and set parity type (odd- or even-numbered) by uartcr1. 14.9 transmit/receive operation 14.9.1 data transmit operation set uartcr1 to ?1?. read uartsr to check ua rtsr = ?1?, then write data in tdbuf (transmit data buffer). writing data in tdbuf zero-cl ears uartsr, transfers the data to the transmit shift register and the data are sequentially output from the txd1 pin. the data output include a one-bit start bit, stop bits whose number is specified in uartcr1 and a parity bit if pari ty addition is specified. select the data transfer baud rate using uartcr1. when data transmit st arts, transmit buffer empty flag uartsr is set to ?1? a nd an inttrx interrupt is generated. while uartcr1 = ?0? and from when ?1? is written to uartcr1 to when send data are written to tdbuf, the txd1 pin is fixed at high level. when transmitting data, first read uartsr, then write data in tdbuf. otherwise, uartsr is not zero-cleared and transm it does not start. 14.9.2 data receive operation set uartcr1 to ?1?. when data are received via the rxd1 pin, the receive data are transferred to rdbuf (receive data buffer). at this time, the data transmitted includes a start bit and stop bit(s) and a parity bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rdbuf (receive data buffer). then the receive buffer full flag uartsr is set and an inttrx inter- rupt is generated. select the data transfer baud rate using uartcr1. if an overrun error (oerr) occurs when data are received, the da ta are not transferre d to rdbuf (receive data buffer) but discarded; data in the rdbuf are not affected. note:when a receive operation is disabled by setting ua rtcr1 bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs , be sure to perform a re-receive operation.
page 142 14. asynchronous serial interface (uart ) 14.10 status flag TMP86CS64AFG 14.10status flag 14.10.1parity error when parity determined using the receive data bits diff ers from the received parity bit, the parity error flag uartsr is set to ?1?. the uartsr is cl eared to ?0? when the rdbuf is read after read- ing the uartsr. figure 14-6 generati on of parity error 14.10.2framing error when ?0? is sampled as the stop bit in the receive data, framing error flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the rdbuf is r ead after reading the uartsr. figure 14-7 generati on of framing error 14.10.3overrun error when all bits in the next data are received while unread data are still in rdbuf, overrun error flag uartsr is set to ?1?. in this case, the receive data is discarded; data in rdbuf are not affected. the uartsr is cleared to ?0? when the rdbuf is read af ter reading the uartsr. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd1 pin uartsr inttrx interrupt after reading uartsr then rdbuf clears perr. final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd1 pin uartsr inttrx interrupt after reading uartsr then rdbuf clears ferr.
page 143 TMP86CS64AFG figure 14-8 generati on of overrun error note:receive operations are di sabled until the overrun error flag uartsr is cleared. 14.10.4receive data buffer full loading the received data in rdbuf sets receive data buffer full flag uartsr to "1". the uartsr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 14-9 generat ion of receive data buffer full note:if the overrun error flag uartsr is set during the period between reading the uartsr and reading the rdbuf, it cannot be cleared by only reading the rdbuf. therefore, after reading the rdbuf, read the uartsr again to check whether or not the overrun er ror flag which should have been cleared still remains set. 14.10.5transmit data buffer empty when no data is in the transmit buffer tdbuf, uartsr is set to ?1?, that is, when data in tdbuf are transferred to the transmit shif t register and data transmit star ts, transmit data buffer empty flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the tdbuf is written after reading the uartsr. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd1 pin uartsr inttrx interrupt after reading uartsr then rdbuf clears oerr. rdbuf uartsr final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd1 pin uartsr inttrx interrupt rdbuf after reading uartsr then rdbuf clears rbfl.
page 144 14. asynchronous serial interface (uart ) 14.10 status flag TMP86CS64AFG figure 14-10 generation of tr ansmit data buffer empty 14.10.6transmit end flag when data are transmitted and no data is in tdbuf (uartsr = ?1?), transmit end flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the data transmit is stated after writing the tdbuf. figure 14-11 generation of transmit end flag and trans mit data buffer empty shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 tdbuf txd1 pin uartsr inttrx interrupt after reading uartsr writing tdbuf clears tbep. shift register * 1yyyy *** 1 xx **** 1 x ***** 1 stop start 1yyyy0 bit 0 txd1 pin uartsr uartsr inttrx interrupt data write for tdbuf
page 145 TMP86CS64AFG 15. synchronous serial interface (sio1) the TMP86CS64AFG has a clocked-synchronous 8-bit serial interface. serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. serial interface is connected to outside peri pherl devices via so1, si1, sck1 port. 15.1 configuration figure 15-1 serial interface sio control / status register serial clock shift clock shift register 3 2 1 0 7 6 5 4 transmit and receive data buffer (8 bytes in dbr) control circuit cpu serial data output serial data input 8-bit transfer 4-bit transfer serial clock i/o buffer control circuit so1 si1 sck 1 sio1cr2 sio1cr1 sio1sr intsio1 interrupt request
page 146 15. synchronous serial interface (sio1) 15.2 control TMP86CS64AFG 15.2 control the serial interface is controlled by sio control registers (sio1cr1/sio1cr2 ). the serial interface status can be determined by reading sio status register (sio1sr). the transmit and receive data buffer is controlled by th e sio1cr2. the data buff er is assigned to address 0f90h to 0f97h for sio in the dbr area, and can continuously transfer up to 8 words (bytes or nibbles) at one time. when the specified number of words has b een transferred, a buffer empty (in th e transmit mode) or a buffer full (in the receive mode or tran smit/receive mode) interrupt (intsio1) is generated. when the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a fixed interval wait can be applied to the serial clock fo r each word transferred. four different wait times can be selected with sio1cr2. note 1: fc; high-frequency clock [hz], fs; low-frequency clock [hz] note 2: set sios to "0" and sioinh to "1" when setting the transfer mode or serial clock. note 3: sio1cr1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. sio control register 1 sio1cr176543210 (0028h) sios sioinh siom sck (initial value: 0000 0000) sios indicate transfer start / stop 0: stop write only 1: start sioinh continue / abort transfer 0: continuously transfer 1: abort transfer (automatically cleared after abort) siom transfer mode select 000: 8-bit transmit mode 010: 4-bit transmit mode 100: 8-bit transmit / receive mode 101: 8-bit receive mode 110: 4-bit receive mode except the above: reserved sck serial clock select normal1/2, idle1/2 mode slow1/2 sleep1/2 mode write only dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 1 dv1ck = 1 000 fc/2 13 fc/2 14 fs/2 5 fs/2 5 fs/2 5 001 fc/2 8 fc/2 9 fc/2 8 fc/2 9 - 010 fc/2 7 fc/2 8 fc/2 7 fc/2 8 - 011 fc/2 6 fc/2 7 fc/2 6 fc/2 7 - 100 fc/2 5 fc/2 6 fc/2 5 fc/2 6 - 101 fc/2 4 fc/2 5 fc/2 4 fc/2 5 - 110 reserved 111 external clock (input from sck1 pin ) sio control register 2 sio1cr276543210 (0029h) wait buf (initial value: ***0 0000)
page 147 TMP86CS64AFG note 1: the lower 4 bits of each buffer are used during 4-bit tr ansfers. zeros (0) are stored to the upper 4bits when receiving. note 2: transmitting starts at the lowest address. received data are also stored starting from the lowest address to the highest address. ( the first buffer address transmitted is 0f90h ). note 3: the value to be loaded to buf is held after transfer is completed. note 4: sio1cr2 must be set when the serial interface is stopped (siof = 0). note 5: *: don't care note 6: sio1cr2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. note 1: t f ; frame time, t d ; data transfer time note 2: after sios is cleared to "0", siof is cleared to "0" at the termination of transfer or the setting of sioinh to "1". figure 15-2 fr ame time (t f ) and data transfer time (t d ) 15.3 serial clock 15.3.1 clock source internal clock or external clock for the source clock is selected by sio1cr1. wait wait control always sets "00" except 8-bit transmit / receive mode. write only 00: t f = t d (non wait) 01: t f = 2t d (wait) 10: t f = 4t d (wait) 11: t f = 8t d (wait) buf number of transfer words (buffer address in use) 000: 1 word transfer 0f90h 001: 2 words transfer 0f90h ~ 0f91h 010: 3 words transfer 0f90h ~ 0f92h 011: 4 words transfer 0f90h ~ 0f93h 100: 5 words transfer 0f90h ~ 0f94h 101: 6 words transfer 0f90h ~ 0f95h 110: 7 words transfer 0f90h ~ 0f96h 111: 8 words transfer 0f90h ~ 0f97h sio status register sio1sr76543210 (0029h) siof sef siof serial transfer operating status moni- tor 0: 1: transfer terminated transfer in process read only sef shift operating status monitor 0: 1: shift operation terminated shift operation in process td tf (output) s ck1 output
page 148 15. synchronous serial interface (sio1) 15.3 serial clock TMP86CS64AFG 15.3.1.1 internal clock any of six frequencies can be selected. the serial clock is output to the outside on the sck1 pin. the sck1 pin goes high when transfer starts. when data writing (in the transmit mo de) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wa it function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. note: 1 kbit = 1024 bit (fc = 16 mhz, fs = 32.768 khz) figure 15-3 automatic wait fu nction (at 4-bit transmit mode) 15.3.1.2 external clock an external clock connected to the sck 1 pin is used as the serial clock. in this case, output latch of this port should be set to "1". to ensure shifting, a pulse width of at least 4 machine cycles is required. this pulse is needed for the shift operatio n to execute certainly. actually, there is necessary processing time for interrupting, writing, and reading. the minimum pulse is determined by setting the mode and the pro- gram. therfore, maximum transfer frequenc y will be 488.3k bit/sec (at fc=16mhz). table 15-1 serial clock rate normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 sck clock baud rate clock baud rate clock baud rate clock baud rate clock baud rate 000 fc/2 13 1.91 kbps fc/2 14 0.95 kbps fs/2 5 1024 bps fs/2 5 1024 bps fs/2 5 1024 bps 001 fc/2 8 61.04 kbps fc/2 9 30.52 kbps fc/2 8 61.04 kbps fc/2 9 30.52 kbps -- 010 fc/2 7 122.07 kbps fc/2 8 61.04 kbps fc/2 7 122.07 kbps fc/2 8 61.04 kbps -- 011 fc/2 6 244.14 kbps fc/2 7 122.07 kbps fc/2 6 244.14 kbps fc/2 7 122.07 kbps -- 100 fc/2 5 488.28 kbps fc/2 6 244.14 kbps fc/2 5 488.28 kbps fc/2 6 244.14 kbps -- 101 fc/2 4 976.56 kbps fc/2 5 488.28 kbps fc/2 4 976.56 kbps fc/2 5 488.28 kbps -- 110---------- 111 external external external external external external external external external external a 1 a 2 b 0 b 1 b 2 b 3 c 0 c 1 a 3 a c b a 0 pin (output) pin (output) written transmit data a utomat i ca ll y wait function sck1 so1
page 149 TMP86CS64AFG figure 15-4 external clock pulse width 15.3.2 shift edge the leading edge is used to transmit, a nd the trailing edge is used to receive. 15.3.2.1 leading edge transmitted data are shifted on the leading edge of the serial clock (falling edge of the sck 1 pin input/ output). 15.3.2.2 trailing edge received data are shifted on th e trailing edge of the serial clock (rising edge of the sck 1 pin input/out- put). figure 15-5 shift edge 15.4 number of bits to transfer either 4-bit or 8-bit serial transfer can be selected. when 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer re gister are used. the upper 4 bits are cleared to ?0? when receiving. the data is transferred in sequence star ting at the least significant bit (lsb). 15.5 number of w ords to transfer up to 8 words consisting of 4 bits of data (4-bit serial tran sfer) or 8 bits (8-bit serial tr ansfer) of data can be trans- ferred continuously. the number of words to be transferred can be selected by sio1cr2. t sckl t sckh tcyc = 4/fc (in the normal1/2, idle1/2 modes) 4/fs (in the slow1/2, sleep1/2 modes) t sckl , t sckh > 4tcyc sck1 pin (output) bit 1 bit 2 bit 3 * 321 3210 ** 32 *** 3 bit 0 shift register shift register bit 1 bit 0 bit 2 bit 3 0 *** **** 210 * 10 ** 3210 (a) leading edge (b) trailing edge * ; don?t care so1 pin si1 pin sck1 pin sck1 pin
page 150 15. synchronous serial interface (sio1) 15.6 transfer mode TMP86CS64AFG an intsio1 interrupt is generated when the specified number of words has been transferred. if the number of words is to be changed during transfer , the serial interface must be stopped before making the ch ange. the number of words can be changed during automatic-wa it operation of an internal clock. in this case, the serial interface is not required to be stopped. figure 15-6 number of words to transfer (example: 1word = 4bit) 15.6 transfer mode sio1cr1 is used to select the tran smit, receive, or transmit/receive mode. 15.6.1 4-bit and 8-bit transfer modes in these modes, firstly set the sio control register to the transmit mode, and then write first transmit data (number of transfer words to be transfer red) to the data buffer registers (dbr). after the data are written, the transmission is star ted by setting sio1cr1 to ?1?. the data are then output sequentially to the so pin in synchronous with th e serial clock, starting with the least significant bit (lsb). as soon as the lsb has been output, the data are transferred from the data buffer register to the shift register. when the final data bit has b een transferred and the data buffer re gister is empty, an intsio1 (buffer empty) interrupt is generated to request the next transmitted data. when the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer regist er by the time the number of data words specified with the sio1cr2 has been transmitted. writing even one word of data cancels the automatic-wait; there- fore, when transmitting two or more words, always wr ite the next word before transmission of the previous word is completed. note:automatic waits are also canceled by writing to a dbr not being used as a transmit data buffer register; there- fore, during sio do not use such dbr for other applicati ons. for example, when 3 words are transmitted, do not use the dbr of the remained 5 words. a 1 a 2 a 3 a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 a 0 a 1 a 0 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 (a) 1 word transmit (b) 3 words transmit (c) 3 words receive so1 pin intsio1 interrupt intsio1 interrupt intsio1 interrupt so1 pin si1 pin sck1 pin sck1 pin sck1 pin
page 151 TMP86CS64AFG when an external clock is used, the data must be writte n to the data buffer register before shifting next data. thus, the transfer speed is determin ed by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. the transmission is ended by clear ing sio1cr1 to ?0? or se tting sio1cr1 to ?1? in buffer empty interrupt service program. sio1cr1 is cleared, the operation will end after all bi ts of words are transmitted. that the transmission has ended can be determin ed from the status of sio1sr because sio1sr is cleared to ?0? when a transfer is completed. when sio1cr1 is set, the transmission is immediately ended and sio1sr is cleared to ?0?. when an external clock is used, it is also necessary to clear sio1cr1 to ?0? before shifting the next data; if sio1cr1 is not cleared before shift out, dummy data will be transmitted and the operation will end. if it is necessary to change th e number of words, si o1cr1 should be cleared to ?0?, then sio1cr2 must be rewritten after confirming that sio1sr has been cleared to ?0?. figure 15-7 transfer m ode (example: 8bit, 1word tr ansfer, internal clock) a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck1 pin (output) so1 pin intsio1 interrupt sio1cr1 sio1sr sio1sr sio1sr
page 152 15. synchronous serial interface (sio1) 15.6 transfer mode TMP86CS64AFG figure 15-8 transfer mode (example: 8b it, 1word transfer , external clock) figure 15-9 transmiiied data ho ld time at end of transfer 15.6.2 4-bit and 8- bit receive modes after setting the control registers to the receive mode, set sio1cr1 to ?1? to enab le receiving. the data are then transferred to the shift register via the si pin in synchronous with the serial clock. when one word of data has been received, it is tran sferred from the shift register to the data buffer register (dbr). when the number of words specified with the sio1cr2 has been received, an intsio1 (buffer full) interrupt is generated to request that these data be read out. the da ta are then read from the da ta buffer registers by the interrupt service program. when the internal clock is used, and the previous data are not read from the data buffer register before the next data are received, the serial cloc k will stop and an automatic-wait will be initiated until the data are read. a wait will not be initiated if even one data word has been read. note:waits are also canceled by readi ng a dbr not being used as a received data buffer register is read; therefore, during sio1 do not use such dbr for other applications. a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck1 pin (input) so1 pin intsio1 interrupt sio1cr1 sio1sr sio1sr msb of last word t sodh = min 3.5/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 3.5/fs [s] (in the slow1/2, sleep1/2 modes) sck1 pin so1 pin sio1sr
page 153 TMP86CS64AFG when an external clock is used, the shift operation is synchronized with the extern al clock; therefore, the previous data are read before the next data are transferred to the data buffer register. if the previous data have not been read, the next data will not be transferred to th e data buffer register and th e receiving of any more data will be canceled. when an external clock is used, th e maximum transfer speed is determined by the delay between the time when the interrupt request is gene rated and when the data received have been read. the receiving is ended by clearing sio1cr1 to ?0? or setting sio1cr1 to ?1? in buffer full interrupt service program. when sio1cr1 is cleared, th e current data are transferred to the buffer. after sio1cr1 cleared, the receiving is ended at the ti me that the final bit of the data has been received. that the receiving has ended can be determined from the status of sio1sr . sio1sr is cleared to ?0? when the receiving is ended. after confirmed the receiving te rmination, the final recei ving data is read. when sio1cr1 is set, the receivi ng is immediately ended and sio1sr is cleared to ?0?. (the received data is ignored, and it is not required to be read out.) if it is necessary to change the number of words in external clock operation, sio1cr1 should be cleared to ?0? then sio1cr2 mu st be rewritten after confirming that sio1sr has been cleared to ?0?. if it is necessary to chan ge the number of words in internal clock, during automatic-wait operation which occurs after completion of data receiving, sio1cr2 must be rewr itten before the received data is read out. note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by clearing sio1cr1 to ?0?, read the last data and then switch the trans- fer mode. figure 15-10 receive mode (example: 8b it, 1word transfer, internal clock) 15.6.3 8-bit trans fer / receive mode after setting the sio control register to the 8-bit transmit/recei ve mode, write the data to be transmitted first to the data buffer registers (dbr). af ter that, enable the transmit/receive by setting sio1cr1 to ?1?. when transmitting, the data are output from the so1 pin at leading edges of the serial clock. when receiving, the data are input to th e si1 pin at the trailing edges of the serial clock. when the all receive is enabled, 8-bit data are transferred from the shift re gister to the data buffer register. an intsio1 interrupt is generated when the number of data words specified with the sio1cr2 has been transferred. usually, read the receive data from the buffer register in the interrupt service. the data buffer register is used for both transmitting and receiving; therefore, always writ e the data to be transmitted af ter reading the all received data. when the internal clock is used, a wait is initiated until the received data are read and the next transfer data are written. a wait will not be initiated if ev en one transfer data word has been written. a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 dbr b a clear sios read out read out sck1 pin (output) si1 pin intsio1 interrupt sio1cr1 sio1sr sio1sr
page 154 15. synchronous serial interface (sio1) 15.6 transfer mode TMP86CS64AFG when an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift oper- ation. when an external clock is us ed, the transfer speed is determined by the maximum delay between genera- tion of an interrupt request and the received data are read and the data to be transmitted next are written. the transmit/receive operation is ended by clearing sio1cr1 to ?0? or setting sio1cr1 to ?1? in intsio1 interrupt service program. when sio1cr1 is cleared, the current data ar e transferred to the buff er. after sio1cr1 cleared, the transmitting/ receiving is ended at the time that the fi nal bit of the data has been transmitted. that the transmitting/receiving has ended can be determined fr om the status of sio1sr. sio1sr is cleared to ?0? when the transmitting/recei ving is ended. when sio1cr1 is set, th e transmit/receive operation is imm ediately ended and sio1sr is cleared to ?0?. if it is necessary to change the number of words in external clock operation, sio1cr1 should be cleared to ?0?, then sio1cr2 must be rewritten after confirming that sio1sr has been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of transmit /receive operation, sio1 cr2 must be rewrit ten before reading and writing of the receive/transmit data. note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by clearing sio1cr1 to ?0?, read the last data and then switch the trans- fer mode. figure 15-11 transfer / receive mode (examp le: 8bit, 1word transfe r, internal clock) a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 c 1 c 0 c 2 c 3 c 4 c 5 c b c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 clear sios dbr d a read out (c) write (a) read out (d) write (b) sck1 pin (output) so1 pin intsio1 interrupt sio1cr1 sio1sr sio1sr si1 pin
page 155 TMP86CS64AFG figure 15-12 transmitted data hold ti me at end of tr ansfer / receive bit 7 of last word bit 6 t sodh = min 4/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 4/fs [s] (in the slow1/2, sleep1/2 modes) sck1 pin so1 pin sio1sr
page 156 15. synchronous serial interface (sio1) 15.6 transfer mode TMP86CS64AFG
page 157 TMP86CS64AFG 16. synchronous serial interface (sio2) the TMP86CS64AFG has a clocked-synchronous 8-bit serial interface. serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. serial interface is connected to outside peri pherl devices via so2, si2, sck2 port. 16.1 configuration figure 16-1 serial interface sio control / status register serial clock shift clock shift register 3 2 1 0 7 6 5 4 transmit and receive data buffer (8 bytes in dbr) control circuit cpu serial data output serial data input 8-bit transfer 4-bit transfer serial clock i/o buffer control circuit so2 si2 sck 2 sio2cr2 sio2cr1 sio2sr intsio2 interrupt request
page 158 16. synchronous serial interface (sio2) 16.2 control TMP86CS64AFG 16.2 control the serial interface is controlled by sio control registers (sio2cr1/sio2cr2 ). the serial interface status can be determined by reading sio status register (sio2sr). the transmit and receive data buffer is controlled by th e sio2cr2. the data buff er is assigned to address 0f98h to 0f9fh for sio in the dbr area, and can continuou sly transfer up to 8 words (bytes or nibbles) at one time. when the specified number of words has been transferre d, a buffer empty (in the tran smit mode) or a buffer full (in the receive mode or tr ansmit/receive mode) interrup t (intsio2) is generated. when the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a fixed interval wait can be applied to the serial clock fo r each word transferred. four different wait times can be selected with sio2cr2. note 1: fc; high-frequency clock [hz], fs; low-frequency clock [hz] note 2: set sios to "0" and sioinh to "1" when setting the transfer mode or serial clock. note 3: sio2cr1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. sio control register 1 sio2cr176543210 (0fb4h) sios sioinh siom sck (initial value: 0000 0000) sios indicate transfer start / stop 0: stop write only 1: start sioinh continue / abort transfer 0: continuously transfer 1: abort transfer (automatically cleared after abort) siom transfer mode select 000: 8-bit transmit mode 010: 4-bit transmit mode 100: 8-bit transmit / receive mode 101: 8-bit receive mode 110: 4-bit receive mode except the above: reserved sck serial clock select normal1/2, idle1/2 mode slow1/2 sleep1/2 mode write only dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 1 dv1ck = 1 000 fc/2 15 fc/2 16 fs/2 7 fs/2 7 fs/2 7 001 fc/2 8 fc/2 9 fc/2 8 fc/2 9 - 010 fc/2 7 fc/2 8 fc/2 7 fc/2 8 - 011 fc/2 6 fc/2 7 fc/2 6 fc/2 7 - 100 fc/2 5 fc/2 6 fc/2 5 fc/2 6 - 101 fc/2 4 fc/2 5 fc/2 4 fc/2 5 - 110 reserved 111 external clock (input from sck2 pin ) sio control register 2 sio2cr276543210 (0fb5h) wait buf (initial value: ***0 0000)
page 159 TMP86CS64AFG note 1: the lower 4 bits of each buffer are used during 4-bit tr ansfers. zeros (0) are stored to the upper 4bits when receiving. note 2: transmitting starts at the lowest address. received data are also stored starting from the lowest address to the highest address. ( the first buffer address transmitted is 0f98h ). note 3: the value to be loaded to buf is held after transfer is completed. note 4: sio2cr2 must be set when the serial interface is stopped (siof = 0). note 5: *: don't care note 6: sio2cr2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. note 1: t f ; frame time, t d ; data transfer time note 2: after sios is cleared to "0", siof is cleared to "0" at the termination of transfer or the setting of sioinh to "1". figure 16-2 fr ame time (t f ) and data transfer time (t d ) 16.3 serial clock 16.3.1 clock source internal clock or external clock for the source clock is selected by sio2cr1. wait wait control always sets "00" except 8-bit transmit / receive mode. write only 00: t f = t d (non wait) 01: t f = 2t d (wait) 10: t f = 4t d (wait) 11: t f = 8t d (wait) buf number of transfer words (buffer address in use) 000: 1 word transfer 0f98h 001: 2 words transfer 0f98h ~ 0f99h 010: 3 words transfer 0f98h ~ 0f9ah 011: 4 words transfer 0f98h ~ 0f9bh 100: 5 words transfer 0f98h ~ 0f9ch 101: 6 words transfer 0f98h ~ 0f9dh 110: 7 words transfer 0f98h ~ 0f9eh 111: 8 words transfer 0f98h ~ 0f9fh sio status register sio2sr76543210 (0fb5h) siof sef siof serial transfer operating status moni- tor 0: 1: transfer terminated transfer in process read only sef shift operating status monitor 0: 1: shift operation terminated shift operation in process td tf (output) s ck2 output
page 160 16. synchronous serial interface (sio2) 16.3 serial clock TMP86CS64AFG 16.3.1.1 internal clock any of six frequencies can be selected. the serial clock is output to the outside on the sck2 pin. the sck2 pin goes high when transfer starts. when data writing (in the transmit mo de) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wa it function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. note: 1 kbit = 1024 bit (fc = 16 mhz, fs = 32.768 khz) figure 16-3 automatic wait fu nction (at 4-bit transmit mode) 16.3.1.2 external clock an external clock connected to the sck 2 pin is used as the serial clock. in this case, output latch of this port should be set to "1". to ensure shifting, a pulse width of at least 4 machine cycles is required. this pulse is needed for the shift operatio n to execute certainly. actually, there is necessary processing time for interrupting, writing, and reading. the minimum pulse is determined by setting the mode and the pro- gram. therfore, maximum transfer frequenc y will be 488.3k bit/sec (at fc=16mhz). table 16-1 serial clock rate normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 sck clock baud rate clock baud rate clock baud rate clock baud rate clock baud rate 000 fc/2 15 0.48 kbps fc/2 16 0.24 kbps fs/2 7 256 bps fs/2 7 256 bps fs/2 7 256 bps 001 fc/2 8 61.04 kbps fc/2 9 30.52 kbps fc/2 8 61.04 kbps fc/2 9 30.52 kbps -- 010 fc/2 7 122.07 kbps fc/2 8 61.04 kbps fc/2 7 122.07 kbps fc/2 8 61.04 kbps -- 011 fc/2 6 244.14 kbps fc/2 7 122.07 kbps fc/2 6 244.14 kbps fc/2 7 122.07 kbps -- 100 fc/2 5 488.28 kbps fc/2 6 244.14 kbps fc/2 5 488.28 kbps fc/2 6 244.14 kbps -- 101 fc/2 4 976.56 kbps fc/2 5 488.28 kbps fc/2 4 976.56 kbps fc/2 5 488.28 kbps -- 110---------- 111 external external external external external external external external external external a 1 a 2 b 0 b 1 b 2 b 3 c 0 c 1 a 3 a c b a 0 pin (output) pin (output) written transmit data a utomat i ca ll y wait function sck2 so2
page 161 TMP86CS64AFG figure 16-4 external clock pulse width 16.3.2 shift edge the leading edge is used to transmit, a nd the trailing edge is used to receive. 16.3.2.1 leading edge transmitted data are shifted on the leading edge of the serial clock (falling edge of the sck 2 pin input/ output). 16.3.2.2 trailing edge received data are shifted on th e trailing edge of the serial clock (rising edge of the sck 2 pin input/out- put). figure 16-5 shift edge 16.4 number of bits to transfer either 4-bit or 8-bit serial transfer can be selected. when 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer re gister are used. the upper 4 bits are cleared to ?0? when receiving. the data is transferred in sequence star ting at the least significant bit (lsb). 16.5 number of w ords to transfer up to 8 words consisting of 4 bits of data (4-bit serial tran sfer) or 8 bits (8-bit serial tr ansfer) of data can be trans- ferred continuously. the number of words to be transferred can be selected by sio2cr2. t sckl t sckh tcyc = 4/fc (in the normal1/2, idle1/2 modes) 4/fs (in the slow1/2, sleep1/2 modes) t sckl , t sckh > 4tcyc sck2 pin (output) bit 1 bit 2 bit 3 * 321 3210 ** 32 *** 3 bit 0 shift register shift register bit 1 bit 0 bit 2 bit 3 0 *** **** 210 * 10 ** 3210 (a) leading edge (b) trailing edge * ; don?t care so2 pin si2 pin sck2 pin sck2 pin
page 162 16. synchronous serial interface (sio2) 16.6 transfer mode TMP86CS64AFG an intsio2 interrupt is generated when the specified number of words has been transferred. if the number of words is to be changed during transfer , the serial interface must be stopped before making the ch ange. the number of words can be changed during automatic-wa it operation of an internal clock. in this case, the serial interface is not required to be stopped. figure 16-6 number of words to transfer (example: 1word = 4bit) 16.6 transfer mode sio2cr1 is used to select the tran smit, receive, or transmit/receive mode. 16.6.1 4-bit and 8-bit transfer modes in these modes, firstly set the sio control register to the transmit mode, and then write first transmit data (number of transfer words to be transfer red) to the data buffer registers (dbr). after the data are written, the transmission is star ted by setting sio2cr1 to ?1?. the data are then output sequentially to the so pin in synchronous with th e serial clock, starting with the least significant bit (lsb). as soon as the lsb has been output, the data are transferred from the data buffer register to the shift register. when the final data bit has b een transferred and the data buffer re gister is empty, an intsio2 (buffer empty) interrupt is generated to request the next transmitted data. when the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer regist er by the time the number of data words specified with the sio2cr2 has been transmitted. writing even one word of data cancels the automatic-wait; there- fore, when transmitting two or more words, always wr ite the next word before transmission of the previous word is completed. note:automatic waits are also canceled by writing to a dbr not being used as a transmit data buffer register; there- fore, during sio do not use such dbr for other applicati ons. for example, when 3 words are transmitted, do not use the dbr of the remained 5 words. a 1 a 2 a 3 a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 a 0 a 1 a 0 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 (a) 1 word transmit (b) 3 words transmit (c) 3 words receive so2 pin intsio2 interrupt intsio2 interrupt intsio2 interrupt so2 pin si2 pin sck2 pin sck2 pin sck2 pin
page 163 TMP86CS64AFG when an external clock is used, the data must be writte n to the data buffer register before shifting next data. thus, the transfer speed is determin ed by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. the transmission is ended by clear ing sio2cr1 to ?0? or se tting sio2cr1 to ?1? in buffer empty interrupt service program. sio2cr1 is cleared, the operation will end after all bi ts of words are transmitted. that the transmission has ended can be determin ed from the status of sio2sr because sio2sr is cleared to ?0? when a transfer is completed. when sio2cr1 is set, the transmission is immediately ended and sio2sr is cleared to ?0?. when an external clock is used, it is also necessary to clear sio2cr1 to ?0? before shifting the next data; if sio2cr1 is not cleared before shift out, dummy data will be transmitted and the operation will end. if it is necessary to change th e number of words, si o2cr1 should be cleared to ?0?, then sio2cr2 must be rewritten after confirming that sio2sr has been cleared to ?0?. figure 16-7 transfer m ode (example: 8bit, 1word tr ansfer, internal clock) a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck2 pin (output) so2 pin intsio2 interrupt sio2cr1 sio2sr sio2sr sio2sr
page 164 16. synchronous serial interface (sio2) 16.6 transfer mode TMP86CS64AFG figure 16-8 transfer mode (example: 8b it, 1word transfer , external clock) figure 16-9 transmiiied data ho ld time at end of transfer 16.6.2 4-bit and 8- bit receive modes after setting the control registers to the receive mode, set sio2cr1 to ?1? to enab le receiving. the data are then transferred to the shift register via the si pin in synchronous with the serial clock. when one word of data has been received, it is tran sferred from the shift register to the data buffer register (dbr). when the number of words specified with the sio2cr2 has been received, an intsio2 (buffer full) interrupt is generated to request that these data be read out. the da ta are then read from the da ta buffer registers by the interrupt service program. when the internal clock is used, and the previous data are not read from the data buffer register before the next data are received, the serial cloc k will stop and an automatic-wait will be initiated until the data are read. a wait will not be initiated if even one data word has been read. note:waits are also canceled by readi ng a dbr not being used as a received data buffer register is read; therefore, during sio2 do not use such dbr for other applications. a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck2 pin (input) so2 pin intsio2 interrupt sio2cr1 sio2sr sio2sr msb of last word t sodh = min 3.5/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 3.5/fs [s] (in the slow1/2, sleep1/2 modes) sck2 pin so2 pin sio2sr
page 165 TMP86CS64AFG when an external clock is used, the shift operation is synchronized with the extern al clock; therefore, the previous data are read before the next data are transferred to the data buffer register. if the previous data have not been read, the next data will not be transferred to th e data buffer register and th e receiving of any more data will be canceled. when an external clock is used, th e maximum transfer speed is determined by the delay between the time when the interrupt request is gene rated and when the data received have been read. the receiving is ended by clearing sio2cr1 to ?0? or setting sio2cr1 to ?1? in buffer full interrupt service program. when sio2cr1 is cleared, th e current data are transferred to the buffer. after sio2cr1 cleared, the receiving is ended at the ti me that the final bit of the data has been received. that the receiving has ended can be determined from the status of sio2sr . sio2sr is cleared to ?0? when the receiving is ended. after confirmed the receiving te rmination, the final recei ving data is read. when sio2cr1 is set, the receivi ng is immediately ended and sio2sr is cleared to ?0?. (the received data is ignored, and it is not required to be read out.) if it is necessary to change the number of words in external clock operation, sio2cr1 should be cleared to ?0? then sio2cr2 mu st be rewritten after confirming that sio2sr has been cleared to ?0?. if it is necessary to chan ge the number of words in internal clock, during automatic-wait operation which occurs after completion of data receiving, sio2cr2 must be rewr itten before the received data is read out. note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by clearing sio2cr1 to ?0?, read the last data and then switch the trans- fer mode. figure 16-10 receive mode (example: 8b it, 1word transfer, internal clock) 16.6.3 8-bit trans fer / receive mode after setting the sio control register to the 8-bit transmit/recei ve mode, write the data to be transmitted first to the data buffer registers (dbr). af ter that, enable the transmit/receive by setting sio2cr1 to ?1?. when transmitting, the data are output from the so2 pin at leading edges of the serial clock. when receiving, the data are input to th e si2 pin at the trailing edges of the serial clock. when the all receive is enabled, 8-bit data are transferred from the shift re gister to the data buffer register. an intsio2 interrupt is generated when the number of data words specified with the sio2cr2 has been transferred. usually, read the receive data from the buffer register in the interrupt service. the data buffer register is used for both transmitting and receiving; therefore, always writ e the data to be transmitted af ter reading the all received data. when the internal clock is used, a wait is initiated until the received data are read and the next transfer data are written. a wait will not be initiated if ev en one transfer data word has been written. a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 dbr b a clear sios read out read out sck2 pin (output) si2 pin intsio2 interrupt sio2cr1 sio2sr sio2sr
page 166 16. synchronous serial interface (sio2) 16.6 transfer mode TMP86CS64AFG when an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift oper- ation. when an external clock is us ed, the transfer speed is determined by the maximum delay between genera- tion of an interrupt request and the received data are read and the data to be transmitted next are written. the transmit/receive operation is ended by clearing sio2cr1 to ?0? or setting sio2cr1 to ?1? in intsio2 interrupt service program. when sio2cr1 is cleared, the current data ar e transferred to the buff er. after sio2cr1 cleared, the transmitting/ receiving is ended at the time that the fi nal bit of the data has been transmitted. that the transmitting/receiving has ended can be determined fr om the status of sio2sr. sio2sr is cleared to ?0? when the transmitting/recei ving is ended. when sio2cr1 is set, th e transmit/receive operation is imm ediately ended and sio2sr is cleared to ?0?. if it is necessary to change the number of words in external clock operation, sio2cr1 should be cleared to ?0?, then sio2cr2 must be rewritten after confirming that sio2sr has been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of transmit /receive operation, sio2 cr2 must be rewrit ten before reading and writing of the receive/transmit data. note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by clearing sio2cr1 to ?0?, read the last data and then switch the trans- fer mode. figure 16-11 transfer / receive mode (examp le: 8bit, 1word transfe r, internal clock) a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 c 1 c 0 c 2 c 3 c 4 c 5 c b c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 clear sios dbr d a read out (c) write (a) read out (d) write (b) sck2 pin (output) so2 pin intsio2 interrupt sio2cr1 sio2sr sio2sr si2 pin
page 167 TMP86CS64AFG figure 16-12 transmitted data hold ti me at end of tr ansfer / receive bit 7 of last word bit 6 t sodh = min 4/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 4/fs [s] (in the slow1/2, sleep1/2 modes) sck2 pin so2 pin sio2sr
page 168 16. synchronous serial interface (sio2) 16.6 transfer mode TMP86CS64AFG
page 169 TMP86CS64AFG 17. 10-bit ad converter (adc) the TMP86CS64AFG have a 10-bit successi ve approximation ty pe ad converter. 17.1 configuration the circuit configuration of the 10-bit ad converter is shown in figure 17-1. it consists of control register adccr1 and adccr2 , converted value register adcdr1 and adcdr2, a da converter, a sample-hold circuit, a compar ator, and a successive comparison circuit. note: before using ad converter, set appropriate value to i/o port register conbining a analog input port. for details, see the sec- tion on "i/o ports". figure 17-1 10-bit ad converter 2 4 10 8 ainds adrs r/2 r/2 r ack amd irefon ad conversion result register 1, 2 ad converter control register 1, 2 adbf eocf intadc sain n successive approximate circuit adccr2 adcdr1 adcdr2 adccr1  sample hold circuit a s en shift clock da converter analog input multiplexer y reference voltage analog comparator 2 3 control circuit avss varef avdd ain0 ain15
page 170 17. 10-bit ad converter (adc) 17.2 register configuration TMP86CS64AFG 17.2 register configuration the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects the analog channels and operatio n mode (software start or repeat) in which to per- form ad conversion and controls the ad converter as it starts operating. 2. ad converter control register 2 (adccr2) this register selects the ad conversion time and co ntrols the connection of the da converter (ladder resistor network). 3. ad converted value register 1 (adcdr1) this register used to store the digital value fter being converted by the ad converter. 4. ad converted value register 2 (adcdr2) this register monitors the oper ating status of the ad converter. note 1: select analog input channel during ad converter stops (adcdr2 = "0"). note 2: when the analog input channel is all use dis abling, the adccr1 should be set to "1". note 3: during conversion, do not perform port output instruction to maintain a precision for all of the pins because analog inp ut port use as general input port. and for port near to anal og input, do not input intense signaling of change. note 4: the adccr1 is automatically cleared to "0" after starting conversion. note 5: do not set adccr1 newly again during ad conv ersion. before setting adccr1 newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). note 6: after stop or slow/sleep mode are started, ad conver ter control register1 (adccr1) is all initialized and no data can be written in this register. therfore, to use ad converter again, set the adccr1 newly after returning to normal1 or normal2 mode. ad converter control register 1 adccr1 (000eh) 76543210 adrs amd ainds sain (initial value: 0001 0000) adrs ad conversion start 0: 1: - ad conversion start r/w amd ad operating mode 00: 01: 10: 11: ad operation disable software start mode reserved repeat mode ainds analog input control 0: 1: analog input enable analog input disable sain analog input channel select 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain11 ain12 ain13 ain14 ain15
page 171 TMP86CS64AFG note 1: always set bit0 in adccr2 to "0" and set bit4 in adccr2 to "1". note 2: when a read instruction for adccr2, bi t6 to 7 in adccr2 read in as undefined data. note 3: after stop or slow/sleep mode are started, ad conver ter control register2 (adccr2) is all initialized and no data can be written in this register. therfore, to use ad converter again, set the adccr2 newly after returning to normal1 or normal2 mode. note 1: setting for " ? " in the above table are inhibited. fc: high frequency oscillation clock [hz] note 2: set conversion time setting should be kept more t han the following time by analog reference voltage (varef) . ad converter control register 2 adccr2 (000fh) 76543210 irefon "1" ack "0" (initial value: **0* 000*) irefon da converter (ladder resistor) connection control 0: 1: connected only during ad conversion always connected r/w ack ad conversion time select (refer to the following table about the con- version time) 000: 001: 010: 011: 100: 101: 110: 111: 39/fc reserved 78/fc 156/fc 312/fc 624/fc 1248/fc reserved table 17-1 ack setting and conversion time (at cgcr="0") condition conversion time 16 mhz 8 mhz 4 mhz 2 mhz 10 mhz 5 mhz 2.5 mhz ack 000 39/fc - - - 19.5 s - - 15.6 s 001 reserved 010 78/fc - - 19.5 s 39.0 s - 15.6 s 31.2 s 011 156/fc - 19.5 s 39.0 s 78.0 s 15.6 s 31.2 s 62.4 s 100 312/fc 19.5 s39.0 s 78.0 s 156.0 s 31.2 s 62.4 s124.8 s 101 624/fc 39.0 s78.0 s 156.0 s - 62.4 s124.8 s- 110 1248/fc 78.0 s 156.0 s - - 124.8 s- - 111 reserved table 17-2 ack setting and conversion time (at cgcr="1") condition conversion time 16 mhz 8 mhz 4 mhz 2 mhz 10 mhz 5 mhz 2.5 mhz ack 000 39/fc - - - 19.5 s - - 15.6 s 001 reserved 010 156/fc - 19.5 s 39.0 s 78.0 s 15.6 s 31.2 s 62.4 s 011 312/fc 19.5 s39.0 s 78.0 s 156.0 s 31.2 s 62.4 s124.8 s 100 624/fc 39.0 s78.0 s 156.0 s - 62.4 s124.8 s- 101 1248/fc 78.0 s 156.0 s - - 124.8 s- - 110 2096/fc 156.0 s------ 111 reserved - varef = 4.5 to 5.5 v 15.6 s and more - varef = 2.7 to 5.5 v 31.2 s and more
page 172 17. 10-bit ad converter (adc) 17.2 register configuration TMP86CS64AFG note 1: the adcdr2 is cleared to "0" when reading the a dcdr1. therfore, the ad conversion result should be read to adcdr2 more first than adcdr1. note 2: the adcdr2 is set to "1" when ad conversion star ts, and cleared to "0" when ad conversion finished. it also is cleared upon entering stop mode or slow mode . note 3: if a read instruction is executed for a dcdr2, read data of bit3 to bit0 are unstable. ad converted value register 1 adcdr1 (0027h) 76543210 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 (initial value: 0000 0000) ad converted value register 2 adcdr2 (0026h) 76543210 ad01 ad00 eocf adbf (initial value: 0000 ****) eocf ad conversion end flag 0: 1: before or during conversion conversion completed read only adbf ad conversion busy flag 0: 1: during stop of ad conversion during ad conversion
page 173 TMP86CS64AFG 17.3 function 17.3.1 software start mode after setting adccr1 to ?01? (software start mode), set adccr1 to ?1?. ad conver- sion of the voltage at the analog input pin specified by adccr1 is thereby started. after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1, adcdr2) and at the same time adcdr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. adrs is automatically cleared afte r ad conversion has started. do not set adccr1 newly again (restart) during ad conversion. before setting adrs newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signa l (intadc) is generated (e.g., interrupt handling rou- tine). figure 17-2 software start mode 17.3.2 repeat mode ad conversion of the voltage at the analog input pin specified by adccr1 is performed repeatedly. in this mode, ad conversion is started by setti ng adccr1 to ?1? after setting adccr1 to ?11? (repeat mode). after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1, adcdr2) and at the same time adcdr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. in repeat mode, each time one ad conversion is complete d, the next ad conversion is started. to stop ad conversion, set adccr1 to ?00? (disable mode) by writing 0s. the ad convert operation is stopped immediately. the converted valu e at this time is not stored in the ad converted value register. adcdr1 status eocf cleared by reading conversion result conversion result read adcdr2 intadc interrupt request adcdr2 adccr1 1st conversion result 2nd conversion result indeterminate ad conversion start ad conversion start a dcdr1 a dcdr2 conversion result read conversion result read conversion result read
page 174 17. 10-bit ad converter (adc) 17.3 function TMP86CS64AFG figure 17-3 repeat mode 17.3.3 regi ster setting 1. set up the ad converter control register 1 (adccr1) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable fo r analog input control (ainds). ? specify amd for the ad converter control operation mode (software or repeat mode). 2. set up the ad converter control register 2 (adccr2) as follows: ? set the ad conversion time using ad conversion time (ack). for details on how to set the con- version time, refer to figure 17-1, figure 17-2 and ad converter control register 2. ? choose irefon for da converter control. 3. after setting up (1) and (2) above, set ad conversion start (adrs) of ad converter control register 1 (adccr1) to ?1?. if software start mode has been selected, ad conversi on starts immediately. 4. after an elapse of the specified ad conversion time, the ad converted value is stored in ad con- verted value register 1 (adcdr1) and the ad conv ersion finished flag (e ocf) of ad converted value register 2 (adcdr2) is set to ?1?, upon wh ich time ad conversion interrupt intadc is gener- ated. 5. eocf is cleared to ?0? by a read of the conversion result. however, if reconverted before a register read, although eocf is cl eared the previous conversi on result is retained until the next conversion is completed. a dcdr1,adcdr2 eocf cleared by reading conversion result conversion result read a dcdr2 intadc interrupt request conversion operation a dccr1 indeterminate ad conversion start adccr1 ?11? ?00? 1st conversion result ad convert operation suspended. conversion result is not stored. 2nd conversion result 3rd conversion result a dcdr1 a dcdr2 2nd conversion result 3rd conversion result 1st conversion result conversion result read conversion result read conversion result read conversion result read conversion result read
page 175 TMP86CS64AFG 17.4 stop/slow modes during ad conversion when standby mode (stop or slow mode) is entered fo rcibly during ad conversi on, the ad convert operation is suspended and the ad converter is in itialized (adccr1 and adccr2 are initia lized to initial value). also, the conversion result is indeterminate. (conversion results up to the previous operation are cleared, so be sure to read the conversion results before entering standby mode (sto p or slow mode).) when restored from standby mode (stop or slow mode), ad conversion is not automatically restarted, so it is necessa ry to restart ad conversion. note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the analog reference voltage. example :after selecting the conversion time 19.5 s at 16 mhz and the analog input channel ain3 pin, perform ad con- version once. after checking eocf, read the converted value, store the lower 2 bits in address 0009eh nd store the upper 8 bits in address 0009fh in ram. the operation mode is software start mode. : (port setting) : ;set port register approrriately before setting ad converter registers. : : (refer to section i/o port in details) ld (adccr1) , 00100011b ; select ain3 ld (adccr2) , 11011000b ;select conversion time(312/fc) and operation mode set (adccr1) . 7 ; adrs = 1(ad conversion start) sloop : test (adcdr2) . 5 ; eocf= 1 ? jrs t, sloop ld a , (adcdr2) ; read result data ld (9eh) , a ld a , (adcdr1) ; read result data ld (9fh), a
page 176 17. 10-bit ad converter (adc) 17.5 analog input voltage and ad conversion result TMP86CS64AFG 17.5 analog input voltage and ad conversion result the analog input voltage is corresponded to the 10-bit dig ital value converted by the ad as shown in figure 17-4. figure 17-4 analog i nput voltage and ad c onversion result (typ.) 1 0 01 h 02 h 03 h 3fd h 3fe h 3ff h 2 3 1021 1022 1023 1024 analog input voltage 1024 ad conversion result varef avss
page 177 TMP86CS64AFG 17.6 precautions about ad converter 17.6.1 analog input pin voltage range make sure the analog input pins (ain0 to ain15) are used at voltages within varef to avss. if any volt- age outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncer- tain. the other analog input pins also are affected by that. 17.6.2 analog input shared pins the analog input pins (ain0 to ain15) are shared with input/output ports. when using any of the analog inputs to execute ad conversion, do not execute input/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversi on from degrading. not only these analog input sh ared pins, some other pins may also be affected by noise arising from input/o utput to and from adjacent pins. 17.6.3 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 17-5. the higher the output impedance of the analog input source, more easily they are susceptible to no ise. therefore, make sure the out- put impedance of the signal source in your design is 5 k ? or less. toshiba also recommends attaching a capac- itor external to the chip. figure 17-5 analog i nput equivalent circuit and exam ple of input pin processing da converter aini analog comparator internal resistance permissible signal source impedance internal capacitance 5 k ? (typ) c = 22 pf (typ.) 5 k ? (max) note) i = 15 to 0
page 178 17. 10-bit ad converter (adc) 17.6 precautions about ad converter TMP86CS64AFG
page 179 TMP86CS64AFG 18. key-on wakeup (kwu) in the TMP86CS64AFG, the stop mode is released by not only p20( int5 / stop ) pin but also four (stop2 to stop5) pins. when the stop mode is released by stop2 to stop5 pins, the stop pin needs to be used. in details, refer to the following section " 18.2 control ". 18.1 configuration figure 18-1 key-on wakeup circuit 18.2 control stop2 to stop5 pins can controlled by key-on wakeup c ontrol register (stopcr). it can be configured as enable/disable in 1-bit unit. when thos e pins are used for stop mode releas e, configure corresponding i/o pins to input mode by i/o port register beforehand. 18.3 function stop mode can be entered by setting up the system control register (syscr1), and can be exited by detecting the "l" level on stop2 to stop5 pins, which are enabled by stopcr, for releasing stop mode (note1). key-on wakeup control register stopcr76543210 (0031h) stop5 stop4 stop3 stop2 (initial value: 0000 ****) stop5 stop mode released by stop5 0:disable 1:enable write only stop4 stop mode released by stop4 0:disable 1:enable write only stop3 stop mode released by stop3 0:disable 1:enable write only stop2 stop mode released by stop2 0:disable 1:enable write only stopcr int5 stop stop mode release signal (1: release) (0031h) stop2 stop3 stop4 stop5 stop2 stop3 stop4 stop5
page 180 18. key-on wakeup (kwu) 18.3 function TMP86CS64AFG also, each level of the stop2 to stop5 pins can be co nfirmed by reading correspondi ng i/o port data register, check all stop2 to stop5 pins "h" that is enabled by stopcr before the stop mode is startd (note2,3). note 1: when the stop mode released by the edge release mo de (syscr1 = ?0?), inhibit input from stop2 to stop5 pins by key-on wakeup control register (stopcr) or must be set "h" level into stop2 to stop5 pins that are available input during stop mode. note 2: when the stop pin input is high or stop2 to stop5 pins input which is enabled by stopcr is low, executing an instruction which starts stop mode wi ll not place in stop mode but instead will immediately start the release sequence (warm up). note 3: the input circuit of key-on wakeup input and port i nput is separated?aso each input voltage threshold value is diffrent. therefore, a value comes from port input before stop mode start may be diffrent from a value which is detected by key-on wakeup input (figure 18-2). note 4: stop pin doesn?t have the control register such as stop cr, so when stop mode is released by stop2 to stop5 pins, stop pin also should be used as stop mode release function. note 5: in stop mode, key-on wakeup pin which is enabled as input mode (for releasing stop mode) by key-on wakeup control register (stopcr) may genarate the penet ration current, so the said pin must be disabled ad conversion input (analog voltage input). note 6: when the stop mode is released by stop2 to stop5 pins, the level of stop pin should hold "l" level (figure 18-3). figure 18-2 key-on wakeup input and port input figure 18-3 priority of stop pin and stop2 to stop5 pins table 18-1 release level (edge) of stop mode pin name release level (edge) syscr1="1" (note2) syscr1="0" stop "h" level rising edge stop2 "l" level don?t use (note1) stop3 "l" level don?t use (note1) stop4 "l" level don?t use (note1) stop5 "l" level don?t use (note1) port input external pin key-on wakeup input stop pin a) stop release stop mode stop mode stop pin "l" b) release stop mode stop mode in case of stop2 to stop5 stop2 pin
page 181 TMP86CS64AFG 19. input/output circuitry 19.1 control pins the input/output circuitries of the TMP86CS64AFG control pins are shown below. note: the test pin of the tmp86ps64 does not have a pull-down resistor. fix the test pin at low-level in mcu mode. control pin i/o input/output circuitry remarks xin xout input output resonator connecting pins (high-frequency) r f = 1.2 m ? (typ.) r o = 1.5 k ? (typ.) xtin xtout input output resonator connecting pins (low-frequency) r f = 6 m ? (typ.) r o = 220 k ? (typ.) reset input hysteresis input pull-up resistor r in = 220 k ? (typ.) r = 1 k ? (typ.) test input pull-down resistor r in = 70 k ? (typ.) r = 1 k ? (typ.) fc r f r o osc. enable xin xout vdd vdd fs r f r o osc. enable xtin xtout vdd xten vdd r r in vdd vdd r in r d 1 vdd
page 182 19. input/output circuitry 19.1 control pins TMP86CS64AFG 19.2 input/output ports port i/o input/output circuitry remarks p0 i/o tri-state i/o r = 100 ? (typ.) p1 p3 p5 p8 p9 i/o tri-state i/o hysteresis input high current output (n-ch)(p5, p9) r = 100 ? (typ.) p6 p7 i/o tri-state i/o programmable pull-up r in = 80 k ? (typ.) r = 100 ? (typ.) pa pb i/o tri-state i/o hysteresis input programmable pull-up r in = 80 k ? (typ.) r = 100 ? (typ.) p2 i/o sink open drain output hysteresis input r = 100 ? (typ.) p4 i/o sink open drain i/o or tri-state i/o hysteresis input r = 100 ? (typ.) initial "high-z" disable data output pin input vdd r initial "high-z" disable data output pin input vdd r initial "high-z" disable data output pin input vdd r r in initial "high-z" disable data output pin input vdd r r in vdd r initial "high-z" data output pin input pch control disable vdd initial "high-z" data output data input pin input r
page 183 TMP86CS64AFG 20. electrical characteristics 20.1 absolute maximum ratings the absolute maximum ratings are rated values which must not be exceeded during operat ion, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum ra ting is exceeded, a device may break down or its performance may be degraded, causi ng it to catch fire or ex plode resulting in injury to the user. thus, when designing products which include this de vice, ensure that no absolute maximu m rating value will ever be exceeded. (v ss = 0 v) parameter symbol pins ratings unit supply voltage v dd ? 0.3 to 6.5 v input voltage v in ? 0.3 to v dd + 0.3 output voltage v out ? 0.3 to v dd + 0.3 output current (per 1 pin) i outh except open drain ? 3.2 ma i out1 except p5, p9 3.2 i out2 p5 30 i out3 p9 output current (total) i out1 except p5, p9 60 i out2 p5 i out3 p9 power dissipation [t opr = 85 c] pd 250 mw soldering temperature (time) tsld 260 (10 s) c storage temperature tstg ? 55 to 125 operating temperature topr ? 40 to 85
page 184 20. electrical characteristics 20.2 recommended operating condition TMP86CS64AFG 20.2 recommended op erating condition the recommended operating co nditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ac/dc values etc.), malfunction may occur. thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol pins condition min max unit supply voltage v dd fc = 16 mhz, each operation modes 4.5 5.5 v fc = 8 mhz, each operation modes 2.7 fs = 32.768 khz, each operation modes 2.7 stop mode 2.0 input high level v ih1 hysteresis v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis v dd 0.75 v ih3 v dd < 4.5 v v dd 0.90 input low level v il1 hysteresis v dd 4.5 v 0 v dd 0.30 v il2 hysteresis v dd 0.25 v il3 v dd < 4.5 v v dd 0.10 clock frequency fc xin, xout v dd = 2.7 v to 5.5 v 1.0 8.0 mhz v dd = 4.5 v to 5.5 v 1.0 16.0 fs xtin, xtout 30.0 34.0 khz
page 185 TMP86CS64AFG 20.3 dc characteristics note 1: typical values show those at topr = 25 c, v dd = 5 v note 2: input current (i in1 , i in3 ); the current through pull-up or pull-down resistor is not included. note 3: i dd does not include i ref current. (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol pins condition min typ. max unit hysteresis voltage v hs hysteresis input ? 0.9 ? v input current i in1 test v dd = 5.5 v, v in = 5.5 v/0 v ?? 2 a i in2 sink open drain, tri-state port i in3 stop , reset input resistance r in1 test ?70? k ? r in2 reset 100 220 450 r in3 programmable pull up (p6, p7, pa, pb) v dd = 5.5 v 40 80 200 osc. feedback resistance rfx xin-xout ? 1.2 ? m ? rfxt xtin-xtout ? 6 ? output leakage current i lo1 sink open drain port v dd = 5.5 v, v out = 5.5 v ??2 a i lo2 tri-state port v dd = 5.5 v, v out = 5.5 v/0 v ?? 2 "h" output voltage v oh tri-state port v dd = 4.5 v, i oh = ? 0.7 ma 4.1 ? ? v ?l? output voltage v ol3 except xout, p5, p9 v dd = 4.5 v, i ol = 1.6 ma ??0.4 ?l? output current i ol1 except xout, p5, p9 v dd = 4.5 v, v ol = 0.4 v ?1.6? ma i ol3 high current port (p5, p9) v dd = 4.5 v, v ol = 1.0 v ?20? supply current in normal 1, 2 mode i dd v dd = 5.5 v v in = 5.3 v/0.2 v fc = 16 mhz fs = 32.768 khz ?78 supply current in idle 1, 2 mode ?45 supply current in slow 1 mode v dd = 3.0 v v in = 2.8 v/0.2 v fs = 32.768 khz ?1020 a supply current in sleep 0, 1 mode ?612 supply current in stop mode v dd = 5.5 v v in = 5.3 v/0.2 v ?0.510
page 186 20. electrical characteristics 20.4 ad conversion characteristics TMP86CS64AFG 20.4 ad conversi on characteristics note 1: total error includes all error except a quantization error, and is defined as a maximum deviation from the ideal convers ion line. note 2: conversion time is different in recommended value by power supply voltage. about conversion time, please re fer to "register framing". note 3: please use input voltage to ain input pin in limit of v aref f ? v ss . when voltage of range outside is input, conversion value bec omes unsettled and gives affect to other channel conversion value. note 4: analog reference voltage range: ? v aref = v aref ? a vss (v ss = 0 v, 4.5 v v dd 5.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd ? 1.0 ? a vdd v power supply voltage of analog control circuit a vdd v dd a vss v ss analog reference of voltage range (note4) ? v aref v aref ? a vss 3.5 ? v dd analog input voltage v ain v ss ? v aref power supply current of analog reference voltage i ref v dd = a vdd = v aref = 5.5 v v ss = a vss = 0.0 v ?0.61.0ma non linearity error v dd = a vdd = 5.0 v v ss = a vss = 0.0 v v aref = 5.0 v ?? 2 lsb zero point error ?? 2 full scale error ?? 2 to t a l e r r o r ?? 4 (v ss = 0 v, 2.7 v v dd < 4.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd ? 1.0 ? a vdd v power supply voltage of analog control circuit a vdd v dd a vss v ss analog reference of voltage range (note 4) ? v aref v aref ? v ss 2.5 ? v dd analog input voltage v ain v ss ? v aref power supply current of analog reference voltage i ref v dd = a vdd = v aref = 4.5 v v ss = a vss = 0.0 v ?0.50.8ma non linearity error v dd = a vdd = 2.7 v v ss = a vss = 0.0 v v aref = 2.7 v ?? 2 lsb zero point error ?? 2 full scale error ?? 2 to t a l e r r o r ?? 4
page 187 TMP86CS64AFG 20.5 ac characteristics (v ss = 0 v, v dd = 4.5 to 5.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit machine cycle time tcy normal 1, 2 mode 0.25 ? 4 s idle 0, 1, 2 mode slow 1, 2 mode 117.6 ? 133.3 sleep 0, 1, 2 mode high level clock pulse width t wch for external clock operation (xin input) fc = 16 mhz ? 31.25 ? ns low level clock pulse width t wcl high level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low level clock pulse width t wsl (v ss = 0 v, v dd = 2.7 to 4.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit machine cycle time tcy normal 1, 2 mode 0.5 ? 4 s idle 0, 1, 2 mode slow 1, 2 mode 117.6 ? 133.3 sleep 0, 1, 2 mode high level clock pulse width t wch for external clock operation (xin input) fc = 8 mhz ? 62.5 ? ns low level clock pulse width t wcl high level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low level clock pulse width t wsl
page 188 20. electrical characteristics 20.6 recommended oscillating conditions TMP86CS64AFG 20.6 recommended osc illating conditions note 1: to ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will act ually be mounted. note 2: for the resonators to be used with toshiba microcont rollers, we recommend ceramic resonators manufactured by murata manufacturing co., ltd. for details, please visit the website of murata at the following url: http://www.murata.com 20.7 handling precaution - the solderability test conditions for lead-free produc ts (indicated by the suffix g in product name) are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used note: the pass criteron of the above test is as follows: solderability rate until forming 95 % - when using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition. xin xout c 2 c 1 xtin ( 1) high-frequency oscillation (2) low-frequency oscillatio xtout c 2 c 1
page 189 TMP86CS64AFG 21. package dimension p-qfp100-1420-0.65a unit: mm
page 190 21. package dimension TMP86CS64AFG
this is a technical document that de scribes the operating functi ons and electrical specif ications of the 8-bit microcontroller series tlcs-870/c (lsi). toshiba provides a variety of development tools a nd basic software to enable efficient software development. these development tools have specifi cations that support advances in microcomputer hardware (lsi) and can be used extensively. both the hardware and so ftware are supported continuous ly with version updates. the recent advances in cmos lsi production technology have be en phenomenal and microcomputer systems for lsi design are constant ly being improved. the products described in this document may also be revised in the future. be sure to check the latest specific ations before using. toshiba is developing highly integrated, high-perfo rmance microcomputers using advanced mos production technology and especially well proven cmos technology. we are prepared to meet the requests for custom packaging for a variet y of application areas. we are confident that our products can satisfy your application needs now and in the future.