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1/29 ? semiconductor msm80C85AHRS/gs/js genral description the msm80c85ah is a complete 8-bit parallel; central processor implemented in silicon gate c-mos technology and compatible with msm80c85a. it is designed with higher processing speed (max.5 mhz) and lower power consumption compared with msm80c85a and power down mode is provided, thereby offering a high level of system integration. the msm80c85ah uses a multiplexed address/data bus. the address is split between the 8- bit address bus and the 8-bit data bus. the on-chip address latch : of a msm81c55-5 memory product allows a direct interface with the msm80c85ah. features ? power down mode (halt-hold) ? low power dissipation: 50mw(typ) ? single + 3 to + 6 v power supply ? C40 to + 85 c, operating temperature ? compatible with msm80c85a ? 0.8 m s instruction cycle (v cc = 5v) ? on-chip clock generator (with external crystal) ? on-chip system controller; advanced cycle status information available for large system control ? bug operation in msm80c85ah is fixed ? four vectored interrupt (one is non-maskable) plus the 8080a-compatible interrupt. ? serial, in/serial out port ? decimal, binary and double precision arithmetic ? addressing capability to 64k bytes of memory ? ttl compatible ? 40-pin plastic dip(dip40-p-600-2.54): (product name: msm80C85AHRS) ? 44-pin plastic qfj(qfj44-p-s650-1.27): (product name: msm80c85ahjs) ? 44-pin plastic qfp(qfp44-p-910-0.80-2k): (product name: msm80c85ahgs-2k) ? semiconductor msm80C85AHRS/gs/js 8-bit cmos microprocessor e2o0009-27-x2 this version: jan. 1998 previous version: aug. 1996
2/29 ? semiconductor msm80C85AHRS/gs/js functional block diagram intr inta 5.5 6.5 7.5 trap sid sod rst power down temporary register (8) arithmetic logic unit alu(8) instruction register (8) instruction decoder and machine cycle encoding flag (5) flip flops clk gen timing and control control status dma reset address buffer (8) data/address buffer (8) stack pointer (16) program counter (16) register array incrementer/decrementer address latch (16) h reg (8) d reg (8) b reg (8) c reg (8) e reg (8) c reg (8) 8-bit internal data bus x 1 x 2 clk out ready rd wr ale s0 s1 io / m hold hlda reset in reset out a 15 - a 8 address bus ad 7 - ad 0 address/data bus interrupt control serial i/o control accumulator (8) power supply +5v gnd
3/29 ? semiconductor msm80C85AHRS/gs/js pin configuration (top view) 40 pin plastic dip 16 15 14 13 x 1 20 19 18 17 gnd 1 2 3 4 5 6 7 8 9 10 11 12 32 31 30 29 28 27 26 37 38 39 40 36 35 34 33 25 a 8 hold hlda clk(out) reset in ready io/ m s 1 rd wr ale s 0 a 15 a 14 a 13 a 12 a 11 a 10 a 9 24 23 22 21 v cc ad 5 ad 6 ad 7 rst7.5 rst6.5 rst5.5 intr inta ad 0 ad 1 ad 2 ad 3 ad 4 x 2 reset out sod sid trap 44 pin plastic qfp 39 38 37 36 35 34 33 ready io/ m s 1 rd wr nc ale trap rst7.5 rst6.5 rst5.5 intr nc inta 18 19 20 21 22 23 24 ad 4 nc ad 5 ad 6 ad 7 gnd a 8 6 5 4 3 2 1 44 sid sod reset out x 2 x 1 nc 7 8 9 10 11 12 13 32 31 30 29 s 0 a 15 a 14 ad 0 ad 1 ad 2 ad 3 14 15 16 17 a 13 v cc 25 26 27 28 a 9 a 10 a 11 a 12 43 42 41 40 hold hlda clk(out) reset in 44 pin plastic qfj 33 32 31 30 29 28 27 ready io/ m s 1 rd wr ale s 0 trap rst7.5 rst6.5 rst5.5 intr inta ad 0 12 13 14 15 16 17 18 ad 4 ad 5 ad 6 ad 7 gnd v cc a 8 44 43 42 41 40 39 38 sid sod reset out x 2 x 1 nc 1 2 3 4 5 6 7 26 25 24 23 a 15 a 14 a 13 ad 1 ad 2 ad 3 nc 8 9 10 11 a 12 v cc 19 20 21 22 a 9 a 10 a 11 nc 37 36 35 34 hold hlda clk(out) reset in
4/29 ? semiconductor msm80C85AHRS/gs/js msm80c85ah functional pin definition the following describes the function of each pin: a 0 - a 7 (input/output) 3-state a 8 - a 15 (output, 3-state) multiplexed address/data bus: lower 8-bits of the memory address (or i/o address) appear on the bus during the first clock cycle (t state) of a machine cycle. it then becomes the data bus during the second and third clock cycles. address bus: the most significant 8-bits of the memory address or the 8-bits of the i/o address, 3-stated during hold and halt modes and during reset. symbol function ale (output) address latch enable: it occurs during the first clock state of a machine cycle and enables address to get latched into the on-chip latch peripherals. the falling edge of ale is set to guarantee setup and hold times for the address information. the falling edge ale can also be used to strobe the status information ale is never 3-state. s 0 , s 1 , io/ m (output) machine cycle status: io/ m s 1 s 0 states s 1 can be used as an advanced r/w status. io/ m , s 0 and s 1 become valid at the beginning of a machine cycle and remain stable throughout the cycle. the falling edge of ale may be used to latch the state of these lines. rd (output, 3-state) read control: a low level on rd indicates the selected memory or i/o device is to be read that the data bus is available for the data transfer, 3-stated during hold and halt modes and during reset. wr (output, 3-state) write control: a low level on wr indicates the data on the data bus is to be written into the selected memory or i/o location. data is set up at the trailing edge of wr , 3-stated during hold and halt modes and during reset. ready (input) if ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. if ready is low, the cpu will wait an integral number of clock cycles for ready to go high before completing the read or write cycle ready must conform to specified setup and hold times. hold (input) hlda (output) hold acknowledge: indicates that the cpu has received the hold request and that it will relinquish the bus in the next clock cycle. hlda goes low after the hold request is removed. the cpu takes the bus one half clock cycle after hlda goes low. hold indicates that another master is requesting the use of the address and data buses. the cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus transfer. internal processing can continue. the processor can regain the bus only after the hold is removed. when the hold is acknowledged, the address, data, rd , wr , and io/ m lines are 3-stated. and status of power down is controlled by hold. intr (output) interrupt request: is used as a general purpose interrupt. it is sampled on during the next to the last clock cycle of an instruction and during hold and halt states. if it is active, the program counter (pc) will be inhibited from incrementing and an inta will be issued. during this cycle a restart or call instruction can be inserted to jump to the interrupt service routine. the intr is enabled and disabled by software. it is disabled by reset and immediately after an interrupt is accepted. power down mode is reset by intr. inta (output) interrupt acknowledge: is used instead of (and has the same timing as) rd during the instruction cycle after an intr is accepted. rst 5.5 rst 6.5 rst 7.5 (input) restart interrupts: these three inputs have the same timing as intr except they cause an internal restart to be automatically inserted. the priority of these interrupts is ordered as shown in table 1. these interrupts have a higher priority than intr. in addition, they may be individually masked out using the sim instruction. power down mode is reset by these interrupts. trap (input) trap interrupt is a nonmaskable restart interrupt. it is recognized at the same timing as intr or rst 5.5 - 7.5. it is unaffected by any mask or interrupt disable. it has the highest priority of any interrupt. (see table 1.) power down mode is reset by input of trap. 0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 memory write memory read i/o write i/o read opcode fetch io/ m s 1 s 0 states 1 . . . 1 0 1 0 interrupt acknowledge halt = 3-state hold (high impedance) reset = unspecified
5/29 ? semiconductor msm80C85AHRS/gs/js name address branched to (1) when interrupt occurs type trigger rst 7.5 3ch 34h rising edge (latched). high level unitl sampled. rst 6.5 rst 5.5 2ch (2) high level until sampled. high level until sampled. intr trap priority 2 3 4 5 1 24h rising edge and high level unit sampled. table 1 interrupt priority, restart address, and sensitivity notes: (1) the processor pushes the pc on the stack before branching to the indicated address. (2) the address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged. reset in (input) sets the program counter to zero and resets the interrupt enable and hlda flip-flops and release power down mode. the data and address buses and the control lines are 3-stated during reset and because of the asynchronous nature of reset in, the processor's internal registers and flags may be altered by reset with unpredictable results. reset in is a schmitt-triggered input, allowing connection to an r-c network for power-on reset delay. the cpu is held in the reset condition as long as reset in is applied. symbol function reset out (output) indicated cpu is being reset. can be used as a system reset. the signal is synchronized to the processor clock and lasts an integral number of clock periods. x 1 , x 2 (input) x 1 and x 2 are connected to a crystal to drive the internal clock generator. x 1 can also be an external clock input from a logic gate. the input frequency is divided by 2 to give the processor's internal operating frequency. sid (input) serial input data line. the data on this line is loaded into accumulator bit 7 whenever a rim instruction is executed. sod (output) serial output data line. the output sod is set or reset as specified by the sim instruction. v cc + 5 volt supply gnd ground reference. clk (output) clock output for use as a system clock. the period of clk is twice the x 1 , x 2 input period.
6/29 ? semiconductor msm80C85AHRS/gs/js functional description the msm80c85ah is a complete 8-bit parallel central processor. it is designed with silicon gate c-mos technology and requires a single +5 volt supply. its basic clock speed is 5 mhz, thus improving on the present msm80c85a's performance with higher system speed and power down mode. also it is designed to fit into a minimum system of two ic's: the cpu (msm80c85ah), and a ram/io (msm81c55-5) the msm80c85ah has twelve addressable 8-bit register pairs. six others can be used interchangeably as 8-bit registers or 16-bit register pairs. the msm80c85ah register set is as follows: pc 16-bit address 8-bit 6 or 16-bits 3 bc, de, hl sp 16-bit address 5 flags (8-bit space) flags or f program counter acc or a 8-bits accumulator mnemonic contents register general-purpose registers; data pointer (hl) stack pointer flag register the msm80c85ah uses a multiplexed data bus. the address is spilt between the higher 8-bit address bus and the lower 8-bit address/data bus. during the first t state (clock cycle) of a machine cycle the low order address is sent out on the address/data bus. these lower 8-bits may be latched externally by the address latch enable signal (ale). during the rest of the machine cycle the data bus is used for mamory or i/o data. the msm80c85ah provides rd , wr , s 0 , s 1 , and io/ m signals for bus control. an interrupt acknowledge signal ( inta ) is also provided. hold and all interrupts are synchronized with the processor's internal clock. the msm80c85ah also provides serial input data (sid) and serial output data (sod) lines for a simple serial interface. in addition to these features, the msm80c85ah has three maskable, vector interrupt pins, one nonmaskable trap interrupt and power down mode with halt and hold. interrupt and serial i/o the msm80c85ah has 5 interrupt inputs: intr, rst 5.5 rst 6.5, rst 7.5, and trap. intr is identical in function to the 8080a int. each of the three restart inputs, 5.5, 6.5, and 7.5, has a programmable mask. trap is also a restart interrupt but it is nonmaskable. the three maskable interrupts cause the internal execution of restart ( saving the program counter in the stack branching to the restart address) it the interrupts are enable and if the interrupt mask is not set. the nonmaskable trap causes the internal execution of a restart vector independent of the state of the interrupt enable or masks. (see table 1.) there are two different types of inputs in the restart interrupt. rst 5.5 and rst 6.5 are high level-sensitive like intr (and int on the 8080a) and are recognized with the same timing as intr. rst 7.5 is rising edge-sensitive.
7/29 ? semiconductor msm80C85AHRS/gs/js for rst 7.5, only a pulse is required to set an internal flip-flop which generates the internal interrupt request. the rst 7.5 request flip-flop remains set until the request is serviced. then it is reset automatically, this flip-flop may also be reset by using the sim instruction or by issuing a reset in to the msm80c85ah. the rst 7.5 internal flip-flop will be set by a pulse on the rst 7.5 pin even when the rst 7.5 interrupt is masked out. the interrupts are arranged in a flixed priority that determines which interrupt is to be recognized if more than one is pending, as follows: trap-highest priority, rst 7.5, rst 6.5, rst 5.5, intr-lowest priority. this priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt. rst 5.5 can interrupt an rst 7.5 routine if the interrupt are re-enabled before the end of the rst 7.5 routine. the trap interrupt is useful for catastrophic evens such as power failure or bus error. the trap input is recognized just as any other interrupt but has the highest priority. it is not affected by any flag or mask. the trap input is both edge and level sensitive. the trap input must go high and remain high until it is acknowledged. it will not be recognized again until it goes low, then high again. this avoids any false triggering due to noise or logic glitches. figure 3 illustrates the trap interrupt request circuitry within the msm80c85ah. note that the servicing of any interrupt (trap, rst 7.5, rst 6.5, rst 5.5,intr) disables all future interrupts (except traps) until an el instruction is executed. the trap interrupt is special in that it disables interrupts, but preserves the previous interrupt enable status. performing the first rim instruction following a trap interrupt allows you to determine whether interrupts were enabled or disabled prior to the trap. all subsequent rim instructions provide current interrupt enable status. performing a rim instruction following intr or rst 5.5-7.5 will provide current interrupt enable status, revealing that interrupts are disabled. the serial i/o system is also controlled by the rim and sim instructions. sid is read by rim, and sim sets the sod data. inside the msm80c85ah external trap interrupt request trap schmitt trigger reset in reset trap interrupt request +5 v d clk d q f/f clear trap f.f internal trap acknowledge fi g ure 3 tra p and reset in circuit
8/29 ? semiconductor msm80C85AHRS/gs/js driving the x 1 and x 2 inputs you may drive the clock inputs of the msm80c85ah with a crystal, or an external clock source. the driving frequency must be at least 1 mhz, and must be twice the desired internal clock frequency; hence, the msm80c85ah is operated with a 6 mhz crystal (for 3 mhz clock). if a crystal is used, it must have the following characteristics: parallel resonance at twice the clock frequency desired c l (load capacitance) 30 pf c s (shunt capacitance) 7 pf r s (equivalent shunt resistance) 75 ohms drive level: 10 mw frequency tolerance: 0.05% (suggested) note the use of the capacitors between x 1 , x 2 and ground. these capacitors are required to assure oscillator startup at the correct frequency. figure 4 shows the recommended clock driver circuits. note in b that a pull-up resistor is required to assure that the high level voltage of the input is at least 4 v. for driving frequencies up to and including 6 mhz you may supply the driving signal to x, and leave x 2 open-circuited (figure 4b). to prevent self-oscillation of the msm80c85ah, be sure that x 2 is not coupled back to x 1 through the driving circuit. note: since the constant values may vary depending on oscillator, consult the manufacturer of the oscillator used when designing a circuit. figure 4 clock driver circuits x 1 c int = 15 pf x 2 c 1 c 2 x 1 x 2 * x 2 left floating v ih > 0.8 v cc high time > 40 ns low time > 40 ns 33 pf capacitor required for crystal frequency 10 to 6.25 mhz 50 pf capacitor required for crystal frequency 6.25 to 4 mhz 100 p f ca p acitor re q uired for cr y stal fre q uenc y <4 mhz msm80c85ah a. quartz crystal clock driver b. 1 - 10 mhz input frequency external clock drive circuit *
9/29 ? semiconductor msm80C85AHRS/gs/js basic system timing the msm80c85ah has a multiplexed data bus. ale is used as a strobe to sample the lower 8-bits of address on the data bus. figure 5 shows an instruction fetch, memory read and i/o write cycle (as would occur during processing of the out instruction). note that during the i/ o write and read cycle that the i/o port address is copied on both the upper and lower half of the address. there are seven possible types of machine cycles. which of these seven takes place is defined by the status of the three status lines (io/ m , s 1 , s 0 ) and the three control signals ( rd , wr ,and inta ). (see table 2.) the status line can be used as advanced controls (for device selection, for example), since they become active at the t 1 state, at the outset of each machine cycle. control lines rd and wr become active later, at the time when the transfer of data is to take place, so are used as command lines. a machine cycle normally consists of three t states, with the exception of opcode fetch, which normally has either four or six t states (unless wait or hold states are forced by the receipt of ready or hold inputs). any t state must be one of ten possible states, shown in table 3. memory read o o memory write i/o read 1 1 i/o write (mr) opcode fetch 0 (of) (mw) (ior) acknowledge of intr 1 (ina) (iow) bus idle 0 1 ts 1 0 1 0 1 1 1 1 0 o 1 o 1 1 1 0 1 0 o 1 o 1 0 1 1 1 ts 1 0 1 0 1 1 1 1 ts 1 1 1 1 1 io/ m s 1 s 0 rd wr inta machine cycle status control 0 1 1 1 (bi): dad ack. of rst, trap halt table 2 msm80c85ah machine cycle chart
10/29 ? semiconductor msm80C85AHRS/gs/js 0 t 2 t wait t 3 t 4 t 1 t 5 ts ts 1 1 1 1 1 1 0 0 0 0 1 (1) 0 a 8 C a 15 ad 0 C ad 7 rd , wr inta ale machine state status & buses control t 6 t reset ts ts t halt t hold ts ts ts ts ts 1 ts ts ts 1 1 1 1 0 0 0 1 1 0 (2) 0 (2) s 1 , s 0 io/ m 1 0 0 (2) ts ts ts table 3 msm80c85ah machine state chart 0 = logic "0" 1 = logic "1" ts = high impedance = unspecified notes: (1) ale not generated during 2nd and 3rd machine cycles of dad instruction. (2) io/ m = 1 during t 4 - t 6 of ina machine cycle. t 1 pc h (high order address) (pc+1) h a 8-15 t 2 t 3 t 4 t 1 t 2 t 3 t 1 t 2 m 3 m 2 m 1 t 3 t ad 0-7 ale clk rd wr status io/ m io port io port pc l s 1 s 0 (fetch) 10 (read) 01 write 11 (low order address) data from memory (instruction) data from memory (i/o port address) data to memory or peripheral (pc+1) l1 figure 5 msm80c85ah basic system timing
11/29 ? semiconductor msm80C85AHRS/gs/js power down mode the msm80c85ah is compatible with the msm80c85a in function and power down mode. this reduces power consumption further. there are two methods available for starting this power down mode. one is through software control by using the halt command and the other is under hardware control by using the pin hold. this mode is released by the hold, reset, and interrupt pins (trap, rst7.5, rst6.5 rst5.5, or intr). (see table 4.) since the sequence of halt, hold, reset, and interrupt is compatible with msm80c85a, every the power down mode can be used with no special attention. start by means of halt command start by means of hold pin released by using pins reset and interrupt (not by pin hold) released by using reset and hold pins (not by interrupt pins) table 4 power down mode releasing method (1) start by means of halt command (see figures 6 and 7.) the power down mode can be started by executing the halt command. at this time, the system is put into the hold status and therefore the power down mode cannot be released even when the hold is released later. in this case, the power down mode can be released by means of the reset or interrupt. (2) start by means of hold pin (see figure 8.) during the execution of commands other than the halt, the power down mode is started when the system is put into hold status by means of the hold pin. since no interrupt works during the execution of the hold, the power down mode cannot be released by means of interrupt pins. in this case, the power down mode can be released either by means of the reset pin or by releasing the hold status by means of hold pin.
12/29 ? semiconductor msm80C85AHRS/gs/js t 1 clk (out) ale address t 2 t 3 t 4 t 1 m 1 m 2 t 1 t 2 m 1 t hlt t reset address address ad 0-7 cpu mode reset in run run 76h power down fi g ure 6 started b y halt and released b y reset in t 1 clk (out) ale t 2 t 3 t 4 m 1 t 1 t 2 m 1 t hold hold cpu mode run run hlda power down fi g ure 8 started and released b y hold t 1 clk (out) ale t 2 t 3 t 4 t 1 m 1 m 2 t 1 t 2 m 1 t hlt cpu mode rst5.5 run run power down figure 7 started by halt and released by rst5.5
13/29 ? semiconductor msm80C85AHRS/gs/js absolute maximum ratings C55 - +150 msm80C85AHRS power supply voltage v cc C0.5 - 7 v input voltage v in C0.5 - v cc + 0.5 v output voltage v out C0.5 - v cc + 0.5 v storage temperature t stg c power dissipation p d 0.7 w parameter units symbol with respect to gnd ta = 25c condition limits msm80c85ahgs msm80c85ahjs 1.0 1.0 operating range limits power supply voltage v cc 3 - 6 v operating temperature t op C40 - +85 c parameter unit symbol recommended operating conditions dc characteristics "l" v ilr C0.3 +0.8 typ. power supply voltage v cc 5v t op +25 "l" input voltage v il "h" output voltage v ih min. 4.5 C40 C0.3 2.2 max. 5.5 +85 +0.8 v cc +0.3 parameter unit symbol c v v operating temperature v v ihr 3.0 v cc +0.3 v reset in input voltage "h" reset in input voltage typ. max. "l" output voltage v ol 0.4 v "h" output voltage v oh v v parameter unit symbol min. 3.0 v cc - 0.4 i ol = 2.5 ma i oh = C2.5 ma i oh = C100 m a conditions v cc = 4.5 v - 5.5 v ta = C40c - +85c input leak current i li 10 m a output leak current i lo 10 m a C10 C10 0 v in v cc 0 v out v cc t cyc = 200 ns c l = 0 pf at reset operating supply current i cc 10 20 ma 510ma t cyc = 200 ns c l = 0 pf at power down mode
14/29 ? semiconductor msm80C85AHRS/gs/js ac characteristics parameter symbol condition min. max. unit cly cycle period t cyc t cyc =200 ns cl=150 pf 200 2000 ns cly low time t 1 40 ns cly high time t 2 70 ns cly rise and fall time t r , t f 30ns x 1 rising to clk rising t xkr 25 120 ns x1 rising to ckk falling t xkf 30 150 ns a 8 ~ 15 valid to leading edge of control (1) t ac 115 ns ad 0 ~ 7 valid to leading edge of control t acl 115 ns ad 0 ~ 15 valid data in t ad 350 ns address float after leading edge of rd inta t afr 0ns a 8 ~ 15 valid before trailing edge of ale (1) t al 50 ns ad 0 ~ 7 valid before trailing edge of ale t all 50 ns ready valid from address valid t ary 100 ns address (a 8 ~ 15 ) valid after control t ca 60 ns width of control law ( rd , wr , inta )t cc 230 ns trailing edge of control to leading edges of ale t cl 25 ns data valid to trailing edge of wr t dw 230 ns hlda to bus enable t habe 150 ns bus float after hlda t habf 150 ns hlda valid to trailing edge of clk t hack 40 ns hold hold time t hdh 0ns hold step up time to trailing edge of clk t hds 120 ns intr hold time t inh 0ns intr, rst and trap setup time to falling edge of clk t ins 150 ns address hold time after ale t la 50 ns trailing edge of ale to leading edge of control t lc 60 ns ale low during clk high t lck 50 ns ale to valid data during read t ldr 270 ns ale to valid data during write t ldw 140 ns ale width t ll 80 ns ale to ready stable t lry 30ns trailing edge of rd to re-enabling of address t rae 90 ns rd (or inta) to valid data t rd 150 ns control trailing edge to leading edge of next control t rv 220 ns data hold time after rd inta (7) t rdh 0ns ready hold time t ryh 0ns ready setup time to leading edge of clk t rys 100 ns data valid after trailing edge of wr t wd 60 ns leading edge of wr to data vaild t wdl 20ns (ta = C40c ~ 85c, v cc = 4.5 v ~ 5.5 v)
15/29 ? semiconductor msm80C85AHRS/gs/js notes: (1) a 8 - a 15 address specs apply to io/ m , s 0 and s 1 . (2) test condition: t cyc =200 ns c l =150 pf (3) for all output timing where c l =150 pf use the following correction factors: 25 pf c l < 150 pf : C0.10ns/pf 150 pf < c l 200 pf : +0.30ns/pf (4) output timings are measured with purely capacitive load. (5) all timings are measured to output voltage v l =0.8 v, v h =2.2 v, and 1.5 v with 10 ns rise and fall time on inputs. (6) to calculate timing specifications at other values of t cyc use table 7. (7) data hold time is guaranteed under all loading conditions. 2.4 test points 2.2 2.2 0.8 0.8 0.45 input waveform for a.c. tests: (1/2)t - 50 t al min (ta = -40c - +85c, v cc = 4.5 v - 5.5 v, c l = 150 pf) (1/2)t - 50 t la min (1/2)t - 20 t ll min (1/2)t - 50 t lck min (1/2)t - 40 t lc min (5/2+n)t - 150 t ad max (3/2+n)t - 150 t rd max (1/2)t - 10 t rae min (1/2)t - 40 t ca min (3/2+n)t -70 t dw min (1/2)t - 40 t wd min (3/2+n)t - 70 t cc min (1/2)t - 75 t cl min (3/2)t - 200 t ary max (1/2)t - 60 t hack min (1/2)t + 50 t habf max (1/2)t + 50 (2/2)t - 85 t habe max t ac min (1/2)t - 60 t 1 min (1/2)t - 30 t 2 min (3/2)t - 80 t rv min t ldr max msm80c85ah table 7 bus timing specification as a t cyc dependent note: n is equal to the total wait states. t = t cyc (2+n)t -130
16/29 ? semiconductor msm80C85AHRS/gs/js x 1 input clk output t xkr t 1 t xkf t cyc t r t 2 t f figure 6 clock timing waveform read operation clk a 8 -a 15 ad 0 -ad 7 ale rd / inta t 1 t 2 t 3 t 1 t lck t ll t al address t afr t lc t ac address t la t ad t ldr t rd t cc t ca t rae t rdh t cl data in write operation clk t 1 t ldw address t wdl data out a 8 -a 15 ad 0 -ad 7 ale wr t 2 t 3 t 1 address t lck t la t lc t ll t al t ac t dw t cc t wd t cl t ca
17/29 ? semiconductor msm80C85AHRS/gs/js clk a 8 ~ a 15 ad 0 ~ ad 7 ale rd / inta ready t 1 t 2 t wait t 3 t 1 t lck t ll t al address t afr t cl t ac t ary t lry t rys t ryh address t la t ad t ldr t rd t cc t ca t rae t rdh t cl data in note: ready must remain stable during setup and hold times. figure 7 msm80c85ah bus timing, with and without wait read operation with wait cycle (typical)C same ready timing applies to write operation clk t 2 (address, controls) t hds hold hlda bus t 3 t hold t hold t 1 t hdh t habf t hack t habe fi g ure 8 msm80c85ah hold timin g hold operation
18/29 ? semiconductor msm80C85AHRS/gs/js t 1 call inst a 8-15 t ins t 2 t 4 t 5 t 6 t hold t 1 t 2 ad 0-7 ale rd inta hold hlda intr bus floating (1) t inh t hds t hdh t hack t habf t habe note: (1) io/ m is also floating during this time. fi g ure 9 msm80c85ah interru p t and hold timin g
19/29 ? semiconductor msm80C85AHRS/gs/js move, load, and store movr1 r2 mov m r mov r m mvi r mvi m lxi b lxi d lxi h lxi sp stax b stax d ldax b ldax d sta lda shld lhld xchg mnemonic description instruction code (1) clock (2) cycles 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 d 1 d d 1 0 0 1 1 0 0 0 0 1 1 1 1 1 d 1 d d 1 0 1 0 1 0 1 0 1 1 1 0 0 0 d 0 d d 0 0 0 0 0 0 0 1 1 0 1 0 1 1 s s 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 s s 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 s s 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 4 7 7 7 10 10 10 10 10 7 7 7 7 13 13 16 16 4 move register to register move register to memory move memory to register move immediate register move immediate memory load immediate register pair b & c load immediate register pair d & e load immediate register pair h & l load immediate stack pointer store a indirect store a indirect load a indirect load a indirect store a direct load a direct store h & l direct load h & l direct exchange d & e h & l registers stack ops push b push d push h push psw pop b pop d pop h pop psw xthl sphl 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 12 12 12 12 10 10 10 10 16 6 push register pair b & c on stack push register pair d & e on stack push register pair h & l on stack push a and flags on stack pop register pair b & c off stack pop register pair d & e off stack pop register pair h & l off stack pop a and flags off stack exchange top of stack h & l h & l to stack pointer jump jmp jc jnc jz jnz jp jm jpe jpo pchl 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 10 7/10 7/10 7/10 7/10 7/10 7/10 7/10 7/10 6 jump unconditional jump on carry jump on no carry jump on zero jump on no zero jump on positive jump on minus jump on parity even jump on parity odd h & l to program counter call call cc cnc cz cnz cp cm cpe cpo 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 18 9/18 9/18 9/18 9/18 9/18 9/18 9/18 9/18 call unconditional call on carry call on no carry call on zero call on no zero call on positive call on minus call on parity even call on parity odd table 8 instruction set summary
20/29 ? semiconductor msm80C85AHRS/gs/js return ret rc rnc rz rnz rp rm rpe rpo mnemonic description instruction code (1) clock (2) cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 6/12 6/12 6/12 6/12 6/12 6/12 6/12 6/12 return return on carry return on no carry return on zero return on no zero return on positive return on minus return on parity even return on parity odd restart rst 11aaa111 12 restart input/output in out 1 1 1 1 0 0 1 1 1 0 0 0 1 1 1 1 10 10 input output increment and decrement inr r dcr r inr m dcr m inx b inx d inx h inx sp dcx b dcx d dcx h dcx sp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d d 1 1 0 0 1 1 0 0 1 1 d d 1 1 0 1 0 1 0 1 0 1 d d 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 4 4 10 10 6 6 6 6 6 6 6 6 increment register decrement register increment memory decrement memory increment b & c registers increment d & e registers increment h & l registers increment stack pointer decrement b & c decrement d & e decrement h & l decrement stack pointer add add r adc r add m adc m adi aci dad b dad d dad h dad sp 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 s s 1 1 1 1 0 0 0 0 s s 1 1 1 1 0 0 0 0 s s 0 0 0 0 1 1 1 1 4 4 7 7 7 7 10 10 10 10 add register to a add register to a with carry add memory to a add memory to a with carry add immediate to a add immediate to a with carry add b & c to h & l add d & e to h & l add h & l to h & l add stack pointer to h & l subtract sub r sbb r sub m sbb m sui sbi 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 1 0 1 s s 1 1 1 1 s s 1 1 1 1 s s 0 0 0 0 4 4 7 7 7 7 subtract register from a subtract register from a with borrow subtract memory from a subtract memory from a with borrow subtract immediate from a subtract immediate from a with borrow table 8 instruction set summary cont'd
21/29 ? semiconductor msm80C85AHRS/gs/js logical ana r xra r ora r cmp r ana m xra m ora m cmp m ani xri ori cpi mnemonic description instruction code (1) clock (2) cycles 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 s s s s 1 1 1 1 1 1 1 1 s s s s 1 1 1 1 1 1 1 1 s s s s 0 0 0 0 0 0 0 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 4 4 4 4 7 7 7 7 7 7 7 7 add register with a exclusive or register with a or register with a compare register with a and memory with a exclusive or memory with a or memory with a compare memory with a and immediate with a exclusive or immediate with a or immediate with a compare immediate with a rotate rlc rrc ral rar 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 4 4 rotate a left rotate a right rotate a left through carry rotate a right through carry specials cma stc cmc daa 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 4 4 4 4 complement a set carry complement carry decimal adjust a control ei di nop hlt rim sim 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 1 1 0 0 0 0 4 4 4 5 4 4 enable interrupts disable interrupts no-operation halt (power down) read interrupt mask set interrupt mask table 8 instruction set summary cont'd notes: (1) ddd or sss. b 000. c 001. d 010. e 011. h 100. l 101. memory 110. a 111. (2) two possible cycle times, (6/12) indicate instruction cycles dependent on condition flags. precautions for operation (1) when the oscillation circuit is to be used, keep the res input low until the oscillation is sufficiently stabilized after power is turned on. (2) when power is turned on, the output level (sod etc.) is unknown before the equipment is reset. (3) bug of msm80c85aC2 at power down has fixed. (4) because spike noise would be output on hlda, reset out and clk pins, depending on the customers condition of usage; please take into account this issue at system board design.
22/29 ? semiconductor msm80C85AHRS/gs/js supplementary explanation (1) sim instruction: the execution of the sim instruction uses the contents of the accumulator to mask msm80c85ahs interrupts. accumulator setting value r7.5 (reset interrupt 7.5 flip-flop): when this bit is set to 1, the edge detecting flip-flop of rst 7.5 interrupt is reset. mse (mask set enable): when this bit is set to 1, the interrupt mask bits are valid. m7.5 (mask rst7.5): when this bit is set to 1 and mse bit is set to 1, rst7.5 interrupt is masked. m6.5 (mask rst6.5): when this bit is set to 1 and mse bit is set to 1, rst6.5 interrupt is masked. m5.5 (mask rst5.5): when this bit is set to 1 and mse bit is set to 1, rst 5.5 interrupt is masked. bit 7 6 5 r7.5 4 mse 3 m7.5 2 m6.5 1 m5.5 0 (2) rim instruction: when the contents of the accumulator are read out after rim instruction has been executed, msm80c85ah interrupt status can be known. accumulator reading value bit 7 17.5 6 16.5 5 15.5 4 ie 3 m7.5 2 m6.5 1 m5.5 0 17.5 (pending rst7.5): when rst7.5 interrupt is pending, "1" is read out. 16.5 (pending rst6.5): when rst6.5 interrupt is pending, "1" is read out. 15.5 (pending rst5.5): when rst5.5 interrupt is pending, "1" is read out. ie (interrupt enable flag): when interrupt is enable, "1" is read out. m7.5 (mask rst7.5): when rst7.5 interrupt is masked, "1" is read out. m6.5 (mask rst6.5): when rst6.5 interrupt is masked, "1" is read out. m5.5 (mask rst5.5): when rst5.5 interrupt is masked ,"1" is read out.
23/29 ? semiconductor msm80C85AHRS/gs/js notice on replacing low-speed devices with high-speed devices the conventional low speed devices are replaced by high-speed devices as shown below. when you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. high-speed device (new) low-speed device (old) remarks m80c85ah m80c85a/m80c85a-2 8bit mpu m80c86a-10 m80c86a/m80c86a-2 16bit mpu m80c88a-10 m80c88a/m80c88a-2 8bit mpu m82c84a-2 m82c84a/m82c84a-5 clock generator m81c55-5 m81c55 ram.i/o, timer m82c37b-5 m82c37a/m82c37a-5 dma controller m82c51a-2 m82c51a usart m82c53-2 m82c53-5 timer m82c55a-2 m82c55a-5 ppi
24/29 ? semiconductor msm80C85AHRS/gs/js differences between msm80c85ah and msm80c85a/msm80c85a-2 1) manufacturing process 2) functions 3) electrical characteristics 3-1) operating conditions 3-2) dc characteristics item msm80c85a msm80c85a-2 msm80c85ah manufacturing process 3 m si-cmos 2.5 m si-cmos 2 m si-cmos notes: "at res'' means ''at reset time'' and ''in pd'' means ''in power down mode''. as shown above, the v ol and v oh ranges the msm80c85ah contain those of the msm80c85a/ msm80c85a-2. although the supply current range (at a power failure) of the msm80c85ah does not contain that of the msm80c85a-2, this does not affect the actual use of the msm80c85ah. 3-3) ac characteristics the ac characteristics (5 mhz) of the msm80c85ah satisfy that (3 mhz) of the msm80c85a. the msm80c85ah also satisfies that (5mhz) of the msm80c85a. parameter msm80c85a msm80c85a-2 msm80c85ah power supply voltage 4 to 6 v 3 to 6 v 3 to 6 v symbol v cc item msm80c85a msm80c85a-2 msm80c85ah power-down function not provided provided (but may malfunction when hold is used) provided (the malfunction has been removed.) address output during t4 to t6 cycles undefined (compatible with intel devices) not fixed the contents of data in t3 cycle are retained (for low power consumption). parameter msm80c85a msm80c85a-2 msm80c85ah ''l''level output voltage 0.45 v maximum (+2 ma) 0.45 v maximum (+2 ma) 0.40 v maximum (+2.5 ma) symbol v ol ''h''level output voltage 2.4 v minimum (-400 m a) 2.4 v minimum (-400 m a) 3.0 v maximum (-2.5 ma) v oh ''h''level output voltage 4.2 v minimum (-40 m a) 4.2 v minimum (-40 m a) v cc -0.2 v minimum (-100 m a) v oh supply current (at res) 22 ma maximum (@3 mhz) 20 ma maximum (@5 mhz) 20 ma maximum (@5 mhz) i cc supply current (in pd) none 7 ma maximum (@5 mhz) 10 ma maximum (@5 mhz) i cc
25/29 ? semiconductor msm80C85AHRS/gs/js ac charasteristics notes: the italicized or underlined values indicate that they are different from those of the msm80c85ah. msm80c85a symbol msm80c85a-2 msm80c85ah 320 ns t cyc 200 ns 200 ns 80 ns t 1 40 ns 40 ns 120 ns t 2 70 ns 70 ns 30 ns t xkr 25 ns 25 ns 270 ns t ac 115 ns 115 ns 240 ns t acl 115 ns 115 ns 575 ns t ad 350 ns 115 ns t al 50 ns 50 ns 90 ns t all 50 ns 50 ns 220 ns t ary 100 ns 100 ns 120 ns t ca 60 ns 60 ns 400 ns t cc 230 ns 230 ns 50 ns t cl 25 ns 25 ns 420 ns t dw 230 ns 230 ns 210 ns t habe 150 ns 150 ns 210 ns t habf 150 ns 150 ns 110 ns t hack 40 ns 40 ns 170 ns t hds 120 ns 120 ns 160 ns t ins 150 ns 150 ns 100 ns t la 50 ns 50 ns 130 ns t lc 60 ns 60 ns 100 ns t lck 50 ns 50 ns 460 ns t ldr 270 ns 200 ns t ldw 140 ns 140 ns 140 ns t ll 80 ns 80 ns 110 ns t lry 30 ns 30 ns 150 ns t rae 90 ns 90 ns 300 ns t rd 150 ns 150 ns 400 ns t rv 220 ns 220 ns 100 ns t wd 60 ns 60 ns 40 ns t wdl 20 ns 20 ns min min min min max min max min min max min min min min min max min min min min min min max max min max min max min max min 330 ns 250 ns
26/29 ? semiconductor msm80C85AHRS/gs/js 4) other notes 1) as the msm80c85ah employs the 2 m process, its noise characteristics may be a little different from those of the msm80c85a. when devices are replaced for upgrading, it is recommended to perform noise evaluation. especially, hlda, resout, and clkout pins must be evaluated. 2) the msm80c85ah basically satisfies the characteristics of the msm80c85a-2 and the msm80c85a, but their timings are a little different, therefore, when critical timing is required in designing, it is recommended to evaluate operating margins at various temperatures and voltages.
27/29 ? semiconductor msm80C85AHRS/gs/js (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). dip40-p-600-2.54 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 6.10 typ.
28/29 ? semiconductor msm80C85AHRS/gs/js (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfj44-p-s650-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin cu alloy solder plating 5 m m or more 2.00 typ. mirror finish
29/29 ? semiconductor msm80C85AHRS/gs/js (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.41 typ. qfp44-p-910-0.80-2k mirror finish

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