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cmx7131/cmx7141 digital pmr processor dpmr/pmr446 ? datasheet advance information 7131/7141fi - 5.x: dpmr and analogue fm baseband data processor with auxiliary system clocks, adcs and dacs features o analogue pmr ? 300hz hpf ? 12.5 and 25 khz channel filters ? pre - emphasis, de - emphasis, limiter ? selectable compander and scrambler ? ctcss and dcs o additional features ? 2 auxiliary adcs (4 multiplexed inputs) ? 4 auxiliary dacs ? 2 auxiliary system clock outputs ? tx outputs for two - point or i/q modulation ? 2 rf synthesisers (cmx7131 only) o digital pmr ? dpmr (etsi ts 102 490) compliant ? air inte rface physical layer (layer 1) ? air interface data link layer (layer 2) o vocoder connectivity ? vocoder management and control (ralcwi vocoders cmx608 and cmx618) ? vocoder data transport (third - party vocoders e.g. ambe3000) o 4fsk modem ? 4.8kbps data rate ? soft - d ecision data output option ? afsd (automated frame sync detection) o c - bus serial interface to host controller o flexible powersave modes o low - power (3.3v) operation o available in small lqfp or vqfn packages cml microcircuits communication semiconductors cmx 7131 cmx 7141 digital pmr processor modulator rf discriminator host c system clock 1 system clock 2 ralcwi vocoder cmx 618 reference clock dac outputs adc inputs 3 . 3 v built on firmasic ? technology gpio tx enable rx enable tx pa ramp rf synthesiser 1 rf synthesiser 2 cmx 7131 only third - party vocoder or sub - audio signalling datasheet user manual this document contains :
digital pmr processor cmx7131/cmx7141 ? 1 brief description the 7131/7141fi - 5.x function image? (fi) implements a half - duplex 4fsk modem and a large proportion of the dpmr air interface, data link and call control layers. in conjunction with a suitable host and a limiter/discriminato r based rf transceiver, a compact, low cost, low power digital pmr radio conforming to etsis dpmr standard ts 102 490 can be realised. dual mode, analogue/digital pmr operation can also be achieved with the cmx7131/cmx7141 . both initial services and facilities (isf) and configured services and facilities (csf) configurations are supported, including built - in support for bcd addressing modes. the device is also compatible with etsis dpmr standard ts 102 658 for mo de 1 operation. the embedded functionality of the cmx7131/cmx7141 (7131/7141fi - 5.x), managing voice and data systems autonomously including cmx6x8 vocoder control (via the auxiliary spi/c - bus interface), minimises host microcontroller interactions enabling the lowest operating power and therefore the longest battery life for a dpmr radio. the cmx7131/cmx7141 can also provide audio codec functionality for vocoders under dir ect host control. the device utilises cmls proprietary firmasic ? component technology. on - chip sub - systems are configured by a function image?: this is a data file that is uploaded during device initialisation and defines the device's function and feature set. the function image? can be loaded automatically from an external serial memory or host controller over the built - in c - bus serial interface. the device's functions and features may be enhanced by subsequent function image? releases, facilitating in - t he - field upgrades. this document refers specifically to the features provided by function image ? 7131/7141fi - 5.0. other features include two auxiliary adcs with four selectable inputs and four auxiliary dac interfaces (with an optional ramdac on the first dac output, to facilitate transmitter power ramping). additionally the cmx7131 features two on - chip rf synthesisers, with easy rx/tx frequency changeover. the cmx7141 is identical in functionality to the cmx7131 with the exception that the two on - chip rf s ynthesisers have been deleted, which enables it to be supplied in a smaller package. this document refers to both parts, unless otherwise stated. the device has flexible powersaving modes and is available in both lqfp and vqfn packages. note that text sho wn in pale grey indicates features that will be supported in future versions of the function image?. this datasheet is the first part of a two - part document comprising datasheet and user manual: the user manual can be obtained by registering your interest in this product with your local cml representative. ambe 3000 is a registered trademark of digital voice systems inc. dpmr is a registered trademark of the dpmr mou
digital pmr processor cmx7131/cmx7141 ? contents section page 1 brief description ................................ ................................ ................................ ...................... 2 1.1 history ................................ ................................ ................................ ........................... 5 2 block diagram ................................ ................................ ................................ .......................... 7 3 sign al list ................................ ................................ ................................ ................................ . 8 3.1 signal definitions ................................ ................................ ................................ ........ 10 4 external components ................................ ................................ ................................ ............ 11 4.1 recommended external components ................................ ................................ ....... 13 4.2 pcb layout guidelines and power supply decoupling ................................ .............. 14 5 general description ................................ ................................ ................................ ............... 16 5.1 7131/7141 fi - 5.x features ................................ ................................ ......................... 16 5.2 system design ................................ ................................ ................................ ............ 17 5.2.1 implementation using the cmx6x8 ................................ ................................ ...... 18 5.2.2 implementing with third - party vocoders ................................ .............................. 19 5.2.3 data transfer ................................ ................................ ................................ ....... 20 5.2.4 rssi measurement ................................ ................................ .............................. 20 5.2.5 serial memory connection ................................ ................................ ................... 20 5.3 dpmr modem description ................................ ................................ .......................... 20 5.3.1 modulation ................................ ................................ ................................ ............ 20 5.3.2 internal data processing ................................ ................................ ...................... 22 5.3.3 frame sync det ection and demodulation ................................ ........................... 23 5.3.4 fec and coding ................................ ................................ ................................ ... 26 5.3.5 voice coding ................................ ................................ ................................ ........ 26 5.3.6 radio performance requirements ................................ ................................ ....... 26 5.4 analogue pmr description ................................ ................................ ......................... 26 5.4.1 sub - audio processing ................................ ................................ .......................... 26 5.4.2 voice processing ................................ ................................ ................................ . 26 6 detailed descriptions ................................ ................................ ................................ ............ 33 6.1 xtal frequency ................................ ................................ ................................ ............ 33 6.2 host interface ................................ ................................ ................................ ............. 33 6.2.1 c - bus operation ................................ ................................ ................................ . 33 6.3 function image ? loa ding ................................ ................................ .......................... 35 6.3.1 fi loading from host controller ................................ ................................ ........... 35 6.3.2 fi loading from serial memory ................................ ................................ ............ 37 6.4 cmx618/cmx608 interface ................................ ................................ ........................ 38 6.5 dvsi vocoder interface ................................ ................................ .............................. 39 6.6 device control ................................ ................................ ................................ ............ 40 6.6.1 general notes ................................ ................................ ................................ ...... 40 6.6.2 interrupt operation ................................ ................................ ............................... 40 6.6.3 signal routing ................................ ................................ ................................ ...... 41 6.6.4 modem control ................................ ................................ ................................ ..... 41 6.6.5 tx mode dpmr ................................ ................................ ................................ .... 42 6.6.6 tx mode prbs ................................ ................................ ................................ .... 42
digital pmr processor cmx7131/cmx7141 ? 6.6.7 tx mode preamble ................................ ................................ ............................... 42 6.6.8 tx mode mod set - up ................................ ................................ ............................ 43 6.6.9 tx mode an alogue ................................ ................................ ............................... 43 6.6.10 rx mode dpmr ................................ ................................ ................................ .... 43 6.6.11 rx mode eye ................................ ................................ ................................ ........ 43 6.6.12 rx mode analogue ................................ ................................ ............................... 43 6.6.13 data transfer ................................ ................................ ................................ ....... 43 6.6.14 cmx6x8 pass - through mode ................................ ................................ ............... 44 6.7 dpmr formatted operation ................................ ................................ ....................... 44 6.7.1 operating modes and addressing ................................ ................................ ........ 44 6.7.2 isf addressing ................................ ................................ ................................ ..... 45 6.7.3 csf addressing ................................ ................................ ................................ ... 45 6.7.4 tx mode (dpmr formatted) ................................ ................................ ................. 45 6.7.5 rx mode (dpmr forma tted) ................................ ................................ ................. 49 6.7.6 slow data ................................ ................................ ................................ ............. 50 6.8 squelch operation ................................ ................................ ................................ ...... 51 6.9 gpio pi n operation ................................ ................................ ................................ .... 51 6.10 auxiliary adc operation ................................ ................................ ............................. 52 6.11 auxiliary dac/ramdac operation ................................ ................................ ............ 52 6.12 rf synthesiser (cmx7131 only) ................................ ................................ ................ 53 6.13 digital system clock generators ................................ ................................ ................ 56 6.13.1 main clock operation ................................ ................................ ........................... 57 6.13.2 system clock operation ................................ ................................ ...................... 57 6.14 signal level optimisation ................................ ................................ ........................... 57 6.14.1 transmit path levels ................................ ................................ ........................... 57 6.14.2 receive path levels ................................ ................................ ............................. 57 6.15 tx spectrum plots ................................ ................................ ................................ ...... 58 6.16 c - bus register summary ................................ ................................ .......................... 59 7 performance specification ................................ ................................ ................................ ... 60 7.1 electrical performance ................................ ................................ ............................... 60 7.1.1 absolute maximum ratings ................................ ................................ ................. 60 7.1.2 operating limits ................................ ................................ ................................ ... 61 7.1.3 opera ting characteristics ................................ ................................ ..................... 62 7.1.4 parametric performance ................................ ................................ ...................... 68 7.2 c - bus timing ................................ ................................ ................................ ............. 70 7.3 packaging ................................ ................................ ................................ ................... 71 table page table 1 definition of power supply and reference voltages ................................ ........................ 10 table 2 dpmr frame format - call set - up, no ack ................................ ................................ .... 24 table 3 dpmr frame format - call set - up with ack ................................ ................................ ... 24 table 4 dc s codes and values ................................ ................................ ................................ ..... 30 table 5 ctcss codes and values ................................ ................................ ................................ 32 table 6 xtal/clock frequency settings for program block 3 ................................ ........................ 33 table 7 booten pin states ................................ ................................ ................................ ......... 35 table 8 modem mode selection ................................ ................................ ................................ ... 42 table 9 m odem control selection ................................ ................................ ................................ . 42
digital pmr processor cmx7131/cmx7141 ? table 10 c - bus data registers ................................ ................................ ................................ ... 43 table 11 c - bus registers ................................ ................................ ................................ ............ 59 figur e page figure 1 block diagram ................................ ................................ ................................ ................... 7 figure 2 cmx7141 (l4 and q3) recommended external components ................................ ....... 11 figure 3 cmx7131 (l9 and q1) recommended external components ................................ ....... 12 figure 4 cmx7141 (l4/q3) power supply and de - coupling ................................ ......................... 14 figure 5 cmx7131 (l9/q1) power supply and de - coupling ................................ ......................... 15 figure 6 cmx618 vocoder connection ................................ ................................ ........................ 18 figure 7 cmx608 vocoder connection ................................ ................................ ........................ 18 figure 8 dvsi vocoder connection ................................ ................................ .............................. 19 figure 9 dual vocoder connection ................................ ................................ ............................... 19 figure 10 4fsk prbs waveform - modulation ................................ ................................ ............ 21 figure 11 4fsk prbs waveform - spectrum ................................ ................................ .............. 21 figure 12 dpmr modulation characteristics ................................ ................................ ................. 22 figure 13 internal data processing blocks ................................ ................................ ................... 23 figure 14 fs detection ................................ ................................ ................................ ................. 25 figure 15 tx level adjustments ................................ ................................ ................................ .... 28 figure 16 rx level adjustments ................................ ................................ ................................ ... 28 figure 17 rx audio response ................................ ................................ ................................ ...... 29 figure 18 tx audio response ................................ ................................ ................................ ....... 29 figure 19 ctcss and dcs filters ................................ ................................ ................................ . 30 figure 20 c - bus transactions ................................ ................................ ................................ ..... 34 figure 21 fi loading from host ................................ ................................ ................................ .... 36 figure 22 fi loading from serial memory ................................ ................................ ..................... 37 figure 23 digital voice rx and tx blocks ................................ ................................ ..................... 39 figure 24 tx data flow ................................ ................................ ................................ ................. 48 figure 25 rx data flow ................................ ................................ ................................ ................. 50 figure 26 auxadc irq operation ................................ ................................ ................................ 52 figure 27 example rf synthe siser components ................................ ................................ ......... 53 figure 28 single rf synthesiser block diagram ................................ ................................ .......... 54 figure 29 digital clock generation schemes ................................ ................................ ............... 56 figure 30 tx modulation spectra - 4800bps ................................ ................................ ................. 58 figure 31 c - bus timing ................................ ................................ ................................ ............... 70 fi gure 32 mechanical outline of 64 - pin vqfn (q1) ................................ ................................ ..... 71 figure 33 mechanical outline of 64 - pin lqfp (l9) ................................ ................................ ....... 71 figure 34 mechanical ou tline of 48 - pin lqfp (l4) ................................ ................................ ....... 72 figure 35 mechanical outline of 48 - pin vqfn (q3) ................................ ................................ ..... 72 1.1 history version changes date ? 3 ? clarification of booten states and corre ctions to rf synthesiser specification ? correction to spi bus chip select pin definition. sep 2011
digital pmr processor cmx7131/cmx7141 ? 2 ? added ctcss and dcs internal generation/detection ? removed references to raw mode ? added reference to ts 102 658 mode 1 june 2011 1 ? original document feb 20 11 this is advance information; changes and additions may be made to this specification. parameters marked tbd or left blank will be included in later issues. items that are highlighted or greyed out should be ignored. these will be clarified in later is sues of this document. information in this datasheet should not be relied upon for final product design.
digital pmr processor cmx7131/cmx7141 ? 2 block diagram figure 1 block diagram alt txena rxena gpioa gpiob mod 2 adc 1 adc 2 adc 3 adc 4 epsclk b o o t e n 1 b o o t e n 2 epcsn sysclk 1 sysclk 2 a v d d v b i a s a v s s x t a l / c l k x t a l n epso epsi multiplexed adcs dacs system clocks system control internal signal mux function image? configured io mux adc 1 thresholds averaging thresholds averaging system clock 1 system clock 2 c - bus interface irqn rdata sclk power control registers spi eeprom interface bias d v d d v d e c d v s s bias crystal oscillator boot control main pll auxiliary functions adc 2 filtering 4 fsk modem demodulator cdata csn tx mode select gpio rx data buffer v bias v bias mic rx signal routing mod 1 tx modulator v bias disc ssout filtering tx data buffer audio core operations tx and rx interfacing audio o / p afsd soft - decision decoding payload decoding 4 fsk modem modulator payload coding rx functions tx functions external vocoder control external vocoder control dac 1 dac 2 dac 3 dac 4 dac 1 dac 2 dac 3 dac 4 ramp profile ram rf synthesiser 1 rf synthesiser 2 rf 1 n cp 1 out iset 1 rf 2 n cp 2 out iset 2 rfvdd cpvdd rfvss rfclk rf synthesisers ( cmx 7131 only ) digital pmr audio processing analogue pmr sub - audio filtering audio processing digital pmr analogue pmr tone generation sub - audio filtering mux rf 1 p rf 2 p discfb altfb micfb ctcss / dcs ctcss / dcs
digital pmr processor cmx7131/cmx7141 ? 3 signal list cmx7131 64 - pin q1/l9 cmx7141 48 - pin q3/l4 p in name type description 1 8 irqn op c - bus: a 'wire - orable' output for connection to the interrupt request input of the host. pulled down to dv ss when active and is high impedance when inactive. an external pull - up resistor (r1) is required. 2 - rf1n i p rf synthesiser 1 negative input 3 - rf1p ip rf synthesiser 1 positive input 4 - rfvss pwr the negative supply rail (ground) for rf synthesiser 1 5 - cp1out op rf synthesiser 1 charge pump output 6 - iset1 ip rf synthesiser 1 charge pump current set i nput 7 - rfvdd pwr the 2.5v positive supply rail for both rf synthesisers. this should be decoupled to rfv ss by a capacitor mounted close to the device pins. 8 - rf2n ip rf synthesiser 2 negative input 9 - rf2p ip rf synthesiser 2 positive input 10 - r fvss pwr the negative supply rail (ground) for rf synthesiser 2 11 - cp2out op rf synthesiser 2 charge pump output 12 - iset2 ip rf synthesiser 2 charge pump current set input 13 - cpvdd pwr the 3.3v positive supply rail for the rf synthesiser charge pu mps. this should be decoupled to rfv ss by a capacitor mounted close to the device pins. 14 - rfclk ip rf clock input (common to both rf synthesisers) 1 15 11 gpioa op general purpose i/o pin 16 12 gpiob op general purpose i/o pin 17 - - nc reserved C do not connect this pin 18 9 vdec pwr internally generated 2.5v digital supply voltage. must be decoupled to dv ss by capacitors mounted close to the device pins. no other connections allowed, except for optional connection to rfv dd . 19 10 rxena op rx enab le C active low when in rx mode ($c1:b0 = 1) 20 13 sysclk1 op synthesised digital system clock output 1 21 14 dvss pwr digital ground 22 - - nc reserved C do not connect this pin 23 15 txena op tx enable C active low when in tx mode ($c1:b1 = 1) 24 16 disc ip discriminator inverting input 25 17 discfb op discriminator input amplifier feedback 26 18 alt ip alternate inverting input, or external sub - audio input 27 19 altfb op alternate input amplifier feedback 1 to minimise crosstalk, this signal should be connected to the same clock source as xtal/clk input.
digital pmr processor cmx7131/cmx7141 ? cmx7131 64 - pin q1/l9 cmx7141 48 - pin q3/l4 p in name type description 28 20 micfb op microphone input amplifie r feedback 29 21 mic ip microphone inverting input 30 22 avss pwr analogue ground 31 23 mod1 op modulator 1 output 32 24 mod2 op modulator 2 output 33 25 vbias op internally generated bias voltage of about av dd /2, except when the device is in powers ave mode when v bias will discharge to av ss . must be decoupled to av ss by a capacitor mounted close to the device pins. no other connections allowed. 34 26 audio op audio output in spi - codec mode and analogue mode 35 27 adc1 ip auxiliary adc input 1 eac h of the two adc blocks can select its input signal from any one of these input pins, or from the mic, alt or disc input pins. see section 6.10 for details. 36 28 adc2 ip auxiliary adc input 2 37 29 adc3 ip auxiliary adc inp ut 3 38 30 adc4 ip auxiliary adc input 4 39 31 avdd pwr analogue +3.3v supply rail. levels and thresholds within the device are proportional to this voltage. this pin should be decoupled to av ss by capacitors mounted close to the device pins. 40 32 dac1 op auxiliary dac output 1/ramdac 41 33 dac2 op auxiliary dac output 2 42 34 avss pwr analogue ground 43 35 dac3 op auxiliary dac output 3 44 36 dac4 op auxiliary dac output 4 or external sub - audio output - 37 dvss pwr digital ground 45 38 vdec p wr internally generated 2.5v supply voltage. must be decoupled to dv ss by capacitors mounted close to the device pins. no other connections allowed, except for the optional connection to rfv dd . 46 39 xtal/clk ip input from the external clock source or xta l 47 40 xtaln op the output of the on - chip xtal oscillator inverter. nc if external clock used. 48 41 dvdd pwr digital +3.3v supply rail. this pin should be decoupled to dv ss by capacitors mounted close to the device pins. 49 42 cdata ip c - bus command data: serial data input from the c 50 43 rdata ts op c - bus reply data: a 3 - state c - bus serial data output to the c. this output is high impedance when not sending data to the c. 51 - - nc reserved C do not connect this pin 53 44 ssout op spi bus chi p select/frame sync (used for cmx6x8)
digital pmr processor cmx7131/cmx7141 ? cmx7131 64 - pin q1/l9 cmx7141 48 - pin q3/l4 p in name type description 52 45 dvss pwr digital ground 54 46 sclk ip c - bus serial clock: the c - bus serial clock input from the c 55 47 sysclk2 op synthesised digital system clock output 2 56 48 csn ip c - bus chip select: the c - bus chip sel ect input from the c - there is no internal pullup on this input 57 - - nc reserved C do not connect this pin 58 1 epsi op serial memory interface: output; spi bus output 59 2 epsclk op serial memory interface: clock; spi bus clock 60 3 epso ip+pd ser ial memory interface: input; spi bus input 61 4 epscsn op serial memory interface: chip select 62 5 booten1 ip+pd used in conjunction with booten2 to determine the operation of the bootstrap program 63 6 booten2 ip+pd used in conjunction with booten1 to determine the operation of the bootstrap program 64 7 dvss pwr digital ground e xposed m etal p ad e xposed m etal p ad substrate ~ on this device, the central metal pad (which is exposed on q1 and q3 packages only) may be electrically unconnected or, alterna tively, may be connected to analogue ground (av ss ). no other electrical connection is permitted. notes: ip = input (+ pu/pd = internal pullup / pulldown resistor) op = output bi = bidirectional ts op = 3 - state output pwr = power connection nc = no c onnection - should not be connected to any signal. 3.1 signal definitions table 1 definition of power supply and reference voltages signal name pins usage av dd avdd power supply for analogue circuits dv dd dvdd power supply for digit al circuits v dec vdec power supply for core logic, derived from dv dd by on - chip regulator v bias vbias internal analogue reference level, derived from av dd av ss avss ground for all analogue circuits dv ss dvss ground for all digital circuits rfv dd rfvdd power supply for rf circuits rfv ss rfvss ground for rf circuits cpv dd cpvdd power supply for charge pump circuits
digital pmr processor cmx7131/cmx7141 ? 4 external components figure 2 cmx7141 (l4 and q3) recommended external components
digital pmr processor cmx7131/cmx7141 ? figure 3 cmx7131 (l9 and q1) recommended external components
digital pmr processor cmx7131/cmx7141 ? 4.1 recommended external components r1 100k ? c1 18pf c11 not used c21 10nf r2 20k ? c2 18pf c12 100pf c22 10nf r3 20k ? c3 10nf c13 see note 5 c23 10nf r4 20k ? c4 not used c14 100pf c24 10f r5 see note 2 c5 1nf c15 see note 5 r6 100k ? c6 100pf c16 200pf r7 see note 3 c7 100nf c17 10f r8 100k ? c8 100pf c18 10nf x1 6.144mhz r9 see note 4 c9 100pf c19 10nf see note 1 r10 100k ? c10 not used c20 10f resistors ? 5%, capacitors and inductors ? 20% unless otherwise stated. notes: 1. x1 can be a crystal or an external clock generator; this will depend on the application. the tracks between the crystal and the device pins should be as short as possible to achi eve maximum stability and best start up performance. by default, a 19.2mhz oscillator is assumed (in which case c1 and c2 are not required), other values could be used if the various internal clock dividers are set to appropriate values. 2. r5 should be sele cted to provide the desired dc gain of the discriminator input, as follows: ? gain disc ? = 100k ? / r5 the gain should be such that the resultant output at the discfb pin is within the disc input signal range specified in 6.14.2 . for 4fsk modulation, this signal should be dc coupled from the limiter/ discriminator output. 3. r7 should be selected to provide the desired dc gain (assuming c13 is not present) of the alternative input as follows: ? gain alt ? = 100k ? / r7 the gain should be such that the resultant output at the altfb pin is within the alternative input signal range specified in 6.14 . 4. r9 should be selected to provide the desired dc gain (assuming c15 is not present) of the microphone input as follo ws: ? gain mic ? = 100k ? / r9 the gain should be such that the resultant output at the micfb pin is within the microphone input signal range specified in 6.14.1 . for optimum performance with low signal microphones, an additional e xternal gain stage may be required. 5. c13 and c15 should be selected to maintain the lower frequency roll - off of the mic and alt inputs as follows: c13 ? 1.0f ? ? gain alt ? c15 ? 30nf ? ? gain mic ? 6. alt and altfb connections allow the user to have a second di scriminator or microphone input. component connections and values are as for the respective disc and mic networks. if this input is not required, the alt pin should be connected to av ss . 7. audio output is used when spi - codec mode or analogue mode has been selected. 8. a single 10f electrolytic capacitor (c24, fitted as shown) may be used for smoothing the power supply to both vdec pins, providing they are connected together on the pcb with an adequate width power supply trace. alternatively, separate smoothi ng capacitors should be connected to each vdec pin. high frequency decoupling capacitors (c3 and c23) must always be fitted as close as possible to both vdec pins.
digital pmr processor cmx7131/cmx7141 ? 4.2 pcb layout guidelines and power supply decoupling figure 4 c mx7141 (l4/q3) power supply and de - coupling component values as per figure 2
digital pmr processor cmx7131/cmx7141 ? figure 5 cmx7131 (l9/q1) power supply and de - coupling component values as per figure 3 notes: it is important to protect th e analogue pins from extraneous inband noise and to minimise the impedance between the cmx7131/cmx7141 and the supply and bias de - coupling capacitors. the de - coupling capacitors c3, c7, c18, c19, c21, c22 and c24 should be as clo se as possible to the cmx7131/cmx7141 . it is therefore recommended that the printed circuit board is laid out with separate ground planes for the av ss and dv ss supplies in the area of the cmx7131/cmx7141 , with provision to make links between them, close to the cmx7131/cmx7141 . use of a multi - layer printed circuit board will facilitate the provision of ground planes on separate layers. v bias is used as an internal reference for detecting and generating the various analogue signals. it must be carefully decoupled, to ensure its integrity, so apart from the decoupling capacitor shown, no other loads should be connected. if v bias needs to be used to set the discriminator mid - point reference, it should be buffered with a high input impedance buffer. the single ended microphone input and audio output must be ac coupled (as shown), so that their return paths can be connected to av ss without introducing dc offsets. further buffering of the audio output is advised. the crystal, x1, may be replaced with an external clock source.
digital pmr processor cmx7131/cmx7141 ? 5 general description 5.1 7131/7141 fi - 5.x features the 7131/7141fi - 5.x function image ? is intended for use in half duplex digital pmr equipment using 4fsk modulation a t 4800 bps suitable for 6.25khz channels and analogue pmr for use in 12.5khz or 25khz channel systems. much of the dpmr etsi ts 102 490 standard air interface protocol is embedded in the 7131/7141fi - 5.x function image ? operation namely: air interface physi cal layer 1 ? 4fsk modulation and demodulation ? bit and symbol definition ? frequency and symbol synchronisation ? transmission burst building and splitting air interface data link layer 2 ? channel coding (fec, crc) ? interleaving, de - interleaving and bit ordering ? f rame and superframe building and synchronising ? burst and parameter definition ? link addressing (source and destination) ? interfacing of voice applications (voice data) with the physical layer ? data bearer services ? exchanging signalling and/or user data with t he call control layer ? automatic own - id and group - id detection analogue pmr features ? complete voice processing o 300hz hpf o 12.5khz channel filter o 25khz channel filter o hard limiter with anti - splatter filter o compander o scrambler o voice agc o level adjust ? inband ton e generation ? sub - audio filtering ? external connection for sub - audio generation/detection ? internal sub - audio (ctcss and dcs) generation/detection the selection of these analogue processing modes is controlled by the analogue mode bits in the modem control r egister, $c1:b15 - 8. a flexible power control facility allows the device to be placed in its optimum powersave mode when not actively processing signals.
digital pmr processor cmx7131/cmx7141 ? the device includes a crystal clock generator, with buffered output, to provide a common system clock i f required. a block diagram of the device is shown in figure 1 . the signal processing blocks can be routed from any of the three disc/alt/mic input pins. other functions include: ? automatic tx sequencer simplifies host control ? ramd ac operation ? txena and rxena hardware signals ? two - point or i/q modulation outputs ? hard or soft data output options. auxiliary functions: ? two programmable system clock outputs ? two auxiliary adcs with four selectable external input paths ? four auxiliary dacs, one with built - in programmable ramdac ? two rf plls (cmx7131 only). interface: ? optimised c - bus (4 wire high speed synchronous serial command/data bus) interface to host for control and data transfer ? open drain irq to host ? auxiliary spi/c - bus interface to c mx618/cmx608 with pass - through mode from host ? spi bus interface for speech codec to support third - party vocoders ? two gpio pins ? serial m emory boot mode ? c - bus (host) boot mode. 5.2 system design a number of system architectures can be supported by the device. th e most highly integrated solution uses a cmx618 vocoder under full control of the cmx7131/cmx7141, relieving the host of all vocoder management duties. in this mode audio codec functions are provided by the cmx618. other architectures using third - party voc oders are supported using spi - codec mode in which the cmx7131/cmx7141 acts as an external audio codec attached to the vocoder. in this mode the host must issue all control commands to the vocoder, and also transfer coded data packets between the vocoder an d cmx7131/cmx7141. the configuration of the auxiliary spi/c - bus port is controlled by the spi - codec enable bit ($b1 bit 0). spi - codec $b1:0 port mode 0 c - bus connect to cmx6x8 c - bus port (default) 1 spi connect to cmx608 or third - party vocoder spi code c port in spi - codec mode 16 - bit pcm audio samples are transferred at 8ksps. when this mode is selected: in tx: the cmx7131/cmx7141 microphone input should be routed from mic to input2. the input signal is lowpass filtered, converted to 16 - bit linear pcm at 8ksps and then output on the epsi pin of the spi - codec port for the external vocoder to process.
digital pmr processor cmx7131/cmx7141 ? in rx: the cmx7131/cmx7141 audio output should be routed to output1. 16 - bit linear pcm samples are read from the epso pin of the spi - codec port, then filte red and output via the audio output attenuator. 5.2.1 implementation using the cmx6x8 figure 6 shows the configuration using the cmx618 ralcwi vocoder where all control and data is handled by the cmx7131/cmx7141 (7131/71 41fi - 5.x) with minimal host cpu involvement: figure 6 cmx618 vocoder connection if the cmx608 is to be used then there are two possible architectures available. if an external audio codec is availabl e then the cmx7131/cmx7141 can take full control over the cmx608 as in figure 6 . otherwise the audio codecs within the cmx7131/cmx7141 can be used at the expense of additional host activity. in this case, all channel data (control , addressing and payload) transferred from the cmx7131/cmx7141 to the host over the main c - bus interface, and the host must then transfer the voice payload (tch) data to the cmx608 using another c - bus interface, as shown in figure 7 . figure 7 cmx608 vocoder connection cmx 7131 / cmx 7141 host cpu cmx 618 radio eeprom c - bus disc mod spi epcsn ssout spi _ ena = 0 cmx 6 x 8 _ dis = 0 c - bus c - bus c - bus mic speaker cmx 7131 / cmx 7141 host cpu cmx 608 radio eeprom c - bus disc mod spi epcsn ssout spi - codec _ ena = 1 cmx 6 x 8 _ dis = 0 spi spi spi mic speaker c - bus c - bus mic audio
digital pmr processor cmx7131/cmx7141 ? 5.2.2 implementing with third - party vocoders as an alternative to the integrated architecture using the cmx618, it is possible to use a third - party vocoders by routi ng all payload data (including voice traffic channel data) through the main c - bus to the host. the host can then transfer it to/from the third party vocoder over a suitable port supported by the chosen vocoder. typically these vocoders do not include audio digital - to - analogue and analogue - to - digital converters, so the cmx7131/cmx7141 can be configured to use its auxiliary c - bus as an spi interface and use its built - in dac/adcs as audio converters. this architecture is shown in figure 8 . figure 8 dvsi vocoder connection additionally, this architecture can be extended to support a dual - mode system with two different vocoders, though this requires some additional host switching as shown in figure 9 . the vocoder enable masks in program block 1 should be set up by the host following power - on, to allow the cmx7131/cmx7141 to configure the spi interface correctly for each call depending on which vocoder is req uired. figure 9 dual vocoder connection cmx 7131 / cmx 7141 host cpu dvsi vocoder radio eeprom c - bus disc mod spi epcsn ssout spi - codec _ ena = 1 cmx 6 x 8 _ dis = 0 spi spi spi mic speaker serial uart mic audio cmx 7131 / cmx 7141 host cpu dvsi vocoder radio eeprom c - bus disc mod spi epcsn ssout spi - codec _ ena = 1 cmx 6 x 8 _ dis = 0 spi spi spi mic speaker serial uart mic audio cmx 608 c - bus c - bus mux spi
digital pmr processor cmx7131/cmx7141 ? 5.2.3 data transfer when transmitting, an initial block of payload or control channel data will need to be loaded from the host into the c - bus txdata registers. the cmx7131/cmx7141 can then format and transmit that data while at the same time loading in the following data blocks from the host or cmx618. when receiving, the host needs to consider that when a signal is received over the air th ere will be a processing delay while the cmx7131/cmx7141 filters, demodulates and decodes the output data before presenting it to the host or cmx618. for best performance, voice payload data can be output in soft - decision (4 - bit log - likelihood ratio) format compatible with the cmx618/cmx608 and other third - party vocoders, although this mode increases the data transfer rate over c - bus by a factor of four. 5.2.4 rssi measurement the auxadc provided by the cmx7131/cmx7141 can be used to detect the squelch or rssi signal from the rf section while the device is in rx or idle mode. this allows a significant degree of powersaving within the cmx7131/cmx7141 and avoids the need to wake the ho st up unnecessarily. the host programmable auxadc thresholds allow for user selection of squelch threshold settings. 5.2.5 serial memory connection in all cases, the auxiliary c - bus/spi - codec bus is shared with the serial memory bus which may be used to hold th e contents of the function image?. bus conflicts are avoided by the use of an additional chip select signal (ssout). if this feature is not used, the epcsn pin should be left un - connected. 5.3 dpmr modem description this modem can run at 4800bps occupying a 6. 25khz bandwidth rf channel. it has been designed such that, when combined with suitable rf, host controller, cmx618/cmx608 vocoder and appropriate control software, it meets the requirements of the en 301 166 or en 300 113 standards as appropriate. see www.etsi.org for details of these standards. ts 102 490 is available on the etsi web site ( www.etsi.org ) which describes a 6.25khz channel spacing fdma dpmr system. this standard uses a 4fsk modulation scheme with an over - air bit rate of 4800bps (ie. 2400 symbols per second). with respect to dpmr formatted modes of operation, this document should be read in conjunction with the etsi standard. the dpmr standard does not specify a voice coding algorithm, but the cmx618 or cmx608 (also available from cml) are both suitable devices for this purpose. in the rest of this document these two devices are referred to generically as the cmx6x8, as the only significant difference between them is th e inclusion of an on - chip audio codec in the cmx618 while the cmx608 requires an external audio codec. version 1.5.1 of ts 102 490 introduces two additional vocoder control bits which specify which vocoder is in use for a particular voice call. function i mage 1.1.0.0 onwards supports these additional bits, however care should be taken if backwards compatibility with earlier implementations is to be maintained. note that the ts 102 490 (dpmr) standard is not compatible with the ts 102 361 (dmr) 12.5khz/960 0baud tdma system. legacy analogue pmr modes are supported allowing voice processing and sub - audio signal filtering. 5.3.1 modulation the dpmr 4fsk modulation scheme operates in a 6.25khz channel bandwidth with a deviation index of 0.29 and has an over - air bit r ate of 4800bps (2400 symbols per second). rrc filters are implemented in both tx and rx with a filter alpha of 0.2. the maximum frequency error is +/ - 625hz and the cmx7131/cmx7141 can adapt to the maximum time - base clock drift of 2ppm over the duration of a 180 - second burst. figure 12 shows the basic parameters of the 4fsk modulation, symbol mapping and filtering requirements. figure 10 and figure 11 s how a transmitted prbs waveform, as recorded on a spectrum analyser in 36k span and zero - span mode, having been two - point modulated using a suitable rf transmitter.
digital pmr processor cmx7131/cmx7141 ? figure 10 4fsk prbs waveform - modula tion figure 11 4fsk prbs waveform - spectrum a r b w 1 0 0 h z v b w 1 k h z s w t 1 8 s u n i t d b m 1 r m 3 0 . 8 d b o f f s e t r e f l v l 3 0 d b m r e f l v l 3 0 d b m r f a t t 2 0 d b 3 . 6 k h z / c e n t e r 4 4 6 . 1 m h z s p a n 3 6 k h z - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 1 0 2 0 - 7 0 3 0 1 m a r k e r 1 [ t 1 ] 1 6 . 4 8 d b m 4 4 6 . 1 0 0 1 0 8 2 2 m h z 1 [ t 1 ] 1 6 . 4 8 d b m 4 4 6 . 1 0 0 1 0 8 2 2 m h z c h p w r 2 7 . 5 3 d b m a c p u p - 6 6 . 5 5 d b a c p l o w - 6 7 . 1 4 d b a l t 1 u p - 7 9 . 4 5 d b a l t 1 l o w - 8 0 . 2 1 d b c u 2 c u 2 c u 1 c u 1 c l 1 c l 1 c l 2 c l 2 c 0 c 0 d a t e : r e f l v l 3 0 d b m 3 0 d b m r e f l v l 3 0 d b m 3 0 d b m 3 0 d b o f f s e t a s t a r t 0 s s t o p 3 5 m s c f 4 4 6 . 1 m h z d e m o d b w : 1 0 0 k h z r e a l t i m e o f f a f - s i g n a l f m [ h z ] 5 0 0 1 v i e w - 2 k - 1 . 5 k - 1 k - 5 0 0 0 5 0 0 1 k 1 . 5 k 2 k - 2 . 5 k 2 . 5 k 1 m a r k e r 1 [ t 1 ] 3 1 . 3 9 9 1 8 m s f m 6 6 1 . 9 8 7 h z 1 [ t 1 ] 3 1 . 3 9 9 1 8 m s f m 6 6 1 . 9 8 7 h z d 1 1 . 0 5 k h z d 2 - 1 . 0 5 k h z d a t e :
digital pmr processor cmx7131/cmx7141 ? figure 12 dpmr modulation characteristics 5.3.2 internal data processing the cmx7131/cmx7141 operates as a half - duplex device, either receiving signals from the rf circuits in rx mode, or sourcing signals to the rf circuits in tx mode. it also has a low power idle mode to support battery saving protocols. the internal data processing blocks for tx and rx m odes are illustrated in figure 13 .
digital pmr processor cmx7131/cmx7141 ? figure 13 internal data processing blocks 5.3.3 frame sync detection and demodulation the analogue signal from the limiter/discriminator of the external rf section should be applied to one of the cmx7131/cmx7141 inputs (normally the disc input) where it can be adjusted to the correct level either by selection of the feedback resistor or using the cmx7131/cmx7141 input gain settings. the signal is filtered using a root - raised cosine filter and inverse rx sinc filter matching the filters applied in the transmitter, then passed to the afsd (automated frame sync dete ctor) block which extracts symbol and frame synchronisation. during this process the 4fsk demodulator and the following data - processing sections are dormant to minimise power consumption. when frame synchronisation has been achieved the afsd section is pow ered down, and timing and symbol - level information is passed to the 4fsk demodulator which starts decoding the subsequent data bits. the cmx7131/cmx7141 can detect the end of a call by scanning the received contro l channel fields and will automatically disable the demodulator and restart frame sync search when required without host intervention. a dpmr call begins with a 72 - bit or longer preamble sequence followed by an 80ms header frame, which contains a 48 - bit fr ame sync (fs1 or fs4). subsequent payload frames contain either a 24 - bit frame sync (fs2) or a 24 - bit colour code. the cmx7131/cmx7141 can scan for all dpmr frame syncs concurrently. it uses fs1 to detect the star t of a transmission, and this is reported to the host by setting the fs1 detect bit in the irq status register. it can also optionally use fs2 to perform late entry into an existing call, reported by setting the fs2 detect bit. the short length of fs2 gi ves a high probability of false detections, so by default the cmx7131/cmx7141 will only generate an fs2 detect if two successive fs2 frame syncs are detected at the correct frame spacing in the received signal. th e frame syncs and preamble defined in ts 102 490 are always used. when frame synchronisation has been achieved, the 4fsk demodulator is enabled, frame sync detection is switched off and any subsequent frame sync sequences embedded in the received data are not reported to the host. c - bus port data buffer frame type detect fec interleave scramble packet formatter data router spi port ( from cmx 6 x 8 ) 4 - fsk modulator filter i / q look - up mux filter afsd 4 - fsk demod frame type detect de - interleave de - scramble de - fec data router spi port ( to cmx 6 x 8 ) data buffer address matcher c - bus port packet de - formatter disc input mod 1 out mod 2 out control info control info voice data voice data
digital pmr processor cmx7131/cmx7141 ? table 2 dpmr frame format - call set - up, no ack table 3 dpmr frame format - call set - up with ack bit no. 24 48 72 96 120 144 168 192 216 240 264 288 312 336 360 384 press ptt header tx cc frame 1 tx fs2 cch payload payload payload payload frame 2 tx cc cch payload payload payload payload frame 3 tx fs2 cch payload payload payload payload frame 4 tx cc cch payload payload payload payload frame 1 tx fs2 cch payload payload payload payload frame 2 tx cc cch payload payload payload payload frame 3 tx fs2 cch payload payload payload payload frame 4 tx cc cch payload payload payload payload tx repeat frames 1 to 4 until ptt released. end tx fs3 header info 1 header info 0 end flag preamble fs1 bit no. 24 48 72 96 120 144 168 192 216 240 264 288 312 336 360 384 press ptt header tx cc end tx fs3 ack rx cc header tx cc frame 1 tx fs2 cch payload payload payload payload frame 2 tx cc cch payload payload payload payload frame 3 tx fs2 cch payload payload payload payload frame 4 tx cc cch payload payload payload payload frame 1 tx fs2 cch payload payload payload payload frame 2 tx cc cch payload payload payload payload frame 3 tx fs2 cch payload payload payload payload frame 4 tx cc cch payload payload payload payload tx repeat frames 1 to 4 until ptt released. end tx fs3 header info 1 header info 0 end flag preamble fs1 header info 0 preamble fs1 header info 1 end flag preamble fs1 header info 0 header info 1
digital pmr processor cmx7131/cmx7141 ? figure 14 fs detection rx enabled afsd active 4 fsk dormant fs 1 detected ? afsd off 4 fsk active irq fs 1 fs 2 detected ? afsd off 4 fsk active irq fs 2 demodulate demodulate irq fs 2 fs 2 detected ? id matched ? irq called irq datardy ( ri + sacch + le ) enable cmx 6 x 8 transfer data to cmx 6 x 8 end detected ? disable cmx 6 x 8 irq datardy ( end ) no no no no no id matched ? no process data afsd process analyse sacch data decode , de - interleave analyse sacch data decode , de - interleave irq called irq datardy ( ri + sacch ) analyse sacch data decode , de - interleave
digital pmr processor cmx7131/cmx7141 ? 5.3.4 fec and coding the cmx7131/cmx7141 implements all crcs, hamming codes, interleaving and scrambling required by the dpmr standard. crc failures in control channel fields and cod ed data blocks are indicated to the host by issuing an event irq with a corresponding error code in the modem status register, $c9. this relieves the host of a substantial processing load and has the added advantage of reducing the complexity and timing constraints of interfacing between the host, vocoder and cmx7131/cmx7141 . the dpmr header frame format contains duplicate copies of all control channel fields (in the hi0 and hi1 header information blocks) but only one decoded co py of each field will be presented back to the host. on receiving a header frame the cmx7131/cmx7141 decodes both hi blocks, checks crcs and can accept the call if either block is valid (the other hi block is discarded). 5.3.5 voice co ding a cml cmx618 or cmx608 ralcwi vocoder can be used under the control of the cmx7131/cmx7141 . the cmx7131/cmx7141 provides an auxiliary spi/c - bus p ort (shared with the boot serial memory ) which is us ed to issue control commands and transfer voice payload data directly to the cmx6x8 vocoder, minimising the loading on the host controller during voice calls. alternatively, the cmx7131/cmx7141 can support any third - party vocode r by routing voice payload data over the main c - bus interface and through the host. in this mode, all vocoder control and data transfers must be managed by the host. voice data transferred to the cmx6x8 in rx mode always uses soft decision (4 - bit log - like lihood ratio) format. this option is also available for voice payload data routed to the host, although it increases the required data transfer rate over c - bus by a factor of four. 5.3.6 radio performance requirements the cmx7131/cmx7141 demodulator is designed to process a 4fsk signal from a limiter / discriminator source. for optimum performance the signal should not be significantly degraded by filters that are excessively narrow and / or cause significant group delay distortion. care sh ould be taken in interfacing the device to the radio circuits to maintain the frequency and phase response (both low and high end), in order to achieve optimum performance. test modes are provided to assist in both the initial design and production set - up procedures. further information and application notes can be found at http://www.cmlmicro.com . 5.4 analogue pmr description 5.4.1 sub - audio processing an external sub - audio processing path is available for the host to genera te or detect sub - audio tones. in tx, sub - audio tones applied to the alt input are filtered and then summed with the in - band signal and presented to the mod1 and mod2 outputs. in rx, the sub - audio tones are separated by filters from the received signal appl ied to the disc input. the sub - audio signal is then routed to the auxiliary dac4 output. the filter used in the path can be set by the program register, either a 260hz chebyshev suitable for ctcss or a 150hz 4 - pole bessel for dcs. an internal generator/det ector is available for the 51 ctcss tones shown in table 5 and the 83 dcs codes shown in table 4 . squelch - tail elimination is provided by inverting the mod outputs in ctcss mode or a 134hz turn - off tone in dcs mode. the tone/code to be generated is set by the value in the auxdata/sub - audio write register ($c2) in tx mode and read from the auxdata/sub - audio read register ($cc) in rx mode (see section 8.1.24 ). the use of the in ternal generator/detector is determined by program block p2.0 b5 and b4 (see section 8.2.3 ). 5.4.2 voice processing a set of audio processing blocks are available for use in analogue mode: ? 300hz hpf ? 12.5khz channel filter or 25khz ch annel filter
digital pmr processor cmx7131/cmx7141 ? ? hard limiter with anti - splatter filter ? compandor ? scrambler ? voice agc ? level adjust ? in C band audio generator/s in both rx and tx paths the 12.5khz channel filter (narrow) will be selected by default, the 25khz filter (wide) can be enabled by sett ing p2.0:b0. 300hz hpf this is designed to reject signals below 300hz from the voice path so that sub - audio signalling can be inserted (in tx) or removed (in rx) as appropriate. it should be enabled whenever sub - audio signalling is required. 12.5khz/25khz channel filters these are designed to meet the requirements of etsi 300 296 for voice signal processing and feature an upper roll - off at 2.55 and 3.0khz respectively. hard limiter this is provided to limit the peak deviation of the radio signal to meet the requirements of etsi en 300 296. an anti - splatter filter is included to reduce the effects of any harmonic signals generated in the process. the limiter threshold can be set using p2.3. compander a syllabic compressor/expander is provided, similar to that used in the 7031/7041 - fi - 1.x to increase the dynamic range of the voice signal. the unity gain points for tx and rx can be set independently using p2.9 and p2.10. scrambler a frequency inversion scrambler is provided to enable a basic level of privacy. th e default inversion frequency is 3300hz, but can be programmed using $cd:1001 b , however some loss of signal at the band edges may occur due to the channel filter roll - off. voice agc an automatic gain control system is provided in the voice path, utilising the programmable gain settings of the input 1 amplifier. when used in conjunction with the hard limiter function, this can compensate large variations in the mic input signal without introducing significant distortion. the agc threshold is programmable usi ng p21. whilst the maximum gain setting and the decay time can be set using p2.2. when this feature is enabled, the host should not attempt to directly control the input 1 gain setting. level adjust independent level adjustments are provided using $c3 reg ister for the voice, in - band and sub - audio signals as shown in figure 15 tx lev el adjustments and figure 16 rx level adjustments .
digital pmr processor cmx7131/cmx7141 ? figure 15 tx lev el adjustments figure 16 rx level adjustments audio tones sub - audio processing voice processing mux $ b 1 : b 5 - 2 mux $ c 1 : b 15 - 13 mux $ b 1 : b 9 - 6 audio mod 1 mod 2 disc alt mic input 1 input 2 output 1 output 2 fine gain : $ c 3 : 1 xxx fine gain : $ c 3 : 1 xxx coarse gain : $ b 0 : b 14 - 12 coarse gain : $ b 0 : b 10 - 8 coarse gain : $ b 0 : b 3 - 0 audio tone tx level : $ c 3 : 6 xxx sa tx level : $ c 3 : 4 xxx input 2 gain : $ b 1 : b 15 - 13 input 1 gain : $ b 1 : b 12 - 10 voice tx level $ c 3 : 2 xxx mux p 2 . 0 : b 7 sum mux p 2 . 0 : b 6 sub - audio detector audio tones sub - audio processing voice processing mux $ b 1 : b 5 - 2 mux $ c 1 : b 15 - 13 mux $ b 1 : b 9 - 6 audio mod 1 mod 2 disc alt mic input 1 input 2 fine gain : $ c 3 : 1 xxx fine gain : $ c 3 : 1 xxx coarse gain $ b 0 : b 14 - 12 coarse gain : $ b 0 : b 10 - 8 coarse gain : $ b 0 : b 3 - 0 audio tone rx level : $ c 3 : 7 xxx sa rx level : $ c 3 : 5 xxx input 2 gain : $ b 1 : b 15 - 13 input 1 gain : $ b 1 : b 12 - 10 voice rx gain $ c 3 : 3 xxx dac 4 sub - audio generator
digital pmr processor cmx7131/cmx7141 ? figure 17 rx audio response figure 18 tx audio response 250 250 3000 3000 2550 2550 300 300 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 10 1000 frequency (hz) db (ref 1khz) $c1=8301, narrow $c1=8301, wide template 250 250 3000 3000 2550 2550 300 300 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 10 1000 frequency (hz) db (ref 1khz) $c1=8302, narrow $c1=8302, wide template
digital pmr processor cmx7131/cmx7141 ? figure 19 ctcss and dcs filters table 4 dcs codes and values register value register value dcs code true inverted dcs code true inverted decimal hex decimal hex decimal hex decimal hex no code 0 00 100 64 311 42 2a 142 8e 23 1 01 101 65 315 43 2b 143 8f 25 2 02 102 66 331 44 2c 144 90 26 3 03 103 67 343 45 2d 145 91 31 4 04 104 68 346 46 2e 146 92 32 5 05 105 69 351 47 2f 147 93 43 6 06 106 6a 364 48 30 148 94 47 7 07 107 6b 365 49 31 149 95 51 8 08 108 6c 3 71 50 32 150 96 54 9 09 109 6d 411 51 33 151 97 65 10 0a 110 6e 412 52 34 152 98 71 11 0b 111 6f 413 53 35 153 99 72 12 0c 112 70 423 54 36 154 9a 73 13 0d 113 71 431 55 37 155 9b 74 14 0e 114 72 432 56 38 156 9c 250 250 3000 3000 2550 2550 300 300 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 10 1000 frequency (hz) db (ref 1khz) $c1=a302, dcs template $c1=a302, ctcss
digital pmr processor cmx7131/cmx7141 ? register value register value dcs code true inverted dcs code true inverted decimal hex decimal hex decimal hex decimal hex 114 15 0f 115 73 445 57 39 15 7 9d 115 16 10 116 74 464 58 3a 158 9e 116 17 11 117 75 465 59 3b 159 9f 125 18 12 118 76 466 60 3c 160 a0 131 19 13 119 77 503 61 3d 161 a1 132 20 14 120 78 506 62 3e 162 a2 134 21 15 121 79 516 63 3f 163 a3 143 22 16 122 7a 532 64 40 164 a4 152 23 17 123 7b 546 65 41 165 a5 155 24 18 124 7c 565 66 42 166 a6 156 25 19 125 7d 606 67 43 167 a7 162 26 1a 126 7e 612 68 44 168 a8 165 27 1b 127 7f 624 69 45 169 a9 172 28 1c 128 80 627 70 46 170 aa 174 29 1d 129 81 631 71 47 171 ab 20 5 30 1e 130 82 632 72 48 172 ac 223 31 1f 131 83 654 73 49 173 ad 226 32 20 132 84 662 74 4a 174 ae 243 33 21 133 85 664 75 4b 175 af 244 34 22 134 86 703 76 4c 176 b0 245 35 23 135 87 712 77 4d 177 b1 251 36 24 136 88 723 78 4e 178 b2 261 37 25 137 89 731 79 4f 179 b3 263 38 26 138 8a 732 80 50 180 b4 265 39 27 139 8b 734 81 51 181 b5 271 40 28 140 8c 743 82 52 182 b6 306 41 29 141 8d 754 83 53 183 b7 user defined 84 54 184 b8
digital pmr processor cmx7131/cmx7141 ? table 5 ctcss codes a nd values register value ctcss tone register value ctcss tone decimal hex frequency decimal hex frequency 200 c8 no tone 228 e4 173.8 201 c9 67.0 229 e5 179.9 202 ca 71.9 230 e6 186.2 203 cb 74.4 231 e7 192.8 204 cc 77.0 232 e8 203.5 205 cd 7 9.7 233 e9 210.7 206 ce 82.5 234 ea 218.1 207 cf 85.4 235 eb 225.7 208 d0 88.5 236 ec 233.6 209 d1 91.5 237 ed 241.8 210 d2 94.8 238 ee 250.3 211 d3 97.4 239 ef 69.3 212 d4 100.0 240 f0 62.5 213 d5 103.5 241 f1 159.8 214 d6 107.2 242 f2 165.5 215 d7 110.9 243 f3 171.3 216 d8 114.8 244 f4 177.3 217 d9 118.8 245 f5 183.5 218 da 123.0 246 f6 189.9 219 db 127.3 247 f7 196.6 220 dc 131.8 248 f8 199.5 221 dd 136.5 249 f9 206.5 222 de 141.3 250 fa 229.1 223 df 146.2 251 fb 254. 1 224 e0 151.4 252 fc user defined 225 e1 156.7 253 fd --- 226 e2 162.2 254 fe dcs turn - off 227 e3 167.9 255 ff invalid tone
digital pmr processor cmx7131/cmx7141 ? 6 detailed descriptions 6.1 xtal frequency the cmx7131/cmx7141 is designed to work with an externa l frequency source of 19.2mhz. if this default configuration is not used, then program register block 3 must be loaded with the correct values to ensure that the device will work to specification with the user selected clock frequency. a table of common v alues can be found in table 6 . note the maximum xtal frequency is 12.288mhz, although an external clock source of up to 24mhz can be used. the register values in table 6 are shown in hex, the default se ttings are shown in bold, and the settings which do not give an exact setting (but are within acceptable limits) are in italics. the new p3.2 - 3 settings take effect following the write to p3.3 (the settings in p3.4 - 7 are implemented on a change to rx or tx mode). table 6 xtal/clock frequency settings for program block 3 program register external frequency source (mhz) 3.579 6.144 9.216 12.0 12.8 16.368 16.8 19.2 p3.2 idle gp timer $017 $018 $018 $019 $019 $018 $019 $018 p3.3 vco output and aux clk divide $085 $088 $08c $10f $110 $095 $115 $099 p3.4 rx or tx ref clk divide $043 $040 $060 $07d $0c8 $155 $15e $0c8 p3.5 pll clk divide $398 $200 $200 $200 $300 $400 $400 $200 p3.6 vco output and aux clk divide $140 $140 $140 $140 $140 $140 $140 $140 p3.7 internal adc/dac clk divide $008 $008 $008 $008 $008 $008 $008 $008 6.2 host interface a serial data interface (c - bus) is used for command, status and data transfers between the cmx7131/cmx7141 and t he host c; this interface is compatible with microwire and spi. interrupt signals notify the host c when a change in status has occurred and the c should read the status register across the c - bus and respond accordingly. interrupts only occur if the app ropriate mask bit has been set. see section 6.6.2 . the cmx7131/cmx7141 will monitor the state of the c - bus registers that the host has written - to every 250s (the c - bus latency period) hence it is no t advisable for the host to make successive writes to the same c - bus register within this period. 6.2.1 c - bus operation this block provides for the transfer of data and control or status information between the cmx7131/cmx7141 s intern al registers and the host c over the c - bus serial interface. each transaction consists of a single address byte sent from the c which may be followed by one or more data byte(s) sent from the c to be written into one of the cmx7131/cmx7141 s write only registers, or one or more data byte(s) read out from one of the cmx7131/cmx7141 s read only registers, as shown in f igure 20 . data sent from the c on the cdata (command data) line is clocked into the cmx7131/cmx7141 on the rising edge of the sclk (serial clock) input. rdata (reply data) sent from the cmx7131/cmx7141 to the c is valid when the sclk is high. the csn line must be held low during a data transfer and kept high
digital pmr processor cmx7131/cmx7141 ? between transfers. the c - bus interface is compatible with most common c serial interfaces and may also be easily implemented with general purpose c i/o pins controlled by a simple software routine. the nu mber of data bytes following an address byte is dependent on the value of the address byte. the most significant bit of the address or data is sent first. for detailed timings see section 7.2 . note that, due to internal timing constraints, there may be a delay of up to 250s between the end of a c - bus write operation and the device reading the data from its internal register. c - bus write: see note 1 see note 2 csn sclk cdata 7 6 5 4 3 2 1 0 7 6 0 7 0 msb lsb msb lsb msb lsb address/command byte upper 8 bits lower 8 bits rdata high z state c - bus read: see note 2 csn sclk cdata 7 6 5 4 3 2 1 0 msb lsb address byte upper 8 bits lower 8 bits rdata 7 6 0 7 0 high z state msb lsb msb lsb data value unimportant repeated cycles either logic level valid (and may change) either logic level valid (but must not change from low to high) f igure 20 c - bus transactions notes: 1. for command byte transfers only the first 8 bits are transferred ($01 = reset). 2. for single byte data transfers only the first 8 bits of the data are transferred. 3. the cdata and rdata lines are nev er active at the same time. the address byte determines the data direction for each c - bus transfer. 4. the sclk input can be high or low at the start and end of each c - bus transaction. 5. the gaps shown between each byte on the cdata and rdata lines in the above diagram are optional, the host may insert gaps or concatenate the data as required.
digital pmr processor cmx7131/cmx7141 ? 6.3 function image ? loading the function image ? (fi), which defines the operational capabilities of the device, may be obtained from the cml technical portal, following regis tration. this is in the form of a 'c' header file which can be included into the host controller software or programmed into an external serial memory. the maximum possible size of function image tm is 46 kbytes, although a typical fi will be less than this . note that the booten pins are only read at power - on or following a c - bus general reset and must remain stable throughout the fi loading process. once the fi load has completed, the booten pins are ignored by the cmx7131/cmx7141 until the next power - up or c - bus general reset. the booten pins are both fitted with internal low current pull - down devices. for c - bus load operation, both pins should be pulled high by connecting them to dv dd either directly or via a 220k resistor (see figure 21 ). for serial memory load, only booten1 needs to be pulled high in a similar manner, however, if it is required to program the serial memory in - situ from the host, either a jumper to dv dd or a link to a host i/o pin shoul d be provided to pull booten2 high when required (see table 7 ). the serial memory interface is shared with the auxiliary c - bus port which controls the cmx6x8 vocoder using a separate chip select (ssout) pin. during boot operations , the ssout will be disabled. once the boot operation has completed, the serial memory chip select (epcsn) will be disabled and the ssout will become operational. once the fi has been loaded, the cmx7131/cmx7141 performs these ac tions: (1) the product identification code ($7141 or $7131) is reported in c - bus register $c5 (2) the fi version code is reported in c - bus register $c9 (3) the two 32 - bit fi checksums are reported in c - bus register pairs $a9, $aa and $b8, $b9 (4) the device waits for the host to load the 32 - bit device activation code to c - bus register $c8 (5) once activated, the device initialises fully, enters idle mode and becomes ready for use, and the programming flag (bit 0 of the status register) will be set. t he checksums should be verified against the published values to ensure that the fi has loaded correctly . once the fi has been activated, the checksum, product identification and version code registers are cleared and these values are no longer available. i f an invalid activation code is loaded, the device will report the value $dead in register $a9 and must be power - cycled before an attempt is made to re - load the fi and re - activate. both the device activation code and the checksum values are available from the cml technical portal. table 7 booten pin states booten2 booten1 c - bus host load 1 1 reserved 1 0 serial memory load 0 1 no fi load 0 0 note: following a general reset, reloading of the function image is strongly recomme nded. 6.3.1 fi loading from host controller the fi can be included into the host controller software build and downloaded into the cmx7131/cmx7141 at power - up over the c - bus interface. the booten pins must be set to the c - bus load conf iguration, the cmx7131/cmx7141 powered up and placed into program mode, the data can then be sent directly over the c - bus to the cmx7131/cmx7141 . if the host detects a brownout, the booten state should be set to re - load the fi. a general reset should then be issued and the appropriate fi load procedure followed.
digital pmr processor cmx7131/cmx7141 ? each time the programming register, $c8, is written, it is necessary to wait for the prg flag (irq status register ($c6) b0) to go high before another write to $c8 . the prg flag going high confirms the write to the programming register has been accepted . the prg flag state can be determined by polling the irq status register or by unmasking the interrupt (interrupt mask register, $ce, b0). the download time is limited by the clock frequency of the c - bus, with a 5mhz sclk, it should take less than 500ms to complete. figure 21 fi loading from host booten 2 = 1 booten 1 = 1 power - up or write general reset to device poll $ c 6 until b 0 = 1 ( programming mode entered ) configure prg flag interrupt if required write $ 0001 to $ c 8 write start block 1 address ( db 1 _ ptr ) to $ b 6 write block 1 length ( db 1 _ len ) to $ b 7 wait for prg flag to go high or interrupt write next data word to $ c 8 wait for prg flag to go high or interrupt write start block 2 address ( db 2 _ ptr ) to $ b 6 write block 2 length ( db 2 _ len ) to $ b 7 write $ 0001 to $ c 8 wait for prg flag to go high or interrupt wait for prg flag to go high or interrupt write next data word to $ c 8 write start block 3 address ( activate _ ptr ) to $ b 6 write block 3 length ( activate _ len ) to $ b 7 write $ 0001 to $ c 8 wait for prg flag to go high or interrupt send activation code hi to $ c 8 read and verify checksum values in register pair : $ a 9 and $ aa , $ b 8 and $ b 9 send activation code lo to $ c 8 wait for prg flag to go high or interrupt wait for prg flag to go high or interrupt booten 1 and booten 2 may be changed from this point on , if required device is now ready for use booten 1 booten 2 v dd
digital pmr processor cmx7131/cmx7141 ? 6.3.2 fi loading from serial memory the fi must be converted into a format for the serial memory programmer (normally intel hex) and loaded into the serial memory either by the host or an external programmer. the cmx7131/cmx7141 needs to have the boot en pins set to serial memory load, and then on power - on, or following a c - bus general reset, the cmx7131/cmx7141 will automatically load the data from the serial memory without intervention from the host controller. figure 22 fi loading from serial memory the cmx7131/cmx7141 has been designed to function with an atmel at25hp512 serial eeprom and the at25f512 flash eep rom devices 2 , however other manufacturers parts may also be suitable. the time taken to load the fi is dependant on the xtal frequency, with a 6.144mhz xtal, it should load in less than 1 second. 2 note that these two devices have slightly different addressing schemes. 7131/7141fi - 5.x is compatible with both schemes. booten 2 = 0 booten 1 = 1 power - up or write general reset to cmx 7131 / cmx 7141 poll $ c 6 until b 0 = 1 ( fi loaded ) configure prg flag interrupt if required send activation code hi to $ c 8 read and verify checksum values in register pair : $ a 9 and $ aa , $ b 8 and $ b 9 send activation code lo to $ c 8 wait for prg flag to go high or interrupt wait for prg flag to go high or interrupt booten 1 and booten 2 may be changed from this point on , if required cmx 7131 / cmx 7141 is now ready for use booten 1 booten 2 vdd jumper for programming serial memory ( if required )
digital pmr processor cmx7131/cmx7141 ? 6.4 cmx618/cmx608 interface an auxiliary spi/c - bus interface is provided which allows the cmx6x8 to be directly controlled by the cmx7131/cmx7141 without the need for the host to intervene. this is acco mplished by re - using the serial memory spi interface with an additional chip select pin (ssout). the serial memory data out pin must not drive the signal line when the chip is not enabled, otherwise the cmx6x8 will not be able to return its data to the cmx7131/cmx7141 . the cmx7131/cmx7141 auxiliary spi/c - bus interface bus should be connected to the c - bus interface on the cmx6x8 using the ssout pin as the csn signal for the cmx6x8 running in c - bus mode (this is the default setting of the spi - c odec ena pin, $b1 bit 0). following receipt of the activation codes at power - on, the function image ? will automatically select c - bus mode and poll the interface to see if a cmx6x8 is connected on its c - bus port. the initialisation and operational settings of the cmx6x8 should be programmed by the host into the cmx7131/cmx7141 program block 1 on power - up. these values will be written to the defined registers in the cmx6x8 at: o initialisation o idle mode o rx mode o tx mode . mic gain and speaker gain commands may be sent to the cmx6x8 whenever the cmx7131/cmx7141 is in rx or tx mode. the dtx and vad modes of the cmx6x8 are not supported in 7131/7141fi - 1 . dtmf mode 1 (transparent) is supported. the default settings for the cmx6x8 are: o 4 - frame packet (80ms) with fec no std, no dtmf o 2400bps with fec o internal sync o throttle = 1 o internal codec o irq disabled o soft - coded data bits. the connections for the cmx6x8 vocoder are: ssout C csn epsi C cdata epso C rdata epsclk C clk no connection C irqn (tied to v dd via 100k resistor).
digital pmr processor cmx7131/cmx7141 ? figure 23 shows one possible implementation of the cmx7141 combined with a cmx618, a host controller and suitable rf se ctions to provide a digital pmr radio. the bold lines show the active signal paths in rx and tx respectively. figure 23 digital voice rx and tx blocks the paralleling of the microphone and speaker connections between the cmx618 an d the cmx7131/cmx7141 is only required if the cmx7131/cmx7141 is also to provide analogue pmr functionality. otherwise, the microphone and speaker should be connected to the cmx618 only. the cmx618 ralc wi vocoder provides an on - chip audio and voice codec, but alternatively a cmx608 device could be used along with an external audio codec. voice payload data is transferred directly from and to the cmx618 by the cmx7131/cmx7141 . 6.5 d vsi vocoder interface if the dvsi vocoder (or other third - party vocoder) is used all radio channel data will need to be transferred over the main c - bus through the host. in this case the vocoder enable program registers (p1.19 and p1.20) should be set app ropriately to respond correctly to the incoming data fields and the spi - codec ena bit ($b1 bit 0) should be set to 1. to speed the power - on process, the automatic presence check for the cmx6x8 may be skipped by setting the spi - codec ena bit before the acti vation codes are loaded during the power - on sequence. cmx 618 cmx 618 host host cmx 7141 cmx 7141 rf section vocoder disc mod 1 mod 2 paramp spi eeprom interface c - bus sclk c - bus cdata c - bus csn c - bus rdata mic spkr modem de - coding rf section vocoder disc mod 1 mod 2 paramp c - bus sclk c - bus cdata c - bus sclk c - bus rdata mic spkr modem coding audio codec audio codec squelch rxena txena squelch rxena txena protocol protocol spi eeprom interface
digital pmr processor cmx7131/cmx7141 ? the connections for the dcr standard vocoder are: ssout C spi_ste epsi C spi_rx_data epso C spi_tx_data epsclk C spi_clk and spi_clk_in. 6.6 device control the cmx7131/cmx7141 can be set into the relevant mode to suit its environment. these modes are described in the following sections and are programmed over the c - bus: either directly to operational registers or, for parameters that are not likely to change during operation, via the programming register ($c8). for basic operation: (1) enable the relevant hardware sections via the power down control register (2) set the appropriate mode registers to the desired state (3) select the required signal routing and gain (4) use the mode control reg ister to place the device into rx or tx mode. to conserve power when the device is not actively processing a signal, place the device into idle mode. this will also command the cmx6x8 to enter powersaving mode as well. additional powersaving can be achieve d by disabling any unused hardware blocks, however, care must be taken not to disturb any sections that are automatically controlled. note that the bias block must be enabled to allow any of the input or output blocks to function. see: o power down control - $c0 write o modem control - $c1 write o modem configuration - $c7 write . 6.6.1 general notes in normal operation, the most significant registers, in addition to the txdata and rxdata blo cks, are: o modem control - $c1 write o irq status - $c6 read o analogue output gain - $b0 write o input ga in and signal routing - $b1 write o auxdata/sub - audio write - $c2 write o cmx6x8 analogue control - $c3 write . setting the mode register to either rx or tx will automatically increase the internal clock speed to its operational speed and bring the cmx6x8 out o f its powersave mode, setting the mode register to idle will automatically return the internal clock to a lower (powersaving) speed. to access the program blocks (through the programming register, $c8) the device must be in idle mode. under normal circums tances the cmx7131/cmx7141 manages the main clock control automatically, using the default values loaded in program block 3. 6.6.2 interrupt operation the cmx7131/cmx7141 will issue an interrupt on the irqn l ine when the irq bit (bit 15) of the irq status register and the irq mask bit (bit 15) are both set to 1. the irq bit is set when the state of the interrupt flag bits in the irq status register change from a 0 to 1 and the corresponding mask bit(s) in the interrupt mask register is(are) set. enabling an interrupt by setting a mask bit (0 ? 1) after the corresponding irq status register bit has already been set to 1 will also cause the irq bit to be set.
digital pmr processor cmx7131/cmx7141 ? all interrupt flag bits in the irq status register, exce pt the programming flag (bit 0), are cleared and the interrupt request is cleared following the command/address phase of a c - bus read of the irq status register. the programming flag bit is set to 1 only when it is permissible to write a new word to the pr ogramming register. see: o irq status - $c6 read o interrupt mask - $ce write . 6.6.3 signal routing the cmx7131/cmx7141 offers a flexible routing architecture, with three signal inputs, a choice of two modulator configurations (to suit two - point modulation or i/q schemes) and a single audio output. see: o input ga in and signal routing - $b1 write o modem control - $c1 write o modem configuration - $c7 write . the analogue gain/attenuation of each input and output can be set individually, with additional fine attenuation control available via the programming registers in the cmx7131/cmx7141 . the mic. and speaker gains are set by the cmx6x8, which is controlled through the cmx6x8 analogue control - $c3 write of the cmx7131/cmx7141 . see: o analogue output gain - $b0 write (mod1 and 2) o input ga in and signal routing - $b1 write (disc input, mod1 and 2) o cmx6x8 analogue control - $c3 write (cmx6x8 mic. and speaker). in common with other fis developed for the cmx7131/cmx7141 , this device is equipped with two signal processing paths. input 1 should be routed to either of the three input sources (alt, disc or mic) which should be connected to the radios discriminator output. the internal signals out put 1 and output 2 are used to provide either two - point or i/q signals 3 and should be routed to the mod1 and mod2 pins as required. in dpmr formatted modes the microphone and speaker paths are automatically re - routed to the cmx6x8 vocoder when appropriate . this routing is controlled by the data field in the header block which indicates whether the payload is speech data, and the cmx6x8 disable bit in the modem control register, $c1. 6.6.4 modem control the cmx7131/cmx7141 operates in o ne of these operational modes: o idle o rx o tx o cmx6x8 pass - through. at power - on or following a reset, the device will automatically enter idle mode, which allows maximum powersaving whilst still retaining the capability of monitoring the auxadc inputs (if enabl ed). it is only possible to write to the programming register whilst in idle mode. see: o modem control - $c1 write . gpio1 and gpio2 pins (rxena and txena) reflect bits 0 and 1 of the modem control register, as shown in table 8 . these can be used to drive external hardware without the host having to intervene. there are also two additional gpio pins that are programmable under host control. 3 i/q mode is only appropriate for digital/dpmr mode. it is not recommended for analogue pmr mode.
digital pmr processor cmx7131/cmx7141 ? table 8 modem mode selecti on modem control ($c1) b0 - 3 modem mode gpio2 - txena gpio1 - rxena 0000 idle C low power mode 1 1 0001 rx 1 0 0010 tx 0 1 0011 reserved x x 0100 cmx6x8 pass - through 1 1 0101 reserved x x 0110 reserved x x 0111 reserved x x 1xxx reserved x x the c mx 6x8 pass - through mode is used to control and monitor the cmx 6x8 directly. this cannot be accessed if the cmx7131/cmx7141 is in rx or tx modes. this mode will transfer data to/from the txdata0/rxdata0 register to the cmx6x8 c - bu s register address specified in the programming register ($c8). see section 6.6.14 . the modem control bits are ignored in this mode. table 9 modem control selection 4fsk modem control ($c1) b7 - 4 rx tx 0000 rx idle tx idle 0001 rx 4fsk formatted tx 4fsk formatted 0010 reserved reserved 0011 rx 4fsk eye tx 4fsk prbs 0100 reserved tx 4fsk preamble 0101 reserved tx 4fsk mod set - up 0110 sync test 0111 reset/abort reset/abort 1xxx reserved reserved the modem mode bits and the modem control bits should be set together in the same c - bus write. 6.6.5 tx mode dpmr in tx dpmr mode operation ($c1, modem control = $0012), the host should write the initial header data block to the c - bus txdata registers and then set the modem mode to 4fsk format and the mode bits to tx, the preamble and frame sync are transmitted automatically followed by the header data. as soon as the data block has been read from the c - bus txdata registers, the datardy irq will be asserted and the next block of data may be loaded, if required. if the vocoder has been enabled, data will be taken directly from it for transmission over - air. when the host sends the end block and after the last data bit has left the modulator a txdone irq will be i ssued. at this point it is now safe for the host to change the modem control and modem mode to idle ($c1, modem control = $0000) and turn the rf transmitter off. 6.6.6 tx mode prbs in prbs mode ($c1, modem control = $0032) the preamble and frame sync are transmi tted automatically followed by a prbs pattern conforming to itu - t o.153 (para 2.1) giving a 511 - bit repeating sequence. 6.6.7 tx mode preamble in preamble mode ($c1, modem control - $0042) the preamble sequence [+3 +3 - 3 - 3] is sent continually. this can be use d to set up and adjust the rf hardware.
digital pmr processor cmx7131/cmx7141 ? 6.6.8 tx mode mod set - up in mod set - up mode ($c1 = $0052), in two - point mode, a repeating sequence of eight +3 symbols followed by eight - 3 symbols, and in i/q mode a continuous sequence of +3 symbols. this can be used to set up and adjust the rf hardware. 6.6.9 tx mode analogue in analogue pmr mode, the mic input is processed and summed with either the external sub - audio signal on the alt input or the internally generated sub - audio signal and then presented at the mod1 and mod2 pins. the choice is determined by program block p2.0 b5 (see section 8.2.3 ). 6.6.10 rx mode dpmr in rx dpmr mode operation ($c1, modem control = $0011), the received signal should be routed through input1 (disc) and the cmx7131/cmx7141 will automatically start searching for frame synchronisation. when a valid frame sync sequence is detected, an fs1 detect or fs2 detect irq is asserted and the data demodulator is enabled. if the addressing parameters are valid, the header block is loaded into the c - bus rxdata registers with a datardy irq. if the vocoder is not required then, all following payload data is loaded into the c - bus rxdata registers with a dataready irq to indicate when each new block is available. if soft data mode has been selected, the payload data is encoded in 4 - bit log - likelihood - ratio format. in this mode the host must be able to service the dataready irqs and rxdata registers at four times the normal rate to avoid over flow. 6.6.11 rx mode eye in rx 4fsk eye mode ($c1 = $0031), the filtered received signal is output at the mod1 pin as an eye diagram for test and alignment purposes. a trigger pulse is output at the mod2 pin to allow viewing on a suitable oscilloscope. the trig ger pulse is generated directly from the receiver xtal source, not from the input signal. 6.6.12 rx mode analogue in rx mode the received signal should be routed through input1 (disc). the signal is filtered and processed so that the inband signal is output on t he audio pin and the sub - audio signal is either output on the auxdac4 pin or routed to the internal sub - audio detector. the choice is determined by program block p2.0 b4 (see section 8.2.3 ). 6.6.13 data transfer payload data is transf erred from/to the host using blocks of five rx and five tx 16 - bit c - bus registers, allowing up to 72 bits (9 bytes) of data to be transferred in sequence. the lowest 8 bits of the register block are reserved for a byte counter, block id and a transaction c ounter. the byte count indicates how many bytes in the data block are valid and avoids the need to perform a full five word c - bus read/write if only a smaller block of data need to be transferred. table 10 c - bus data registers c - bu s address function c - bus address function $b5 tx data 0 - 7 and info $b8 rx data 0 - 7 and info $b6 tx data 8 - 23 $b9 rx data 8 - 23 $b7 tx data 24 - 39 $ba rx data 24 - 39 $ca tx data 40 - 55 $bb rx data 40 - 55 $cb tx data 56 - 71 $c5 rx data 56 - 71 bits 7 and 6 ho ld the transaction counter, which is incremented modulo 4 on every read/write of the data block to allow detection of data underflow and overflow conditions. in tx mode the host must increment the counter on every write to the txdata block, and if the cmx7131/cmx7141 identifies that a block has been written out of sequence, the event bit (c - bus register $c6, b14) will be asserted and an irq raised, if enabled. the device detects that new data from the host is available by the chan ge in the value of the transaction counter, therefore the host should ensure that all the data is available in the txdata block before updating this register (ie, it should be the last register the host writes to in any block transfer). in rx
digital pmr processor cmx7131/cmx7141 ? mode, the cmx7131/cmx7141 will automatically increment the counter every time it writes to the rxdata block, if the host identifies that a block has been written out of sequence, then it is likely that a data overrun condition has occurred an d some data has been lost. 6.6.14 cmx6x8 pass - through mode to allow the host to communicate directly with the cmx 6x8 for test and configuration purposes, a pass - through mode is available which allows any cmx 6x8 c - bus register to be read or written (as appropriate ). this mode uses the txdata0, rxdata0 and programming registers on the cmx7131/cmx7141 . to write to the cmx 6x8 : o set the cmx7131/cmx7141 to cmx 6x8 pass - through mode ($c1=$0004) o wait for the program fla g to be set ($c6 b0) o write the cmx 6x8 data value to the txdata0 register ($b5) o write the cmx 6x8 c - bus address to the programming register ($c8) with b15=0 o wait for the program flag to be set ($c6 b0). to read from the cmx 6x8 : o set the cmx7131/cmx7141 to cmx 6x8 pass - through mode ($c1=$0004) o wait for the program flag to be set ($c6 b0) o write the cmx 6x8 c - bus address to the programming register ($c8) with b15=1 o wait for the program flag to be set ($c6 b0) o read the cmx 6x8 data value f rom the rxdata0 register ($b8). cmx 6x8 c - bus addresses are all 8 bits long and should be written to bits 0 - 7 of the programming register. bit 15 is the read/write flag (0 = read, 1 = write) and bit 14 is the register - size flag (0 = 16 - bit, 1 = 8 - bit). un used bits should be cleared to zero. when an 8 - bit register is read or written, the data occupies the lower 8 bits of the appropriate data register (txdata0 or rxdata0). 6.7 dpmr formatted operation the cmx7131/cmx7141 performs all frame building/splitting and fec coding/decoding, which relieves the host controller of a significant processing load. during voice calls the cmx7131/cmx7141 can automatically enable and control the cmx6x8, and transfer voice pa yload data from/to it without host intervention. in rx mode the cmx7131/cmx7141 monitors address fields in incoming transmissions and only accepts calls if the programmed address requirements are satisfied. this allows the host t o remain in a power - down or sleep state until it is really necessary to wake up, extending the battery life of the final product design. 6.7.1 operating modes and addressing ts 102 490 describes two operating modes for a dpmr radio: o isf C initial services a nd facilities C out of the box mode o csf C configured services and facilities C managed mode. the cmx7131/cmx7141 can support either of these modes, as selected by b9 of the modem configuration register, $c7 (see user manual s ection 8.1.28 ). the standard also defines two addressing schemes: 24 - bit binary or 7 - digit bcd (binary - coded - decimal). radios operating in isf mode are required to use binary addressing, but in csf mode either binary or bcd add ressing can be used. both addressing schemes are supported by the cmx7131/cmx7141 , selected by b11 in the modem configuration register, $c7 (see user manual section 8.1.28 ). the host can load two own ids (binary or bcd) into program block 1 for use in both tx and rx modes. in tx mode the host can select which of these to send in the caller id field of the outgoing call. in rx mode the cmx7131/cmx7141 compares the called i d field from incoming calls against each of its own ids, and will accept the call if a valid id match is found. address matching can be disabled using b12 of the modem configuration register, $c7 in which case the cmx7131/cmx7141 will accept all incoming calls.
digital pmr processor cmx7131/cmx7141 ? the cmx7131/cmx7141 implements bcd address translation in both tx and rx, to relieve the host of the processing required to map bcd digits to over - air binary values. bcd addresses can include wildcard digits in any of the lower four digits, and there are ten bcd all - call addresses with wildcards in all six lower digits. the cmx7131/cmx7141 handles wildcard digits appropriately during address matching in rx. binary addresses do not support group calling with wildcards, but the cmx7131/cmx7141 provides six binary - only group call ids in addition to the two own ids. these can be programmed by the host to be used for address matchin g in rx only. ts 102 490 also specifies a system - wide all call facility using the communication format field in the header frame (ts 102 490 section 5.8). the normal setting for this field is peer - to - peer, but when set to call all the cmx7131/cmx7141 will always accept the call regardless of isf/csf mode and all other address settings. the host should take care not to transmit in all call mode unless actually intended. 6.7.2 isf addressing the services available i n isf mode are described in ts 102 490 section 8.1. radios using isf mode provide a style of operation broadly similar to analogue pmr446. isf mode requires 24 - bit binary addressing to be used, with only the top 8 bits (the common id field) in active use f or addressing isf mode devices. the remaining 16 bits must be set to all 1s. this is the default mode of the cmx7131/cmx7141 and the default common ids are: o id1: $01 o id2: $02. the isf common all - call id is $ff. wh en in isf mode the cmx7131/cmx7141 will always accept calls to this address regardless of other address settings. 6.7.3 csf addressing the services available in csf mode are described in ts 102 490 section 8.2 and annex a. csf mode does not mandate bcd addressing unless the host implements the standard user interface, but the advantages of bcd addressing are direct mapping of user keypad entries to destination addresses and the option of wildcard digits to implement grou p calls. the host can select the addressing mode using b11 of the modem configuration register, $c7. 6.7.4 tx mode (dpmr formatted) in tx dpmr formatted mode ($c1, modem control = $0012), the cmx7131/cmx7141 builds head er, control channel and end information blocks, performs all fec coding, interleaving and scrambling functions and inserts frame sync and colour code sequences to generate the required frame formats for transmission. during voice calls the cmx7131/cmx7141 can automatically enable and control the cmx6x8, and transfer voice payload data from/to it without host intervention. the txdata registers are used to transfer header and end information fields in addition to payload data. the b lock id field in the txdata0 register informs the cmx7131/cmx7141 how to process each transfer. b5 - 4 block id 00 hdr - header data 01 pld - payload data 10 pls - payload data with slow data 11 end - end data the host should preload the txdata registers with header data before placing the device in tx dpmr formatted mode. the cmx7131/cmx7141 reads the header type field to determine the burst type and then sends the p reamble and header frame. if the call information field indicates that repeated extended wake - up headers are to be sent, the cmx7131/cmx7141 will do so automatically. the header fields are saved for re - use wh en building the control channel information blocks in following payload frames: the host does not need to re - load them.
digital pmr processor cmx7131/cmx7141 ? header data: txdata rxdata 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 le 0 own id header type counter 0 0 1 0 0 1 1 0 0 call information comms mode 2 version format 0 0 0 0 0 0 colour code 3 0 0 0 0 binary mode: called address lower 12 bits bcd mode: called address lower 4 digits k4, k5, k6, k7 4 0 0 0 0 binary mode: called address upper 12 bits 0 0 0 0 bcd mode: called address up per 3 digits k1, k2, k3 header type: see ts 102 490 section 5.11 (communication start, ack, etc.) own id: 00 = reserved 01 = send own id 1 (from program block 1) 10 = send own id 2 (from program block 1) 11 = reserved reserved : see ts 102 490 section 5.4 (00) comms mode: see ts 102 490 section 5.7 (sets data type and source, host or vocoder) le: late - entry (rx only) C some data fields may be missing due to late entry into the call call information: see ts 102 490 section 5.10 (inclu des extended headers, data frame size etc.) comms format: see ts 102 490 section 5.8 (all - call or peer - to - peer) 00 = call all (broadcast) 01 = peer - to - peer communication 10 = reserved 11 = reserved version: see ts 102 490 section 5.16 (vocoder version) n ote: the dpmr mou group has agreed standard bit allocations for the voice burst and the host should set this field accordingly 00 = dvsi ambe+2 01 = tbd 10 = ralcwi cmx6x8 11 = manufacturer defined colour code: 6 - bit index into the colour code table as sh own in ts 102 490 section 6.1.5 payload data: see table 10 and user manual section 8.1.15 payload data with slow data: see table 10 and user manual section 8.1.15 end data: txdata rxdata 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 tx wait ack req end type counter 1 1 0 0 1 1 1 0 0 0 0 0 0 reserved 0 status message 2 not used 3 not used 4 not used end type: see ts 102 490 section 5.12 ack reque st: see ts 102 490 section 5.13 tx wait: see ts 102 490 section 5.14 status msg: see ts 102 490 section 5.15 reserved : 0000.
digital pmr processor cmx7131/cmx7141 ? depending on the burst type, the cmx7131/cmx7141 will expect the host to load a series of payload data blocks and/or an end data block (except for ack bursts which consist of a bare header frame). disconnect bursts contain a repeated header/end frame pair but the host should only load single blocks of header and end data fields, as the cmx7131/cmx7141 will send the duplicate frames automatically. if the cmx 6x8 vocoder is enabled and the communication mode field in the header frame indicates a voice call, the cmx7131/cmx7141 will automatically enable the cmx 6x8 microphone input and route payload data from the cmx 6x8 for transmission. note that the cmx6x8 takes a finite time to encode the incoming voice data, during which the cmx7131/cmx7141 will automatically insert silence data into the payload frames. the host can load an end frame at any point during the call. to terminate the voice call, the host should place the cmx7131/cmx7141 modem into tx idle mode ($c1, modem control = $0002). the cmx7131/cmx7141 will disable the cmx 6x8 and send the end frame that was loaded previously. at the end of all dpmr transmissions the cmx7131/cmx7141 will issue a txdone irq when it is safe for the host to place the device back into idle mode ($c1, modem control = $0000).
digital pmr processor cmx7131/cmx7141 ? figure 24 tx data flow load header to c - b us txdatablock transaction count = 0 , byte count = 9 set modem control to : 4 fsk , mode = tx irq = datardy ? no gpio 2 and gpio 1 will change to 0 1 and the modem will transmit the preamble , frame sync and data the host should ensure that any external hardware is also set into tx mode ( if not automatically controlled by the gpio pins ). note : yes more data to send ? load data to c - b us txdatablock transaction count ++ , byte count = 9 yes no see rx _ process flow diagram note : set modem control to idle : mode = idle gpio 2 and gpio 1 will change to 11 and the modem will drop into idle mode . the host should ensure that any external hardware is also set into idle mode ( if not automatically controlled by the gpio pins ). note : goto rx _ process goto idle mode ramdac has been enabled data is in 9 byte blocks note : tx _ process irq = txdone ? no yes irq = error , modem status = underflow may occur at this point , if enabled . note : due to internal processing delays in the filters etc , the host should wait for irq = txdone or implement its own delay to ensure all data has been transmitted . note : execute ramdac down execute ramdac up ensure that ramdac speed is fast enough to allow for hardware and internal processing delays note : load end to c - b us txdatablock transaction count ++ , byte count = 9
digital pmr processor cmx7131/cmx7141 ? 6.7.5 rx mod e (dpmr formatted) in rx dpmr formatted mode ($c1, modem control = $0011) the cmx7131/cmx7141 automatically splits incoming calls to extract header information, control channel information and end information bloc ks and performs all the necessary de - scrambling, de - interleaving and fec decoding functions. in speech calls the cmx7131/cmx7141 can automatically enable the cmx6x8 vocoder when required and transfer received spee ch data without host intervention. the rxdata registers are used to transfer header and end data fields in addition to payload data. the block id field in the rxdata0 register informs the host what type of data block each transfer contains. the field layou t in the rxdata registers for the different transfer types is the same as for tx dpmr formatted mode (section 6.7.4 ). when placed in rx dpmr formatted mode the cmx7131/cmx7141 automati cally starts searching for the dpmr frame sync sequences. in addition to detecting the 48 - bit fs1 frame sync at the start of a transmission, the cmx7131/cmx7141 can also perform late entry into a call by detecti ng two successive copies of the 24 - bit fs2 sequence at the correct two - frame spacing. when a valid frame sync sequence has been detected, an fs1 detect or fs2 detect irq is issued and the data demodulator is enabled. the cmx7131/cmx7141 then decodes the contents of the header frame (after an fs1 detect) or the following four control channel information blocks (after an fs2 detect). the header information or control channel information crcs are checked and proce ssing continues only if a full set of valid fields has been received. header frames contain two duplicate header information blocks: the cmx7131/cmx7141 checks both block crcs, uses the first valid block and disca rds the other. when repeated extended wake - up header frames are received (see ts 102 490 section 11.1) the cmx7131/cmx7141 will decode the first valid header but delay address checking until all following repeat headers have been received. this maximises the time the host can be kept in powersave. address checking now takes place depending on isf/csf mode and the addressing mode selected. the communications format field is checked first: if this is set to call all the call is accepted. if not, the called station id is checked against the devices own ids (programmed by the host into program block 1) and if a match is found the call is accepted. in isf mode the common all - call id $ff is also always accepted. in any of these cases a called irq is issued to the host, otherwise the call is dropped with no further host notification and the cmx7131/cmx7141 returns to frame sync search. address matching can be disabled by setting b12 of the modem configuration register, in which case the cmx7131/cmx7141 will accept all incoming calls. the header fields are presented to the host in the rxdata block. late entry is indicated by bit 1 5 of rxdata1: in this case the header type and call information fields in the header data block returned to the host will not contain valid data, as these fields are only sent in header frames and are not re - sent in the control channel information bloc ks during a call. depending on the burst type the cmx7131/cmx7141 will decode the following payload and/or end frames and present their contents to the host or vocoder. if the cmx 6x8 vocoder is enabled and the co mmunication mode field in the header frame indicates a voice call, the cmx7131/cmx7141 will automatically enable the cmx 6x8 speaker output and route payload data to the cmx 6x8 for decoding. in this mode, the data is transferred in 4 - bit log - likelihood - ratio format. otherwise payload data is presented to the host in the rxdata registers in soft or hard format as specified. when an end frame is received the cmx7131/cmx7141 will report its contents to the host, disable the vocoder (if necessary) and return to frame sync search.
digital pmr processor cmx7131/cmx7141 ? figure 25 rx data flow all frame sync sequences, colour codes and crcs contained in payload sup erframes are checked and an event irq is issued when any are received incorrectly. if all the frame sync sequences, colour codes and crcs in a superframe are received incorrectly, the superframe is considered corrupt. the host can set a threshold for con secutive corrrupt superframes (in program block 0) after which the cmx7131/cmx7141 will issue an event irq, drop the call and return to frame sync search. see: o rxdata 0 - $b8 read o auxdata/sub - audio read - $cc read . 6.7.6 slow data slow data may be transferred in voice calls alongside voice payload data, by setting the block id to payload with slow data and using the auxdata registers. if the cmx6x8 is enabled, there will be no voice payload transfers and so dummy payload transfers are used with the byte counter field cleared to zero. in type1 and type 2 data calls the slow data field is used to control the data flow over - air and so is rx _ process set modem control to : 4 fsk , mode = rx irq = datardy ? no gpio 2 and gpio 1 will change to 1 0 , the modem will start to look for frame sync . the host should ensure that any external hardware is also set into rx mode ( if not automatically controlled by the gpio pins ). note : yes end block receive d ? load data from c - b us rxdatablock check transaction count and byte count no see tx _ process flow diagram note : set modem control to : rx idle , mode = idle gpio 2 and gpio 1 will change to 11 , and the modem will drop into idle mode . the host should ensure that any external hardware is also set into idle mode ( if not automatically controlled by the gpio pins ). note : goto tx _ process goto idle _ process ramdac has been enabled data is in 9 byte blocks note : if enabled , irq = framesync will occur before irq = datardy note : an irq = datardy may still be pending at this point note : yes
digital pmr processor cmx7131/cmx7141 ? generated or decoded by the cmx7131/cmx7141 itself and the only data field that is visible to the host is the format field as defined in ts 102 490 section 5.9.2. which is made available, or supplied by the host, in the lowest 4 bits of the auxdata register. in tx mode: o load auxdata register with two bytes of slow data: auxdata/sub - audio write - $c2 write o set communications mode to voice with slow data o set blockid to payload with slow data: txdata 0 - $b5 write o set byte counter field (to zero if cmx6x8 is in use): txdata 0 - $b5 write . the cmx7131/cmx7141 has an internal 64 - byte buffer for slow data. while the host keeps this internal data buffer toppe d - up the cmx7131/cmx7141 will continue to transmit slow data and add the continuation bits to the over - air data. note that only two bytes of slow data are sent over - air for every 36 bytes of voice payload, so the buffer may ov erflow if a large quantity of slow data is loaded continuously. an irq bit will be raised when there are only two bytes left in the fifo. when the host allows the internal buffer to empty, the cmx7131/cmx7141 will terminate the t ransmission of slow data in the current burst. it is not possible to re - start slow data transmission within a burst. in rx mode: o blockid will report payload with slow data: rxdata 0 - $b8 read o communications mode will report v oice with slow data o if payload is being sent to the cmx6x8, then the byte counter field will be cleared to zero o slow data is available in the auxdata register: auxdata/sub - audio read - $cc read . when the slow data transfer has c ompleted, the cmx7131/cmx7141 will stop presenting data to the host. 6.8 squelch operation many limiter/discriminator chips provide a noise - quieting squelch circuit around an op - amp configured as a filter. this signal is conventional ly passed to a comparator to provide a digital squelch signal, which can be routed directly to one of the cmx7131/cmx7141 s gpio pins or to the host. however with the cmx7131/cmx7141 , the comparator and threshold operations can be replaced by one of the auxadcs with programmable thresholds and hysteresis functions. see: o irq status - $c6 read o modem configuration - $c7 write . 6.9 gpio pin operation the cmx7131/cmx7141 provides four gpio pins: gpio1, gpio2, gpioa and gpiob. rxena (gpio1) and txena (gpio2) are configured to reflect the tx/rx state of the mode register (txena and rxena, active low). see: o modem configuration - $c7 write . note that rxena and txena will not change state until the relevant mode change has been executed by the cmx7131/cmx7141 . this is to allow the host sufficient time to load the relevant data buffers and the cmx7131/cmx7141 time to encode the data required prior to its transmission. there is thus a fixe d time delay between the gpio pins changing state and the data signal appearing at the mod output pins. during the power - on sequence (until the fi has completed its load sequence) these pins have only a weak pull - up applied to them, so care should be taken to ensure that any loading during this period does not adversely affect the operation of the unit. gpioa and gpiob are host programmable for input or output using the auxadc configuration register, $a7. the default state is output, high level. when set fo r input, the values can be read back using the modem status register, $c9.
digital pmr processor cmx7131/cmx7141 ? 6.10 auxiliary adc operation the inputs to the two auxiliary adcs can be independently routed from any of the signal input pins under control of the auxadc configuration register, $a7. c onversions will be performed as long as a valid input source is selected. to stop the adcs, the input source should be set to off. register $c0, b6, bias, must be enabled for auxiliary adc operation. averaging can be applied to the adc readings by selec ting the relevant bits in the auxadc configuration register, $a7, the length of the averaging is determined by the value in the programming register (p3.0 and p3.1), and defaults to a value of 0. this is a rolling average system such that a proportion of t he current data will be added to the last average value. the proportion is determined by the value of the average counter in p3.0 and p3.1. for an average value of: 0 = 50% of the current value will be added to 50% of the last average value, 1 = 25% of t he current value will be added to 75% of the last average value, 2 = 12.5% etc. the maximum useful value of this field is 9. high and low thresholds may be independently applied to both adc channels (the comparison is applied after averaging, if this is e nabled) and an irq generated when a rising edge passes the high threshold or a falling edge passes the low threshold, see figure 26 . the thresholds are programmed via the auxadc threshold register, $cd. see figure 26 . figure 26 auxadc irq operation auxiliary adc data is read back in the auxadc data registers ($a9 and $aa) and includes the threshold status as well as the actual conversion data (subject to averaging, if enabled). see: o auxadc configuration - $a7 write o auxadc1 data and status - $a9 read o auxadc2 data and status - $aa read o auxadc threshold data - $cd write . 6.11 auxiliary dac/ramdac operation the four auxiliary dac channels are programmed via the auxdac data/control register, $a8. auxdac channel 1 may also be programmed to operate as a ramdac which will automatically output a pr e - signal irq irq irq irq high threshold low threshold
digital pmr processor cmx7131/cmx7141 ? programmed profile at a programmed rate. the auxdac data/control register, $a8, with b12 set, controls this mode of operation. the default profile is a raised cosine (see table 15 ), but this may be over - written with a user - defin ed profile by writing to programming register p3.11. the ramdac operation is only available in tx mode and, to avoid glitches in the ramp profile, it is important not to change to idle or rx mode whilst the ramdac is still ramping. the auxdac outputs hold the user - programmed level during a powersave operation if left enabled, otherwise they will return to zero. note that access to all four auxdacs is controlled by the auxdac data/control register, $a8, and therefore to update all auxdacs requires four write s to this register. it is not possible to simultaneously update all four auxdacs. auxdac4 is used in analogue mode to output the filtered sub - aaudio signal. see: o auxdac data / control - $a8 write . 6.12 rf synthesiser (cmx7131 only) the cmx7131 includes two integer - n rf synthesisers, each comprising a divider, phase comparator and charge pump. the divider has two sets of n and r registers: one set can be used for transmit and the other for receive. the division ratios can be set up in ad vance by means of c - bus registers. a single c - bus command will change over from the transmit to the receive division ratios, or vice versa, enabling a fast turnaround. see: o rf synthesiser data - $b2 write o rf synthesiser control - $b3 write o rf synthesiser status - $b4 8 - bit read . external rf components are needed to complete the synthesiser circuit. a typical schematic for a 446mhz synthesiser (3.1 25khz comparison frequency) is shown in figure 27 . figure 27 example rf synthesiser components r31 0 ? c31 22nf r32 5.6k ? c32 470nf r33 10k ? c33 10nf r34 100 ? c34 1n f c35 1nf resistors ? 5%, capacitors and inductors ? 20% unless otherwise stated. note: r31 is chosen within the range 0 ? to 30k ? and selects the nominal charge pump current. cmx 7131 + - rf output rfnp rfnn rfv ss rfv dd cpv dd charge pump dividers and phase detector rfv ss r 31 rfv ss vco c 35 c 34 r 33 c 33 c 32 r 32 c 31 cpnout isetn reference frequency note : n = 1 or 2 for synthesiser 1 or 2 r 34
digital pmr processor cmx7131/cmx7141 ? it is recommended that c34 and c35 are kept close to the vco and that the s tub from the vco to the cmx7131 is kept as short as possible. the loop filter components should be placed close to the vco. figure 28 single rf synthesiser block diagram the two rf synthesisers are programmable to any frequency in the range 100mhz to 600mhz. figure 28 is a block diagram of one synthesiser channel. the rf synthesiser clock is selectable between the xtal or the clock supplied to the rfclk input pin. the rf synthesiser clock is common to both synthesisers. the charge pump supply (cp supply, cpvdd) is also common to both synthesisers. the rfnp and rfnn input pins, cpnout, isetn and rfvss pins are channel specific and designated as either rf1p, rf1n, cp1out, iset1, rfvss or rf2p , rf2n, cp2out, iset2, rfvss on the signal list in section 3 . the n and r values for tx and rx modes are synthesiser specific and can be set from the host c via the c - bus. various synthesiser specific status signals are also a ccessible via c - bus. the divide by n counter is 20 bits; the r counter is 13 bits. typical external components are shown in figure 27 . both synthesisers are phase locked loops (plls) of the same design, utilising e xternal vcos and loop filters. the vcos need to have good phase noise performance although it is likely that the high division ratios used will result in the dominant noise source being the reference oscillator. the phase detectors are of the phase - frequen cy type with a high impedance charge pump output requiring just passive components in the loop filter. lock detect functions are built in to each synthesiser and the status reported via c - bus. a transition to out - of - lock can be detected and communicated vi a a c - bus interrupt to the host c. this can be important in ensuring that the transmitter cannot transmit in the event of a fault condition arising. two levels of charge pump gain are available to the user, to facilitate the possibility of locking at dif ferent rates under program control. a current setting resistor (r31) is connected between the iset pin (one for each pll system) and the respective rfvss pin. this resistor will have an internally generated band gap voltage expressed across it and may have a value of 0 ? to 30k ? , which (in conjunction with the on - chip series resistor of 9.6k ? ) will give charge pump current settings over a range of 2.5ma down to 230a (including the control bit variation of 4 to 1). the value of the current setting resistor ( r31) is determined in accordance with the following formulae: gain bit set to 1: r31 (in ) = (24/i cp ) C 9600 gain bit cleared to 0: r31 (in ) = (6/i cp ) C 9600 where i cp is the charge pump current (in ma). note that the charge pump current should always be set to at least 230a. the gain bit refers to either bit 3 or bit 11 in the rf synthesiser control register, $b3.
digital pmr processor cmx7131/cmx7141 ? the step size (comparison frequency) is programmable; to minimise the effects of phase noise this should be kept as high as possible. this can be set as low as 2.5khz (for a reference input of 20 mhz or less), or up to 200khz C limited only by the performance of the phase comparator. the frequency for each synthesiser is set by using two registers: an r register that sets the division value of the input reference frequency to the comparison fre quency (step size), and an n register that sets the division of the required synthesised frequency from the external vco to the comparison frequency. this yields the required synthesised frequency (fs), such that: fs = (n/r) x f ref where f ref is the s elected reference frequency other parameters for the synthesisers are the charge pump setting (high or low) since the set - up for the plls takes four rf synthesiser data register writes it follows that, while updating the pll settings, the registers may contain unwanted or intermediate values of bits. these will persist until the last register is written. it is intended that users should change the content of the rf synthesiser data register on a pll that is disabled, powersaved or selected to work fro m the alternate register set (tx and rx are alternate register sets). there are no interlocks to enforce this intention. the names tx and rx are arbitrary and may be assigned to other functions as required. they are independent sets of registers, o ne of which is selected to command each pll by changing the settings in the rf synthesiser control - $b3 write register. for optimum performance, a common master clock should be used for the rf synthesisers (the r f synthesiser clock ) and the baseband sections (main and auxiliary system clocks). using unsynchronised clocks can result in spurious products being generated in the synthesiser output and in some cases difficulty may be experienced with obtaining lock in the rf synthesisers. lock status the lock status can be observed by reading the rf synthesiser status register, $b4, and the individual lock status bits can (subject to masking) provide a c - bus interrupt. the lock detector can use a tolerance of one cycle or four cycles of the reference clock (not the divided version that is used as a comparison frequency) in order to judge phase lock. an internal shift register holds the last three lock status measurements and the lock status bits are flagged according to a majority vote of these previous three states. hence, one occasional lock error will not flag a lock fail. at least two successive phase lock events are required for the lock status to be true. note that the lock status bits confirm phase lock to the me asured tolerance and not frequency lock. the synthesiser may take more time to confirm phase lock with the lock status bits than the time to switch from channel to channel. the purpose of a four - cycle tolerance is for the case where a high frequency refere nce oscillator would not forgive a small phase error. rf inputs the rf inputs are differential and self biased (when not powersaved). they are intended to be capacitatively coupled to the rf signal. the signal should be in the range 0dbm to C 20dbm (not nec essarily balanced). to ensure an accurate input signal the rf should be termi nated with 50 as close to the chip as possible and with the p and n inputs capacitatively coupled to the input and ground, keeping these connections as short as possible. the rf input impedance is almost purely capacitative and is dominated by package and printed circuit board parasitics. guidelines for using the rf synthesisers ? rf input slew rate (dv/dt) should be 14v/s minimum. ? the rf synthesiser 2.5v digital supply can be powered from the vdec output pin. ? rf clock sources and other, different clock sources must not share common ic components, as this may introduce coupling into the rf. unused ac - coupled clock buffer circuits should be tied off to a dc supply , to prevent them oscillating. ? it is recommended that the rf synthesisers are operated with maximum charge pump gain (ie. iset tied to rfvss). ? the loop filter components should be optimised for each vco.
digital pmr processor cmx7131/cmx7141 ? 6.13 digital system clock generators figure 29 digital clock generation schemes the cmx7131/cmx7141 includes a two - pin crystal oscillator circuit. this can either be configured as an oscillator, as shown in section 4.2 , or the xtal input can be driven by an externally generated clock. the c rystal (xtal) source frequency can go up to 12.288mhz (clock source frequency up to 24.576mhz), but a 19.2mhz oscillator is assumed by default for the functionality provided in the cmx7131/cmx7141 . ref clk div / 1 to 512 $ ac b 0 - 8 pd vco pll div / 1 to 1024 $ ab b 0 - 9 lpf sysclk 1 ref sysclk 1 div vco op div / 1 to 64 $ ab b 10 - 15 sysclk 1 pre - clk $ ac b 11 - 15 sysclk 1 output 384 khz - 20 mhz 48 C 192 khz ( 96 khz typ ) sysclk 1 vco 24 . 576 - 98 . 304 mhz ( 49 . 152 mhz typ ) ref clk div / 1 to 512 $ ae b 0 - 8 pd vco pll div / 1 to 1024 $ ad b 0 - 9 lpf sysclk 2 ref sysclk 2 div vco op div / 1 to 64 $ ad b 10 - 15 sysclk 2 pre - clk $ ae b 11 - 15 sysclk 2 output 384 khz - 20 mhz 48 C 192 khz ( 96 khz typ ) sysclk 2 vco 24 . 576 - 98 . 304 mhz ( 49 . 152 mhz typ ) ref clk div / 1 to 512 p 3 . 4 pd vco pll div / 1 to 1024 p 3 . 5 lpf mainclk ref mainclk div vco op div / 1 to 64 p 3 . 3 & 3 . 6 mainclk pre - clk mainclk output 384 khz - 50 mhz ( 24 . 576 mhz typ ) 48 C 192 khz ( 96 khz typ ) mainclk vco 24 . 576 - 98 . 304 mhz ( 49 . 152 mhz typ ) to internal adc / dac dividers auxadc div p 3 . 3 & p 3 . 6 aux _ adc ( 83 . 3 khz typ ) osc 3 . 0 - 12 . 288 mhz xtal or 3 . 0 - 24 . 576 mhz clock to rf synthesiser ref clk selection
digital pmr processor cmx7131/cmx7141 ? 6.13.1 main clock operation a digital pll is used to create the main clock (nominally 24.576mhz) for the internal sections of the cmx7131/cmx7141 . at the same time, other internal clocks are generated by division of either the xtal reference clock or the main clock . these internal clocks are used for determining the sample rates and conversion times of a - to - d and d - to - a converters, running a general purpose (gp) timer and the signal processing block. in particular, it should be noted that in idle mode the setting of the gp timer divider directly affects the c - bus latency (with the default values this is nominally 250 s). the cmx7131/cmx7141 defaults to the settings appropriate for a 19.2mhz oscillator, however if other frequencies are to be used then the program block registers p3.2 to p3.7 will need to be programmed appropriately at power - o n. this flexibility allows the device to re - use an external clock source, so reducing total cost and potential noise sources. a table of common values is provided in table 6 . see: o program block 3 C auxdac, ramdac and clock control . 6.13.2 system clock operation two system clock outputs, sysclk1 and sysclk2, are available to drive additional circuits, as required. these are digital phase locked loop (pll) clocks that can be programmed via the system clock register s with suitable values chosen by the user. the system clock pll configure registers ($ab and $ad) control the values of the vco output divider and main divide registers, while the system clock ref. configure registers ($ac and $ae) control the values of th e reference divider and signal routing configurations. the plls are designed for a reference frequency of 96khz. if not required, these clocks can be independently powersaved. the clock generation scheme is shown in the block diagram of figure 29 . note that at power - on, these pins are disabled. see: o sysclk 1 and sysclk 2 pll data - $ab, $ad write o sysclk 1 and sysclk 2 ref - $ac and $ae write . 6.14 signal level optimisat ion the internal signal processing of the cmx7131/cmx7141 will operate with wide dynamic range and low distortion only if the signal level at all stages in the signal processing chain is kept within the recommended limits. for a device working from a 3.3v 10% supply, the maximum signal level which can be accommodated without distortion is [(3.3 x 90%) - (2 x 0.3v)] volts pk - pk = 838mv rms, assuming a sine wave signal. this should not be exceeded at any stage. in analogue pmr mod e, adjustable voice agc and limiter functions are provided with independent internal level setting registers to ensure that these requirements can be met. in particular, the effects of pre and de - emphasis must be taken into account when determining the app ropriate levels to use. see figure 15 tx lev el adjustments and figure 16 rx level adjustments . 6.14.1 transmit path levels for the maximum signal out of the mod1 and mod2 attenuators, the signal level at the o utput of the modem block is set to be 0db, the fine output adjustment ($c3) has a maximum attenuation of 1.8db and no gain, whereas the coarse output adjustment ($b0) has a variable attenuation of up to +40.0db and no gain. 6.14.2 receive path levels the coarse i nput adjustment ($b1) has a variable gain of up to +22.4db and no attenuation. with the lowest gain setting (0db), the maximum allowable input signal level at the discfb pin would be 838mvrms. this signal level is an absolute maximum, which should not be e xceeded.
digital pmr processor cmx7131/cmx7141 ? 6.15 tx spectrum plots the following figure shows the tx spectrum when using a suitable signal generator as measured on a spectrum analyser using the cmx7131/cmx7141 internal prbs generator. note that the i/q mode is sensiti ve to variations in dc offset in the modulation path and these must be minimised. two - point modulation spectrum i/q modulation spectrum figure 30 tx modulation spectra - 4800bps r e f l v l - 1 8 d b m r e f l v l - 1 8 d b m r b w 5 0 0 h z v b w 2 k h z s w t 7 0 0 m s r f a t t 1 0 d b a u n i t d b m 3 . 5 k h z / c e n t e r 4 4 6 . 1 m h z s p a n 3 5 k h z 1 v i e w 1 s a - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 1 1 8 - 1 8 1 m a r k e r 1 [ t 1 ] - 7 5 . 8 5 d b m 4 4 6 . 0 9 6 3 1 2 5 0 m h z 1 [ t 1 ] - 7 5 . 8 5 d b m 4 4 6 . 0 9 6 3 1 2 5 0 m h z c h p w r - 2 1 . 1 9 d b m a c p u p - 6 6 . 2 5 d b a c p l o w - 6 7 . 4 2 d b a l t 1 u p - 8 3 . 6 3 d b a l t 1 l o w - 8 4 . 5 8 d b c l 2 c l 2 c l 1 c l 1 c 0 c 0 c u 1 c u 1 c u 2 c u 2 d a t e : 1 3 : 4 5 : 4 4 r e f l v l - 1 8 d b m r e f l v l - 1 8 d b m r b w 5 0 0 h z s w t 7 0 0 m s r f a t t 1 0 d b a u n i t d b m 3 . 5 k h z / c e n t e r 4 4 6 . 1 m h z s p a n 3 5 k h z v b w 2 k h z 1 v i e w 1 r m - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 1 1 8 - 1 8 1 m a r k e r 1 [ t 1 ] - 7 6 . 3 0 d b m 4 4 6 . 0 9 6 3 1 2 5 0 m h z 1 [ t 1 ] - 7 6 . 3 0 d b m 4 4 6 . 0 9 6 3 1 2 5 0 m h z c h p w r - 2 2 . 0 2 d b m a c p u p - 6 3 . 3 5 d b a c p l o w - 6 7 . 6 5 d b a l t 1 u p - 7 4 . 9 3 d b a l t 1 l o w - 7 4 . 2 2 d b c l 2 c l 2 c l 1 c l 1 c 0 c 0 c u 1 c u 1 c u 2 c u 2 d a t e : 1 3 : 3 0 : 0 9
digital pmr processor cmx7131/cmx7141 ? 6.16 c - bus register summary table 11 c - bus registers addr. (hex) register word size (bits) $01 w c - bus reset 0 $a7 w auxadc configuration 16 $a8 w auxdac data and control 16 $a9 r auxadc1 data and status/checksum 2 hi 16 $aa r auxadc2 data and status/checksum 2 lo 16 $ab w sysclk 1 pll data 16 $ac w sysclk 1 ref 16 $ad w sysclk 2 pll data 16 $ae w sysclk 2 ref 16 $af reserved $b0 w analogue output gain 16 $b1 w input gain and signal routing 16 $b2 w r f synthesiser data (cmx7131 only) 16 $b3 w rf synthesiser control (cmx7131 only) 16 $b4 r rf synthesiser status (cmx7131 only) 8 $b5 w txdata 0 16 $b6 w txdata 1 16 $b7 w txdata 2 16 $b8 r rxdata 0/checksum 1 hi 16 $b9 r rxdata 1/checksum 1 lo 16 $ ba r rxdata 2 16 $bb r rxdata 3 16 $bc reserved $bd reserved $be reserved $bf reserved $c0 w power down control 16 $c1 w modem control 16 $c2 w auxdata/sub - audio write 16 $c3 w cmx6x8 analogue gain 16 $c4 reserved $c5 r rx data 4 16 $c6 r irq status 16 $c7 w modem configuration 16 $c8 w programming register 16 $c9 r modem status 16 $ca w tx data 3 16 $cb w tx data 4 16 $cc r auxdata/sub - audio read 16 $cd w auxadc threshold data 16 $ce w interrupt mask 16 $cf reserved all other c - bus addresses (including those not listed above) are either reserved for future use or allocated for production testing and must not be accessed in normal operation.
digital pmr processor cmx7131/cmx7141 ? 7 performance specification 7.1 electrical performance 7.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. unit supply: dv dd - dv ss ? dd - av ss ? dd - rfv ss (cmx7131 only) ? dd - rfv ss (cmx7131 only) ? ss ? dd + 0.3 v voltage on any pin to av ss ? dd + 0.3 v current into or out of any power supply pin (excluding bias) (i.e.vdec, avdd, avss, dvdd, dvss, cpvdd , rfvdd or rfvss) ? ? dd and av dd or cpv dd 0 0.3 v av dd and cpv dd (cmx7131 only) 0 0.3 v dv ss and av ss or rfv ss (cmx7131 only) 0 50 mv av ss and rfv ss (cmx7131 only) 0 50 mv l4 package (48 - pin lqfp) min. max. unit total allowable power dissipation at tamb = 25c C 1600 mw ... derating C 16 mw/c storage temperature ? 55 +125 c operating temperature ? 40 +85 c q3 package (48 - pin vqfn) min. max. unit total allowable power dissipation at tamb = 25c C 1750 mw ... derating C 17.5 mw/c storage temperature ? 55 +125 c operating temperature ? 40 +85 c l9 package (64 - pin lqfp) min. max. unit total allowable power dissipation at tamb = 25c C 1690 mw derating C 16.9 mw/c stora ge temperature ? 55 +125 c operating temperature ? 40 +85 c q1 package (64 - pin vqfn) min. max. unit total allowable power dissipation at tamb = 25c C 3500 mw derating C 35.0 mw/c storage temperature ? 55 +125 c operating temper ature ? 40 +85 c
digital pmr processor cmx7131/cmx7141 ? 7.1.2 operating limits correct operation of the device outside these limits is not implied. notes min. max. unit supply voltage: dv dd C ss 3.0 3.6 v av dd C ss 3.0 3.6 v cpv dd C ss (cmx7131 only) 3.0 3.6 v rfv d d C ss (cmx7131 only) 3 2.25 2.75 v v dec C ss 2 2.25 2.75 v operating temperature ? notes: 1 nominal xtal/clk frequency is 19.2mhz. 2 the v dec supply is automatically derived from dv dd by the on - chip voltage regulator. 3 the rfv dd supply can be supplied from the v dec supply, if preferred.
digital pmr processor cmx7131/cmx7141 ? 7.1.3 operating characteristics for the following conditions unless other wise specified: external components as recommended in figure 2 . maximum load on digital outputs = 30pf. oscillator frequency = 19.2mhz ? 0.01% (100ppm); tamb = ? 40c to +85c. av dd = dv dd = cpv dd (cmx7131) = 3.0v to 3.6v; rfv dd (cmx7131) = 2.25v to 2.75v. v dec = 2.5v. reference signal level = 308mvrms at 1khz with av dd = 3.3v. signal levels track with supply voltage, so scale accordingly. signal to noise ratio (snr) in bit rate bandwidth. input stage gain = 0db. out put stage attenuation = 0db. current consumption figures quoted in this section apply to the device when loaded with 7131/7141fi - 5.0 only. the use of other cmx7131/7141 function images, can modify the current consumption of the device. dc parameters note s min. typ. max. unit supply current 21 all powersaved di dd C 8 100 a ai dd C 4 20 a idle mode 22 di dd C 1.4 C ma ai dd 23 C 1.6 C ma rx mode 22 di dd (4800bps C search for fs) C 4.7 C ma di dd (9600bps C search fo r fs) C 7.5 C ma di dd (4800bps C fs found) C 2.8 C ma di dd (9600bps C fs found) C 3.7 C ma ai dd C 1.6 C ma tx mode 22 di dd (4800bps C two - point) C 4.3 C ma di dd (9600bps C two - point) C 5.2 C ma di dd (4800bps C i/q) C 5.4 C ma di dd (9600bps C i/q) C 7.3 C ma ai dd (av dd = 3.3v) C 1.5 C ma additional current for each auxiliary system clock (output running at 4mhz) di dd (dv dd = 3.3v, v dec = 2.5v) C 250 C a additional current for each auxiliary adc di dd (dv dd = 3.3 v, v dec = 2.5v) C 50 C a additional current for each auxiliary dac ai dd (av dd = 3.3v) C 200 C a additional current for each rf synthesiser 24 cpi dd + rfi dd (cpv dd = 3.3v, rfv dd = 2.5v) C 2.5 4.5 ma notes: 21 tamb = 25c: not in cluding any current drawn from the device pins by external circuitry. 22 system clocks: auxiliary circuits disabled, but all other digital circuits (including the main clock pll) enabled. 23 may be further reduced by power - saving unused sections 2 4 when using the external components shown in figure 27 and when supplying the current for rfv dd from the regulated 2.5v digital ( v dec ) supply. the latter is derived from dv dd by an on - chip voltage regulator.
digital pmr processor cmx7131/cmx7141 ? dc parameters (con tinued) notes min. typ. max. unit xtal/clk input 25 input logic 1 70% C C dd input logic 0 C C dd input current (vin = dv dd ) C C ss ) ? C C c - bus interface and logic inputs input lo gic 1 70% C C dd input logic 0 C C dd input leakage current (logic 1 or 0) ? C C C c - bus interface and logic outputs output logic 1 (i oh = 2ma) 90% C C dd output logic 0 (i ol = - 5ma) C C dd off state leakage current C C dd ) ? C ? C v bias 26 output voltage offset wrt av dd /2 (i ol < 1 ? C C dd output impedan ce C C ? notes: 25 characteristics when driving the xtal/clk pin with an external clock source. 26 applies when utilising v bias to provide a reference voltage to other parts of the system. when using v bias as a reference, v bias must be buf fered. v bias must always be decoupled with a capacitor as shown in figure 2 .
digital pmr processor cmx7131/cmx7141 ? a c parameters notes min. typ. max. unit xtal/clk input 'high' pulse width 31 15 C C C C C C ? C C C C ? C C C C system clk 1/2 outputs xtal/clk input to clock_out timing: (in high to out high) 32 C C C C v bias start - up time (from powersave) C C microph one, alternative and discriminator inputs (mic, alt, disc) input impedance 34 C C ? C C dd load resistance (feedback pins) 80 C C ? ? ? C C C C programmable input gain stage 36 gain (at 0db) 37 ? ? ? ? notes: 31 timing for an external input to the xtal /clk pin. 32 xtal/clk input driven by an external source. 33 6.144mhz xtal fitted and 6.144mhz output selected (scale for 19.2mhz). 34 with no external components connected, measured at dc. 35 centered about av dd /2; after multiplying by the gain of input circuit (with external components connected). 36 gain applied to signal at output of buffer amplifier: discfb, altfb or micfb. 37 design value. overall attenuation input to output has a tolerance of 0db 1.0db.
digital pmr processor cmx7131/cmx7141 ? a c parameters notes min. typ. max. unit modulator outputs 1/2 and audio output (mod 1, mod 2, audio) power - up to output stable 41 C modulator attenuators attenuation (at 0db) 43 ? ? ? ? ? C C ? ? C C ? dd = 3.3v) C C C dd C C C ? audio attenuator attenuation (at 0db) 43 ? ? ? ? ? C C ? ? C C ? dd = 3.3v) C C C dd C C C ? notes: 41 power - up refers to issuing a c - bus command to turn on an output. these limits apply only if v bias is on and stable. at power supply switch - on, the default state is for all blocks, except the xtal and c - bus inte rface, to be in placed in powersave mode. 42 small signal impedance, at av dd = 3.3v and tamb = 25c. 43 with respect to the signal at the feedback pin of the selected input port. 44 centered about av dd /2; with respect to the output driving a 20k ? dd /2.
digital pmr processor cmx7131/cmx7141 ? a c parameters (cont.) notes min. typ. max. unit auxiliary signal inputs (aux adc 1 to 4) source output impedance 51 C C ? auxiliary 10 bit adcs resolution C C C C dd conversion time 52 C C C C ? C C C C C C C auxiliary 10 bit dacs resol ution C C C C dd zero error 56 0 C C C ? C C C C notes: 51 denotes output impedance of the driver of the auxiliary input signal, to ensure <1 bit additional error under nominal conditions. 52 with an auxiliary clock frequency of 6.144mhz. 53 guaranteed monotonic with no missing codes. 54 centred about av dd /2. 55 input offset from a n ominal v bias input, which produces a $0200 adc output. 56 output offset from a $0200 dac input, measured wrt a nominal v bias output. 57 measured at dc.
digital pmr processor cmx7131/cmx7141 ? a c parameters (cont.) notes min. typ. max. unit rf synthesisers C phase locked loops reference clock input input logic 1 62 70% C C dd input logic 0 62 C C dd frequency 64, 66 5.0 19.2 40.0 mhz divide ratios (r) 63 2 C each rf synthesiser 69 comparison frequency C C C ? C C C C C ? C cp ) (high) 65 ? ? ? cp ) (low) 65 ? ? ? C C C C C C cp notes: 62 square wave input. 63 separate dividers are provided for each pll. 64 for op timum performance of the s ynthesiser subsystems, a common master clock should be used for the rf s ynthesiser s and the baseband sections. using unsynchronised clocks is likely to result in spurious products being generated in the synthesiser outputs and in some cases difficulty may be experienced in obtaining lock in the rf synthesisers. 65 external iset resistor (r31) = 0 (internal iset resistor = 9k6 nominally). 10 (n) + 10log 10 (f comparison ). 69 it is recommended that rf synthesiser 1 be used for the higher frequency use (eg: rf 1 st lo) and rf synthesiser 2 be used for lower frequency use (eg: if lo ).
digital pmr processor cmx7131/cmx7141 ? 7.1.4 parametric performance for the following conditions unless otherwise specified: external components as recommended in figure 2 . maximum load on digital outputs = 30pf. oscillator frequency = 19.2mhz ? 0.01% ( 100ppm); tamb = ? 40c to +85c. av dd = dv dd = 3.0v to 3.6v. reference signal level = 308mvrms at 1khz with av dd = 3.3v. signal levels track with supply voltage, so scale accordingly. signal - to - noise ratio (snr) in bit rate bandwidth. input stage gain = 0db , output stage attenuation = 0db. all figures quoted in this section apply to the device when loaded with fi - 5.x only. the use of other cmx7131/7141 function images, can modify the parametric performance of the device. dpmr modem notes min. typ. max. u nit modem symbol rate C 2400 C symbols /sec modulation 4fsk filter (rc) alpha C 0.2 C tx output level (mod1, mod2, two - point) 70 C 2.88 C vpk - pk tx output level (mod1, mod2, i/q) 70 C 2.20 C vpk - pk tx adjacent channel power (mod1, mod2, prbs) 71, 73 - 60 C C db rx sensitivity (ber 4800 symbols/sec ) 72 C tbd C dbm rx co - channel rejection 71, 73 15 12 C db rx input level C C 838 mvrms rx input dc offset 0.5 C av dd - 0.5 v notes: 70 transmitting continuous default preamble. 71 see user manual section 6.15 . 72 measured at baseband C audio performance notes min. typ. max. unit audio compandor at tack time C C C C C C C C inband tone encoder frequency range 288 C C C ? C analogue channel audio filtering pass - band (nominal bandwidth): 12.5khz channel 83 300 C C C C ? C C C ? C C ? C C C C ? C
digital pmr processor cmx7131/cmx7141 ? audio performance notes min. typ. max. unit audio scrambler inversion frequency C 3300 C hz pass - band 320 C 2900 hz audio expandor input signal range 85 C C 0.55 vrms notes: 80 measured at mod 1 or mod 2 output. 81 av dd = 3.3v and tx audio level set to 871mv p - p (308mvrms). 82 av dd = 3.3v. 83 see figure 17 and figure 18 . 84 psophometrically weighted. pre/de - emphasis, compandor and 25khz channel filter selected. 85 av dd = 3.3v.
digital pmr processor cmx7131/cmx7141 ? 7.2 c - bus timing figure 31 c - bus timing c - bus timing notes min. typ. max. unit t cse csn enable to sclk high time 100 C C csh last sclk high to csn high time 100 C C loz sclk low to rdata output enable time 0.0 C C hiz csn high to rdata high impedance C C csoff csn high time betw een transactions 1.0 C C nxt inter - byte time 200 C C ck sclk cycle time 200 C C ch sclk high time 100 C C cl sclk low time 100 C C cds cdata setup time 75 C C cdh cdata hold time 25 C C rds rdata setup time 50 C C rdh rdata hold time 0 C C notes: 1. depending on the command, 1 or 2 bytes of cdata are transmitted to the peripheral msb (bit 7) first, lsb (bit 0) last. rdata is read from the peripheral msb (bit 7) first, lsb (bit 0) last. 2. data is clocked into the peripheral on the rising sclk edge. 3. commands are acted upon at the end of each command (rising edge of csn). 4. to allow for differing c serial interface formats c - bus compatible ics are able to work with sclk pulses starting and ending at either polarity. 5. maximum 30pf load on irqn pin and each c - bus interface line. these timings are for the latest version of c - bus and allow faster transfers than the original c - bus timing specification. the cmx7131/cmx7141 can be used in conjunction with devices that comply with the slower timings, subject to system throughput constraints.
digital pmr processor cmx7131/cmx7141 ? 7.3 packaging figure 32 mechanical outline of 64 - pin vqfn (q1) order as part no. CMX7131Q1 figure 33 mechanical outline of 64 - pin lqfp (l9) order as part no. cmx7131l9
digital pmr processor cmx7131/cmx7141 ? figure 34 mechanical outline of 48 - pin lqfp (l4) order as part no. cmx7141l4 figure 35 mechanical outli ne of 48 - pin vqfn (q3) order as part no. cmx7141q3 as package dimensions may change after publication of this datasheet, it is recommended that you check for the latest packaging information from the design support/package information page of the cml web site: [www.cmlmicro.com].
digital pmr processor cmx7131/cmx7141 ? about firmasic ? cmls proprietary firmasic ? component technology reduces cost, time to market and development risk, with increased flexibility for the designer and end application. firmasic ? combines analogue, digital, firmware and memory technologies in a single silicon platform that can be focused to deliver the right feature mix, performance and price for a target application family. specific functions of a firmasic ? device are determined by upload ing its function image? during device initialization. new function images? may be later provided to supplement and enhance device functions, expanding or modifying end - product features without the need for expensive and time - consuming design changes. firm asic ? devices provide significant time to market and commercial benefits over custom asic, structured asic, fpga and dsp solutions. they may also be exclusively customised where security or intellectual property issues prevent the use of application specif ic standard products (assps). handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro - static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circuit patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test e quipment to ensure compliance with this product specification. specific testing of all circuit parameters is not necessarily performed.

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Price & Availability of CMX7131Q1

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CMX7131Q1 2032-1078-ND	CML Microcircuits Plc	DIGITAL PMR (DPMR) PROCESSOR WIT	30: USD17.39	0

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CMX7131Q1 226-CMX7131Q1	CML Microcircuits Plc	RF Wireless Misc Built on FirmASIC Reconfigurable Component Technology		0
CMX7131Q1-REEL 226-CMX7131Q1-R	CML Microcircuits Plc	RF Wireless Misc		0

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