3936 designed for pulse width modulated (pwm) current control of three phase brushless dc motors, the A3936sed is capable of peak output currents to 3a and operating voltages to 50 v. internal fixed off-time pwm current control timing circuitry can be configured to operate in slow, fast and mixed decay modes. internal synchronous rectification control circuitry is provided to improve power dissipation during pwm operation. internal circuit protection includes thermal shutdown with hysteresis, and crossover current protection. special power up sequencing is not required. the A3936 is supplied in a 44-lead plastic plcc with a copper batwing tab (suffix ed). the power tab is at ground potential and needs no electrical isolation. features ? 3a, 50 v continuous output rating ? low r ds(on) outputs, typically 500 mohm source, 315 mohm sink ? configurable mixed, fast and slow current decay modes ? synchronous rectification for low power dissipation ? internal uvlo and thermal shutdown circuitry ? crossover-current protection ? tachometer output for external speed control loop absolute maximum ratings at t a =+25 c load supply voltage, vbb ......................... 50 v output current, i out ................................. 3a* logic supply voltage, v dd ........................ 7.0 v logic input voltage range, v in .................... -0.3 v to v dd +0.3v (t w <30ns) ................ -1.0v to v dd +1v sense voltage, v sense ................................ 0.5 v reference voltage, v ref .............................. v dd package power dissipation (t a =+25 c), p d A3936sed ............................ 32 c/w operating temperature range, t a ............................... -20 cto+85 c junction temperature, t j ....................... +150 c storage temperature range, t s ............................. -55 c to +150 c * output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specified current rating or a junction temperature of 150 c. d mos three phase pwm motor driver
3936 three phase pwm motor driver functional block diagram v dd gnd ref ha- sense current sense +- zero current detect +- .1uf r s regulator charge pump vreg cp1 cp2 bandgap .22uf/100v .22uf/50v .22uf/50v gate drive ha+ hb- pwm timer osc tach outa outb outc overvoltage undervoltage and fault detect buffer/ divider vcp vreg hb+ hc- hc+ hall hall hall comm logic dir sleep control logic vcp vbb1 enable extmode brake sr blank hbias pfd1 pfd2 vdd vbb2 lss1 lss2
3936 three phase pwm motor driver electrical characteristics at t j = +25c, vbb = 50 v, v dd =5.0v, f pwm < 50khz ( unless noted otherwise) limits characteristics symbol test conditions min. typ. max. units output drivers load supply voltage range vbb operating 9 ? 50 v during sleep mode 0 50 v output leakage current i dss v out =v bb ?<1.020 a v out = 0 v ? 3936 three phase pwm motor driver electrical characteristics at t j = +25c, v bb =50v,v dd = 5.0 v, f pwm < 50khz ( unless noted otherwise) limits characteristics symbol test conditions min. typ. max. units control logic buffer input offset volt. v io 10 mv v ref input voltage range operating 0.0 ? v dd v reference input current i ref v ref =v dd ,v bb =0 to 50v -.5 0 0.5 m a comparator input offset volt. v io v ref =0v 5 mv v ref =v dd -4 4 % g m error v err (note 3) v ref =.5v -14 14 % propagation delay times tpd 50% to 90%, sr enabled pwm change to source on 600 750 1000 ns pwm change to source off 50 150 350 ns pwm change to sink on 600 750 1000 ns pwm change to sink off 50 100 150 ns crossover delay t cod sr enabled 300 600 1000 ns thermal shutdown temp. t j ? 165 ? c thermal shutdown hysteresis d t j ?15? c uvlo enable threshold rising v dd 2.45 2.7 2.95 v uvlo hysteresis 0.05 0.10 ? v notes: 1. typical data is for design information only. 2. negative current is defined as coming out of (sourcing) the specified device pin. 3. v err =((v ref /10) ? v sense )/(v ref /10)
3936 three phase pwm motor driver electrical characteristics at t a = +25c, v bb =50v,v dd =5.0vf pwm < 50khz ( unless noted otherwise) limits characteristics symbol test conditions min. typ. max. units hall logic hall input current i hall v in =1.2v -1 0 1 m a common mode input range vcmr .3 2.5 v ac input voltage range v hall .120 vp-p hysteresis v hys t a = -20 to 85 deg c. 10 30 mv pulse reject filter 35.58 m s hall bias output sat voltage v hb i out =40ma, t a = -20 to 85 deg c. .4 .5 v i hb 40 ma tach output v ol i out = 500ua .5 v notes: 1. typical data is for design information only. 2. negative current is defined as coming out of (sourcing) the specified device pin. commutation truth table 120 spacing outputs ha hb hc dir outa outb outc 1+ - + for hi lo z 2+ - - for hi z lo 3++- for z hi lo 4-+- for lo hi z 5-++for lo z hi 6- -+for z lo hi 1+ - + rev lo hi z 2 + - - rev lo z hi 3 + + - rev z lo hi 4-+- rev hi lo z 5-++rev hi z lo 6 - - + rev z hi lo --- x z z z +++ x z z z
3936 three phase pwm motor driver functional description vreg. the vreg pin should be decoupled with a 0.22 m f capacitor to ground. this supply voltage is used to run the sink side dmos outputs. vreg is intern ally monitored and in the case of a fault condition, the outputs of the device are disabled. charge pump. the charge pump is used to generate a supply a bove vbb to drive the source side dmos gates. a 0.22 uf ceramic monolithic capacitor should be connected between cp 1 and cp 2 for pumping purposes. a 0.22 uf ceramic monolithic capacitor should be connected between v cp and vbb to act as a reservoir to run the high side dmos devices. the v cp voltage is internally monitored and in the case of a fault condition the outputs of the device are disabled. shutdown. in the event of a fault due to excessive junction temperature, or low voltage on v cp or v reg ,the outputs of the device are disabled until the fault condition is removed. at power up, and in the event of low v dd ,the uvlo circuit disables the drivers. current regulation. load current is regulated by an internal fixed off time pwm control circuit. when the outputs of the dmos h-bridge are turned on, current increases in the motor winding until it reaches a value given by: i trip =v ref /(10*r sense ) at the trip point, the sense comparator resets the source enable latch, turning off the source driver. at this point, load inductance causes the current to recirculate for the fixed off time period. the current path during recirculation is determined by the configuration of slow/mixed decay mode and the synchronous rectification control setting. enable logic. the enable input terminal allows external pwm. enable high turns on the selected sink- source pair, enable low switches off the appropriate drivers and the load current decays. if the enable pin is held high, the current will rise until it reaches the level set by the internal current control circuit. enable outputs 0 source chopped 1on extmode logic. when using external pwm current control, the extmode input determines the current path during the chopped cycle. with extmode set low, fast decay mode, both the source and sink drivers are chopped off during the decay time (enable=0). with extmode high, slow decay mode, only the source driver turns off during the current decay time. extmode decay 0fast 1slow sleep mode. the input pin sleep is dedicated to put the device into a minimum current draw mode. when asserted low, all circuits are disabled. fixed off-time. the 3936 is set for a fixed off time of 96 counts of the internal oscillator, typically 24 m s with 4mhz oscillator. internal current control mode. input pins pfd1 and pfd2 determine the current decay method after an overcurrent event is detected at sense input. in slow decay mode both sink side drivers are turned on for the fixed off time period. mixed decay mode starts out in fast decay mode for the selected percentage of the fixed off time, and then is followed by slow decay for the rest of the period. pfd2 pfd1 % t off decay 00 0 slow 0 1 15 mixed 1 0 48 mixed 1 1 100 fast
3936 three phase pwm motor driver pwm blank timer. when a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. to prevent this current spike from erroneously resetting the source enable latch, the sense comparator is blanked. the blank timer runs after the off time counter to provide the blanking function. the blank timer is reset when enable is chopped or dir is changed. for external pwm control, a dir change or enable on will trigger the blanking function. the duration is adjusted by control input blank. blank t blank 06/f osc 1 12/f osc synchronous rectification. logic high applied to the sr terminal enables synchronous rectification. when a pwm off cycle is triggered, either by an enable chop command or internal fixed off time cycle, load current will recirculate according to the decay mode selected by control logic. the A3936 synchronous rectification feature will turn on the appropriate mosfet(s)during the current decay and effectively short out the body diodes with the low rdson driver. this will lower power dissipation significantly and can eliminate the need for external schottky diodes. reversal of load current is prevented by turning off synchronous rectification when a zero current level is detected. brake. logic high to the brake terminal activates the brake function, logic low allows normal operation. brake will turn all three sink drivers on and effectively shorts out the motor generated bemf. it is important to note that the internal pwm current control circuit will not limit the current when braking, since the current does not flow through the sense resistor. the maximum current can be approximated by v bemf /r l . care should be taken to insure that the maximum ratings of the device are not ex ceeded in worse case braking situations of high speed and high inertial loads. oscillator. the pwm timer is based on an internal oscillator set by a resistor connected from the osc terminal to v dd . typical value of 4mhz is set with 51k resistor. f osc = 204e9/r osc . tach. a tachometer signal is available for speed measurement. this open collector output toggles at each hall transition.
3936 terminal list pin no. pin name pin description 1gnd 2gnd 3 ha+ hall input 4 ha- hall input 5 hb+ hall input 6 hb- hall input 7 hc+ hall input 8 hc- hall input 9v dd logic supply voltage 10 ref g m reference input voltage 11 gnd 12 gnd 13 gnd 14 brake logic input 15 sense sense resistor connection 16 sr logic input (disabled = low, active sr = high) 17 outa dmos h ? bridge a 18 hbias connection for hall element neg side 19 vbb1 load supply voltage 20 lss1 low side source connection 21 outb dmos h ? bridge b 22 gnd 23 gnd 24 gnd 25 lss2 low side source connection 26 vbb2 load supply voltage 27 tach speed output 28 outc dmos h ? bridge c 29 v cp reservoir capacitor terminal 30 cp1 charge pump capacitor terminal 31 cp2 charge pump capacitor terminal 32 sleep logic input for sleep mode 33 gnd 34 gnd 35 gnd 36 osc oscillator terminal 37 v reg regulator decoupling terminal 38 dir logic input 39 enable logic input 40 extmode logic input 41 blank logic input 42 pfd2 logic input 43 pfd1 logic input 44 gnd power ground tab
3936
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