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cop87l88eb/cop87l89eb 8-bit one time programmable (otp) microcontroller with can interface, a/d and uart general description the cop87l88eb/cop87l89eb are members of the cop8 ? microcontroller feature family, which uses an 8-bit core architecture. they are pin and software compatible to the mask rom cop888eb product family. the devices are designed to perform complex embedded control applications such as those found in automotive control applications, while providing control/diagnostic communications via the can bus interface. the devices comply with the basic can bus specification 2.0b (passive). they are fully static de- vices fabricated using national's double metal silicon gate microcmos technology. efficient throughput is achieved through a regular efficient instruction set operating at a maxi- mum of 1 s instruction rate. key features n can bus interface, with software power save mode n 8-bit a/d converter with 8 channels n fully buffered uart n multi-input wake up (miwu) on both port l and m n spi compatible master/slave interface n 8096 bytes of on-board otp eprom with security feature n 192 bytes of on-board ram additional peripheral features n idle timer (programmable) n two 16-bit timer, with two 16-bit registers supporting e processor independent pwm mode e external event counter mode e input capture mode n watchdog ? and clock monitor n microwire/plus ? serial i/o i/o features n memory mapped i/o n software selectable i/o options (tri-state ? outputs, push pull outputs, weak pull up input, high impedance input) n schmitt trigger inputs on port g, l and m n packages: 44 plcc with 31 i/o pins; 68 plcc with 58 i/o pins cpu/instruction set features n 1 s instruction cycle time n fourteen multi-sourced vectored interrupts servicing e external interrupt e idle timer t0 e timers (t1 and t2) (4 interrupts) e microwire/plus and spi e multi-input wake up e software trap e can interface (3 interrupts) e uart (2 inputs) n versatile easy to use instruction set n 8-bit stacker pointer (sp) (stack in ram) n two 8-bit registerr indirect memory pointers (b, x) fully static cmos n low current drain (typically < 1 a) n two power saving modes: halt, idle n single supply operation: 4.5v to 5.5v n temperature range: ?40c to +85c development support n emulation device for cop888eb n real time emulation and full program debug offered by metalink development system basic functional description n can i/f e can serial bus interface block as described in the can specification part 2.0b (passive) e interface rates up to 250k bit/s are supported utilizing standard message identifiers n programmable double buffered uart n a/d e 8-bit, 8 channel, 1-lsb resolution, with improved source impedance and improved channel to channel cross talk immunity n multi-input-wake-up (miwu) e edge selectable wake-up and interrupt capability via input port and can interface (port l, port m and can i/f); supports wake-up capability on spi, uart, and t2 n port c e 8-bit bi-directional i/o port n port d e 8-bit output port with high current drive capability (10 ma) n port e e 8-bit bidirectional i/o n port f e 8-bit bidirectional i/o n port g e 8-bit bidirectional i/o port, including alternate functions for: e microwire ? input and output e timer 1 input or output (depending on mode selected) e external interrupt input e watchdog output n port i e 8-bit input port combining either digital input, or up to eight a/d input channels tri-state ? is a registered trademark of national semiconductor corporation. cop8 ? , microwire/plus ? , watchdog ? and microwire ? are trademarks of national semiconductor corporation. icemaster ? is a trademark of metalink corporation. obsolete january 2000 cop87l88eb/cop87l89eb 8-bit one time programmable (otp) microcontroller with can interface, a/d and uart ? 2000 national semiconductor corporation ds012871 www.national.com
basic functional description (continued) n port l e 8-bit bidirectional i/o port, including alternate functions for: e uart transmit/receive i/o e multi-input-wake up (miwu on all pins) n port m e 8-bit i/o port, with the following alternate function e spi interface e miwu e can interface wake-up (msb) e timer 2 input or output (depending on mode selected) n port n e 8-bit bidirectional i/o e spi slave select expander n two 16-bit multi-function timer counters (t1 and t2) plus supporting registers e (i/p capture, pwm and event counting) n idle timer e provides a basic time-base counter, (with interrupt) and automatic wake up from idle mode programmable n microwire/plus e microwire serial peripheral interface, supporting both master and slave operation n halt and idle e software programmable low current modes e halt e processor stopped, minimum current e idle e processor semi-active more than 60 % power saving n 8 kbytes rom and 192 bytes of on board static ram n spi master/slave interface includes 12 bytes transmit and 12 bytes receive fifo buffers. operates up to 1m bit/s n on board programmable watchdog and clock monitor applications n automobile body control and comfort system n integrated driver informaiton systems n steering wheel control n car radio control panel n sensor/actuator applications in automotive and industrial control block diagram ds012871-1 figure 1. block diagram cop87l88eb/cop87l89eb www.national.com 2
connection diagrams plastic chip carrier ds012871-2 top view order number cop87l88eb-xe see ns plastic chip package number v44a plastic leaded chip carrier ds012871-3 note: -x crystal oscillator -e halt enable top view order number COP87L89EB-XE see ns plastic chip package number v68a figure 2. connection diagrams cop87l88eb/cop87l89eb www.national.com 3
connection diagrams (continued) table 1. pinouts for 44-pin and 68-pin packages port type alt 44-pin 68-pin pin function plcc plcc g0 i/o int 44 1 g1 i/o wdout 1 2 g2 i/o t1b 2 3 g3 i/o t1a 3 4 g4 i/o so 4 5 g5 i/o sk 5 6 g6 i si 6 7 g7 i cko 7 8 d0 o 17 27 d1 o 18 28 d2 o 19 29 d3 o 20 30 d4 o 31 d5 o 32 d6 o 33 d7 o 34 i0 i adch0 36 53 i1 i adch1 37 54 i2 i adch2 38 55 i3 i adch3 39 56 i4 i adch4 57 i5 i adch5 58 i6 i adch6 59 i7 i adch7 60 l0 i/o miwu 40 61 l1 i/o miwu;ckx 41 62 l2 i/o miwu;tdx 42 63 l3 i/o miwu;rdx 43 64 l4 i/o miwu 65 l5 i/o miwu 66 l6 i/o miwu 67 l7 i/o miwu 68 e4 i/o e5 i/o e6 i/o e7 i/o m0 i/o miwu;miso 21 38 m1 i/o miwu;mosi 22 39 m2 i/o miwu;sck 23 40 m3 i/o miwu;ss 24 41 m4 i/o miwu;t2a 25 42 m5 i/o miwu;t2b 26 43 m6 i/o miwu 27 44 m7 i/o n0 i/o ess0 12 18 n1 i/o ess1 13 19 n2 i/o ess2 14 20 port type alt 44-pin 68-pin pin function plcc plcc n3 i/o ess3 15 21 n4 i/o ess4 22 n5 i/o ess5 23 n6 i/o ess6 24 n7 i/o ess7 25 f0 i/o 10 f1 i/o 11 f2 i/o 12 f3 i/o 13 f4 i/o 14 f5 i/o f6 i/o f7 i/o c0 i/o 35 c1 i/o 36 c2 i/o 37 c3 i/o c4 i/o c5 i/o c6 i/o rx0 i 31 48 rx1 i 30 47 tx0 o 29 46 tx1 o 28 45 canv ref 32 49 cki 8 9 reset 16 26 dv cc 10, 33 16, 50 gnd 9, 11, 34 15, 17, 51 a/d v ref 35 52 cop87l88eb/cop87l89eb www.national.com 4
absolute maximum ratings (note 1) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. supply voltage (v cc )6v voltage at any pin ?0.3v to v cc +0.3v total current into v cc pins (source) 90 ma total current out of gnd pins (sink) 100 ma storage temperature range ?65c to +150c note 1: absolute maximum ratings indicate limits beyond which damage to the device may occur. dc and ac electrical specifications are not ensured when operating the device at absolute maximum ratings. dc electrical characteristics ?40c t a +85c parameter conditions min typ max units operating voltage 4.5 5.5 v power supply ripple (note 2) peak-to-peak 0.1 v cc v supply current v cc = 5.5v, t c =1s 16 ma cki = 10 mhz (note 3) halt current (notes 4, 5) v cc = 5.5v, ck i=0mhz < 1a idle current (note 5) v cc = 5.5v, t c = 1 s 5.5 ma cki = 10 mhz input levels (v ih ,v il ) reset, cki logic high 0.8v cc v logic low 0.2v cc v all other inputs logic high 0.7v cc v logic low 0.2v cc v hi-z input leakage v cc = 5.5v 2a input pull-up current v cc = 5.5v, v in = 0v ?40 ?250 a port g, l and m input hysteresis (note 8) 0.05v cc v output current levels d outputs source v cc = 4.5v, v oh = 3.3v ?0.4 ma sink v cc = 4.5v, v ol = 1.0v 10 ma can transmitter outputs source (tx1) v cc = 4.5v, v oh =v cc ?0.1v ?1.5 ma v cc = 4.5v, v oh =v cc ? 0.6v ?10 +5.0 ma sink (tx0) v cc = 4.5v, v ol = 0.1v 1.5 ma v cc = 4.5v, v ol = 0.6v 10 ma all others source (weak pull-up) v cc = 4.5v, v oh = 2.7v ?10 ?110 a source (push-pull) v cc = 4.5v, v oh = 3.3v ?0.4 ma sink (push-pull) v cc = 4.5v, v ol = 0.4v 1.6 ma tri-state leakage v cc = 5.5v 2.0 a allowable sink/source current per pin d outputs (sink) 15 ma tx0 (sink) (note 8) 30 ma tx1 (source) (note 8) 30 ma all other 3ma maximum input current room temp 200 ma without latchup (notes 6, 8) ram retention voltage, v r (note 7) 500 ns rise and fall time 2.0 v input capacitance (note 8) 7 pf load capacitance on d2 1000 pf note 2: maxiumum rate of voltage change must be < 0.5v/ms cop87l88eb/cop87l89eb www.national.com 5
dc electrical characteristics (continued) note 3: supply current is measured after running 2000 cycles with a square wave cki input, cko open, inputs at v cc or gnd, and outputs open. note 4: the halt mode will stop cki from oscillating in the crystal configurations. halt test conditions: all inputs tied to v cc ; port c, g, e, f, l, m and n i/os con- figured as outputs and programmed low; d outputs programmed high. parameter refers to halt mode entered via setting bit 7 of the port g data register. pa rt will pull up cki during halt in crystal clock mode. both can main comparator and the can wakeup comparator need to be disabled. note 5: . halt and idle current specifications assume can block comparators are disabled. note 6: pins g6 and reset are designed with a high voltage input network. these pins allow input voltages greater than v cc and the pins will have sink current to v cc when biased at voltages greater than v cc (the pins do not have source current when biased at a voltage below v cc ). the effective resistance to v cc is 750 w (typical). these two pins will not latch up. the voltage at the pins must be limited to less than 14v. note 7: condition and parameter valid only for part in halt mode. note 8: parameter characterized but not tested. ac electrical characteristics ?40c t a +85c parameter conditions min typ max units instruction cycle time (t c ) crystal/resonator v cc 3 4.5v 1.0 dc s inputs t setup v cc 3 4.5v 200 ns t hold v cc 3 4.5v 60 ns output propagation delay (t pd1 ,t pd0 ) (note 9) c l = 100 pf, r l = 2.2 k w sk, so v cc 3 4.5v 0.7 s all others v cc 3 4.5v 1 s microwire setup time (tuws) (note 10) 20 ns hold time (tuwh) (note 10) 56 ns output pop delay (tupd) 220 ns input pulse width interrupt high time 1 t c interrupt low time 1t c timer 1, 2 high time 1 t c timer 1, 2 low time 1 t c reset pulse width (note 10) 1.0 s t c = instruction cycle time the maximum bus speed achievable with the can interface is a function of crystal frequency, message length and software overhead. the device can suppo rt a bus speed of up to 1 mbit/s with a 10 mhz oscillator and 2 byte messages. the 1m bus speed refers to the rate at which protocol and data bits are transferred on th e bus. longer messages require slower bus speeds due to the time required for software intervention between data bytes. the device will support a maximu m of 125k bits/s with eight byte messages and a 10 mhz oscillator. for device testing purpose of all ac parameters, v oh will be tested at 0.5*v cc . note 9: the output propagation delay is referenced to the end of the instruction cycle where the output change occurs. note 10: parameter not tested. on-chip voltage reference ?40c t a +85c parameter conditions min max units reference voltage i out < 80 a, 0.5v cc ?0.12 0.5v cc +0.12 v v ref v cc =5v reference supply i out = 0a, (no load) 120 a current, i dd v cc = 5v (note 11) note 11: reference supply i dd is supplied for information purposes only, it is not tested. cop87l88eb/cop87l89eb www.national.com 6
can comparator dc and ac characteristics 4.8v v cc 5.2v, ?40c t a +85c parameter conditions min typ max units differential input voltage 25 mv input offset voltage 1.5v < v in < v cc ?1.5v 10 mv input common mode 1.5 v cc ?1.5 v voltage range input hysteresis 8 mv ds012871-4 figure 3. microwire/plus timing diagram ds012871-5 figure 4. spi timing diagram cop87l88eb/cop87l89eb www.national.com 7
a/d converter specifications (4.5v v cc 5.5v) (v ss ? 0.050v) any input (v cc + 0.050v) parameter conditions min typ max units resolution 8 bits absolute accuracy v ref =v cc 2 lsb non-linearity 1 lsb deviation from the best straight line differential non-linearity 1 lsb common mode input range (note 14) gnd v cc v dc common mode error 0.5 lsb off channel leakage current 1 2.0 a on channel leakage current 1 2.0 a a/d clock frequency (note 13) 0.1 1.67 mhz conversion time (note 12) 17 a/d clock cycles internal reference resistance turn-on time (note 15) 1 s note 12: conversion time includes sample and hold time. note 13: see prescaler description. note 14: for v in (?) > =v in (+) the digital output code will be 0000 0000. two on-chip doides are ties to each analog input. the diodes will forward conduct for analog input voltages below ground or above the v cc supply. be careful, during testing at low v cc levels (4.5v), as high level analog inputs (5v) can cause this input diode to conduct e especially at elevated temperatures, and cause errors for analog inputs near full-scale. the spec allows 50 mv forward bias of either diod e. this means that as long as the analog v in does not exceed the supply voltage by more than 50 mv, the output code will be correct. to achieve an absolute 0 v dc to 5 v dc input voltage range will therefore require a minimum supply voltage of 4.950 v dc over temperature variations, initial tolerance and loading. note 15: time for internal reference resistance to turn on after coming out of halt or idle mode. pin description v cc and gnd are the power supply pins. cki is the clock input. the clock can come from a crystal os- cillator (in conjunction with cko). see oscillator description section. reset is the master reset input. see reset description sec- tion. the device contains seven bidirectional 8-bit i/o ports (c, e, f, g, l, m, n) where each individual bit may be indepen- dently configured as an input (schmitt trigger inputs on all ports), output or tri-state under program control. three data memory address locations are allocated for each of these i/o ports. each i/o port has two associated 8-bit memory mapped registers, the configuration register and the output data register. a memory mapped address is also reserved for the input pins of each i/o port. (see the memory map for the various addresses associated with the i/o ports.) figure 5 shows the i/o port configurations for the device. the data and configuration registers allow for each port bit to be individually configured under software control as shown below: configuration data port set-up register register 0 0 hi-z input (tri-state output) 0 1 input with weak pull-up 1 0 push-pull zero output 1 1 push-pull one output port l and m are 8-bit i/o ports, they support multi-input wake-up (miwu) on all eight pins. all l-pins and m-pins have schmitt triggers on the inputs. port l and m only have one (1) interrupt vector. port l has the following alternate features: l0 miwu l1 miwu or ckx l2 miwu or tdx l3 miwu or rdx l4 miwu l5 miwu l6 miwu l7 miwu port g is an 8-bit port with 5 i/o pins (g0g5), an input pin (g6), and one dedicated output pin (g7). pins g0g6 all have schmitt triggers on their inputs. g7 serves as the dedi- cated output pin for the cko clock output. there are two reg- isters associated with the g port, a data register and a con- figuration register. therefore, each of the 6 i/o bits (g0g5) can be individually configured under software control. ds012871-6 figure 5. i/o port configurations cop87l88eb/cop87l89eb www.national.com 8
pin description (continued) since g6 is an input only pin and g7 is the dedicated cko clock output pin the associated bits in the data and configu- ration registers for g6 and g7 are used for special purpose functions as outlined below. reading the g6 and g7 data bits will return zeroes. note that the chip will be placed in the halt mode by wirting a ''1o to bit 7 of the port g data register. similarly the chip will be placed in the idle mode by writing a a1o to bit 6 of the port g data register. writing a a1o to bit 6 of the port g configuration register en- ables the microwire/plus to operate with the alternate phase of the sk clock config. reg. data reg. g7 clkdly halt g6 alternate sk idle port g has the following alternate features: g0 intr (external interrupt input) g1 dedicated watchdog output g2 (timer t1 capture input) g3 t1a (timer i/o) g4 so (microwire serial data output) g5 sk (microwire serial clock) g6 si (microwire serial data input) port g has the following dedicated function: g7 cko oscillator dedicated output port m is a bidirectional i/o, it may be configured in software as hi-z input, weak pull-up, or push-pull output. these pins may be used as general purpose input/output pins or for se- lected altlernate functions. port m pins have optional alternate functions. each pin (m0m5) has been assigned an alternate data, configura- tion, or wakeup source. if the respective alternate function is selected the content of the associated bits in the configura- tion and/or data register are ignored. if an alternate wakeup source is selected the input level at the respective pin will be ignored for the purpose of triggering a wakeup event, how- ever it will still be possible to read that pin by accessing the input register. the spi (serial peripheral interface) block, for example, uses four of the port m pins to automatically re- configure its miso (master input, slave output), mosi (master output, slave input), sck (serial clock) and slave- select pins as inputs or outputs, depending on whether the interface has been configured as a master or slave. when the spi interface is disabled those pins are available as gen- eral purpose i/o pins configurable by user software writing to the associated data and configuration bits. the can inter- face on the device makes use of one of the port m's alter- nate wake-ups, to trigger a wakeup if such a condition has been detected on the can's dedicated receive pins. port m has the following alternate pin functions: m0 multi-input wakeup or miso m1 multi-input wakeup or mosi m2 multi-input wakeup or sck m3 multi-input wakeup or ss m4 multi-input wakeup or t2a m5 multi-input wakeup or t2b m6 multi-input wakeup m7 multi-input wakeup or can ports c, e, f and n are general-purpose, bidirectional i/o ports. any device package that has port c, e, f, m, n but has fewer than eight pins, contains unbonded, floating pads internally on the chip. for these types of devices, the software should writ ea1tothe configuration register bits corresponding to the non-existent port pins. this configures the port bits as outputs, thereby reducing leakage current of the device. port n is an 8-bit wide port with alternate function capability used for extending the slave select (ss ) lines of the on spi interface. the spi expander block provides mutually exclu- sive slave select extension signals (ess0 to ess7 ) accord- ing to the state of the ss line and specific contents of the spi shift register. these slave select extension lines can be routed to the port n i/o pins by enabling the alternate func- tion of the port in the portnx register. if enabled, the inter- nal signal on the essx line causes the ports state to change exactly like a change to the portnd register. it is the user's responsibility to switch the port to an output when enabling the alternate function. cop87l88eb/cop87l89eb www.national.com 9
pin description (continued) port n has the following alternate pin functions: n0 ess0 n1 ess1 n2 ess2 n3 ess3 n4 ess4 n5 ess5 n6 ess6 n7 ess7 can pins: for the on-chip can interface this device has five dedicated pins with the following features: v ref on-chip reference voltage with the value of v cc /2 rx0 can receive data input pin. rx1 can receive data input pin. tx0 can transmit data output pin. this pin may be put in the tri-state mode with the txen0 bit in the can bus control register. tx1 can transmit data output pin. this pin may be put in the tri-state mode with the txen1 bit in the can bus control register. alternate port functions many general-purpose pins have alternate functions. the software can program each pin to be used either for a general-purpose or for a specific function. the chip hardware determines which of the pins have alternate functions, and what those functions are. this section lists the alternate functions available on each of the pins. port d is an 8-bit output port that is preset high when reset goes low. the user can tie two or more port d outputs (ex- cept d2) together in order to get a higher drive. note: care must be exercised with d2 pin operation. at reset, the external loads on this pin must ensure that the output voltages stay above 0.8 v cc to prevent the chip from entering special modes. also keep the ex- ternal loading on d2 to < 1000 pf. port 1 is an 8-bit hi-z input port, and also provides the ana- log inputs to the a/d converter. if unterminated, port 1 pins will draw power only when addressed. cop87l88eb/cop87l89eb www.national.com 10
functional description the architecture of the device utilizes a modified harvard ar- chitecture. with the harvard architecture, the control store program memory (rom) is separated from the data store memory (ram). both rom and ram have their own sepa- rate addressing space with separate address buses. the ar- chitecture, though based on harvard architecture, permits transfer of data from rom to ram. cpu registers the cpu can do an 8-bit addition, subtraction, logical or shift operation in one instruction (t c ) cycle time. there are five cpu registers: a is the 8-bit accumulator register pc is the 15-bit program counter register pu is the upper 7 bits of the program counter (pc) pl is the lower 8 bits of the program counter (pc) b is an 8-bit ram address pointer, which can be optionally post auto incremented or decremented. x is an 8-bit alternate ram address pointer, which can be optionally post auto incremented or decremented. sp is the 8-bit stack pointer, which points to the subroutine/ interrupt stack (in ram). the sp is initialized to ram ad- dress 02f with reset. all the cpu registers are memory mapped with the excep- tion of the accumulator (a) and the program counter (pc). program memory program memory for the device consists of 8 kbytes of otp eprom. these bytes may hold program instructions or con- stant data (data tables for the laid instruction, jump vectors for the jid instruction and interrupt vectors for the vis in- struction). the program memory is addressed by the 15-bit program counter (pc). all interrupts in the device vector to program memory location 0ff hex. the device can be configured to inhibit external reads of the program memory. this is done by programming the security byte. security feature the program memory array has an associate security byte that is located outside of the program address range. this byte can be addressed only from programming mode by a programmer tool. security is an optional feature and can only be asserted after the memory array has been programmed and verified. a se- cured part will read all 00(hex) by a programmer. the part will fail blank check and will fail verify operations. a read operation will fill the programmer's memory with 00(hex). the security byte itself is always readable with value of 00(hex) if unsecure and ff(hex) if secure. data memory the data memory address space includes the on-chip ram and data registers, the i/o registers (configuration, data and pin), the control registers, the microwire/plus sio shift register, and the various registers, and counters associated with the timers (with the exception of the idle timer). data memory is addressed directly by the instruction or indirectly by the b, x and sp pointers. the device has 192 bytes of ram. sixteen bytes of ram are mapped as aregisterso at addresses 0f0 to 0ff hex. these registers can be loaded immediately, and also decremented and tested with the drsz (decrement register and skip if zero) instruction. the memory pointer registers x, sp, and b are memory mapped into this space at address locations 0fc to 0fe hex respectively, with the other registers (other than reserved register 0ff) being available for general us- age. the instruction set permits any bit in memory to be set, reset or tested. all i/o and registers (except a and pc) are memory mapped; therefore i/o bits and register bits can be directly and individually set, reset and tested. the accumula- tor (a) bits can also be directly and individually tested. note: ram contents are undefined upon power-up. reset the reset input when pulled low initializes the microcon- troller. initialization will occur whenever the reset input is pulled low. upon initialization, the data and configuration registers for ports l and g, are cleared, resulting in these ports being initialized to the tri-state mode. port d is ini- tialized high with reset. the pc, cntrl, and inctrl control registers are cleared. the multi-input wakeup regis- ters wken, wkedg, and wkpnd are cleared. the stack pointer, sp, is initialized to 06f hex. the following initializations occur with reset: spi: spicntrl: cleared spistat: cleared stbe bit: set t1cntrl & t2cntrl: cleared itmr: cleared and idle timer period is reset to 4k instr. clk enad: cleared addslt: random sior: unaffected after reset with power already ap- plied. random after reset at power on. port l: tri-state port g: tri-state port d: high pc: cleared psw, cntrl and icntrl registers: cleared accumulator and timer 1: random after reset with power already applied random after reset at power-on sp (stack pointer): loaded with 6f hex b and x pointers: unaffected after reset with power already applied random after reset at power-up ram: unaffected after reset with power already applied random after reset at power-up can: the can interface comes out of external reset in the aerror-activeo state and waits until the user's software sets either one or both of the txen0, txen1 bits to a1o. after that, the device will not start transmission or reception of a frame util eleven consecutive areces- siveo (undriven) bits have been received. this is done to ensure that the output drivers are not enamble dur- ing an active message on the bus. cscal, ctim, tcntl, tec, rec: cleared cop87l88eb/cop87l89eb www.national.com 11
functional description (continued) rtstat: cleared with the exception of the tbe bit which is set to 1 rid, ridl, tid, tdlc: random watchdog: the device comes out of reset with both the watchdog logic and the clock monitor detector armed, with the watchdog ser- vice window bits set and the clock monitor bit set. the watchdog and clock monitor circuits are inhibited during reset. the watchdog service window bits being ini- tialized high default to the maximum watchdog service window of 64k t c clock cycles. the clock monitor bit being initial- ized high will cause a clock monitor bit be- ing initialized high will cause a clock moni- tor error following reset if the clock has not reached the minimum specified frequency at the termination of reset. a clock monitor error will cause an active low error output on pin g1. this error output will continue until 16 t c 32 t c clock cycles following the clock frequency reaching the minimum specified value, at which time the g1 output will enter the tri-state mode. the reset signal goes directly to the halt latch to restart a halted chip. when using external reset, the external rc network shown in figure 6 should be used to ensure that the reset pin is held low until the power supply to the chip stabilizes. under no circumstances should the reset pin be allowed to float. oscillator circuits the chip can be driven by a clock input on the cki input pin which can be between dc and 10 mhz. the cko output clock is on pin g7. the cki input frequency is divided by 10 to produce the instruction cycle clock (1/t c ). figure 7 shows the crystal diagram. crystal oscillator cki and cko can be connected to make a closed loop crys- tal (or resonator) controlled oscillator. table 2 shows the component values required for various standard crystal values. table 2. crystal oscillator configuration, t a = 25c r1 r2 c1 c2 cki freq. conditions (k w )(m w ) (pf) (pf) (mhz) 0 1 30 3036 10 v cc =5v 0 1 30 3036 4 v cc =5v 0 1 200 100150 0.455 v cc =5v ds012871-7 rc > 5 x power supply rise time figure 6. recommended reset circuit ds012871-8 figure 7. crystal oscillator diagram cop87l88eb/cop87l89eb www.national.com 12
control registers cntrl register (address x'00ee) the timer1 (t1 and microwire/plus control register contains the following bits: sl1 & sl0 select the microwire/plus clock divide by (00=2,01=4,1x=8) iedg external interrupt edge polarity select (0 = rising edge , 1 = falling edge) msel selects g5 and g4 as microwire/plus signals sk and so respectively t1c0 timer t1 start/stop control in timer timer t1 underflow interrupt pending flag in timer mode 3 t1c1 timer t1 mode control bit t1c2 timer t1 mode control bit t1c3 timer t1 mode control bit t1c3 t1c2 t1c1 t1c0 msel iedg sl1 sl0 bit 7 bit 0 psw register (address x'00ef) the psw register contains the following select bits: gie global interrupt enable (enables interrupts) exen enable external interrupt busy microwire/plus busy shifting flag expnd external interrupt pending t1ena timer t1 interrupt enable for timer underflow or t1a input capture edge t1pnda timer t1 interrupt pending flag (autoreload ra in mode 1, t1 underflow in mode 2, t1a capture edge in mode 3) c carry flag hc half carry flag hc c t1pnda t1ena expnd busy exen gie bit 7 bit 0 the half-carry bit is also affected by all the instructions that affect the carry flag. the sc (set carry) and rc (reset carry) in- structions will respectively set or clear both the carry flags. in addition to the sc and rc instructions, adc, subc, rrc and rlc instructions affect the carry and half carry flags. icntrl register (address x'00e8) the icntrl register contains the following bits: t1enb timer t1 interrupt enable for t1b input capture edge t1pndb timer t1 interrupt pending flag for t1b capture edge wen enable microwire/plus interrupt wpnd microwire/plus interrupt pending t0en timer t0 interrupt enable (bit 12 toggle) t0pnd timer t0 interrupt pending lpen port l interrupt enable (multi-input wakeup/interrupt) bit 7 could be used as a flag unused lpen t0pnd t0en wpnd wen t1pndb t1enb bit 7 bit 0 cop87l88eb/cop87l89eb www.national.com 13
control registers (continued) t2cntrl register (address x'00c6) the t2cntrl register contains the following bits: t2enb timer t2 interrupt enable for t2b input capture edge t2pndb timer t2 interrupt pending flag for t2b capture edge t2ena timer t2 interrupt enable for timer underflow or t2 input capture edge t2pnda timer t2 interrupt pending flag (autoreload ra in mode 1, t2 underflow in mode 2, t2a capture edge in mode 3) t2c0 timer t2 start/stop control in timer modes 1 and 2 timer t2 underflow interrupt pending flag in timer mode 3 t2c1 timer t2 mode control bit t2c2 timer t2 mode control bit t2c3 timer t2 mode control bit t2c3 t2c2 t2c1 t2c0 t2pnda t2ena t2pndb t2enb bit 7 bit 0 timers the device contains a very versatile set of timers (t0, t1 and t2). all timers and associated autoreload/capture registers power up containing random data. timer t0 (idle timer) the device supports applications that require maintaining real time and low power with the idle mode. this idle mode support is furnished by the idle timer t0, which is a 16-bit timer. the timer t0 runs continuously at the fixed rate of the instruction cycle clock, t c . the user cannot read or write to the idle timer t0, which is a count down timer. the timer t0 supports the following functions: exit out of the idle mode (see idle mode description) watchdog logic (see watchdog description) start up delay out of the halt mode figure 8 is a functional block diagram showing the structure of the idle timer and its associated interrupt logic. bits 11 through 15 of the itmr register can be selected for triggering the idle timer interrupt. each time the selected bit under- flows (every 4k, 8k, 16k, 32k or 64k instruction cycles), the idle timer interrupt pending bit t0pnd is set, thus generating an in- terrupt (if enabled), and bit 6 of the port g data register is reset, thus causing an exit from the idle mode if the device is in that mode. in order for an interrupt to be generated, the idle timer interrupt enable bit t0en must be set, and the gie (global interrupt en- able) bit must also be set. the t0pnd flag and t0en bit are bits 5 and 4 of the icntrl register, respectively. the interrupt can be used for any purpose. typically, it is used to perform a task upon exit from the idle mode. for more information on the idle mode, refer to the power save modes section. ds012871-9 figure 8. functional block diagram for idle timer t0 cop87l88eb/cop87l89eb www.national.com 14
timers (continued) the idle timer period is selected by bits 02 of the itmr register bits 37 of the itmr register are reserved and should not be used as software flags. table 3. idle timer window length itsel2 itsel1 itsel0 idle timer period (instruction cycles) 0 0 0 4,096 0 0 1 8,192 0 1 0 16,384 0 1 1 32,768 1 x x 65,536 the itmr register is cleared on reset and the idle timer period is reset to 4,096 instruction cycles. itmr register (address x'0xcf) reserved itsel2 itsel1 itsel0 bit 7 bit 0 any time the idle timer period is changed there is the possibility of generating a spurious idle timer interrupt by setting the t0pnd bit. the user is advised to disable idle timer interrupts prior to changing the value of the itsel bits of the itmr register and then clear the t0pnd bit before attempting to synchronize operation to the idle timer. timer t1 and timer t2 the device has a set of three powerful timer/counter blocks, t1 and t2. the associated features and functioning of a timer block are described by referring to the timer block tx. since the three timer blocks, t1 and t2 are identical, all comments are equally applicable to either of the three timer blocks. each timer block consists of a 16-bit timer, tx, and two supporting 16-bit autoreload/capture registers, rxa and rxb. each timer block has two pins associated with it, txa and txb. the pin txa supports i/o required by the timer block, while the pin txb is an input to the timer block. the powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead. the timer block has three operating modes: processor independent pwm mode, external event counter mode, and input capture mode. the control bits txc3, txc2, and txc1 allow selection of the different modes of operation. mode 1. processor independent pwm mode as the name suggests, this mode allows the device to generate a pwm signal with very minimal user intervention. the user only has to define the parameters of the pwm signal (on time and off time). once begun, the timer block will con- tinuously generate the pwm signal completely independent of the microcontroller. the user software services the timer block only when the pwm parameters require updating. in this mode the timer tx counts down at a fixed rate of t c . upon every underflow the timer is alternately reloaded with the contents of supporting registers, rxa and rxb. the very first underflow of the timer causes the timer to reload from the register rxa. sub- sequent underflows cause the timer to be reloaded from the registers alternately beginning with the register rxb. the tx timer control bits, txc3, txc2 and txc1 set up the timer for pwm mode operation. figure 9 shows a block diagram of the timer in pwm mode. ds012871-10 figure 9. timer in pwm mode cop87l88eb/cop87l89eb www.national.com 15
timers (continued) the underflows can be programmed to toggle the txa output pin. the underflows can also be programmed to generate interrupts. underflows from the timer are alternately latched into two pending flags, txpnda and txpndb. the user must reset these pend- ing flags under software control. two control enable flags, txena and txenb, allow the interrupts from the timer underflow to be enabled or disabled. setting the timer enable flag txena will cause an interrupt when a timer underflow causes the rxa register to be reloaded into the timer. setting the timer enable flag txenb will cause an interrupt when a timer underflow causes the rxb register to be reloaded into the timer. resetting the timer enable flags will disable the associated interrupts. either or both of the timer underflow interrupts may be enabled. this gives the user the flexibility of interrupting once per pwm period on either the rising or falling edge of the pwm output. alternatively, the user may choose to interrupt on both edges of the pwm output. mode 2. external event counter mode this mode is quite similar to the processor independent pwm mode described above. the main difference is that the timer, tx, is clocked by the input signal from the txa pin. the tx timer control bits, txc3, txc2 and txc1 allow the timer to be clocked either on a positive or negative edge from the txa pin. underflows from the timer are latched into the txpnda pending flag. setting the txena control flag will cause an interrupt when the timer underflows. in this mode the input pin txb can be used as an independent positive edge sensitive interrupt input if the txenb control flag is set. the occurrence of the positive edge on the txb input pin is latched to the txpndb flag. figure 10 shows a block diagram of the timer in external event counter mode. note: the pwm output is not available in this mode since the txa pin is being used as the counter input clock. mode 3. input capture mode the device can precisely measure external frequencies or time external events by placing the timer block, tx, in the input capture mode. in this mode, the timer tx is constantly running at the fixed t c rate. the two registers, rxa and rxb, act as capture registers. each register acts in conjunction with a pin. the register rxa acts in conjunction with the txa pin and the register rxb acts in conjunc- tion with the txb pin. the timer value gets copied over into the register when a trigger event occurs on its corresponding pin. control bits, txc3, txc2 and txc1, allow the trigger events to be specified either as a positive or a negative edge. the trigger condition for each input pin can be specified independently. the trigger conditions can also be programmed to generate interrupts. the occurrence of the specified trigger condition on the txa and txb pins will be respectively latched into the pending flags, txpnda and txpndb. the control flag txena allows the interrupt on txa to be either enabled or disabled. setting the txena flag enables interrupts to be generated when the selected trigger condition occurs on the txa pin. similarly, the flag txenb controls the interrupts from the txb pin. underflows from the timer can also be programmed to generate interrupts. underflows are latched into the timer txc0 pending flag (the txc0 control bit serves as the timer underflow interrupt pending flag in the input capture mode). consequently, the txc0 control bit should be reset when entering the input capture mode. the timer underflow interrupt is enabled with the txena control flag. when a txa interrupt occurs in the input capture mode, the user must check both whether a txa input capture or a timer underflow (or both) caused the interrupt. figure 11 shows a block diagram of the timer in input capture mode. ds012871-11 figure 10. timer in external event counter mode cop87l88eb/cop87l89eb www.national.com 16
timers (continued) timer control flags the timers t1 and t2 have identical control structures. the control bits and their functions are summarized below. txc0 timer start/stop control in modes 1 and 2 (processor independent pwm and extenral event counter), where 1 = state , 0 = stop timer underflow interrupt pending flag in mode 3 (input capture) txpnda timer interrupt pending flag txpndb timer interrupt pending flag txena timer interrupt enable flag txenb timer interrupt enable flag 1 = timer interrupt enabled 0 = timer interrupt disabled txc3 timer mode control txc2 timer mode control txc1 timer mode control the timer mode control bits (txc3, txc2 and txc1) are detailed below: txc3 txc2 txc1 timer mode interrupt a interrupt b timer source source counts on 0 0 0 mode 2 (external event counter) time underflow pos. txb edge txa pos. edge 0 0 1 mode 2 (external event counter) timer underflow pos. txb edge txa neg. edge 1 0 1 mode 1 (pwm) txa toggle autoreload ra autoreload rb t c 1 0 0 mode 1 (pwm) no txa toggle autoreload ra autoreload rb t c 0 1 0 mode 3 (capture) captures: pos. txa edge or pos. txb edge t c txa pos. edge timer underflow txb pos. edge 1 1 0 mode 3 (capture) captures: pos. txa edge or neg. txb edge t c txa pos. edge timer underflow txb neg. edge 0 1 1 mode 3 (capture) captures: neg. txa edge or pos. txb edge t c txa neg. edge timer underflow txb pos. edge 1 1 1 mode 3 (capture) captures: neg. txa edge or neg. txb edge t c txa neg. edge timer underflow txb neg. edge ds012871-12 figure 11. timer in input capture mode cop87l88eb/cop87l89eb www.national.com 17
power save modes the device offer the user two power save modes of opera- tion: halt and idle. in the halt mode, all microcontroller activities are stopped. in the idle mode, the on-board oscil- lator circuitry and timer t0 are active but all other microcon- troller activities are stopped. in either mode, all on-board ram, registers, i/o states, and timers (with the exception of t0) are unaltered. halt mode the device is placed in the halt mode by writing a ''1o to the halt flag (g7 data bit). all microcontroller activities, includ- ing the clock, and timers, are stopped. in the halt mode, the power requirements of the device are minimal and the applied voltage (v cc ) may be decreased to vr (vr = 2.0v) without altering the state of the machine. can halt/idle mode: in order to reduce the device overall current consumption in halt/idle mode a two step power save mechanism is implemented on the device: step 1: disable main receive comparator. this is done by resetting both the txen0 and txen1 bits in the cbus register. note: these bits should always be reset before entering halt/idle mode to allow proper resynchronization to the can bus after ex- iting halt/idle mode. step 2: disable the can wake-up comparators, this is done by resetting bit 7 in the port-m wakeup en- able register (mwken) a transition on the can bus will then not wake the device up. note: if both the main receive comparator and the wake-up comparator are disabled the on chip can voltage reference is also disabled. the can- v ref output is then high-z the device supports two different ways of exiting the halt mode. the first method of exiting the halt mode is with the multi-input wakeup feature on the l & m port. the second method of exiting the halt mode is by pulling the reset pin low. since a crystal or ceramic resonator may be selected as the oscillator, the wakeup signal is not allowed to start the chip running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach full ampli- tude and frequency stability. the idle timer is used to gen- erate a fixed delay to ensure that the oscillator has indeed stabilized before allowing instruction execution. in this case, upon detecting a valid wakeup signal, only the oscillator cir- cuitry is enabled. the idle timer is loaded with a value of 256 and is clocked with the t c instruction cycle clock. the t c clock is derived by dividing the oscillator clock down by a fac- tor of 10. the schmitt trigger following the cki inverter on the chip ensures that the idle timer is clocked only when the oscillator has a sufficiently large amplitude to meet the schmitt trigger specifications. this schmitt trigger is not part of the oscillator closed loop. the start-up time-out from the idle timer enables the clock signals to be routed to the rest of the chip. the device has two mask options associated with the halt mode. the first mask option enables the halt mode feature, while the second mask option disables the halt mode. with the halt mode enable mask option, the device will enter and exit the halt mode as described above. with the halt disable mask option, the device cannot be placed in the halt mode (writing a a1o to the halt flag will have to effect). the following table shows the two can power save modes and the active can transceiver blocks. idle mode the device is placed in the idle mode by writing a a1o to the idle flag (g6 data bit). in this mode, all activity, except the associated on-board oscillator circuitry, ad the idle timer t0, is stopped. the power supply requirements of the micro- controller in this mode of operation are typically around 30 of normal power requirement of the microcontroller. as with the halt mode, the device can be returned to nor- mal operation with a reset, or with a multi-input wakeup from the port l or can interface. alternately, the microcontroller resumes normal operation from the idle mode when the thirteenth bit (representing 4.096 ms at internal clock fre- quency of 1 mhz, t c = 1 s) of the idle timer toggles. this toggle condition of the thirteenth bit of the idle timer t0 is latched into the t0pnd pending flag. the user has the option of being interrupted with a transition on the thirteenth bit of the idle timer t0. the interrupt can be enabled or disabled via the t0en control bit. setting the t0en flag enables the interrupt and vice versa. the user can enter the idle mode with the timer t0 inter- rupt enabled. in this case, when the t0pnd bit gets set, the device will first execute the timer t0 interrupt service routine and then return to the instruciton following the aenter idle modeo instruction. alternatively, the user can enter the idle mode with the idle timer t0 interrupt disabled. in this case, the device will resume normal operation with the instruction immediately following the aenter idle modeo instruction. note: it is necessary to program two nop instructions following both the set halt mode and set idle mode instructions. these nop instructions are necessary to allow clock resynchronization following the halt or idle modes. step 1 step 2 main-comp wake-up-comp can-v ref v ref pin 0 0 on on on v cc /2 0 1 on off on v cc /2 1 0 off on on v cc /2 1 1 off off off high-z multi-input wakeup the multi-input wakeup feature is used to return (wakeup) the device from either the halt or idle modes. alternately, the multi-input wakeup/interrupt feature may also be used to generate up to 7 edge selectable external interrupts. note: the following description is for both the port l and the m port. when the document refers to the registers wkegd, wken or wkpnd, the user will have to put either m (for m port) or l (for port) in front of the register, i.e., lwken (port l wken), mwken (port m wken). figure 12 and figure 13 show the multi-input wakeup logic for the microcontroller. the multi-input wakeup feature uti- lizes the l port. the user selects which particular port l bit (or combination of port l bits) will cause the device to exit cop87l88eb/cop87l89eb www.national.com 18
multi-input wakeup (continued) the halt or idle modes. the selection is done through the reg: wken. the reg: wken is an 8-bit read/write register, which contains a control bit for every port l bit. setting a par- ticular wken bit enables a wakeup from the associated port l pin. the user can select whether the trigger condition on the se- lected port l pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition). this selection is made via the reg: wkedg, which is an 8-bit control register with a bit assigned to each port l pin. setting the control bit will select the trigger condition to be a negative edge on that particular port l pin. resetting the bit selects the trigger condition to be a positive edge. changing an edge select entails several steps in order to avoid a pseudo wakeup condition as a result of the edge change. first, the associated wken bit should be reset, followed by the edge select change in wkedg. next, the associated wkpnd bit should be cleared, followed by the associated wken bit being re-enabled. an example may serve to clarify this procedure. suppose we wish to change the edge select from positive (low going high) to negative (high going low) for port l bit 5, where bit 5 has previously been enabled for an input interrupt. the program would be as follows: rbit 5,wken ;disable port bit 5 for wake-up sbit 5,wkedg ;select neg-rising edge rbit 5,wkpnd ;clear pending bit sbit 5,wken ;re-enable the bit ds012871-13 figure 12. port m multi-input wake-up logic cop87l88eb/cop87l89eb www.national.com 19
multi-input wakeup (continued) if the port l bits have been used as outputs and then changed to inputs with multi-input wakeup/interrupt, a safety procedure should also be followed to avoid inherited pseudo wakeup conditions. after the selected port l bits have been changed from output to input but before the associated wken bits are enabled, the associated edge select bits in wkedg should be set or reset for the desired edge selects, followed by the assoicated wkpnd bits being cleared. this same procedure should be used following reset, since the port l inputs are left floating as a result of reset. the oc- currence of the selected trigger condition for multi-input wakeup is latched to a pending register called wkpnd. the respective bits of the wkpnd register will be set on the oc- currence of the selected trigger edge on the corresponding port l and port m pin. the user has the responsibility of clearing these pending flags. since wkpnd is a pending register for the occurrence of selected wakeup conditions, the device will not enter the halt mode if any wakeup bit is both enabled and pending. consequently, the user has the responsibility of clearing the pending flags before attempting to enter the halt mode. the wken, wkpnd and wkedg are all read/write regis- ters, and are cleared at reset. port l interrupts port l provides the user with additional eight fully selectable, edge sensitive interrupts which are all vectored into the same service subroutine. the interrupt from port l shares logic with the wake up cir- cuitry. the register wken allows interrupts from port l to be individually enabled or disabled. the register wkedg speci- fies the trigger condition to be either a positive or a negative edge. finally, the register wkpnd latches in the pending trigger conditions. the gie (global interrupt enable) bit enables the interrupt function. a control flag, lpen, functions as a global interrupt enable for port l interrupts. setting the lpen flag will enable interrupts and vice versa. a separate global pending flag is not needed since the register wkpnd is adequate. since port l is also used for waking the device out of the halt or idle modes, the user can elect to exit the halt or idle modes either with or without the interrupt enabled. if he elects to disable the interrupt, then the device will restart ex- ecution from the instruction immediately following the in- struction that placed the microcontroller in the halt or idle modes. in the other case, the device will first execute the in- terrupt service routine and then revert to normal operation. the wakeup signal will not start the chip running immedi- ately since crystal oscillators or ceramic resonators have a fi- nite start up time. the idle timer (t0) generates a fixed de- lay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions. in this case, upon detecting a valid wakeup signal, only the oscillator cir- cuitry and the idle timer t0 are enabled. the idle timer is loaded with a value of 256 and is clocked from the t c instruc- tion cycle clock. the t c clock is derived by dividing down the oscillator clock by a factor of 10. a schmitt trigger following the cki on-chip inverter ensures that the idle timer is clocked only when the oscillator has a sufficiently large am- plitude to meet the schmitt trigger specifications. this schmitt trigger is not part of the oscillator closed loop. the start-up time-out from the idle timer enables the clock sig- nals to be routed to the rest of the chip. port m interrupts port m provides the user with seven fully selectable, edge sensitive interrupts which are all vectored into the same ser- vice subroutine. the interrupt from port m shares logic with the wake up cir- cuitry. the mwken register allows interrupts from port m to be individually enabled or disabled. the mwkedg register specifies the trigger condition to be either a positive or a negative edge. the mwkpnd register latches in the pend- ing trigger conditions. ds012871-14 figure 13. port l multi-input wake-up logic cop87l88eb/cop87l89eb www.national.com 20
multi-input wakeup (continued) the lpen control flag in the icntrl register functions as a global interrupt enable for port m interrupts. setting the lpen flag enables interrupts. note that the gie bit in the psw register must also be set to enable these port l inter- rupts. a global pending flag is not needed since each pin has a corresponding pending flag in the mwkpnd register. since port m is also used for exiting the device from the halt or idle mode, the user can elect to exit the halt or idle mode either with or without the interrupt enabled. if the user elects to disable the interrupt, then the device restarts execution from the point at which it was stopped (first in- struction cycle of the instruction following the enter halt or idle mode instruction). in the other case, the device finishes the instruction which was being executed when the part was stopped (the nop (note 16) instruction following the enter halt or idle mode instruction), and then branches to the interrupt service routine. the device then reverts to normal operation. note 16: the user must place two nops after an enter halt or idle mode instruction. to prevent erroneous clearing of the spi receive fifo when entering halt/idle mode, the user needs to enable the miwu on port m3. (ss ) by setting bit 3 in the mwken reg- ister. can receive wakeup the can receive wakeup source can be enabled or dis- abled. there is no specific enable bit for the can wakeup feature. although the wakeup feature on pins l0..17 and m0..m7 can be programmed to generate an interrupt (port l or port m interrupt), no interrupt is generated upon a can re- ceive wakeup condition. the can block has it's own, dedi- cated receiver interrupt upon receive buffer full (see can section). can wake-up: the can interface can be programmed to wake the device from halt/idle mode. this is done by setting bit 7 in the port m wake-up enable register (mwken). a transition on the bus will cause the bit 7 of the port m wake-up pending (mwkpnd) to be set and thereby waking up the device. the frame on the can bus will be lost. the mwedg (m port wake-up edge) register bit 7 can be programmed high or low (high will wake-up on the first falling edge on rx0). resetting bit 7 in the mwken will disable the can wake-up. the following sequence should be executed before entering halt/idle mode: rbit 7, mwkpnd ;clear can wake-up pending ld a, cbus and a, #0cf ;resettxen0 and txen1 x a, cbus ;disable main receive ;comparator after the device woke-up the cbus bits txen0 and/or txen1 need be set to allow synchronization on the bus and to enable transmission/reception of can frames. interrupts the device supports a vectored interrupt scheme. it supports a total of fourteen interrupt sources. the following table lists all the possible device interrupt sources, their arbitration ranking and the memory locations reserved for the interrupt vector for each source. two bytes of program memory space are reserved for each interrupt source. all interrupt sources except the software in- terrupt are maskable. each of the maskable interrupts have an enable bit and a pending bit. a maskable interrupt is ac- tive if its associated enable and pending bits are set. if gie = 1 and an interrupt is active, then the processor will be inter- rupted as soon as it is ready to start executing an instruction except if the above conditions happen during the software trap service routine. this exception is described in the soft- ware trap sub-section. the interruption process is accomplished with the intr in- struction (opcode 00), which is jammed inside the instruction register and replaces the opcode about to be executed. the following steps are performed for every interrupt: 1. the gie (global interrupt enable) bit is reset. 2. the address of the instruction about to be executed is pushed into the stack. 3. the pc (program counter) branches to address 00ff. this procedure takes 7 t c cycles to execute. at this time, since gie = 0, other maskable interrupts are dis- abled. the user is now free to do whatever context switching is required by saving the context of the machine in the stack with push instructions. the user would then program a vis (vector interrupt select) instruction in order to branch to the interrupt service routine of the highest priority interrupt en- abled and pending at the time of the vis. note that this is not necessarily the interrupt that caused the branch to address location 00ff hex prior to the context switching. thus, if an interrupt with a higher rank than the one which caused the interruption becomes active before the decision of which interrupt to service is made by the vis, then the in- terrupt with the higher rank will override any lower ones and will be acknowledged. the lower priority interrupt(s) are still pending, however, and will cause another interrupt immedi- ately following the completion of the interrupt service routine associated with the higher priority interrupt just serviced. this lower priority interrupt will occur immediately following the reti (return from interrupt) instruction at the end of the interrupt service routine just completed. inside the interrupt service routine, the associated pending bit has to be cleared by software. the reti (return from in- terrupt) instruction at the end of the interrupt service routine will set the gie (global interrupt enable) bit, allowing the processor to be interrupted again if another interrupt is active and pending. the vis instruction looks at all the active interrupts at the time it is executed and performs an indirect jump to the be- ginning of the service routine of the one with the highest rank. the addresses of the different interrupt service routines, called vectors, are chosen by the user and stored in rom in a table starting at 01e0 (assuming that vis is located be- tween 00ff and 01df). the vectors are 15-bit wide and therefore occupy 2 rom locations. vis and the vector table must be located in the same 256- byte block (0y00 to 0yff) except if vis is located at the last address of a block. in this case, the table must be in the next block. the vector table cannot be inserted in the first 256- byte block. the vector of the maskable interrupt with the lowest rank is located at 0ye0 (hi-order byte) and 0ye1 (lo-order byte) and so forth in increasing rank number. the vector of the maskable interrupt with the highest rank is located at 0yfa (hi-order byte) and 0yfb (lo-order byte). cop87l88eb/cop87l89eb www.national.com 21
interrupts (continued) the software trap has the highest rank and its vector is lo- cated at 0yfe and 0yff. if, by accident, a vis gets executed and no interrupt is ac- tive, then the pc (program counter) will branch to a vector located at 0ye00ye1. warning: a default vis interrupt handle routine must be present. as a minimum, this handler should confirm that the gie bit is cleared (this indicates that the interrupt sequence has been taken), take care of any required housekeeping, restore con- text and return. some sort of warm restart procedure should be implemented. these events can occur without any error on the part of the system designer or programmer. note: there is always the possibility of an interrupt occurring during an in- struction which is attempting to reset the gie bit or any other interrupt enable bit. if tis occurs when a single cycle instruction is being used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. this is because interrupt processing is started at the same time as the interrupt bit is being reset. to avoid this scenario, the user should always use a two, three, or four cycle instruc- tion to reset interrupt enable bits. figure 14 shows the interrupt block diagram. table 4. interrupt vector table arbitration rank interrupt source description vector address (note 17) 1 software trap intr instruction 0yfe0yff 2 reserved nmi 0yfc0yfd 3 can receive rbf, rfv set 0yfa0yfb 4 can error terr, rerr set 0yf80yf9 (transmit/receive) 5 can transmit tbe set 0yf60yf7 6 pin g0 edge external 0yf40yf5 7 microwire/plus busy goes low 0yf20yf3 spi interface srbf or stbe set 8 timer t0 idle timer underflow 0yf00yf1 9 uart receive buffer full 0yee0yef 10 uart transmit buffer empty 0yec0yed 11 timer t2 t2a/underflow 0yea0yeb 12 timer t2 t2b 0ye80ye9 13 timer t1 t1a/underflow 0ye60ye7 14 timer t1 t1b 0ye40ye5 15 port l, port m; port l edge or 0ye20ye3 miwu port m edge 16 default vis interrupt vis interrupt 0ye00ye1 note 17: y=1to7f, depending on the location of the vis instruction. cop87l88eb/cop87l89eb www.national.com 22
interrupts (continued) software trap the software trap (st) is a special kind of non-maskable in- terrupt which occurs when the intr instruction (used to ac- knowledge interrupts) is fetched from rom and placed in- side the instruction register. this may happen when the pc is pointing beyond the available rom address space or when the stack is over-popped. when an st occurs, the user can re-initialize the stack pointer and do a recovery procedure (similar to reset, but not necessarily containing all of the same initialization proce- dures) before restarting. the occurrence of an st is latched into the st pending bit. the gie bit is not affected and the st pending bit ( not ac- cessible by the user ) is used to inhibit other interrupts and to direct the program to the st service routine with the vis instruciton. the rpnd instruction is used to clear the soft- ware interrupt pending bit. this bit is also cleared on reset. the st as the highest rank among all interrupts. nothing (except another st) can interrupt an st being serviced. can block description * this device contains a can serial bus interface as described in the can specification rev. 2.0 part b. *patents pending. can interface block this device supports applications which require a low speed can interface. it is designed to be programmed with two transmit and two receive registers. the user's program may check the status bytes in order to get information of the bus state and the received or transmitted messages. the device has the capability to generate an interrupt as soon as one byte has been transmitted or received. care must be taken if more than two bytes in a message frame are to be transmitted/received. in this case the user's program must poll the transmit buffer empty (tbe)/receive buffer full (rbf) bits or enable their respective interrupts and perform a data exchange between the user data and the tx/rx registers. fully automatic transmission on error is supported for mes- sages not longer than two bytes. messages which are longer than two bytes have to be processed by software. the interface is compatible with can specification 2.0 part b, without the capability to receive/transmit extended frames. extended frames on the bus are checked and ac- knowledged according to the can specification. the maximum bus speed achievable with the can interface is a function of crystal frequency, message length and soft- ware overhead. the device can support a bus speed of up to 1 mbit/s with a 10 mhz oscillator and 2 byte messages. the 1 mbit/s bus speed refers to the rate at which protocol and data bits are transferred on the bus. longer messages re- quire slower bus speeds due to the time required for soft- ware intervention between data bytes. the device will sup- port a maximum of 125k bit/s with eight byte messages and a 10 mhz oscillator. ds012871-15 figure 14. interrupt block diagram cop87l88eb/cop87l89eb www.national.com 23
can interface block (continued) functional block description of the can interface interface management logic (iml) the iml executes the cpu's transmission and reception commands and controls the data transfer between cpu, rx/tx and can registers. it provides the can interface with rx/tx data from the memory mapped register block. it also sets and resets the can status information and generates interrupts to the cpu. bit stream processor (bsp) the bsp is a sequencer controlling the data stream between the interface management logic (parallel data) and the bus line (serial data). it controls the transceive logic with regard to reception and arbitration, and creates error signals ac- cording to the bus specification transceive logic (tcl) the tcl is a state machine which incorporates the bit stuff logic and controls the output drivers, crc logic and the rx/tx shift registers. it also controls the synchronization to the bus with the can clock signal generated by the btl. error management logic (eml) the eml is responsible for the fault confinement of the can protocol. it is also responsible for changing the error counters, setting the appropriate error flag bits and interrupts and changing the error status (passive, active and bus off). cyclic redundancy check (crc) generator and register the crc generator consists of a 15-bit shift register and the logic required to generate the checksum of the destuffed bit- stream. it informs the eml about the result of a receiver checksum. ds012871-16 figure 15. can interface block diagram cop87l88eb/cop87l89eb www.national.com 24
functional block description of the can interface (continued) the checksum is generated by the polynomial: c 15 + c 14 + c 10 + c 8 + c 7 + c 4 + c 3 +1 receive/transmit (rx/tx) registers the rx/tx registers are 8-bit shift registers controlled by the tcl and the bsp. they are loaded or read by the interface management logic, which holds the data to be transmitted or the data that was received. bit time logic (btl) the bit time logic divider divides the cki input clock by the value defined in the can prescaler (cscal) and bus timing register (ctim). the resultig bit time (tcan) can be computed by the formula: where divider is the value of the clock prescaler, ps is the programmable value of phase segment 1 and 2 (1..8) and pps the programmed value of the propagation segment (1..8) (located in ctim). bus timing considerations the internal architecture of the can interface has been op- timized to allow fast software response times within mes- sages of more than two data bytes. the tbe (transmit buffer empty) bit is set on the last bit of odd data bytes when can internal sample points are high. it is the user's responsibility to ensure that the time between setting tbe and a reload of txd2 is longer than the length of phase segment 2 as indicated in the following equation: table 5 shows examples of the minimum required t load for different cscal settings based on a clock frequency of 10 mhz. lower clock speeds require recalculation of the can bit rate and the mimimum t load . table 5. can timing (cki = 10 mhz t c = 1 s) ps cscal can bit rate (kbit/s) minimum t load (s) 4 3 250 2.0 4 9 100 5.0 4 15 62 8.0 4 24 40 12.5 439 25 20 499 10 50 4 199 5 100 figure 17 illustrates the minimum time required for t load . in the case of an interrupt driven can interface, the calculation of the actual t load time would be done as follows: int: ;interrupt latency = 7t c=7s push a; 3t c=3s ld: a,b ;2tc=2s push a ;3t c=3s vis ;5tc=5s cantx: ;20tc = s to this point ;additional time for instructions which check ;status prior to reloading the transmit data ;registers with subsequent data bytes. ld txd2,data ds012871-17 figure 16. bit rate generation ds012871-18 figure 17. tbe timing cop87l88eb/cop87l89eb www.national.com 25
functional block description of the can interface (continued) interrupt driven programs use more time than programs which poll the tbe flag, however programs which operate at lower baud rates (which are more likely to be sensitive to this issue) have more time for interrupt response. output drivers/input comparators the output drivers/input comparators are the physical interface to the bus. control bits are provided to tri-state the output driv- ers. a dominant bit on the bus is represented as a a0o in the data registers and a recessive bit on the bus is represented as a a1o in the data registers. table 6. bus level definition bus level pin tx0 pin tx1 data adominanto drive low dirve high 0 (gnd) (v cc ) arecessiveo tri-state tri-state 1 register block the register block consists of fifteen 8-bit registers which are described in more detail in the following paragraphs. note: the contents of the receiver related registers rxd1, rxd2, rdlc, ridh and rtstat are only changed if a received frame passes the acceptance filter or the receive identifier acceptance filter bit (riaf) is set to accept all received messages. transmit data register 1 (txd1) (address x'00a0) the transmit data register 1 contians the first data byte to be transmitted within a frame and then the successive odd byte num- bers (i.e., bytes number 1,3,..,7). transmit data register 2 (txd2) (address x'00a1) the transit data register 2 contains the second data byte to be transmitted within a frame and then the successive even byte numbers (i.e., bytes number 2,4,..,8). transmit data length code and identifier low register (tdlc) (address x'00a2) tid3 tid2 tid1 tid0 tdlc3 tdlc2 tclc1 tdlc0 bit 7 bit 0 this register is read/write. tid3..tido transmit identifier bits 3..0 (lower 4 bits) the transmit identifier is composed of eleven bits in total, bits 3 to 0 of the tid are stored in bits 7 to 4 of this register. tdlc3..tdlc0 transmit data length code these bits determine the number of data bytes to be transmitted within a frame. the can specification allows a maximum of eight data bytes in any message. transmit identifier high (tid) (address x'00a3) trtr tid10 tid9 tid8 tid7 tid6 tid5 tid4 bit 7 bit 0 this register is read/write. trtr transmit remote frame request this bit is set if the frame to be transmitted is a remote frame request. tid10..tid4 transmit identifier bits 10 .. 4 (higher 7 bits) bits tid10..tid4 are the upper 7 bits of the 11 bit transmit identifier. receiver data register 1 (rxd1) (address x'00a4) the receive data register 1 (rxd1) contains the first data byte received in a frame and then successive odd byte numbers (i.e., bytes 1, 3,..7). this register is read-only. receive data register 2 (rxd2) (address x'00a5) the receive data register 2 (rxd2) contains the second data byte received in a frame and then successive even byte numbers (i.e., bytes 2,4,..,8). this register is read-only. cop87l88eb/cop87l89eb www.national.com 26
functional block description of the can interface (continued) register data length code and identifier low register (ridl) (address x'00a6) rid3 rid2 rid1 rid0 rdlc3 rdlc2 rdlc1 rdlc0 bit 7 bit 0 this register is read only. rid3..rid0 receive identifier bits (lower four bits) the rid3..rid0 bits are the lower four bits of the eleven bit long receive identifier. any received message that matches the upper 7 bits of the receive identifier (rid10..rid4) is accepted if the receive identifier acceptance filter (riaf) bit is set to zero. rdlc3..rdlc0 receive data length code bits the rdlc3..rdlc0 bits determine the number of data bytes within a received frame. receive identifier high (rid) (address x'00a7) unused rid10 rid9 rid8 rid7 rid6 rid5 rid4 bit 7 bit 0 this register is read/write. rid10..rid4 receive identifier bits (upper bits) the rid10...rid4 bits are the upper 7 bits of the eleven bit long receive identifier. if the receive identifier acceptance filter (riaf) bit (see cbus register) is set to zero, bits 4 to 10 of the received identifier are compared with the mask bits of rid4..rid10. if the corresponding bits match, the message is accepted. if the riaf bit is set to a one, the filter function is disabled and all messages, independent of identifier, will be accepted. can prescaler register (cscal) (address x'00a8) cks7 cks6 cks5 cks4 cks3 cks2 cks1 cks0 bit 7 bit 0 this register is read/write. cks7..0 prescaler divider select. the resulting clock value is the can prescaler clock. can bus timing register (ctim) (00a9) pps2 pps1 pps0 ps2 ps1 ps0 reserved reserved bit 7 bit 0 this register is read/write. pps2..pps0 propagation segment, bits 2..0 the pps2..pps0 bits determine the length of the propagation delay in prescaler clock cycles (psc) per bit time. (for a more de- tailed discussion of propagation delay and phase segments, see synchronization.) ps2..ps0 phase segment 1, bits 2..0 the ps2..ps0 bits fix the number of prescaler clock cycles per bit time for phase segment 1 and phase segment 2. the ps2..ps0 bits also set the synchronization jump width to a value equal to the lesser of the 4 psc or the length of ps1/2 (min : 4 l length of ps1/2). table 7. synchronization jump width length of synchronization ps2 ps1 ps0 phase jump width segment 1 2 000 1t can 1t can 001 2t can 2t can 010 3t can 3t can 011 4t can 4t can 100 5t can 4t can 101 6t can 4t can 110 7t can 4t can 111 8t can 4t can cop87l88eb/cop87l89eb www.national.com 27
functional block description of the can interface (continued) length of time segments (see figure 29 ) the synchronization segment is 1 can prescaler clock (psc) the propagation segment can be programmed (pps) to be 1,2...,8 psc in length. phase segment 1 and phase segment 2 are program- mable (ps) to be 1,2,..,8 psc long. note: (btl settings at high speed; psc = 0) due to the on-chip delay from the rx-pins through the receive comparator (worst case assumption: 3 clocks dela y * 2 (devices on the bus )+1tx delay) the user needs to set the sample point to > (2*3 + 1) i.e., > 7 cki clocks to ensure correct communication on the bus under all circumstances. with prescaler set- tings of > 0 this is a given (i.e., no caution has to be applied). example: for 1 mbit ctim = b'10000100 (pss = 5; ps1 = 2). example for 500 kbit ctim = b'01011100 (pps = 3; ps1 = 8). ? all at 10 mhz cki and cscal = 0. can bus control register (cbus) (00aa) re- riaf txen1 txen0 rxref1 rxref0 re- fmod served served bit 7 bit 0 reserved this bit is reserved and should be zero. riaf receive identifier acceptance filter bit if the riaf bit is set to zero, bits 4 to 10 of the received identifier are compared with the mask bits of rid4..rid10 and if the cor- responding bits match, the message is accepted. if the riaf bit is set to a one, the filter function is disabled and all messages independent of the identifier will be accepted. txen0, txen1 txd output driver enable table 8. output drivers txen1 txen0 output 0 0 tx0, tx1 tri-state, can input comparator disabled 0 1 tx0 enabled 1 0 tx1 enabled 1 1 tx0 and tx1 enabled bus synchronization of the device is done in the following way: if the output was disabled (txen1, txen0 = a0o) and either txen1 or txen0, or both are set to 1, the device will not start trans- mission or reception of a frame until eleven consecutive arecessiveo bits have been received. resetting the txen1 and txen0 bits will disable the output drivers and the can input comparator. all other can related registers and flags will be unaffected. it is recommended that the user reset the txen1 and txen0 bits before switching the device into the halt mode (the can receive wakeup will still work) in order to reduce current consumption and to assure a proper resychronization to the bus after exiting the halt mode. note: a abus offo condition will also cause tx0 and tx1 to be at tri-state (independent of the values of the txen1 and txen0 bits). rxref1 reference voltage applied to rx1 if bit is set rxref0 reference voltage applied to rx0 if bit is set fmod fault confinement mode select setting the fmod bit to a0o (default after power on reset) will select the standard fault confinement mode. in this mode the de- vice goes from abus offo to aerror activeo after monitoring 128*11 recessive bits (including bus idle) on the bus. this mode has been implemented for compatibility with existing solutions. setting the fmod bit to a1o will select the enhanced fault confinement mode. in this mode the device goes from abus offo to aerror activeo after monitoring 128 agoodo messages, as indicated by the re- ception of 11 consecutive arecessiveo bits including the end of frame, whereas the standard mode may time out after 128 x 11 recessive bits (e.g., bus idle). ds012871-19 figure 18. acceptance filter block-diagram cop87l88eb/cop87l89eb www.national.com 28
functional block description of the can interface (continued) transmit control/status (tcntl) (00ab) ns1 ns0 terr rerr ceie tie rie txss bit 7 bit 0 ns1..ns0 node status, i.e., error status. table 9. node status ns1 ns0 output 0 0 error active 0 1 error passive 1 0 bus off 1 1 bus off the node status bits are read only. terr transmit error this bit is automatically set when an error occurs during the transmission of a frame. terr can be programmed to generate an interrupt by setting the can error interrupt enable bit (ceie). this bit must be cleared by the user's software. note: this is used for messages for more than two bytes. if an error occurs during the transmission of a frame with more than 2 data bytes, the user's software ha s to handle the correct reloading of the data bytes to the txd registers for retransmission of the frame. for frames with 2 or less data bytes the interface logic of this chip does an automatic retransmission. regardless of the number of data bytes, the user's software must reset this bit if ceie is enabled. other wise a new interrupt will be generated immediately after return from the interrupt service routine. rerr receiver error this bit is automatically set when an error occurred during the reception of a frame. rerr can be programmed to generate an interrupt by setting the can error interrupt enable bit (ceie). this bit has to be cleared by the user's software. ceie can error interrupt enable if set by the user's software, this bit enables the tansmit and receive error interrupts. the interrupt pending flags are terr and rerr. resetting this bit with a pending error interrupt will inhibit the interrupt, but will not clear the cause of the interrupt (rerr or terr). if the bit is then set without clearing the cause of the interrupt, the interrupt will reoccur. tie transmit interrupt enable if set by the user's software, this bit enables the transmit interrupt. (see tbe and txpnd.) resetting this bit with a pending trans- mit interrupt will inhibit the interrupt, but will not clear the cause of the interrupt. if the bit is then set without clearing the cause of the interrupt, the interrupt will reoccur. rie receive interrupt enable if set by the user's software, this bit enables the receive interrupt or a remote transmission request interrupt (see rbf, rfv and rrtr). resetting this bit with a pending receive interrupt will inhibit the interrupt, but will not clear the cause of the interrupt. if the bit is then set without clearing the cause of the interrupt, the interrupt will reoccur. txss transmission start/stop this bit is set by the user's software to initiate the transmission of a frame. once this bit is set, a transmission is pending, as in- dicated by the txpnd flag being set. it can be reset by software to cancel a pending transmission. resetting the txss bit will only cancel a transmission, if the transmission of a frame hasn't been started yet (bus idle), if arbitration has been lost (receiving) or if an error occurs during transmission. if the device has already started transmission (won arbitration) the txpnd and txss flags will stay set until the transmission is completed, even if the user's software has written zero to the txss bit. if one or more data bytes are to be transmitted, care must be taken by the user, that the transmit data register(s) have been loaded before the txss bit is set. txss will be cleared on three conditions only: successful completion of a transmitted message; successful can- cellation of a pending transmision; transition of the can interface to the bus-off state. writing a zero to the txss bit will request cancellation of a pending transmission but txss will not be cleared until completion of the operation. if an error occurs during transmission of a frame, the logic will check for cancellation requests prior to restarting transmission. if zero has been written to txss, retransmission will be canceled. receive/transmit status (rtstat) (address x'00ac) tbe txpnd rrtr rold rorn rfv rcv rbf 1 000000 0 bit 7 bit 0 this register is read only. tbe transmit buffer empty this bit is set as soon as the txd2 register is copied into the rx/tx shift register, i.e., the 1st data byte of each pair has been trans- mitted. the tbe bit is automatically reset if the txd2 register is written (the user should write a dummy byte to the txd2 register when transmitting an odd number of bytes of zero bytes). tbe can be programmed to generate an interrupt by setting the trans- cop87l88eb/cop87l89eb www.national.com 29
functional block description of the can interface (continued) mit interrupt enable bit (tie). when servicing the interrupt the user has to make sure that tbe gets cleared by executing a write instruction on the txd2 register, otherwise a new interrupt will be generated immediately after return from the interrupt service routine. the tbe bit is read only. it is set to 1 upon reset. tbe is also set upon completion of transmission of a valid message. txpnd transmission pending this bit is set as soon as the transmit start/stop (txss) bit is set by the user. it will stay set until the frame was successfully transmitted, until the transmission was successfully canceled by writing zero to the transmission start/stop bit (txss), or the de- vice enters the bus-off state. resetting the txss bit will only cancel a transmission if the transmission of a frame hasn't been started yet (bus idle) or if arbitration has been lost (receiving). if the device has already started transmission (won arbitration) the txpnd flag will stay set until the transmission is completed, even if the user's software has requested cancellation of the mes- sage. if an error occurs during transmission, a requested cancellation may occur prior to the begining of retransmission. rrtr received remote transmission request this bit is set when the remote transmission request (rtr) bit in a received frame was set. it is automatically reset through a read of the rxd1 register. to detect rrtr the user can either poll this flag or enable the receive interrupt (the reception of a remote transmission request will also cause an interrupt if the receive interrupt is enabled). if the receive interrupt is enabled, the user should check the rrtr flag in the service routine in order to distinguish between a rrtr interrupt and a rbf interrupt. it is the responsibility of the user to clear this bit by reading the rxd1 register, before the next frame is received. rold received overload frame this bit is automatically set when an overload frame was received on the bus. it is automatically reset through a read of the receive/transmit status register. it is the responsibility of the user to clear this bit by reading the receive/transmit status reg- ister, before the next frame is received. rorn receiver overrun this bit is automatically set on an overrun of the receive data register, i.e., if the user's program does not maintain the rxdn reg- isters when receiving a frame. it it automatically reset through a read of the receive/transmit status register. it is the responsi- bility of the user to clear this bit by reading the receive/transmit status register before the next frame is received. rfv received frame valid this bit is set if the received frame is valid, i.e., after the penultimate bit of the end of frame is received. it is automatically reset through a read of the receive/transmit status register. it is the responsibility of the user to clear this bit by reading the receive/ transmit status register (rtstat), before the next frame is received. rfv will cause a receive interrupt if enabled by rie. the user should be careful to read the last data byte (rxd1) of odd length messages (1, 3, 5 or 7 data bytes) on receipt of rfv. rfv is the only indication that the last byte of the message has been received. rcv receive mode this bit is set after the data length code of a message that passes the device's acceptance filter has been received. it is auto- matically reset after the crc-delimiter of the same frame has been received. it indicates to the user's software that arbitration is lost and that data is coming in for that node. rbf receive buffer full this bit is set if the second rx data byte was received. it is reset automatically, after the rxd1-register has been read by the soft- ware. rbf can be programmed to generate an interrupt by setting the receive interrupt enable bit (rie). when servicing the in- terrupt, the user has to make sure that rbf gets cleared by executing a ld instruction from the rxd1 register, otherwise a new interrupt will be generated immediately after return from the interrupt service routine. the rbf bit is read only. cop87l88eb/cop87l89eb www.national.com 30
functional block description of the can interface (continued) transmit error counter (tec) (address x'00ad) tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 bit 7 bit 0 this register is read/write. for test purposes and to identify the node status, the transmit error counter, an 8-bit error counter, is mapped into the data memory. if the lower seven bits of the counter overflow, i.e., tec7 is set, the device is error passive. caution to prevent interference with the can fault confinement, the user must not write to the rec/tec registers. both counters are au- tomatically updated following the can specification. receive error counter (rec) (00ae) rovl rec6 rec5 rec4 rec3 rec2 rec1 rec0 bit 7 bit 0 this register is read/write. rovl receive error counter overflow for test purposes and to identify the node status the receive error counter, a 7-bit error counter, is mapped into the data memory. if the counter overflows the rovl bit is set to indicate that the device is error passive and won't transmit any active error frames. if rovl is set then the counter is frozen. message identification a. transmitted message the user can select all 11 transmit identifier bits to transmit any message whigh fulfills the can2.0, part b spec without an ex- tended identifier (see note below). fully automatic retransmission is supported for messages no longer than 2 bytes. b. received messages the lower four bits of the receive identifier are don't care, i.e., the controller will receive all messages that fit in that window (16 messages). the upper 7 bits can be defined by the user in the receive identifier high register to mask out groups of messages. if the riaf bit is set, all messages will be received. note: the can interface tolerates the extended can frame format of 29 identifier bits and gives an acknowledgment. if an error occurs the receive error count er will be increased, and decreased if the frame is valid. bus synchronization during operation resetting the txen1 and txen0 bits in bus control register will disable the output drivers and do a resynchronization to the bus. all other can related registers and flags will be unaffected. bus synchronization of the device is this case is done in the following way: if the output was disabled (txen1, txen0 = a0o) and either txen1 or txen0, or both are set to 1, the device will not start trans- mission or reception of a frame until eleven consecutive arecessiveo bits have been received. a abus offo condition will also cause the output drivers tx1 and tx0 to be at tri-state (independent of the status of txen1 and txen0). the device will switch from abus offo to aerror activeo mode as described under the fmod-bit description (see can bus control register). this will ensure that the device is synchronized to the bus, before starting to transmit or receive. for information on bus synchronization and status of the can related registers after external reset refer to the reset section. on-chip voltage reference the on-chip voltage reference is a ratiometric reference. for electrical characteristics of the voltage reference refer to the elec- trical specifications section. analog switches analog switches are used for selecting between rx0 and v ref and between rx1 and v ref . cop87l88eb/cop87l89eb www.national.com 31
basic can concepts the following paragraphs provide a generic overview of the basic concepts of the controller area network (can) as de- scribed in chapter 4 of iso/dis11519-1. implementation re- lated issues of the national semiconductor device will be discussed as well. this device will process standard frame format only. ex- tended frame formats will be acknowledged, however the data will be discarded. for this reason the description of frame formats in the following section will cover only the standard frame format. the following section provides some more detail on how the device will handle received extended frames: if the device's remote identifier acceptance filter bit (riaf) is set to a1o, extended frame messages will be acknowledged. however, the data will be discarded and the device will not reply to a remote transmission request received in extended frame format. if the device's riaf bit is set to a0o, the upper 7 received id bits of an extended frame that match the de- vice's receive identifier (rid) acceptance filtler bits, are stroed in the device's rid register. however, the device does not reply to an rtr and any data is discarded. the device will only acknowledge the message. multi-master priority based bus access the can protocol is message based protocol that allows a total of 2032 (= 2 11 ?16) different messages in the standard format and 512 million (= 2 29 ?16) different messages in the extended frame format. multicast frame transfer by acceptance filtering every can frame is put on the common bus. each module receives every frame and filters out the frames which are not required for the module's task. remote data request a can master module has the ability to set a specific bit called the aremote transmission request bito (rtr) in a frame. this causes another module, either another master or a slave, to transmit a data frame after the current frame has been completed. system flexibility additional modules can be added to an existing network without a configuration change. these modules can either perform completely new functions requiring new data or pro- cess existing data to perform a new function. system wide data consistency as the can network is message oriented, a message can be used like a variable which is automatically updated by the controlling processor. if any module cannot process informa- tion it can send an overload frame. the device is incapable of initiating an overload frame, but will join a overload frame initiated by another device as required by can specifica- tions. non-destructive contention-based arbitration the can protocol allows several transmitting modules to start a transmission at the same time as soon as they moni- tor the bus to be idle. during the start of transmission every node monitors the bus line to detect whether its message is overwritten by a message with a higher priority. as soon as a transmitting module detects another module with a higher priority accessing the bus, it stops transmitting its own frame and switches to receive mode. for illustration see figure 19 . automatic retransmission of frames if a data or remote frame is overwritten by either a higher- prioritized data frame, remote frame or an error frame, the transmitting module will automatically retransmit it. this de- vice will handle the automatic retransmission of up to two data bytes automatically. messages with more than 2 data bytes require the user's software to update the transmit reg- isters. error detection and error signaling all messages on the bus are checked by each can node and acknowledge if they are correct. if any node detects an error it starts the transmission of an error frame. switching off defective nodes there are two error counters, one for transmitted data and one for received data, which are incremented, depending on the error type, as soon as an error occurs. if either counter goes beyond a specific value the node goes to an error state. a valid frame causes the error counters to decrease. the device can be in one of three states with respect to error handling: error active: an error active unit can participate in bus communication and sends an active (adominanto) error flag. error passive: an error passive unit can participate in bus communication. however, if the unit detects an error it is not allowed to send an active error flag. the unit sends only a passive (arecessiveo) error flag. bus off a unit that is abus offo has the output drivers disabled, i.e., it does not participate in any bus activity. (see error management and detection for more detailed information.) frame formats introduction there are basically two different types of frames used in the can protocol. the data transmission frames are:: data/remote frame the control frames are:: error/overload frame note: this device cannot send an overload frame as a result of not being able to process all information. however, the device is able to recog- nize an overload condition and join overload frames initiated by other devices. if no message is being transmitted, i.e., the bus is idle, the bus is kept at the arecessiveo level. figure 20 and figure 21 give an overview of the various can frame formats. data and remote frame data frames consist of seven bit fields and remote frames consist of six different bit fields: 1. start of frame (sof) 2. arbitration field 3. control field (ide bit, r0 bit, and dlc field) 4. data field (not in remote frame) 5. crc field 6. ack field cop87l88eb/cop87l89eb www.national.com 32
frame formats (continued) 7. end of frame (eof) a remote frame has no data field and is used for requesting data from other (remote) can nodes. figure 22 shows the format of a can data frame. ds012871-20 figure 19. can message arbitration ds012871-21 ds012871-22 a remote frame is identical to a data frame, except that the rtr bit is arecessiveo, and there is no data field. ide = identifier extension bit the ide bit in the standard format is transmitted adominanto, whereas in the extended format the ide bit is arecessiveo and the id is expanded to 29 bits. r = recessive d = dominant figure 20. can data transmission frames cop87l88eb/cop87l89eb www.national.com 33
frame formats (continued) frame coding remote and data frames are nrz codes with bit-stuffing in every bit field which holds computable information for the in- terface, i.e., start of frame arbitration field, control field, data field (if present) and crc field. error and overload frames are nrz coded without bit stuff- ing. bit stuffing after five consecutive bits of the same value, a stuff bit of the inverted value is inserted by the transmitter and deleted by the receiver. destuffed bit stream 100000x 011111x stuffed bit stream 1000001x 0111110x note : x = {0,1} start of frame (sof) the start of frame indicates the beginning of data and re- mote frames. it consists of a single adominanto bit. a node is only allowed to start transmission when the bus is idle. all nodes have to synchronize to the leading edge (first edge af- ter the bus was idle) caused by sof of the node which starts transmission first. arbitration field the arbitration field is composed of the identifier field and the rtr (remote transmission request) bit. the value of the rtr bit is adominanto in a data frame and arecessiveo in a re- mote frame. control field the control field consists of six bits. it starts with two bits re- served for future expansion followed by the four-bit data length code. receivers must accept all possible combina- tions of the two reserved bits. until the function of these re- ds012871-23 an error frame can start anywhere in the middle of a frame. ds012871-24 int = intermission suspend transmission is only for error passive nodes. ds012871-25 an overload frame can only start at the end of a frame. figure 21. can control frames ds012871-26 figure 22. can frame format cop87l88eb/cop87l89eb www.national.com 34
frame formats (continued) served bits is defined, the transmitter only sends a0o (domi- nant) bits. the first reserved bit (ide) is actually defined to indicate an extended frame with 29 identifier bits if set to a1o. can chips must tolerate extended frames, even if they can only understand standard frames, to prevent the destruction of an extended frames on an existing network. the data length code indicates the number of bytes in the data field. this data length code consists of four bits. the data field can be of length zero. the permissible number of data bytes for a data frame ranges from 0 to 8. data field the data field consists of the data to be transferred within a data frame. it can contain 0 to 8 bytes and each byte con- tains 8 bits. a remote frame has no data field. crc field the crc field consists of the crc sequence followed by the crc delimiter. the crc sequence is derived by the trans- mitter from the modulo 2 division of the preceding bit fields, starting with the sof up to the end of the data field, exclud- ing stuff-bits, by the generator polynomial: c 15 + c 14 + c 10 + c 8 + c 7 + c 4 + c 3 +1 the remainder of this division is the crc sequence transmit- ted over the bus. on the receiver side the module divides all bit fields up to the crc delimiter, excluding stuff-bits, and checks if the result is zero. this will then be interpreted as a valid crc. after the crc sequence a single arecessiveo bit is transmitted as the crc delimiter. ack field the ack field is two bits long and contains the ack slot and the ack delimiter. the ack slot is filled with a arecessiveo bit by the transmitter. this bit is overwritten with a adominanto bit by every receiver that has received a correct crc se- quence. the second bit of the ack field is a arecessiveo bit called the acknowledge delimiter. as a consequence the ac- knowledge flag of a valid frame is surrounded by two areces- siveo bits, the crc-delimiter and the ack delimiter. eof field the end of frame field closes a data and a remote frame. it consists of seven arecessiveo bits. interframe space data and remote frames are separate from every preceding frame (data, remote, error and overload frames) by the inter- frame space see figure 23 and figure 24 for details. error and overload frames are not preceded by an interframe space. they can be transmitted as soon as the condition oc- curs. the interframe space consists of a minimum of three bit fields depending on the error state of the node. these bit fields are coded as follows: the intermission has the fixed form of three arecessiveo bits. while this bit field is active, no node is allowed to start a transmission of a data or a remote frame. the only action to be taken is signaling an overload condition. this means that an error in this bit field would be interpreted as an overload condition. suspend transmission has to be inserted by error- passive nodes that were transmitter for the last message. this bit field has the form of eight arecessiveo bits. however, it may be overwritten by a adominanto start-bit from another non error passive node which starts transmission. the bus idle field consists of arecessiveo bits. its length is not speci- fied and depends on the bus load. error frame the error frame consists of two bit fields: the error flag and the error delimiter. the error field is built up from the various error flags of the different nodes. therefore, its length may vary from a minimum of six bits up to a maximum of twelve bits depending on when a module detects the error. when- ever a bit error, stuff error, form error, or acknowledgment er- ror is detected by a node, this node starts transmission of the error flag at the next bit. if a crc error is detected, transmis- sion of the error flag starts at the bit following the acknowl- edge delimiter, unless an error flag for a previous error con- dition has already been started. figure 25 shows how a local fault at one module (module 2) leads to a 12-bit error frame on the bus. the bus level may either be adominanto for an error-active node or arecessiveo for an error-passive node. an error ac- tive node detecting an error, starts transmitting an active er- ror flag consisting of six adominanto bits. this causes the de- ds012871-27 figure 23. interframe space for nodes which are not error passive or have been receiver for the last frame ds012871-28 figure 24. interframe space for nodes which are error passive and have been transmitter for the last frame cop87l88eb/cop87l89eb www.national.com 35
frame formats (continued) struction of the actual frame on the bus. the other nodes detect the error flag as either a violation of the rule of bit- stuffing or the value of a fixed bit field is destroyed. as a con- sequence all other nodes start transmission of their own er- ror flag. this means, that the error sequence which can be monitored on the bus as a maximum length of twelve bits. if an error passive node detects an error it transmits six areces- siveo bits on the bus. this sequence does not destroy a mes- sage sent by another node and is not detected by other nodes. however, if the node detecting an error was the transmitter of the frame the other modules will get an error condition by a violation of the fixed bit or stuff rule. figure 26 shows how an error passive transmitter transmits a passive error frame and when it is detected by the receivers. after any module has transmitted its active or passive error flag it waits for the error delimiter which consists of eight are- cessiveo bits before continuing. ds012871-29 modul e 1 = error active transmitter detects bit error at t2 modul e 2 = error active receiver with a local fault at t1 modul e 3 = error active receiver detects stuff error at t2 figure 25. error frame e error active transmitter cop87l88eb/cop87l89eb www.national.com 36
frame formats (continued) overload frame like an error frame, an overload frame consists of two bit fields: the overload flag and the overload delimiter. the bit fields have the same length as the error frame field: six bits for the overload flag and eight bits for the delimiter. the over- load frame can only be sent after the end of frame (eof) field and in they way destroys the fixed form of the intermis- sion field. order of bit transmission a frame is transmitted starting with the start of frame, se- quentially followed by the remaining bit fields. in every bit field the msb is transmitted first. frame validation frames have a different validation point for transmitters and receivers. a frame is valid for the transmitter of a message, if there is no error until the end of the last bit of the end of frame field. a frame is valid for a receiver, if there is no error until and including the end of the penultimate bit of the end of frame. frame arbitration and priority except for an error passive node which transmitted the last frame, all nodes are allowed to start transmission of a frame after the intermission, which can lead to two or more nodes starting transmission at the same time. to prevent a node from destroying another node's frame, it monitors the bus during transmission of the identifier field and the rtr-bit. as soon as it detects a adominanto bit while transmitting a are- cessiveo bit it releases the bus, immediately stops transmis- sion and starts receiving the frame. this causes no data or remote frame to be destroyed by another. therefore the highest priority message with the identifier 0x000 out of ds012871-30 modul e 1 = error active receiver with a local fault at t1 modul e 2 = error passive transmitter detects bit error at t2 modul e 3 = error passive receiver detects stuff error at t2 figure 26. error frame e error passive transmitter ds012871-31 figure 27. order of bit transmission within a can frame cop87l88eb/cop87l89eb www.national.com 37
frame formats (continued) 0x7ef (including the remote data request (rtr) bit) always gets the bus. this is only valid for standard can frame for- mat. note that while the can specification allows valid stan- dard identifiers only in the range 0x000 to 0x7ef, the device will allow identifiers to 0x7ff. there are three more items that should be taken into consid- eration to avoid unrecoverable collisions on the bus: within one system each message must be assigned a unique identifier. this is to prevent bit errors, as one mod- ule may transmit a adominanto data bit while the other is transmitting a arecessiveo data bit. this could happen if two or more modules start transmission of a frame at the same time and all win arbitration. data frames with a given identifier and a non-zero data length code may be initiated by one node only. other- wise, in worst case, two nodes would count up to the bus- off state, due to bit errors, if they always start transmitting the same id with different data. every remote frame should have a system-wide data length code (dlc). otherwise two modules starting transmission of a remote frame at the same time will overwrite each other's dlc which result in bit errors. acceptance filtering every node may perform acceptance filtering on the identi- fier of a data or a remote frame to filter out the messages which are not required by the node. in they way only the data of frames which match the acceptance filter is stored in the corresponding data buffers. however, every node which is not in the bus-off state and has received a correct crc- sequence acknowledges each frame. error management and detection there are multiple mechanisms in the can protocol, to de- tect errors and to inhibit erroneous modules from disabling all bus activities. the following errors can be detected: bit error a can device that is sending also monitors the bus. if the monitored bit value is different from the bit value that is sent, a bit error is detected. the reception of a adominanto bit in- stead of a arecessiveo bit during the transmission of a pas- sive error flag, during the stuffed bit stream of the arbitration field or during the acknowledge slot, is not interpreted as a bit error. stuff error a stuff error is detected, if the bit level after 6 consecutive bit times has not changed in a message field that has to be coded according to the bit stuffing method. form error a form error is detected, if a fixed frame bit (e.g., crc delim- iter, ack delimiter) does not have the specified value. for a receiver a adominanto bit during the last bit of end of frame does not constitute a form error. bit crc error a crc error is detected if the remainder of the crc calcula- tion of a received crc polynomial is non-zero. acknowledgment error an acknowledgment error is detected whenever a transmit- ting node does not get an acknowledgment from any other node (i.e., when the transmitter does not receive a adomi- nanto bit during the ack frame). the device can be in one of three states with respect to error handling: error active an error active unit can participate in bus communication and sends an active (adominanto) error flag. error passive an error passive unit can participate in bus communication. however, if the unit detects an error it is not allowed to send an active error flag. the unit sends only a passive (areces- siveo) error flag. a device is error passive when the transmit error counter is greater than 127 or when the receive error counter is greater than 127. a device becoming error passive sends an active error flag. an error passive device becomes error active again when both transmit and receive error counter are less than 128. bus off a unit that is abus offo has the output drivers disabled, i.e., it does not participate in any bus activity. a device is bus off when the transmit error counter is greater than 255. a bus off device will become error active again in one of two ways de- pending on which mode is selected by the user through the fault confinement mode select bit (fmod) in the can bus control register (cbus). setting the fmod bit to a0o (de- fault after power on reset) will select the standard fault con- finement mode. in this mode the device goes from abus offo to aerror activeo after monitoring 128*11 recessive bits (in- cluding bus idle) on the bus. this mode has been imple- mented for compatibility reasons with existing solutions. set- ting the fmod bit to a1o will select the enhanced fault confinement mode. in this mode the device goes from abus offo to aerror activeo after monitoring 128 agoodo messages, as indicated by the reception of 11 consecutive arecessiveo bits including the end of frame. the enhanced mode offers the advantage that a abus offo device (i.e., a device with a se- rious fault) is not allowed to destroy any messages on the bus until other devices can transmit at least 128 messages. this is not guaranteed in the standard mode, where a defec- tive device could seriously impact bus communication. when the device goes from abus offo to aerror activeo, both error counters will have the value a0o. in each can module there are two error counters to perform a sophisticated error management. the receive error counter (rec) is 7 bits wide and switches the device to the error passive state if it overflows. the transmit error counter (tec) is 8 bits wide. if it is greater than 127, the device is switched to the error passive state. as soon as the tec overflows, the device is switched bus-off, i.e., it does not par- ticipate in any bus activity. cop87l88eb/cop87l89eb www.national.com 38
frame formats (continued) the counters are modified by the device's hardware accord- ing to the following rules: table 10. receive error counter handling condition receive error counter a receiver detects a bit error during sending an active error flag. increment by 8 a receiver detects a adominanto bit as the first bit after sending an error flag. increment by 8 after detecting the 14th consecutive adominanto bit following an active error flag or overload flag or after detecting the 8th consecutive adominanto bit following a passive error flag. after each sequence of additional 8 consecutive adominanto bits. increment by 8 any other error condition (stuff, frame, crc, ack). increment by 1 a valid reception or transmission. decrement by 1 if counter is not 0 table 11. transmit error counter handling condition transmit error counter a transmitter detects a bit error during sending an active error flag. increment by 8 after detecting the 14th consecutive adominanto bit following an active error flag or overload flag or after detecting the 8th consecutive adominanto bit following a passive error flag. after each sequence of additional 8 consecutive adominanto bits. increment by 8 any other error condition (stuff, frame, crc, ack). increment by 8 a valid reception or transmission. decrement by 1 if counter is not 0 special error handling for the tec counter is performed in the following situations: a stuff error occurs during arbitration, when a transmitted arecessiveo stuff bit is received as a adorminanto bit. this does not lead to an incrementation of the tec. an ack-error occurs in an error passive device and no adominanto bits are detected while sending the passive error flag. this does not lead to an incrementation of the tec. if only one device is on the bus and this device transmits a message, it will get no acknowledgment. this will be detected as an error and message will be repeated. when the device goes aerror passiveo and detects an ac- knowledge error, the tec counter is not incremented. therefore the device will not go from aerror passiveo to the abus offo state due to such a condition. figure 28 shows the connection of different bus states ac- cording to the error counters. synchronization every receiver starts with a ahard synchronizationo on the falling edge of the sof bit. one bit time consists of four bit segments: synchronization segment, propagation segment, phase segment 1 and phase segment 2. a falling edge of the data signal should be in the synchroni- zation segment. this segment has the fixed length of one time quanta. to compensate for the various delays within a network, the propagation segment is used. its length is pro- grammable from 1 to 8 time quanta. phase segment 1 and phase segment 2 are used to resynchronize during an active frame. the length of these segments is from 1 to 8 time quanta long. two types of synchronization are supported: hard synchronization is done with the falling edge on the bus while the bus is idle, which is then interpreted as the sof. it restarts the internal logic. soft synchronization is used to lengthen or shorten the bit time while a data or remote frame is received. whenever a falling edge is detected in the propagation segment or in phase segment 1, the segment is lengthened by a specific value, the resynchronization jump width (see figure 30 ). if a falling edge lies in the phase segment 2 (as shown in fig- ure 30 ) it is shortened by the resynchronization jump width. only one resynchronization is allowed during one bit time. the sample point lies between the two phase segments and is the point where the received data is supposed to be valid. the transmission point lies at the end of phase segment 2 to start a new bit time with the synchronization segment. note: the resynchronization jump width (rjw) is automatically determined from the programmed value of ps. if a soft resynchronization is done during phase segment 1 or the propagation segment, then rjw will ei- ther be equal to 4 internal can clocks (cki/(1 + divider) ) or the pro- grammed value of ps, whichever is less. ps2 will never be shorter than 1 internal can clock. note: (ps1 e btl settings any psc setting) the ps1 of the btl should al- ways be programmed to values greater than 1. to allow device resyn- chronization for positive and negative phase errors on the bus. (if ps1 is programmed to one, a bit time could only be lengthened and never shortened which basically disables half of the synchronization). ds012871-32 figure 28. can bus states cop87l88eb/cop87l89eb www.national.com 39
frame formats (continued) ds012871-33 a) synchronization segment b) propagation segment figure 29. bit timing ds012871-34 figure 30. resynchronization 1 ds012871-35 figure 31. resynchronization 2 cop87l88eb/cop87l89eb www.national.com 40
detection of illegal conditions the device can detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. reading of underfined rom gets zeros. the opcode for soft- ware interrupt is zero. if the program fetches instructions from undefined rom, this will force a software interrupt, thus signaling that an illegal condition has occurred. the subroutine stack grows down for each call (jump to sub- routine), interrupt, or push, and grows up for each return or pop. the stack pointer is initialized to ram location 02f hex during reset. consequently, if there are more returns than calls, the stack pointer will point to addresses 030 and 031 hex (which are undefined ram). undefined ram from ad- dress 030 to 03f hex is read as all 1's, which in turn will cause the program to return to address 7fff hex. this is an undefined rom location and the instruction fetched (all 0's) from this location will generate a software interrupt signaling an illegal condition. thus, the chip can detect the following illegal conditions: 1. executing from undefined rom. 2. over apopoing the stack by having more returns than calls. when the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery procedure before restart- ing (this recovery program is probably similar to that follow- ing reset, but might not contain the same program initializa- tion procedures). microwire/plus microwire/plus is a serial synchronous communications interface. the microwire/plus capability enables the de- vice to interface with any of national semiconductor's mi- crowire peripherals (i.e., a/d converters, display drivers, e2proms etc.) and with other microcontrollers which sup- port the microwire interface. it consists of an 8-bit serial shift register (sio) with serial data input (si), serial data out- put (so) and serial shift clock (sk). figure 32 shows a block diagram of the microwire/plus logic. the shift clock can be selected from either an internal source or an external source. operating the microwire/plus ar- rangement with the internal clock source is called the master mode of operation. similarly, operating the microwire/ plus arrangement with an external shift clock is called the slave mode of operation. the cntrl register is used to configure and control the microwire/plus mode. to use the microwire/plus, the msel bit in the cntrl register is set to one. in the mas- ter mode the sk clock rate is selected by the two bits, sl0 and sl1, in the cntrl register. table 12 details the different clock rates that may be selected. microwire/plus operation setting the busy bit in the psw register causes the microwire/plus to start shifting the data. it gets reset when eight data bits have been shifted. the user may reset the busy bit by software to allow less than 8 bits to shift. if enabled, an interrupt is generated when eight data bits have been shifted. the device may enter the microwire/plus mode either as a master or as a slave. figure 33 shows how two cop888 family microcontrollers and several peripherals may be interconnected using the microwire/plus ar- rangements. warning: the sio register should only be loaded when the sk clock is low. loading the sio register while the sk clock is high will result in undefined data in the sio register. sk clock is nor- mally low when not shifting. setting the busy flag when the input sk clock is high in the microwire/plus slave mode may cause the current sk clock for the sio shift register to be narrow. for safety, the busy flag should only be set when the input sk clock is low. ds012871-36 figure 32. microwire/plus block diagram cop87l88eb/cop87l89eb www.national.com 41
microwire/plus (continued) microwire/plus master mode operation in the microwire/plus master mode of operation the shift clock (sk) is generated internally. the microwire master always initiates all data exchanges. the msel bit in the cntrl register must be set to enable the so and sk functions onto the g port. the so and sk pins must also be selected as outputs by setting appropriate bits in the port g configuraiton register. table 13 summarizes the bit settings required for master or slave mode of operation. table 12. microwire/plus master mode clock selection sl1 sl0 sk 0 0 2xt c 0 1 4xt c 1 x 8xt c where t c is the instruction cycle clock microwire/plus slave mode operation in the microwire/plus slave mode of operation the sk clock is generated by an external source. setting the msel bit in the cntrl register enables the so and sk functions onto the g port. the sk pin must be selected as an input and the so pin is selected as an output pin by setting and re- setting the appropriate bit in the port g configuration regis- ter. table 5 summarizes the settings required to enter the slave mode of operation. the user must set the busy flag immediately upon entering the slave mode. this will ensure that all data bits sent by the master will be shifted properly. after eight clock pulses the busy flag will be cleared and the sequence may be re- peated. alternate sk phase operation the device allows either the normal sk clock or an alternate phase sk clock to shift data in and out of the sio register. in both the modes the sk is normally low. in the normal mode data is shifted in on the rising edge of the sk clock and the data is shifted out on the falling edge of the sk clock. the sio register is shifted on each falling edge of the sk clock in the normal mode. in the alternate sk phase mode the sio register is shifted on the rising edge of the sk clock. a control flag, sksel, allows either the normal sk clock or the alternate sk clock to be selected. resetting sksel causes the microwire/plus logic to be clocked from the normal sk signal. setting the sksel flag selects the alter- nate sk clock. the sksel is mapped into the g6 configura- tion bit. the sksel flag will power up in the reset condition, selecting the normal sk signal. table 13. microwire/plus mode selection g4 g5 g4 fun. g5 fun. operation (so) (sk) config. config. bit bit 1 1 so int. sk microwire/ plus master 0 1 tri-state int. sk microwire/ plus master 1 0 so ext. sk microwire/ plus slave 0 0 tri-state ext. sk microwire/ plus slave this table assumes that the control flag msel is set. ds012871-37 figure 33. microwire/plus application cop87l88eb/cop87l89eb www.national.com 42
serial peripheral interface the serial peripheral interface (spi) is used in master-slave bus systems. it is a synchronous bidirectional serial commu- nication interface with two data lines miso and mosi ( m as- ter i n s lave o ut, m aster o ut s lave i n). a serial clock and a slave select (ss) signal are always generated by the spi master. the interface receives/transmits protocol frames with up to 12 bytes length within a frame, where a frame is defined as the time between a falling edge and a rising edge of ss. theory of operation figure 36 shows a block diagram illustrating the basic opera- tion of the spi circuit. in the spi interface, data is transmitted/received in packets of 8 bits length which are shifted into/out of a shift register with the active edge of the shift clock sck. two 12 byte fifos, which serve as a re- ceive and a transmit buffer, allow a maximum message length of 1 2 x 8 bits in both transmit and receive direction without cpu intervention. with cpu intervention, many more bytes can be received. two registers, the spi control register (spicntl) and the spi status register (spistat), are used to control the spi interface via the internal cop bus. several different operation modes, such as master or slave operation, are possible. an ss-expander allows the generation of up to 8 signals on the n-port, which can be used as additional ss-signals (ess [7:0]) or as host programmable general purpose signals. the ss-expander is programmed with the content of the first mosi-byte (i.e., the content of the 1st byte [7:0] appears at ess [7:0]) (n-port[7:0]), respectively), if the ess program- ming mode is selected. the ess programming mode is se- lected by the condition mosi = l at the falling edge of ss . use of the ess expander requires the setup of four condi- tions by the user. 1. set the sessen bit of spicntl. 2. set portnx to select which bits are used for ss expan- sion. 3. configure the portnc register to enable the desired ss expansion bits as outputs. 4. have an ess condition (mosi = low at the falling edge of ss). loop back mode setting the sloop bit enables the loop back mode, which can be used for test purposes. if the loop back mode is se- lected, tx fifo data are communicated to the rx fifo via the spi register. in the slave mode, miso output is inter- nally connected to the mosi input. in the master mode, the mosi output is internally connected to the miso input. ds012871-38 figure 34. spi transmission example ds012871-39 figure 35. loop back mode block diagram cop87l88eb/cop87l89eb www.national.com 43
serial peripheral interface (continued) ds012871-40 figure 36. spi block diagram cop87l88eb/cop87l89eb www.national.com 44
serial peripheral interface (continued) the spiu control register table 14. spi control (spicntl) (0098) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srie stie sessen spimod[1:0] sce spien sloop 00 0 00000 b7 srie s pi r eceive i nterrupt e nable 0 e disable receive interrupt 0 e enable receive interrupt b6 stie s pi t ransmit buffer i nterrupt e nable 0 e disable transmit buffer interrupt 0 e enable transmit buffer interrupt b5 sessen s pi ss expander (ess ) enable 0 e the detection of the ess programming mode is disabled, i.e., the value of mosi at the falling edge of ss is adon't careo. 1 e ess programming mode detection is enabled, i.e., if the condition amos i=0atthe falling edge of ss o occurs, the ss -expander is selected and bits [7:0] of the first transmitted byte determine the state of the n-port (ess [7:0]). ess [7:0] will go 1 at the positive edge of ss . b[4:3] spimod[1:0] spi operation mode select spimod[1:0] 0 0: slave mode, e sck is spi clock input e miso is spi data output e mosi is spi data input e ss is slave select input 1 0: standard master mode, e sck is spi clock output (cki/40) e miso is spi data input e mosi is spi data output e ss is slave select output in the master mode, 3 different spi clock frequencies are available: 01:f sck = 1/(t c ) = cki/10 10:f sck = 1/(4 t c ) = cki/40 11:f sck = 1/(16 t c ) = cki/160 b2 sce s pi a ctive clock e dge select 0: data are shifted out on the falling edge of sck and are shifted in on the rising edge of sck 1: data are shifted out on the rising edge of sck and are shifted in on the falling edge of sck b1 spien spi en able enables the spi interface and the alternate functions of the miso, mosi, sck and ss pins. 0: disable spi 1: enable spi, all port mess signals are set to 1 b0 sloop s pi loop back mode 0: disable loop back mode 1: enable loop back mode, miso and mosi are internally connected (see figure 37 ) programming the spi expander if the ss expander is enabled by setting sesse n=1inthe spi control register (spicntl), the n-port will be pro- grammed with the content of the first mosi-byte (i.e., the content of the 1st byte [7:0] appears at n-port[7:0] after com- plete reception of the first byte), if the ess programming mode is detected. if any bytes follow after the 1st mosi byte, all data will be ignored by the spi. cop87l88eb/cop87l89eb www.national.com 45
serial peripheral interface (continued) the ess programming mode is detected by the ess control logic, which decodes the condition amosi = l at the falling edge of ss . for further details, see figure 37 . the selected n-port bits will be set to 1 after the positive edge of ss . single n-port bits may be enabled for use as ss expansion, or disabled to allow for general purpose i/o, by the respec- tive bits in the portnx register. ds012871-41 figure 37. programming the spi expander ds012871-42 sessen = 1, sce = 0. if mos i=0atthe falling edge of ss , the ess programming mode is detected and all n-port alternate functions are enabled. figure 38. programming the ss expander cop87l88eb/cop87l89eb www.national.com 46
spi status register table 15. spi status register (spistat) (0099) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srorn srbne stbf stbe stfl sessdet x x 0 0110 0 0 the spi status register is a read only register. ds012871-43 a) slave mode; rising sck edge is active edge. (spimod[1,0] = [0,0], sce =0) ds012871-44 b) slave mode; falling sck edge is active edge. (spimod[1,0] = [0,0], sce=1) figure 39. slave mode communication ds012871-45 a) master mode; rising sck edge is active edge. (spimod[1,0] = [1,0], sce = 0) ds012871-46 b) master mode; falling sck edge is active edge. (spimod[1,0] = [1,0], sce = 1) figure 40. master mode communication cop87l88eb/cop87l89eb www.national.com 47
spi status register (continued) b7 srorn s pi r eceiver o verrun. this bit is set on the attempt to overwrite valid data in the rx fifo by the spi interface. (the condition to detect this is: srwp = srrp & cop has not read the data at srrp and attempting to write to the rx fifo by the spi interface.) this bit can generate a receive interrupt if the receive interrupt is enabled (srie = 1). note 0: at this condition the write operation will not be executed and all data get lost. note 1: the srorn bit stays set until the reset condition. this bit is reset with a dummy write to the spistat register. (as the register is read only a dummy write does not have any effect on any other bits in this register.) as a result of the srorn condition, the srwp becomes frozen (i.e., does not change until the srorn bit is reset) and the spi will not store any new data in the rx fifo. note 2: with the srrp being still available, the user can read the data in the rx fifo before resetting the srorn bit. b6 srbne s pi r eceive b uffer n ot e mpty this bit is set with a write to the spi rx fifo resulting in srw p ! = srrp (caution at rollover!). this bit is reset with the read of the spirxd register resulting in srwp to be equal to srrp. b5 stbf this bit can generate a receive interrupt if enabled with the rie bit. s pi t ransmit b uffer f ull this bit is set after a write operation to the spitxd register (from the cop side), which results in strp = stwp. it gets reset as soon as the strp gets incremented - by the spi if reading data out of the tx fifo. b4 stbe s pi t ransmit b uffer e mpty this bit is set after the last bit of the a read from the spitxd register, which results in strp = stwp. it gets reset as soon as the stwp gets incremented - by the cop if writing data into the tx fifo. it is set on reset. b3 stfl s pi t ransmit b uffer f lush this bit indicates that the contents of the transmit buffer got discharged by the ss signal becoming high before all data in the transmit buffer could be transmitted. this bit gets set if the ss signal gets high and 1.strp != stwp or 2.strp = stwp and the current byte has not been completely transmitted from the spi shift register these conditions will reset strp and stwp to 0. these are virtual pointers and cannot be viewed. note: strp = stwp & stbe = 1 will generate an interrupt. this bit gets reset with a write to the spitxd register. b2 sessdet s pi sse xpander d etection this bit indicates the detection of a ss expand condition (mos i=0atthe falling edge of ss ) immediately after the n-port has been programmed (8th sck bit, 8 s at sc k = 1 mhz). this bit is reset at the rising edge of ss . 1: ss expand condition detected. 0: normal communication. note: the spi master must hold s s = 0 long enough to allow the device to read sessdet. otherwise the sessdet information will get lost. b1 unused b0 unused spi synchronization after the spi is enabled (spien = 1), the spi internal receive and transmit shift clock is kept disabled until ss becomes in- active. this includes ss being active at the time spien is set, i.e., no receive/transmit is possible until ss becomes in- active after enabling the spi. cop87l88eb/cop87l89eb www.national.com 48
spi status register (continued) halt/idle mode if the device enters the halt/idle mode, both rx and tx fifos get reset (flushed). if the device is exiting halt/idle mode, and spi synchronization takes place as described above. spirxd and spitxd have the same state as after reset, spistat bits after halt/idle mode are: srorn: unchanged srbne: 0 stbf: 0 stbe: 1 stfl: 1 sessdet: x (depending on ss and mosi line) transmission start in master mode the transmission of data in the master mode is started if the user controlled ss signal is switched active. no sck will be generated in master mode and thus no data is transmitted if the ss signal is kept high, i.e., ss must be switched low to generate sck. resetting the ss signal in the master mode will immediately stop the transmission and flush the transmit fifo. thus, the user must only reset the ss if: 1. tbe is set or 2. sck is high (sce = 0) or low (sce = 1) tx and rx fifo if the spi is disabled (spien = 0), all spi fifo related point- ers are reset and kept at zero until the spi is enabled again. also, the read/write operation to both spitxd and spirxd will not cause the pointers to change, if spien is set, read operations from the rxfifo and write operation to txfifo will increment the respective read/write pointers. spirxd spi receive data register spirxd is at address location a009ao. it is a read/write reg- ister. this register holds the receive data at the current srrp lo- cation: a cop read operation from this register to the accu- mulator will read the rx fifo at the srrp location and in- crement srrp afterwards. a write to this register (by the controllers sw) will write to the rx fifo at the current srrp location. the srrp is not changed. note: during breakpoint the srrp is not incremented. a write to this register from the spi interface side will write to the current srwp location and increment srwp afterwards. spitxd spi transmit data register spitxd is at address location a009bo. it is a read/write reg- ister. this register holds the transmit data at the current stwp lo- cation: a write from the controller to this register will write to the stwp location and increment the stwp afterwards. a read from the controller to this register will read the tx fifo at the current stwp location. the pointer is not changed. writing data into this register will start a transmission of data in the master mode. note: no read modify write instructions should be used on this register. reading this register from the spi side will read the byte at the current strp location and afterwards increment strp. spi rx fifo the spi rx fifo is a 12 byte first in first out buffer. spi rx fifo data are read from the controller by reading the spirxd register. a pointer (srrp) controls the controller read location. data is written to this register by the spi inter- face. the write location is controlled by the srwp. srwp is incremented after data is stored to the fifo srwp is never decremented srwp has a roll-over 10 ? 11 ? 0 ? 1 ? 2 ? etc. it is a circularly linked list. srrp is incremented after data is read from the fifo srrp is never decremented srrp has a roll-over 10 ? 11 ? 0 ? 1 ? 2 ? etc. it is a circularly linked list. both pointers are cleared at reset. the following bits indicate the status of the rx fifo: srbne = (srwp != srrp) and !srorn .srorn is set at (srwp = srrp) and after a write from the spi side, reset at write to spistat. special conditions: if .srorn is set, no writes to the rx fifo are allowed from the spi side. srwp is frozen. reset- ting .srorn (after it was set) clears both srwp and srrp. to prevent erroneous clearing of the receive fifo when en- tering halt/idle mode, the user needs to enable the miwu or port m3 (ss) by setting bit 3 in mwken register. spi tx fifo the spi tx fifo is a 12 byte first in first out buffer. data is written to the fifo by the controller executing a write instruc- tion to the spitxd register. a pointer (stwp) controls the controller write location. data is read from this register by the spi interface. the read location is controlled by the strp. strp is incremented after data is read from the fifo strp is never decremented strp has a roll-over 10 ? 11 ? 0 ? 1 ? 2 ? etc. it is a circularly linked list. stwp is incremented after data is written to the fifo stwp is never decremented stwp has a roll-over 10 ? 11 ? 0 ? 1 ? 2 ? etc. it is a circularly linked list. both pointers are cleared at reset. the following bits indicate the status of the tx fifo: stbf = set at (strp = stwp) after a write from the controller re- set at ((strp != stwp) i stbe) after a read from the spi stbe = (strp = stwp) after a read from the spi. special conditions: if the ss signal becomes high before data the last bit of the last byte in the tx fifo is transmitted both strp and stwp will be set to 0. the stfl bit will be set. (stbe will be set as well.) note: the srrp, srwp, strp and stwp registers are not available to the user. their operation description is included for clarity and to enhance the user's understanding. a/d converter the device contains an 8-channel, multiplexed input, suc- cessive approximation, analog-to-digital convertor. the de- vice contains agnd/av cc and adv ref for voltage refer- ence. operating modes the a/d convertor supports ratiometric measurements. it supports both single ended and differential modes of opera- tion. four specific analog channel selection modes are sup- ported. these are as follows: allow any specific channel to be selected at one time. the a/d convertor performs the specific conversion requested and stops. cop87l88eb/cop87l89eb www.national.com 49
a/d converter (continued) allow any specific channel to be scanned continuously. in other words, the user specifies the channel and the a/d con- vertor scans it continuously. at any arbitrary time the user can immediately read the result of the last conversion. the user must wait for only the first conversion to complete. allow any differential channel pair to be selected at one time. the a/d convertor performs the specific differential conver- sion requested and stops. allow any differential channel pair to be scanned continu- ously. in other words, the user specifies the differential chan- nel pair and the a/d convertor scans it continuously. at any arbitrary time the user can immediately read the result of the last differential conversion. the user must wait for only the first conversion to complete. the a/d convertor is supported by two memory mapped reg- isters, the result register and the mode control register. when the device is reset, the mode control register (enad) is cleared, the a/d is powered down and the a/d result reg- ister has unknown data. a/d control register the enad control register contains 3 bits for channel selec- tion, 2 bits for prescaler selection, 2 bits for mode selection and a busy bit. an a/d conversion is initiated by setting the adbsy bit and the enad control register. the result of the conversion is available to the user in the a/d result register, adrslt, when adbsy is cleared by the hardware on completion of the conversion. enad (address (0xcb) channel mode prescaler busy select select select adch2 adch1 adch0 admod1 admod0 psc1 psc0 adbsy bit 7 bit 0 channel select this 3-bit field selects one of eight channels to be the v in+ . the mode selection determines the v in? input. single ended mode: bit 7 bit 6 bit 5 channel no. 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 differential mode: bit 7 bit 6 bit 5 channel pairs (+, ?) 000 0,1 001 1,0 010 2,3 011 3,2 100 4,5 101 5,4 110 6,7 bit 7 bit 6 bit 5 channel pairs (+, ?) 111 7,6 mode select this 2-bit field is used to select the mode of operation (single conversion, continuous conversions, differential, single ended) as shown in the following table. bit 4 bit 3 mode 0 0 single ended mode, single conversion 0 1 single ended mode, continuous scan of a single channel into the result register 1 0 differential mode, single conversion 1 1 differential mode, continuous scan of a channel pair into the result register prescaler select this 2-bit field is used to select one of the four prescaler clocks for the a/d converter. the following table shows the various prescaler options. a/d convertor clock prescaler bit 2 bit 1 clock select 0 0 divide by 2 0 1 divide by 4 1 0 divide by 6 1 1 divide by 12 busy bit the adbsy bit of the enad register is used to control start- ing and stopping of the a/d conversion. when adbsy is cleared, the prescale logic is disabled and the a/d clock is turned off. setting the adbsy bit starts the a/d clock and ini- tiates a conversion based on the mode select value currently in the enad register. normal completion of an a/d conver- sion clears the adbsy bit and turns off the a/d convertor. the adbsy bit remains a one during continuous conversion. the user can stop continuous conversion by writing a zero to the adbsy bit. if the user wishes to restart a conversion which is already in progress, this can be accomplished only by writing a zero to the adbsy bit to stop the current conversion and then by writing a one to adbsy to start a new conversion. this can be done in two consecutive instructions. a/d operation the a/d convertor interface works as follows. setting the adbsy bit in the a/d control register enad initiates an a/d conversion. the conversion sequence starts at the begin- ning of the write to enad operation which sets adbsy, thus powering up the a/d. at the first falling edge of the convertor clock following the write operation, the sample signal turns on for seven clock cycles. if the a/d is in single conversion mode, the conversion complete signal from the a/d will gen- erate a power down for the a/d convertor and will clear the adbsy bit in the enad register at the next instruction cycle boundary. if the a/d is in continuous mode, the conversion complete signal will restart the conversion sequence by de- selecting the a/d for one convertor clock cycle before start- ing the next sample. the a/d 8-bit result is immediately loaded into the a/d result register (adrslt) upon comple- cop87l88eb/cop87l89eb www.national.com 50
a/d converter (continued) tion. internal logic prevents transient data (resulting from the a/d writing a new result over an old one) being read from adrslt. inadvertent changes to the enad register during conversion are prevented by the control logic of the a/d. any attempt to write any bit of the enad register except adbsy, while adbsy is a one, is ignored. adbsy must be cleared either by completion or an a/d conversion or by the user before the prescaler, conversion mode or channel select values can be changed. after stopping the current conversion, the user can load different values for the prescaler, conversion mode or channel select and start a new conversion in one instruction. it is important for the user to realize that, when used in differ- ential mode, only the positive input to the a/d converter is sampled and held. the negative input is constantly con- nected and should be held stable for the duration of the con- version. failure to maintain a stable negative input will result in incorrect conversion. prescaler the a/d convertor (a/d) contains a prescaler option that al- lows four different clock selections. the a/d clock frequency is equal to cki divided by the prescaler value. note that the prescaler value must be chosen such that the a/d clock falls within the specified range. the maximum a/d frequency is 1.67 mhz. this equates to a 600 ns a/d clock cycle. the a/d convertor takes 17 a/d clock cycles to complete a conversion. thus the minimum a/d conversion time for the device is 10.2 s when a prescaler of 6 has been selected. the 17 a/d clock cycles needed for conversion consist of 1 cycle at the beginning for reset, 7 cycles for sampling, 8 cycles for converting, and 1 cycle for loading the result into the a/d result register (adrslt). this a/d result register is a read-only register. the user cannot write into adrslt. the adbsy flag provides an a/d clock inhibit function, which saves power by powering down the a/d when it is not in use. note: the a/d convertor is also powered down when the device is in either the halt or idle modes. if the a/d is running when the device enters the halt or idle modes, the a/d powers down and then restarts the conversion with a corrupted sampled voltage (and thus an invalid re- sult) when the device comes out of the halt or idle modes. analog input and source resistance considerations figure 41 shows the a/d pin model in single ended mode. the differential mode has a similar a/d pin model. the leads to the analog inputs should be kept as short as possible. both noise and digital clock coupling to an a/d input can cause conversion errors. the clock lead should be kept away from the analog input line to reduce coupling. the a/d channel input pins do not have any internal output driver cir- cuitry connected to them because this circuitry would load the analog input signals due to output buffer leakage current. source impedances greater than 3 k w on the analog input lines will adversely affect the internal rc charging time dur- ing input sampling. as shown in figure 41 , the analog switch to the dac array is closed only during the 7 a/d cycle sample time. large source impedances on the analog inputs may result in the dac array not being charged to the correct voltage levels, causing scale errors. if large source resistance is necessary, the recommended solution is to slow down the a/d clock speed in proportion to the source resistance. the a/d convertor may be operated at the maximum speed for r s < 3k w . for r s > 3k w , a/d clock speed needs to be reduced. for example, with r s =6 k w , the a/d convertor may be operated at half the maximum speed. a/d convertor clock speed may be slowed down by either increasing the a/d prescaler divide-by or decreasing the cki clock frequency. the a/d minimum clock speed is 100 khz. ds012871-47 * the analog switch is closed only during the sample time. figure 41. a/d pin model (single ended mode) cop87l88eb/cop87l89eb www.national.com 51
uart the device contains a full-duplex software programmable uart. the uart ( figure 42 ) consists of a transmit shift reg- ister, a receiver shift register and seven addressable regis- ters, as follows: a transmit buffer register (tbuf), a receiver buffer register (rbuf), a uart control and status register (enu), a uart receive control and status register (enur), a uart interrupt and clock source register (enui), a pres- caler select register (psr) and baud (baud) register. the enu register contains flags for transmit and receive func- tions; this register also determines the length of the data frame (7, 8 or 9 bits), the value of the ninth bit in transmis- sion, and parity selection bits. the enur register flags fram- ing, data overrun and parity errors while the uart is receiving. other functions of the enur register include saving the ninth bit received in the data frame, enabling or disabling the uart's attention mode of operation and providing additional receiver/transmitter status information via rcvg and xmtg bits. the determination of an internal or external clock source is done by the enui register, as well as selecting the number of stop bits and enabling or disabling transmit and receive inter- rupts. a control flag in this register can also select the uart mode of operation: asynchronous or synchronous. ds012871-48 figure 42. uart block diagram cop87l88eb/cop87l89eb www.national.com 52
uart (continued) uart control and status registers the operation of the uart is programmed through three registers: enu, enur and enui. the function of the individual bits in these registers is as follows: enu-uart control and status register (address at 0ba) xbit9/ pen psel1 psel0 chl1 chl0 err rbfl tbmt 0rw 0rw 0rw 0rw 0rw 0r 0r 1r bit 7 bit 0 enu-uart receive control and status register (address at 0bb) doe fe pe spare rbit9 attn xmtg rcvg 0rd 0rd 0rd 0rw* 0r 0rw 0r 0r bit 7 bit 0 enui-uart interrupt and clock source register (address at 0bc) stp2 stp78 etdx ssel xrclk xtclk eri eti 0rw 0rw 0rw 0rw 0rw 0rw 0rw 0rw bit 7 bit 0 *: bit is not used. 0: bit is cleared on reset. 1: bit is set to one on reset. r: bit is read-only; it cannot be written by software. r/w: bit is read/write. d: bit is cleared on read; when read by software as a one, it is cleared automatically. writing to the bit does not affect its state. description of uart register bits enu e uart control and status register tbmt: this bit is set when the uart transfers a byte of data from the tbuf register into the tsft register for transmis- sion. it is automatically reset when software writes into the tbuf register. rbfl: this bit is set when the uart has received a com- plete character and has copied it into the rbuf register. it is automatically reset when software reads the character from rbuf. err: this bit is a global uart error flag which gets set if any or a combination of the errors (doe, fe, pe) occur. chl1, chl0: these bits select the character frame format. parity is not included and is generated/verified by hardware. chl1 = 0, chl0 = 0 the frame contains eight data bits. chl1 = 0, chl0 = 1 the frame continues seven data bits. chl1 = 1, chl0 = 0 the frame continues nine data bits. chl1 = 1, chl0 = 1 loopback mode selected. transmit- ter output internally looped back to receiver input. nine bit framing for- mat is used. xbit9/psel0: programs the ninth bit for transmission when the uart is operating with nine data bits per frame. for seven or eight data bits per frame, this bit in conjunction with psel1 selects parity. psel1, psel0: parity select bits. psel1 = 0, psel0 = 0 odd parity (if parity enabled) psel1 = 0, psel1 = 1 odd parity (if parity enabled) psel1 = 1, psel0 = 0 mark(1) (if parity enabled) psel1 = 1, psel1 = 1 space(0) (if parity enabled) pen: this bit enables/disabled parity (7- and 8-bit modes only). pen = 0 parity disabled. pen = 1 parity enabled. enur e uart receive control and status register rcvg: this bit is set high whenever a framing error occurs and goes low when rdx goes high. xmtg: this bit is set to indicate that the uart is transmit- ting. it gets reset at the end of the last frame (end of last stop bit). attn: attention mode is enabled while this bit is set. this bit is cleared automatically on receiving a character with data bit nine set. rbit9: contains the ninth data bit received when the uart is operating with nine data bits per frame. spare: reserved for future use. pe: flags a parity error. pe = 0 indicates no parity error has been detected since the last time the enur register was read. pe = 1 indicates the occurrence of a parity error. fe: flags a framing error. fe = 0 indicates no framing error has been detected since the last time the enur register was read. fe = 1 indicates the occurrence of a framing error. cop87l88eb/cop87l89eb www.national.com 53
uart (continued) doe: flags a data overrun error. doe = 0 indicates no data overrun error has been de- tected since the last time the enur register was read. doe = 1 indicates the occurrence of a data overrun error. enue e uart interrupt and clock source register eti: this bit enables/disables interrupt from the transmitter section. eti = 0 interrupt from the transmitter is disabled. eti = 1 interrupt from the transmitter is enabled. eri: this bit enables/disables interrupt from the receiver section. eri = 0 interrupt from the receiver is disabled. eri = 1 interrupt from the receiver is enabled. xtclk: this bit selects the clock source for the transmitter section. xtclk = 0 the clock source is selected through the psr and baud registers. xtclk = 1 signal on ckx (l1) pin is used as the clock. xrclk: this bit selects the clock source for the receiver section. xrclk = 0 the clock source is selected through the psr and baud registers. xrclk = 1 signal on ckx (l1) pin is used as the clock. ssel: uart mode select. ssel = 0 asynchronous mode. ssel = 1 synchronous mode. etdx: tdx (uart transmit pin) is the alternate function assigned to port l pin l2; it is selected by setting edtx bit. to simulate line break generation, software should reset etdx bit and output logic zero to tdx pin through port l data and configuration registers. stp78: this bit is set to program the last stop bit to be 7/8th of a bit in length. stp2: this bit programs the number of stop bits to be trans- mitted. stp2 = 0 one stop bit transmitted. stp2 = 1 two stop bits transmitted. associated i/o pins data is transmitted on the tdx pin and received on the rdx pin. tdx is the alternate function assigned to port l pin l2; it is selected by setting etdx (in the enui register) to one. rdx is an inherent function of port l pin l3, requiring no setup. the baud rate clock for the uart can be generated on-chip, or can be taken from an external source. port l pin l1 (ckx) is the external clock i/o pin. the ckx pin can be either an in- put or an output, as determined by port l configuration and data registers (bit 1). as an input, it accepts a clock signal which may be selected to drive the transmitter and/or re- ceiver. as an output, it presents the internal baud rate gen- erator output. uart operation the uart has two modes of operation; asynchronous mode and synchronous mode. asynchronous mode this mode is selected by resetting the ssel (in the enui register) bit to zero. the input frequency to the uart is 16 times the baud rate. the tsft and tbuf registers double-buffer data for trans- mission. while tsft is shifting out the current character on the tdx pin, the tbuf register may be loaded by software with the next byte to be transmitted. when tsft finishes transmitting the current character the contents of tbuf are transferred to the tsft register and the transmit buffer empty flag (tbmt in the enu register) is set. the tbmt flag is automatically reset by the uart when software loads a new character into the tbuf register. there is also the xmtg bit which is set to indicate that the uart is transmit- ting. this bit gets reset at the end of the last frame (end of last stop bit). tbuf is a read/write register. the rsft and rbuf registers double-buffer data being re- ceived. the uart receiver continually monitors the signal on the rdx pin for a low level to detect the beginning of a start bit. upon sensing this low level, it waits for half a bit time and samples again. if the rdx pin is still low, the re- ceiver considers this to be a valid start bit, and the remaining bits in the character frame are each sampled a single time, at the mid-bit position. serial data input on the rdx pin is shifted into the rsft register. upon receiving the complete character, the contents of the rsft register are copied into the rbuf register and the received buffer full flag (rbfl) is set. rbfl is automatically reset when software reads the character from the rbuf register. rbuf is a read only reg- ister. there is also the rcvg bit which is set high when a framing error occurs and goes low once rdx goes high. tbmt, xmtg, rbfl and rcvg are read only bits. synchronous mode in this mode data is transferred synchronously with the clock. data is transmitted on the rising edge and received on the falling edge of the synchronous clock. this mode is selected by setting ssel bit in the enui regis- ter. the input frequency to the uart is the same as the baud rate. when an external clock input is selected at the ckx pin, data transmit and receive are performed synchronously with this clock through tdx/rdx pins. if data transmit and receive are selected with the ckx pin as clock output, the device generates the synchronous clock output at the ckx pin. the internal baud rate generator is used to produce the synchronous clock. data transmit and receive are performed synchronously with this clock. framing formats the uart supports several serial framing formats ( figure 43 ). the format is selected using control bits in the enu, enur and enui registers. the first format (1, 1a, 1b, 1c) for data transmission (chl0 = 1, chl1 = 0) consists of start bit, seven data bits (excluding parity) and 7/8, one or two stop bits. in applications using parity, the parity bit is generated and verified by hardware. the second format (chl0 = 0, chl1 = 0) consists of one start bit, eight data bits (excluding parity) and 7/8, one or two stop bits. parity bit is generated and verified by hard- ware. the third format for transmission (chl0 = 0, chl1 = 1) con- sists of one start bit, nine data bits and 7/8, one or two stop bits. this format also supports the uart aattentiono fea- ture. when operating in this format, all eight bits of tbuf cop87l88eb/cop87l89eb www.national.com 54
uart operation (continued) and rbuf are used for data. the ninth data bit is transmitted and received using two bits in the enu and enur registers, called xbit9 and rbit9. rbit9 is a read only bit. parity is not generated or verified in this mode. for any of the above framing formats, the last stop bit can be programmed to be 7/8th of a bit in length. if two stop bits are selected and the 7/8th bit is set (selected), the second stop bit will be 7/8th of a bit in length. the parity is enabled/disabled by pen bit located in the enu register. parity is selected for 7-bit and 8-bit modes only. if parity is enabled (pen = 1), the parity selection is then per- formed by psel0 and psel1 bits located in the enu regis- ter. note that the xbit9/psel0 bit located in the enu register serves two mutually exclusive functions. this bit programs the ninth bit for transmission when the uart is operating with nine data bits per frame. there is no parity selection in this framing format. for other framing formats xbit9 is not needed and the bit is psel0 used in conjunction with psel1 to select parity. the frame formats for the receiver differ form the transmitter in the number to stop bits required. the receiver only re- quires one stop bit in a frame, regardless of the setting of the stop bit selection bits in the control register. note that an im- plicit assumption is made for full duplex uart operatioin that the framing formats are the same for the transmitter and receiver. uart interrupts the uart is capable of generating interrupts. interrupts are generated on receive buffer full and transmit buffer empty. both interrupts have individual interrupt vectors. two bytes of program memory space are reserved for each interrupt vector. the two vectors are located at addresses 0xec to 0xef hex in the program memory space. the interrupts can be individually enabled or disabled using enable transmit in- terrupt (eti) and enable receive interrupt (eri) bits in the enui register. the interrupt from the transmitter is set pending, and re- mains pending, as long as both the tbmt and eti bits are ds012871-49 figure 43. framing formats cop87l88eb/cop87l89eb www.national.com 55
uart operation (continued) set. to remove this interrupt, software must either clear the eti bit or write to the tbuf register (thus clearing the tbmt bit). the interrupt from the receiver is set pending, and remains pending, as long as both the rbfl and eri bits are set. to remove this interrupt, software must either clear the eri bit or read from the rbuf register (thus clearing the rbfl bit). baud clock generation the clock inputs to the transmitter and receiver sections of the uart can be individually selected to come either from an external source at the ckx pin (port l, pin l1) or from a source selected in the psr and baud registers. internally, the basic baud clock is created from the oscillator frequency through a two-stage divider chain consisting of a 116 (in- crements of 0.5) prescaler and an 11-bit binary counter. ( fig- ure 44 ). the divide factors are specified through two read/ write registers shown in figure 45 . note that the 11-bit baud rate divisor spills over into the prescaler select register (psr). psr is cleared upon reset. as shown in table 16 , a prescaler factor of 0 corresponds to no clock. no clock condition is the uart power down mode where the uart clock is turned off for power saving purpose. the user must also turn the uart clock off when a different baud rate is chosen. the correspondences between the 5-bit prescaler select and prescaler factors are shown in table 16 . there are many ways to calculate the two divisor factors, but one par- ticularly effective method would be to achieve a 1.8432 mhz frequency coming out of the first stage. the 1.8432 mhz prescaler output is then used to drive the software program- mable baud rate counter to create a x16 clock for the follow- ing baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, 19200 and 38400 ( table 17 ). other baud rates may be created by using appropriate divisors. the x16 clock is then divided by 16 to provide the rate for the serial shift registers of the transmitter and receiver. table 16. prescaler factors prescaler prescaler select factor 00000 no clock 00001 1 00010 1.5 00011 2 00100 2.5 00101 3 00110 3.5 00111 4 01000 4.5 01001 5 01010 5.5 01011 6 01100 6.5 01101 7 01110 7.5 01111 8 10000 8.5 10001 9 10010 9.5 10011 10 10100 10.5 10101 11 10110 11.5 10111 12 11000 12.5 11001 13 11010 13.5 11011 14 11100 14.5 11101 15 11110 15.5 11111 16 ds012871-50 figure 44. uart baud clock generation ds012871-51 figure 45. uart baud clock divisor registers cop87l88eb/cop87l89eb www.national.com 56
baud clock generation (continued) table 17. baud rate divisors (1.8432 mhz prescaler output) baud baud rate rate divisor ?1 (n-1) 110 (110.03) 1046 134.5 (134.58) 855 150 767 300 383 600 191 1200 95 1800 63 2400 47 3600 31 4800 23 7200 15 9600 11 19200 5 38400 2 note 18: the entries in table 17 assume a prescaler output of 1.8432 mhz. in the asynchronous mode the baud rate could be as high as 625k. as an example, considering the asynchronous mode and a cki clock of 4.608 mhz, the prescaler factor selected is: 4.608/1.8432 = 2.5 the 2.5 entry is available in table 16 . the 1.8432 mhz pres- caler output is then used with proper baud rate divisor ( table 2 ) to obtain different baud rates. for a baud rate of 19200 e.g., the entry in table 17 is 5. n?1=5(n?1isthe value from table 17 ) n=6(nisthe baud rate divisor) baud rate = 1.8432 mhz/(16 x 6) = 19200 the divide by 16 is performed because in the asynchronous mode, the input frequency to the uart is 16 times the baud rate. the equation to calculate baud rates is given below. the actual baud rate may be found from: br = fc/(1 6xnxp) where: br is the baud rate fc is the cki frequency n is the baud rate divisior ( table 17 ). p is the prescaler divide factor selected by the value in the prescaler select register ( table 16 ) note: in the synchronous mode, the divisor 16 is replaced by two. example: asynchronous mode: crystal frequenc y=5mhz desired baud rate = 9600 using the above equatio nnxpcanbe calculated first. n x p = (5 x 106)/(16 x 9600) = 32.552 now 32.552 is divided by each prescaler factor ( table 3 )to obtain a value closet to an integer. this factor happens to be 6.5 (p = 6.5). n = 32.552/6.5 = 5.008 (n = 5) the programmed value (from table 4 ) should be 4 (n ?1). using the above values calculated for n and p: br = (5 x 106)/(1 6x5x 6.5) = 9615.384 error = (9615.385 ? 9600)/9600 = 0.16 effect of halt/idle the uart logic is reinitialized when either the halt or idle modes are entered. this reinitialization sets the tbmt flag and resets all read only bits in the uart control and status registers. read/write bits remain unchanged. the transmit buffer (tbuf) is not affected, but the transmit shift register (tsft) bits are set to one. the receiver registers rbuf and rsft are not affected. the device will exit from the halt/idle modes when the start bit of a character is detected at the rdx (l3) pin. this feature is obtained by using the multi-input wakeup scheme provided on the device. before entering the halt or idle modes the user program must select the wakeup source to be on the rxd pin. this selection is done by setting bit 3 of wken (wakeup enable) register. the wakeup trigger condition is then selected to be high to low transition. this is done via the wkedg register. (bit 3 is one.) if the device is halted and crystal oscillator is used, the wakeup signal will not start the chip running immediately be- cause of the finite start up time requirement of the crystal os- cillator. the idle timer (t0) generates a fixed (256 t c ) delay to ensure that the oscillator has indeed stabilized before allow- ing the device to execute code. the user has to consider this delay when data transfer is expected immediately after exit- ing the halt mode. diagnostic bits charl0 and charl1 in the enu register provide a loopback feature for diagnostic testing of the uart. when these bits are set to one, the following occur: the receiver in- put pin (rdx) is internally connected to the transmitter out- put pin (tdx); the output of the transmitter shift register is alooped backo into the receive shift register input. in this mode, data that is transmitted is immediately received. this feature allows the processor to verify the transmit and re- ceive data paths of the uart. note that the framing format for this mode is the nine bit for- mat; one start bit, nine data bits, and 7/8, one or two stop bits. parity is not generated or verified in this mode. attention mode the uart receiver section supports an alternate mode of operation, referred to as attention mode. this mode of operation is selected by the attn bit in the enur register. the data format for transmission must also be selected as having nine data bits and either 7/8, one or two stop bits. cop87l88eb/cop87l89eb www.national.com 57
attention mode (continued) the attention mode of operation is intended for use in networking the device with other processors, typically in such environments the messages consists of device ad- dresses, indicating which of several destinations should re- ceive them, and the actual data. this mode supports a scheme in which addresses are flagged by having the ninth bit of the data field set to a 1. if the ninth bit is reset to a zero the byte is a data byte. while in attention mode, the uart monitors the commu- nication flow, but ignores all characters until an address character is received. upon receiving an address character, the uart signals that the character is ready by setting the rbfl flag, which in turn interrupts the processor if uart re- ceiver interrupts are enabled. the attn bit is also cleared automatically at this point, so that data characters as well as address characters are recognized. software examines the contents of the rbuf and responds by deciding either to ac- cept the subsequent data stream (by leaving the attn bit re- set) or to wait until the next address character is seen (by setting the attn bit again). operation of the uart transmitter is not affected by selec- tion of this mode. the value of the ninth bit to be transmitted is programmed by setting xbit9 appropriately. the value of the ninth bit received is obtained by reading rbit9. since this bit is located in enur register where the error flags re- side, a bit operation on it will reset the error flags. watchdog the device contains a watchdog and clock monitor. the watchdog is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or arunawayo programs. the clock monitor is used to detect the absence of a clock or a very slow clock below a specified rate on the cki pin. the watchdog consists of two independent logic blocks: wd upper and wd lower. wd upper establishes the upper limit on the service window and wd lower defines the lower limit of the service window. servicing the watchdog consists of writing a specific value to a watchdog service register named wdsvr which is memory mapped in the ram. this value is com- posed of three fields, consisting of a 2-bit window select, a 5-bit key data field, and the 1-bit clock monitor select field. table 18 shows the wdsvr register. table 18. watchdog service register window key data clock select monitor x x01100 y bit 7 bit 0 the lower limit of the service window is fixed at 2048 instruc- tion cycles. bits 7 and 6 of the wdsvr register allow the user to pick an upper limit of the service window. table 19 shows the four possible combinations of lower and upper limits for the watchdog service window. this flex- ibility in choosing the watchdog service window prevents any undue burden on the user software. table 19. watchdog service window select wdsvr wdsvr service window bit 7 bit 6 (lower-upper limits) 00 2k8kt c cycles 0 1 2k16k t c cycles 1 0 2k32k t c cycles 1 1 2k64k t c cycles bits 5, 4, 3, 2 and 1 of the wdsvr register represent the 5-bit key data field. the key data is fixed at 01100. bit 0 of the wdsvr register is the clock monitor select bit. clock monitor the clock monitor aboard the device can be selected or de- selected under program control. the clock monitor is guar- anteed not to reject the clock if the instruction cycle clock (1/ t c ) is greater or equal to 10 khz. this equates to a clock input rate on cki of greater or equal to 100 khz. watchdog operation the watchdog and clock monitor are disabled during re- set. the device comes out of reset with the watchdog armed, the watchdog window select (bits 6, 7 of the wdsvr register) set, and the clock monitor bit (bit 0 of the wdsvr register) enabled. thus, a clock monitor error will occur after coming out of reset, if the instruction cycle clock frequency has not reached a minimum specified value, in- cluding the case where the oscillator fails to start. the wdsvr register can be written to only once after reset and the key data (bits 5 through 1 of the wdsvr register) must match to be a valid write. this write to the wdsvr reg- ister involves two irrevocable choices: (i) the selection of the watchdog service window (ii) enabling or disabling of the clock monitor. hence, the first write to wdsvr register in- volves selecting or deselecting the clock monitor, select the watchdog service window and match the watchdog key data. subsequent writes to the wdsvr register will compare the value being written by the user to the watch- dog service window value and the key data (bits 7 through 1) in the wdsvr register. table 20 shows the sequence of events that can occur. the user must service the watchdog at least once before the upper limit of the service window expires. the watch- dog may not be serviced more than once in every lower limit of the service window. the user may service the watchdog as many times as wished in the time period be- tween the lower and upper limits of the service window. the first write to the wdsvr register is also counted as a watchdog service. the watchdog has an output pin associated with it. this is the wdout pin, on pin 1 of the port g. wdout is active low. the wdout pin is in the high impedance state in the in- active state. upon triggering the watchdog, the logic will pull the wdout (g1) pin low for an additonal 16 t c 32 t c cycle after the signal level on wdout pin goes below the lower schmitt trigger threshold. after this delay, the device will stop forcing the wdout output low. the watchdog service window will restart when the wd- out pin goes high. it is recommended that the user tie the wdout pin back to v cc through a resistor in order to pull wdout high. cop87l88eb/cop87l89eb www.national.com 58
watchdog operation (continued) a watchdog service while the wdout signal is active will be ignored. the state of the wdout pin is not guaranteed on reset, but if the powers up low then the watchdog will time out and wdout will enter high impedance state. the clock monitor forces the g1 pin low upon detecting a clock frequency error. the clock monitor error will continue until the clock frequency has reached the minimum specified value, after which the g1 output will enter the high imped- ance tri-state mode following 16 t c 32 t c clock cycles. the clock monitor generates a continual clock monitor error if the oscillator fails to start, or fails to reach the minimum specified frequency. the specification for the clock monitor is as follows: 1/t c > 10 khz e no clock rejection. 1/t c < 10 hz e guaranteed clock rejection. watchdog and clock monitor summary the following salient points regarding the cop888 watch- dog and clock monitor should be noted: both the watchdog and clock monitor detector cir- cuits are inhibited during reset. following reset, the watchdog and clock moni- tor are both enabled, with the watchdog having the maximum service window selected. the watchdog service window and clock monitor enable/disable option can only be changed once, during the initial watchdog service following reset. the initial watchdog service must match the key data value in the watchdog service register wdsvr in or- der to avoid a watchdog error. subsequent watchdog services must match all three data fields in wdsvr in order to avoid watchdog er- rors. the correct key data value cannot be read from the watchdog service register wdsvr. any attempt to read this key data value of 01100 from wdsvr will read as key data value of all 0's. the watchdog detector circuit is inhibited during both the halt and idle modes. the clock monitor detector circuit is active during both the halt and idle modes. consequently, the device in- advertently entering the halt mode will be detected as a clock monitor error (provided that the clock monitor en- able option has been selected by the program). with the single-pin r/c oscillator mask option selected and the clkdly bit reset, the watchdog service win- dow will resume following halt mode from where it left off before entering the halt mode. with the crystal oscillator mask option selected, or with the single-pin r/c oscillator mask option selected and the clkdly bit set, the watchdog service window will be set to its selected value from wdsvr following halt. consequently, the watchdog should not be serviced for at least 2048 instruction cycles following halt, but must be serviced within the selected window to avoid a watchdog error. the idle timer t0 is not initialized with reset. the user can sync in to the idle counter cycle with an idle counter (t0) interrupt or by monitoring the t0pnd flag. the t0pnd flag is set whenever the thirteenth bit of the idle counter toggles (every 4096 instruction cycles). the user is responsible for resetting the t0pnd flag. a hardware watchdog service occurs just as the de- vice exits the idle mode. consequently, the watch- dog should not be serviced for at least 2048 instruction cycles following idle, but must be serviced within the se- lected window to avoid a watchdog error. following reset, the initial watchdog service (where the service window and the clock monitor enable/ disable must be selected) may be programmed any- where within the maximum service window (65,536 in- struction cycles) initialized by reset. note that this initial watchdog service may be programmed within the inti- tial 2048 instruction cycles without causing a watch- dog error. table 20. watchdog service actions key window clock action data data monitor match match match valid service: restart service window don't care mismatch don't care error: generate watchdog output mismatch don't care don't care error: generate watchdog output don't care don't care mismatch error: generate watchdog output cop87l88eb/cop87l89eb www.national.com 59
memory map all ram, ports and registers (except a and pc) are mapped into data memory address space. address contents 0000 to 006f on-chip ram bytes (112 bytes) 0070 to 007f unused ram address space (reads as all ones) 0080 portmd, port m data register 0081 portmc, port m configuration register 0082 portmp, port m input pins (read only) 0083 reserved for port m 0084 mmiwu edge select register (mwkedg) 0085 mmiwu enable register (mwken) 0086 mmiwu pending register (mwkpnd) 0087 reserved for mmiwu 0088 portnd, port n data register 0089 portnc, port n configuration register 008a portnp, port n input pins (read only) 008b portnx, port n alternate function enable 008c to 008f unused ram address space (reads undefined data) 0090 ported, port e data register 0091 portec, port e configuration register 0092 portep, port e input pins (read only) 0093 reserved for port e 0094 portfd, port f data register 0095 portfc, port f configuration register 0096 portfp, port f input pins (read only) 0097 reserved for port f 0098 spicntl, spi control register 0099 spistat, spi status register 009a spirxd, spi current receive data (read only) 009b spitxd, spi transmit data 009c to 009f unused 00a0 txd1, transmit 1 data 00a1 txd2, transmit 2 data 00a2 tdlc, transmit data length code and identifier low 00a3 tid, transmit identifier high 00a4 rxd1, receive data 1 00a5 rxd2, receive data 2 00a6 ridl, receive data length code 00a7 rid, receive identify high address contents 00a8 cscal, can prescaler 00a9 ctim, bus timing register 00aa cbus, bus control register 00ab tcntl, transmit/receive control register 00ac rtstat receive/transmit status register 00ad tec, transmit error count register 00ae rec, receive error count register 00af platst, can bit stream processor test register 00b8 uart transmit buffer (tbuf) 00b9 uart receive buffer (rbuf) 00ba uart control status (enu) 00bb uart receive control status (enur) 00bc uart interrupt and clock (enui) 00bd uart baud register (baud) 00be uart prescaler register (psr) 00bf reserved for uart 00c0 timer t2 lower byte (tmr2lo) 00c1 timer t2 upper byte (tmr2hi) 00c2 timer t2 autoload register t2ra lower byte (t2ralo) 00c3 timer t2 autoload register t2ra upper byte (t2rahi) 00c4 timer t2 autoload register t2rb lower byte (t2rblo) 00c5 timer t2 autoload register t2rb upper byte (t2rbhi) 00c6 timer t2 control register (t2cntrl) 00c7 watchdog service register (reg:wdsvr) 00c8 lmiwu edge select register (lwkedg) 00c9 lmiwu enable register (lwken) 00ca llmiwu pending register (lwkpnd) 00cb a/d converter control register (reg:enad) 00cc a/d converter result register (reg:adrslt) 00cd to 00ce reserved 00cf idle timer control register (reg:itmr) 00d0 portld, port l data register 00d1 portlc, port l configuration register 00d2 portlp, port l input pins (read only) 00d3 reserved for port l 00d4 portgd, port g data register 00d5 portgc, port g configuration register cop87l88eb/cop87l89eb www.national.com 60
memory map (continued) address contents 00d6 portgp, port g input pins (read only) 00d7 port i input pins (read only) 00d8 port cd, port c data register 00d9 port cc, port c configuration register 00da port cp, port c input pins (read only) 00db reserved for port c 00dc port d 00dd to 00df reserved for port d 00e0 to 00e5 reserved for ee control registers 00e6 timer t1 autoload register t1rb lower byte (t1brlo) 00e7 timer t1 autoload register t1rb upper byte (t1brhi) 00e8 icntrl register 00e9 microwire/plus shift register (soir) 00ea timer t1 lower byte (tmr1lo) 00eb timer t1 upper byte (tmr1hi) 00ec timer t1 autoload register t1ra lower byte (t1ralo) 00ed timer t1 autoload register t1ra upper byte (t1rahi) 00ee cntrl, control register 00ef psw, processor status word register 00f0 to 00fb on-chip ram mapped as registers 00fc x register 00fd sp register 00fe b register 00ff s register 0100 to 013f on-chip ram bytes (64 bytes) reading memory locations 0070h007fh will return all ones. reading unused memory locations 00xxh00xxh will return undefined data. addressing modes there are ten addressing modes, six for operand addressing and four for transfer of control. operand addressing modes register indirect this is the anormalo addressing mode. the operand is the data memory addressed by the b pointer or x pointer. register indirect (with auto post increment or decrement of pointer) this addressing mode is used with the ld and x instruc- tions. the operand is the data memory addressed by the b pointer or x pointer. this is a register indirect mode that au- tomatically post increments or decrements the b or x regis- ter after executing the instruction. direct the instruction contains an 8-bit address field that directly points to the data memory for the operand. immediate the instruction contains an 8-bit immediate field as the oper- and. short immediate this addressing mode is used with the load b immediate in- struction. the instruction contains a 4-bit immediate field as the operand. indirect this addressing mode is used with the laid instruction. the contents of the accumulator are used as a partial address (lower 8 bits of pc) for accessing a data operand from the program memory. transfer of control addressing modes relative this mode is used for the jp instruction, with the instruction field being added to the program counter to get the new pro- gram location. jp has a range from ?31 to +32 to allow a 1-byte relatie jump (jp + 1 is implemented by a nop instruc- tion). there are no apageso when using jp, since all 15 bits of pc are used. absolute the mode is used with the jmp and jsr instructions, with the instruction field of 12 bits replacing the lower 12 bits of the program counter (pc). this allows jumping to any loca- tion in the current 4k program memory segment. absolute long this mode is used with the jmpl and jsrl instructions, with the instruction field of 15 bits replacing the entire 15 bits of the program counter (pc). this allows jumping to any loca- tion up to 32k in the program memory space. indirect this mode is used with the jid instruction. the contents of the accumulator are used as a partial address (lower 8 bits of pc) for accessing a location in the program memory. the contents of this program memory location serve as a partial address (lower 8 bits of pc) for the jump to the next instruc- tion. note: the vis is a special case of the indirect transfer of control addressing mode, where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (pc) in order to jump to the associated interrupt ser- vice routine. cop87l88eb/cop87l89eb www.national.com 61
instruction set register and symbol definition registers a 8-bit accumulator register b 8-bit address register x 8-bit address register sp 8-bit stack pointer register pc 15-bit program counter register pu upper 7 bits of pc pl lower 8 bits of pc c 1 bit of psw register for carry hc 1 bit of psw register for half carry gie 1 bit of psw register for global interrupt enable vu interrupt vector upper byte registers vl interrupt vector lower byte symbols [b] memory indirectly addressed by b register [x] memory indirectly addressed by x register md direct addressed memory mem direct addressed memory or [b] meml direct addressed memory or [b] or immediate data imm 8-bit immediate data reg register memory: addresses f0 to ff (includes b, x and sp) bit bit number (0 to 7) ? loaded with ? exchanged with add a,meml add a ? a + meml adc a,meml add with carry a ? a+meml+c,c ? carry, hc ? half carry, subc a,meml subtract with carry a ? a?memi+c,c ? carry, hc ? half carry and a,meml logical and a ? a and meml andsz a,imm logical and immed., skip if zero skip next if (a and imm) = 0 or a,meml logical or a ? a or meml xor a,meml logical exclusive or a ? a xor meml ifeq md,imm if equal compare md and imm, do next if md = imm ifeq a,meml if equal compare a and meml, do next i f a = meml ifne a,meml if not equal compare a and meml, do next if a 1 meml ifgt a,meml if greater than compare a and meml, do next if a > meml ifbne # if b not equal do next if lower 4 bits of b 1 imm drsz reg decrement reg., skip if zero reg ? reg ? 1, skip if reg = 0 sbit #,mem set bit 1 to bit, mem (bi t=0to7 immediate) rbit #,mem reset bit 0 to bit, mem ifbit #,mem if bit if bit in a or mem is true do next instruction rpnd reset pending flag reset software interrupt pending flag x a,mem exchange a with memory a ? mem x a,[x] exchange a with memory [x] a ? [x] ld a,meml load a with memory a ? meml ld a,[x] load a with memory [x] a ? [x] ld b,imm load b with immed. b ? imm ld mem,imm load memory immed. mem ? imm ld reg,imm load register memory immed. reg ? imm x a, [b] exchange a with memory [b] a ? [b], (b ? b1) x a, [x] exchange a with memory [x] a ? [x], (x ? x1) ld a, [b] load a with memory [b] a ? [b], (b ? b1) ld a, [x] load a with memory [x] a ? [x], (x ? x1) ld [b],imm load memory [b] immed. [b] ? imm, (b ? b1) clr a clear a a ? 0 inc a increment a a ? a+1 dec a decrement a a ? a?1 cop87l88eb/cop87l89eb www.national.com 62
instruction set (continued) laid load a indirect from rom a ? rom (pu,a) dcor a decimal correct a a ? bcd correction of a (follows adc, subc) rrc a rotate a right thru c c ? a7 ? ? ? a0 ? c rlc a rotate a left thru c c ? a7 ? ? ? a0 ? c swap a swap nibbles of a a7?a4 ? a3?a0 sc set c c ? 1, hc ? 1 rc reset c c ? 0, hc ? 0 ifc if c if c is true, do next instruction ifnc if not c if c is not true, do next instruction pop a pop the stack into a sp ? sp+1,a ? [sp] push a push a onto the stack [sp] ? a, sp ? sp?1 vis vector to interrupt service routine pu ? [vu], pl ? [vl] jmpl addr. jump absolute long pc ? ii (ii = 15 bits, 0 to 32k) jmp addr. jump absolute pc9?0 ? i (i = 12 bits) jp disp. jump relative short pc ? pc+r(ris?31to +32, except 1) jsrl addr. jump subroutine long [sp] ? pl, [sp?1] ? pu,sp?2, pc ? ii jsr addr. jump subroutine [sp] ? pl, [sp?1] ? pu,sp?2, pc9?0 ? i jid jump indirect pl ? rom (pu,a) ret return from subroutine sp + 2, pl ? [sp], pu ? [sp?1] retsk return and skip sp + 2, pl ? [sp],pu ? [sp?1] reti return from interrupt sp + 2, pl ? [sp],pu ? [sp?1],gie ? 1 intr generate an interrupt [sp] ? pl, [sp?1] ? pu, sp?2, pc ? 0ff nop no operation pc ? pc+1 instruction execution time most instructions are single byte (with immediate addressing mode instructions taking two bytes). most single byte instructions take one cycle time to execute. skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. see the bytes and cycles per instruction table for details. bytes and cycles per instruction the following table shows the number of bytes and cycles for each instruction in the format of byte/cycle. arithmetic and logic instructions [b] direct immed. add 1/1 3/4 2/2 adc 1/1 3/4 2/2 subc 1/1 3/4 2/2 and 1/1 3/4 2/2 or 1/1 3/4 2/2 xor 1/1 3/4 2/2 ifeq 1/1 3/4 2/2 ifgt 1/1 3/4 2/2 ifbne 1/1 drsz 1/3 sbit 1/1 3/4 rbit 1/1 3/4 ifbit 1/1 3/4 rpnd 1/1 cop87l88eb/cop87l89eb www.national.com 63
instruction set (continued) instructions using a and c clra 1/1 inca 1/1 deca 1/1 laid 1/3 dcora 1/1 rrca 1/1 rlca 1/1 swapa 1/1 sc 1/1 rc 1/1 ifc 1/1 ifnc 1/1 pusha 1/3 popa 1/3 andsz 2/2 transfer of control instructions jmpl 3/4 jmp 2/3 jp 1/3 jsrl 3/5 jsr 2/5 jid 1/3 vis 1/5 ret 1/5 retsk 1/5 reti 1/5 intr 1/7 nop 1/1 memory transfer instructions register register indirect indirect direct immed. auto incr. and decr. [b] [x] [x+, x?] x a, (note 19) 1/1 1/3 2/3 1/2 1/3 ld a, (note 19) 1/1 1/3 2/3 2/2 1/2 1/3 ld b, imm 1/1 (if b < 16) ld b, imm 2/3 (if b > 15) ld mem, imm 2/2 3/3 2/2 ld reg, imm 2/3 ifeq md, imm 3/3 note 19: = > memory location addressed by b or x or directly. cop87l88eb/cop87l89eb www.national.com 64
instruction set (continued) cop888 family opcode table upper nibble f e d c ba9 876 5 4 3 2 10 lower nibble jp?15 jp?31 ld 0f0, #i drsz 0f0 rrca rc adc a, #i adc a, [b] ifbit 0, [b] andsz a, #i ld b, #0f ifbne 0 jsr x000x0ff jmp x000x0ff jp+17 intr 0 jp?14 jp?30 ld 0f1, #i drsz 0f1 * sc subc a, #i subc a, [b] ifbit 1, [b] *ldb, #0e ifbne 1 jsr x100x1ff jmp x100x1ff jp+18 jp+2 1 jp?13 jp?29 ld 0f2, #i drsz 0f2 x a,[x+] x a,[b+] ifeq a,#i ifeq a,[b] ifbit 2,[b] *ld b,#0d ifbne 2 jsr x200x2ff jmp x200x2ff jp+19 jp+3 2 jp?12 jp?28 ld 0f3, #i drsz 0f3 x a,[x?] x a,[b?] ifgt a,#i ifgt a,[b] ifbit 3,[b] *ld b,#0c ifbne 3 jsr x300x3ff jmp x300x3ff jp+20 jp+4 3 jp?11 jp?27 ld 0f4, #i drsz 0f4 vis laid add a,#i add a,[b] ifbit 4,[b] clra ld b,#0b ifbne 4 jsr x400x4ff jmp x400x4ff jp+21 jp+5 4 jp?10 jp?26 ld 0f5, #i drsz 0f5 rpnd jid and a,#i and a,[b] ifbit 5,[b] swapa ld b,#0a ifbne 5 jsr x500x5ff jmp x500x5ff jp+22 jp+6 5 jp?9 jp?25 ld 0f6, #i drsz 0f6 x a,[x] x a,[b] xor a,#i xor a,[b] ifbit 6,[b] dcora ld b,#09 ifbne 6 jsr x600x6ff jmp x600x6ff jp+23 jp+7 6 jp?8 jp?24 ld 0f7, #i drsz 0f7 * * or a,#i or a,[b] ifbit 7,[b] pusha ld b,#08 ifbne 7 jsr x700x7ff jmp x700x7ff jp+24 jp+8 7 jp?7 jp?23 ld 0f8, #i drsz 0f8 nop rlca ld a,#i ifc sbit 0,[b] rbit 0,[b] ld b,#07 ifbne 8 jsr x800x8ff jmp x800x8ff jp+25 jp+9 8 jp?6 jp?22 ld 0f9, #i drsz 0f9 ifne a,[b] ifeq md,#i ifne a,#i ifnc sbit 1,[b] rbit 1,[b] ld b,#06 ifbne 9 jsr x900x9ff jmp x900x9ff jp+26 jp+10 9 jp?5 jp?21 ld 0fa, #i drsz 0fa ld a,[x+] ld a,[b+] ld [b+],#i inca sbit 2,[b] rbit 2,[b] ld b,#05 ifbne 0a jsr xa00xaff jmp xa00xaff jp+27 jp+11 a jp?4 jp?20 ld 0fb, #i drsz 0fb ld a,[x?] ld a,[b?] ld [b?],#i deca sbit 3,[b] rbit 3,[b] ld b,#04 ifbne 0b jsr xb00xbff jmp xb00xbff jp+28 jp+12 b jp?3 jp?19 ld 0fc, #i drsz 0fc ld md,#i jmpl x a,md popa sbit 4,[b] rbit 4,[b] ld b,#03 ifbne 0c jsr xc00xcff jmp xc00xcff jp+29 jp+13 c jp?2 jp?18 ld 0fd, #i drsz 0fd dir jsrl ld a,md retsk sbit 5,[b] rbit 5,[b] ld b,#02 ifbne 0d jsr xd00xdff jmp xd00xdff jp+30 jp+14 d jp?1 jp?17 ld 0fe, #i drsz 0fe ld a,[x] ld a,[b] ld [b],#i ret sbit 6,[b] rbit 6,[b] ld b,#01 ifbne 0e jsr xe00xeff jmp xe00xeff jp+31 jp+15 e jp?0 jp?16 ld 0ff, #i drsz 0ff * * ld b,#i reti sbit 7,[b] rbit 7,[b] ld b,#00 ifbne 0f jsr xf00xfff jmp xf00xfff jp+32 jp+16 f where, i is the immediate data md is a directly addressed memory location * is an unused opcode the opcode 60 hex is also the opcode for ifbit #i,a cop87l88eb/cop87l89eb www.national.com 65
mask options the cop684e and cop884eb mask programmable options are shown below. the options are programmed at the same time as the rom pattern submission. option 1: clock configuration = 1 crystal oscillator (cki/10) g7 (cko) is clock generator output to crystal/ resonator cki is the clock input option 2: halt = 1 enable halt mode option 3: bonding options = 1 68-pin plcc = 2 44-pin plcc the chip can be driven by a clock input on the cki input pin which can be between dc and 10 mhz. the cko output clock is on pin g7. the cki input frequency is divided down by 10 to produce the instruction cycle clock (1/t c ). development support summary icemaster ? : im-cop8/400 e full feature in-circuit emulation for all cop8 products. a full set of cop8 basic and feature family device and package specific probes are available. cop8 debug module: moderate cost in-circuit emulation and development programming unit. cop8 evaluation and programming unit: epu- cop888gg e low cost in-circuit simulation and develop- ment programming unit. assembler: cop8-dev-ibma. a dos installable cross development assembler, linker, librarian and utility soft- ware development tool kit. c compiler: cop8c. a dos installable cross develop- ment software tool kit. otp/eprom programmer support: covering needs from engineering prototype, pilot production to full pro- duction environments. icemaster (im) in-circuit emulation the icemaster im-cop8/400 is a full feature, pc based, in-circuit emulation tool development and marketed by met- alink corporation to support the whole cop8 family of prod- ucts. national is a resale vendor for these products. see figure 46 for configuration. the icemaster im-cop8/400 with its device specific cop8 probe provides a rich feature set for developing, test- ing and maintaining product: real-time in-circuit emulation; full 2.4v5.5v operation range, full dc-10 mhz clock. chip options are program- mable or jumper selectable. direct connection to application board by package com- patible socket or surface mount assembly. full 32-kbyte of loadable programming space that over- lays (replaces) the on-chip rom or eprom. on-chip ram and i/o blocks are used directly or recreated on the probe as necessary. full 4k frame synchronous trace memory. address, in- struction, and eight unspecified, circuit connectable trace lines. display can be hll source (e.g., c source), as- sembly or mixed. a full 64k hardware configurable break, trace on, trace off control, and pass count increment events. tool set integrated interactive symbolic debugger e supports both assembler (coff) and c compiler (.cod) linked object formats. real time performance profiling analysis; selectable bucket definition. watch windows, content updated automatically at each execution break. instruction by instruction memory/register changes dis- played on source window when in single step operation. single base unit and debugger software reconfigurable to support the entire cop8 family; only the probe personal- ity needs to change. debugger software is processor customized, and reconfigured from a master model file. processor specific symbolic display of registers and bit level assignments, configured from master model file. halt/idle mode notification. on-line help customized to specific processor using master model file. includes a copy of cop8-dev-ibma assembler and linker sdk. im order-information base unit im-cop8/400-1 icemaster base unit, 110v power supply im-cop8/400-2 icemaster base unit, 220v power supply icemaster probe mhw-888eb44pwpc 44 plcc mhw-888eb68pwpc 68 plcc cop87l88eb/cop87l89eb www.national.com 66
development support (continued) icemaster debug module (dm) the icemaster debug module is a pc based, combination in-circuit emulation tool and cop8 based otp/eprom pro- gramming tool developed and marketed by metalink corpo- ration to support the whole cop8 family of products. na- tional is a resale vendor for these products. see figure 47 for configuration. the icemaster debug module is a moderate cost develop- ment tool. it has the capability of in-circuit emulation for a specific cop8 microcontroller and in addition serves as a programming tool for cop8 otp and eprom product fami- lies. summary of features is as follows: real-time in-circuit emulation; full operating voltage range operation, full dc-10 mhz clock. all processor i/o pins can be cabled to an application de- velopment board with package compatible cable to socket and surface mount assembly. full 32 kbyte of loadable programming space that over- lays (replaces) the on-chip rom or eprom. on-chip ram and i/o blocks are used directly or recreated as necessary. 100 frames of synchronous trace memory. the display can be hll source (c source), assembly or mixed. the most recent history prior to a break is available in the trace memory. configured break points; uses intr instruction which is modestly intrusive. software e only supported features are selectable. tool set integrated interactive symbolic debugger e supports both assembler (coff) and c compiler (.cod) sdk linked object formats. instruction by instruction memory/register changes dis- played when in single step operation. debugger software is processor customized, and recon- figured from a master model file. processor specific symbolic display of registers and bit level assignments, configured from master model file. halt/idle mode notification. programming menu supports full product line of program- mable otp and eprom cop8 products. program data is taken directly from the overlay ram. programming of 44 plcc and 68 plcc parts requires external programming adapters. includes wallmount power supply. on-board vpp generator from 5v input or connection to external supply supported. requires vpp level adjust- ment per the family programming specification (correct level is provided on an on-screen pop-down display). on-line help customized to specific processor using master model file. includes a copy of cop8-dev-ibma assembler and linker sdk. dm order-information debug module unit cop8-dm/888eb cable adapters dm-cop8/44p 44 plcc dm-cop8/68p 68 plcc please contact local sales office for ordering information of programming adapter. ds012871-52 figure 46. cop8 icemaster environment cop87l88eb/cop87l89eb www.national.com 67
development support (continued) cop8 assembler/linker software development tool kit national semiconductor offers a relocatable cop8 macro cross assembler, linker, librarian and utility software develop- ment tool kit. features are summarized as follows: basic and feature family instruction set by adeviceo type. nested macro capability. extensive set of assembler directives. supported on pc/dos platform. generates national standard coff output files. integrated linker and librarian. integrated utilities to generate rom code file outputs. dumpcoff utility. this product is integrated as a part of metalink tools as a de- velopment kit, fully supported by the metalink debugger. it may be ordered separately or it is bundled with the metalink products at no additional cost. order information assembler sdk: cop8-dev-ibma assembler sdk on installable 3.5" pc/dos floppy disk drive format. periodic upgrades and most recent version is available on national's bbs and internet. cop8 c compiler a c compiler is developed and marketed by byte craft lim- ited. the cop8c compiler is a fully integrated development tool specifically designed to support the compact embedded configuration of the cop8 family of products. features are summarized as follows: ansi c with some restrictions and extensions that opti- mize development for the cop8 embedded application. bits data type extension. register declaration #pragma with direct bit level definitions. c language support for interrupt routines. expert system, rule based code generation and optimiza- tion. performs consistency checks against the architectural definitions of the target cop8 device. generates program memory code. supports linking of compiled object or cop8 assembled object formats. global optiomization of linked code. symbolic debug load format fully source level supported by the metalink debugger. single chip otp/emulator support the cop8 family is supported by single chip otp emulators. for detailed information refer to the emulator specific datasheet and the emulator selection table below: otp emulator ordering information device number clock package emulates option cop87l88eb-xe crystal 44 plcc cop888eb COP87L89EB-XE crystal 68 plcc cop889eb industry wide otp/eprom programming support programming support, in addition to the metalink develop- ment tools, is provided by a full range of independent ap- proved vendors to meet the needs from the engineering laboratory to full production. ds012871-53 figure 47. cop8-dm environment cop87l88eb/cop87l89eb www.national.com 68
development support (continued) approved list manufacturer north europe asia america bp (800) 225-2102 +49-8152-4183 +852-234-16611 microsystems (713) 688-4600 +49-8856-932616 +852-2710-8121 fax: (713) 688-0920 data i/o (800) 426-1045 +44-0734-440011 call (206) 881-6444 north america fax: (206) 882-1043 hilo (510) 623-8860 call asia +886-2-764-0215 fax: +886-2-756-6403 ice (800) 624-8949 +44-1226-767404 technology (919) 430-7915 fax: 0-1226-370-434 metalink (800) 638-2423 +49-80 9156 96-0 +852-737-1800 (602) 926-0797 fax: +49-80 9123 86 fax: (602) 693-0681 systems (408) 263-6667 +41-1-9450300 +886-2-917-3005 general fax: +886-2-911-1283 needhams (916) 924-8037 fax: (916) 924-8065 available literature for more information, please see the cop8 basic family user's manual, literature number 620895, cop8 feature family user's manual, literature number 620897 and na- tional's family of 8-bit microcontrollers cop8 selection guide, literature number 630006. dial-a-helper service dial-a-helper is a service provided by the microcontroller applications group. the dial-a-helper is an electronic infor- mation system that may be accessed as a bulletin board system (bbs) via data modem, as an ftp site on the inter- net via standard ftp client application or as an ftp site on the internet using a standard internet browser such as netscape or mosaic. the dial-a-helper system provides access to an automated information storage and retrieval system. the system capa- bilities include a message section (electronic mail, when accessed as a bbs) for communications to and from the microcontroller applications group and a file section which consists of several file areas where valuable applica- tion software and utilities could be found. dial-a-helper bbs via a standard modem modem: canada/u.s.: (800) nsc-micro (800) 672-6427 europe: (+49) 0-814-135 13 32 baud: 14.4k set-up: length: 8-bit parity: none stop bit: 1 operation: 24 hrs., 7 days dial-a-helper via ftp ftp nscmicro.nsc.com user: anonymous password: username @ yourhost.site.domain dial-a-helper via a worldwide web browser ftp://nscmicro.nsc.com national semiconductor on the worldwide web see us on the worldwide web at: http://www.national.com cop87l88eb/cop87l89eb www.national.com 69
development support (continued) customer response center complete product information and technical support is avail- able from national's customer response centers. canada/u.s.: tel: (800) 272-9959 email: support @ tevm2.nsc.com europe: email: europe.support @ nsc.com deutsch tel: +49 (0) 180-530 85 85 english tel: +49 (0) 180-532 78 32 japan: tel: +81-043-299-2309 s.e. asia: beijing tel: (+86) 10-6856-8601 shanghai tel: (+86) 21-6415-4092 hong kong tel: (+852) 2737-1600 korea tel: (+82) 2-3771-6909 malaysia tel: (+60-4) 644-9061 singapore tel: (+65) 255-2226 taiwan tel: +886-2-521-3288 australia: tel: (+61) 3-9558-9999 india: tel: (+91) 80-559-9467 cop87l88eb/cop87l89eb www.national.com 70
physical dimensions inches (millimeters) unless otherwise noted 44-lead molded plastic leaded chip carrier order number cop87l88ebv-xe ns plastic chip package number v44a 68-lead molded plastic leaded chip carrier order number cop87l89ebv-xe ns plastic chip package number v68a cop87l88eb/cop87l89eb www.national.com 71
notes life support policy national's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. national semiconductor corporation americas tel: 1-800-272-9959 fax: 1-800-737-7018 email: support@nsc.com national semiconductor europe fax: +49 (0) 1 80-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 1 80-530 85 85 english tel: +49 (0) 1 80-532 78 32 fran?ais tel: +49 (0) 1 80-532 93 58 italiano tel: +49 (0) 1 80-534 16 80 national semiconductor asia pacific customer response group tel: 65-2544466 fax: 65-2504466 email: sea.support@nsc.com national semiconductor japan ltd. tel: 81-3-5639-7560 fax: 81-3-5639-7507 www.national.com cop87l88eb/cop87l89eb 8-bit one time programmable (otp) microcontroller with can interface, a/d and uart national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the righ t at any time without notice to change said circuitry and specifications.

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