this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number fo r guaranteed specific ation limits. 1 www.visha y .com v ishay siliconix spice device model SUD25N15-52 document number: 70553 s-60409 ? n-channel 150-v (d-s) 175 mosfet characteristics ? n-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and switching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the typical electrical characteristics of the n-channel ve rtical dmos. the subcircuit model is extracted and optimized over the ? 55 to 125 c temperature ranges under the puls ed 0-v to 10-v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capac itance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched c gd model. all model parameter values are optimized to provide a best fit to the m easured electrical data and are not intended as an exact physical interpretation of the device. subcircuit model schematic
2 v ishay siliconix spice device model SUD25N15-52 www.visha y .com document number: 70553 s-60409 ? c unless otherwise noted) parameter symbol test condition simulated data measured data unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 3 v on-state drain current a i d(on) v ds = 5 v, v gs = 10 v 124 a v gs = 10 v, i d = 5 a 0.040 0.042 v gs = 10 v, i d = 5 a, t j = 125 c 0.070 v gs = 10 v, i d = 5 a, t j = 175 c 0.086 drain-source on-state resistance a r ds(on) v gs = 6 v, i d = 5 a 0.047 0.047 ? forward voltage a v sd i s = 15 a, v gs = 0 v 0.89 0.90 v dynamic b input capacitance c iss 1695 1725 output capacitance c oss 231 216 reverse transfe r capacitance c rss v gs = 0 v, v ds = 25 v, f = 1 mhz 101 100 pf total gate charge c q g 34 33 gate-source charge c q gs 9 9 gate-drain charge c q gd v ds = 75 v, v gs = 10 v, i d = 25 a 12 12 nc turn-on delay time c t d(on) 33 15 rise time c t r 40 70 turn-off delay time c t d(off) 55 25 fall time c t f v dd = 50 v, r l = 3 ? i d ? 25 a, v gen = 10 v, r g = 2.5 ? 60 60 source-drain reverse recovery time t rr i f = 25 a, di/dt = 100 a/ s 69 95 ns notes a. pulse test; pulse width 300 s, duty cycle 2%. b. guaranteed by design, not s ubject to production testing. c. independent of operat ing temperature.
3 v ishay siliconix spice device model SUD25N15-52 www.visha y .com document number: 70553 s-60409 ? c unless otherwise noted)
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