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s3c821a/p821a product overview 1 - 1 1 product overview s3c8-series microcontrolles samsung's s3c8 series of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. among the major cpu features ar e: ? efficient register-oriented architecture ? selectable cpu clock sources ? idle and stop power-down mode release by interrupt ? built-in basic timer with watchdog function a sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum of six cpu clocks) can be assigned to specific interrupt levels. s3c821a/p821a microcontroller the s3c821a/p821a single-chip cmos microcontroller is fabricated using the highly advanced cmos process, based on samsung?s newest cpu architecture . the s3c821a is a microcontroller with a 48-kbyte mask-programmable rom embedded. the S3P821A is a microcontroller with a 48-kbyte one-time-programmable rom embedded. using a proven modular design approach, samsung engineers have successfully developed the s3c821a/p821a by integrating the following peripheral modules with the powerful sam8 core : ? six programmable i/o ports, including five 8-bit ports and one 7-bit port, for a total of 47 pins. ? twelve bit-programmable pins for external interrupts. ? one 8-bit basic timer for oscillation stabilization and watchdog functions (system reset) . ? one 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. ? watch timer for real time. ? 4-input a/d converter ? serial i/o interface the s3c821a/p821a is versatile microcontroller for cordless phone, pager, etc. they are currently available in 80-pin tqfp and 80-pin qfp package. otp the S3P821A is an otp (one time programmable) version of the s3c821a microcontroller. the S3P821A microcontroller has an on-chip 48-kbyte one-time-programmable eprom instead of a masked rom. the S3P821A is comparable to the s3c821a, both in function and in pin configuration.
product overview s3c821a/p821a 1 - 2 feature s cpu ? sam8 cpu core memory ? data memory: 1040- byte of internal register file (excluding lcd ram) ? program memory: 48 -kbyte internal program memory (rom ) external interface ? 64-kbyte external data memory area instruction execution time ? 750 n s at 8 mhz (minimum, main oscillator) ? 183 m s at 32,768 hz (minimum, sub oscillator) interrupts ? 7 interrupt levels and 19 interrupt sources ? 19 vectors ? fast interrupt processing feature (for one selected interrupt level) i/o ports ? five 8-bit i/o ports (p0?p4) and one 7-bit i/o port (p5) for a total of 47 bit-programmable pins 8-bit basic timer ? one p rogrammable 8-bit basic timer (bt) for oscillation stabilization control or watchdog timer (software reset) function watch timer ? time internal generation: 3.91 ms, 0.5 s at 32,768 hz ? four frequency outputs to buz pin ? clock source generation for lcd timer s and timer/counters ? one 8-bit timer/counter (timer 0) with three operating modes: interval, capture, and pwm ? one 16-bit timer/counter (timer 1) with two 8-bit timer/counter modes lcd controller/driver ? up to 32 segment pins ? 3, 4, and 8 common selectable ? choice of duty cycle ? all dots can be switched on/off ? internal resistor circuit for lcd bias serial port ? one synchronous sio a/d converter ? 8-bit conversion resolution 4 channel ? 34 m s conversion time (4 mhz cpu clock, fxx/4) oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal or external oscillator for subsystem clock ? main system clock frequency: 8 mhz ? subsystem clock frequency: 32.768 khz power-down modes ? main idle mode (only cpu clock stops) ? sub idle mode ? stop mode (main/sub system oscillation stops) operating temperature range ? ? 4 0 c to + 85 c operating voltage range ? 2.0 v to 5.5 v at 32 khz (sub clock)-6 mhz (main clock) ? 2.2 v to 5.5 v at 8 mhz package type ? 80-pin tqfp, 80-pin qfp
s3c821a/p821a produc t overview 1 - 3 block diagram i/o port and interrupt control sam8 cpu internal bus port 3 48 -kb rom 1-k byte register file port 0 p1.0-p1.7 port 1 timer 0 sio port 4 p0.0-p0.7 lcd driver com0-com3 seg0-seg3/ com4 - c om7 seg4 - seg31 vlc1 t1ck ta tb buz sck si so watch timer reset main osc sub osc timer 1 a and b a/d converter port 5 p2.0-p2.7 port 2 p3.0-p3.7 p4.0-p4.7 p5.0-p5.6 v dd 1 (internal) v ss 1 (internal) v dd 2 (external) v ss 2 (external) adc0 - adc3 a v ss a v ref t0ck t0/t0cap/ t0pwm x in x o ut x in x o ut figure 1-1. s3c821a simplified block diagram
product overview s3c821a/p821a 1 - 4 pin assignments p1.1/seg25/ad1 p1.2/seg26/ad2 p1.3/seg27/ad3 p1.4/seg28/ad4 p1.5/seg29/ad5 p1.6/seg30/ad6 p1.7/seg31/ad7 p2.0/ as p2.1/ dr v dd1 (int) v ss1 x out x in test xt in xt out reset p2.2/ dw p2.3/ dm p2.4/int0/t0ck s3c821a (80-tqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 65 64 63 62 61 60 p2.5/int1/t1ck p2.6/int2/ta p2.7/int3/tb av ref p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3/adc3 av ss p3.4 p3.5 p3.6 p3.7/t0/t0pwm/t0cap p4.0/int4 p4.1/int5 p4.2/int6 p4.3/int7 p4.4/int8 p4.5/int9 p4.6/int10 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 seg4 seg3/com7 seg2/com6 seg1/com5 seg0/com4 com3 com2 com1 com0 v dd2 (ext) v ss2 v lc1 p5.6 p5.5 p5.4 p5.3/buz p5.2/so p5.1/si p5.0/sck p4.7/int11 p1.0/seg24/ad0 p0.7/seg23/a15 p0.6/seg22/a14 p0.5/seg21/a13 p0.4/seg20/a12 p0.3/seg19/a11 p0.2/seg18/a10 p0.1/seg17/a9 p0.0/seg16/a8 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 figure 1-2. s3c821a pin assignments (80-tqfp-1212)
s3c821a/p821a produc t overview 1 - 5 p0.6/seg22/a14 p0.5/seg21/a13 p0.4/seg20/a12 p0.3/seg19/a11 p0.2/seg18/a10 p0.1/seg17/a9 p0.0/seg16/a8 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 p0.7/seg23/a15 p1.0/seg24/ad0 p1.1/seg25/ad1 p1.2/seg26/ad2 p1.3/seg27/ad3 p1.4/seg28/ad4 p1.5/seg29/ad5 p1.6/seg30/ad6 p1.7/seg31/ad7 p2.0/ as p2.1/ dr v dd1 (int) v ss1 x out x in test xt in xt out reset p2.2/ dw p2.3/ dm p2.4/int0/t0ck p2.5/int1/t1ck p2.6/int2/ta s3c821a (80-qfp) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p2.7/int3/tb av ref p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3/adc3 av ss p3.4 p3.5 p3.6 p3.7/t0/t0pwm/t0cap p4.0/int4 p4.1/int5 p4.2/int6 p4.3/int7 p4.4/int8 seg6 seg5 seg4 seg3/com7 seg2/com6 seg1/com5 seg0/com4 com3 com2 com1 com0 v dd2 (ext) v ss2 v lc1 p5.6 p5.5 p5.4 p5.3/buz p5.2/so p5.1/si p5.0/sck p4.7/int11 p4.6/int10 p4.5/int9 figure 1-3. s3c821a pin assignments (80-qfp-1420c)
product overview s3c821a/p821a 1 - 6 pin descriptions table 1 - 1. s3c821a pin descriptions pin names pin type pin description circuit type pin numbers (note) share pins p0.0 ?p0.7 i/o 4-bit -programmable i/o port . pull-up resistors and open-drain outputs are software assignable . pull-up resistors are automatically disabled for output pins . configurable as lcd segments/ external interface address and data lines h-32 72?79 (74-80, 1) seg16/a8 ? seg23/a15 p1.0 ?1.7 i /o 4-bit -programmable i/o port . pull-up resistors and open-drain outputs are software assignable . pull-up resistors are automatically disabled for output pins . configurable as lcd segments/ external interface address and data lines h-32 80, 1?7 (2-9) seg24/ad0 ? seg31/ad7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2. 7 i/o 1-b it-programmable i/o port . pull-up resistors are software assignable , and automatically disabled for output pins . p2.0?p2.3 can alternately be used as external interface lines. p2.4?p2.7 are configurable as alternate functions or external interrupts at falling edge with noise filters. d-4 8 (10) 9 (11) 18 (20) 19 (21) 20 (22) 21 (23) 22 (24) 23 (25) as dr dw dm int0/t0ck int1/t1ck int2/ta int3/tb p 3 .0 ?p3.3 p3.4?p3.6 p3.7 i/o 1-b it-programmable i/o port . pull-up resistors are software assignable , and automatically disabled for output pins . p3.0?p3.3 can alternately be used as adc. p3.7 is configurable as an alternate function. f-16 d-4 d-4 25?28 (27?30) 30?32 (32?34) 33 (35) adc0?adc3 t0/t0pwm/ t0cap p 4 .0 ? p 4 . 7 i/o 1-b it-programmable i/o port . pull-up resistors and open-drain outputs are software assignable . pull-up resistors are automatically disabled for output pins . p4.0?p4.7 are configurable as external interrupts at a selectable edge with noise filters. e-4 34?41 (36?43) int4?int11 p 5 .0 p5.1 p5.2 p5.3 p5.4?p5.6 i/o 1-b it-programmable i/o port . pull-up resistors are software assignable , and automatically disabled for output pins . p5.0?p5.3 are configurable as alternate functions. if sck and si are used as input, these pins have noise filters. d-4 42 (44) 43 (45) 44 (46) 45 (47) 46?48 (48?50) sck si so buz note: parentheses indicate pin number for 80-qfp package.
s3c821a/p821a produc t overview 1 - 7 table 1 - 1. s3c821a pin descriptions (continued) pin names pin type pin description circuit type pin numbers (note) share pins v ss1 , v dd1 ? power input pins for internal power block ? 10, 11 (12, 13) ? x out , x in ? main oscillator pins ? 12, 13 (14, 15) ? test ? chip test input pin hold gnd when the device is operating ? 14 (16) ? xt in , xt out ? sub oscillator pins for sub-system clock ? 15, 16 (17,18) ? reset i reset signal input pin. schmitt trigger input with internal pull-up resistor. b 17 (19) ? int0?int3 i/o external interrupts input with noise filter. d-4 20?23 (22?25) p2.4?p2.7 t0ck i/o 8bit timer 0 external clock input. d-4 20 (22) p2.4 t1ck i/o timer 1/a external clock input. d-4 21 (23) p2.5 ta i/o timer 1/a clock output d-4 22 (24) p2.6 tb i/o timer b clock output d-4 23 (25) p2.7 t0 i/o timer 0 clock output d-4 33 (35) p3.7 t0pwm i/o timer 0 pwm output d-4 33 (35) p3.7 t0cap i/o timer 0 capture input d-4 33 (35) p3.7 adc0?adc3 i/o analog input pins for a/d converts module f-16 25?28 (27?30) p3.0?p3.3 av ref , av ss ? a/d converter reference voltage and ground ? 24, 29 (26, 31) ? int4?int11 i/o external interrupts input with noise filter. e-4 34?41 (36?43) p4.0?p4.7 buz i/o buzzer signal output d-4 45 (47) p5.3 sck, si, so i/o serial clock, serial data input, serial data output d-4 42?44 (44?46) p5.0?p5.2 v lc1 ? lcd bias voltage input pins ? 49 (51) ? v ss2 , v dd2 ? power input pins for external power block ? 50, 51 (52, 53) ? com0?com3 o lcd common signal output h-30 52?55 (54?57) ? seg0?seg3 (com4?com7) o lcd common or segment signal output h-31 56?59 (58?61) ? seg4?seg15 o lcd segment signal output h-29 60?71 (62?73) ? note: parentheses indicate pin number for 80-qfp package.
product overview s3c821a/p821a 1 - 8 table 1 - 1. s3c821a pin descriptions (continued) pin names pin type pin description circuit type pin numbers share pins seg16? seg23 i/o lcd segment signal output h-32 72?79 (74?80, 1) p0.0?p0.7 seg24? seg31 i/o lcd segment signal output h-32 80, 1?7 (2?9) p1.0?p1.7 a8?a15 i/o external interface address lines h-32 72?79 (74?80, 1) p0.0?p0.7 ad0?ad7 i/o external interface address/data lines h-32 80, 1?7 (2?9) p1.0?p1.7 as i/o address strobe d-4 8 (10) p2.0 dr i/o data read d-4 9 (11) p2.1 dw i/o data write d-4 18 (20) p2.2 dm i/o data memory select d-4 19 (21) p2.3 note: parentheses indicate pin number for 80-qfp package.
s3c821a/p821a produc t overview 1 - 9 pin circuits v dd p - channel n - channel in put figure 1- 4 . pin circuit type a pull-up resistor reset noise filter v dd figure 1- 5 . pin circuit type b output v ss data output disable v dd figure 1- 6 . pin circuit type c pull-up enable data output disable schmitt triger i/o v dd circuit type c figure 1- 7 . pin circuit type d-4
product overview s3c821a/p821a 1 - 10 pull-up resistor v dd i/o v ss open-drain en pull-up enable output disable v dd data figure 1 -8 . pin circuit type e-4 pull-up enable data output disable i/o v dd circuit type c data aden adselect t0 adc figure 1 -9 . pin circuit type f-16
s3c821a/p821a produc t overview 1 - 11 v lc1 v lc3 v ss v lc4 output figure 1 - 1 0. pin circuit type h-29 v lc1 v lc2 v ss v lc5 output figure 1-1 1. pin circuit type h-30 v lc1 v lc2 output v lc3 v lc4 v lc5 v ss figure 1-1 2. pin circuit type h-31
product overview s3c821a/p821a 1 - 12 pull-up resistor v dd i/o pull-up enable v ss output disable v dd data seg circuit type h-29 lcd out en open-drain en figure 1-1 3. pin circuit type h-32
s3c821a/p821a address spaces 2- 1 2 address spaces overview the s3c821a microcontroller has three types of address space: ? internal program memory (rom) ? internal register file ? external data memory a 16-bit address bus supports program memory operations. a separate 8- bit register bus carries addresses and data between the cpu and the register file . the s3c821a has an internal 48 -kbyte mask-programmable rom. an external data memory interface is implemented. the 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing modes. a 32-byte lcd display register file is implemented. the re are 1,125 mapped registers in the internal register file. of these, 1,040 are for general-purpose. (this number includes a 16-byte working register common area used as a ?scratch area? for data operations, four 192- byte prime register areas, and four 64-byte areas (set 2)). nineteen 8-bit registers are used for the cpu and the system control , and 34 registers are mapped for peripheral controls and data registers. eleven register locations are not mapped.
address spaces s3c821a/p821a 2- 2 program memory (rom ) program memory (rom) stores program code s or table data. the s3c821a has 48 k byte s of internal mask- programmable program memory. the program memory address range is therefore 0h ?b fffh (see figure 2-1). the first 256 bytes of the rom (0h ? 0ffh) are reserved for interrupt vector addresses. unused locations in this address range can be used as normal program memory. if you use the vector address area to store a program code, be careful not to overwrite the vector addresses stored in these locations. the rom address at which a program execution starts after a reset is 0100h. (decimal) (hex) b fffh 49,151 0 0h interrupt vector area 48 -kbyte internal program memory 255 0ffh figure 2-1. program memory address space
s3c821a/p821a address spaces 2- 3 register architecture in the s3c821a implementation, the upper 64-byte area of register files is expanded two 64 - byte areas, called set 1 and set 2 . the upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1) , and the lower 32-byte area is a single 32-byte common area. in addition, set 2 is logically expanded four separately addressable register pages, page 0? page 3. t he total number of addressable 8-bit registers is 1125 . of the se 1 125 registers, 19 bytes are for cpu and system control register s , 32 bytes are for lcd data registers, 3 4 bytes are for peripheral control and data registers , 16 bytes are used as a shared working register s , and 1024 registers are for general-purpose use . you can always address s et 1 register locations, regardless of which of the four register pages is currently selected. set 1 locations , however, can only be addressed using direct address ing modes . the extension of register space into separately addressable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions ( sb0 and sb1 ) and the register page pointer (pp). specific register types and the area (in bytes) that they occupy in the register file are summarized in table 2 - 1. table 2-1. s3c821a register type summary register type number of bytes general-purpose registers (including the 16-byte common working register area , four 192-byte prime register area, and four 64-byte set 2 area ) lcd data registers cpu and system control registers mapped clock, peripheral, i/o control , and data registers 1,040 32 19 34 total addressable bytes 1,125
address spaces s3c821a/p821a 2- 4 ~ page 3 page 2 ~ page 1 ~ system registers (register addressing mode) working registers (working register addressing only) e0h c0h cfh dfh d0h 64 bytes ffh 32 bytes 256 bytes bfh 00h ffh c0h e0h prime data registers (all addressing modes) general-purpose data registers (indirect register, indexed mode, and stack operations) page 0 set 2 ~ ~ 1 fh 00h page 4 ~ ~ 3 2 bytes 192 bytes ffh ffh ffh lcd data registers (all addressing modes) lcd display register system and peripheral control registers (register addressing mode) set 1 bank 0 bank 1 page 0 figure 2-2. internal register file organization
s3c821a/p821a address spaces 2- 5 register page pointer (pp ) the s3c8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. page addressing is controlled by the register page pointer (pp, dfh). in the s3c821a microcontroller, a paged register file expansion is implemented for lcd data registers, and the register page pointer must be changed to address other pages. after a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always " 0000 b" , automatically selecting page 0 as the source and destination page for register addressing. lsb msb .2 .1 .0 .3 .6 .5 .4 .7 register page pointer (pp) dfh, set 1, r/w source register page selection bits: 0 0 0 0 source: page 0 destination register page selection bits: 0 0 0 0 destination: page 0 note : in the s3c821a microcontroller, pages 0, 1, 2, 3, and 4 are implemented. a hardware reset operation writes the 4-bit destination and source values shown above to the register page pointer. these values should be modified to address other pages. figure 2-3. register page pointer (pp ) + + programming tip ? using the page pointer for ram clear (page 0, page 1) ld pp, # 0 0h ; destination ? 0 , source ? 0 srp # 0c0 h ld r0, #0 ff h ; page0 ram clear starts ramcl0 clr @r0 djnz r0,ramcl0 clr @r0 ; r0 = 00h ld pp,#10h ; destination ? 1 , source ? 0 ld r0 ,#0ffh ; page1 ram clear starts ramcl1 clr @r0 djnz r0,ramcl1 clr @r0 ; r0 = 00h note: you should refer to page 6-39 and use djnz instruction properly when djnz instruction is used in your program.
address spaces s3c821a/p821a 2- 6 register set 1 the term set 1 refers to the upper 64 bytes of the register file, locations c0h?ffh. the upper 32-byte area of this 64-byte space (e0h?ffh) is expanded two 32-byte register banks, bank 0 and bank 1 . the set register bank instructions, sb0 or sb1, are used to address one bank or the other. a hardware reset operation always selects bank 0 addressing. the upper 32-byte area (bank 0 and bank 1, e0h?ffh) of set 1 contains 37 mapped system and peripheral control registers. the lower 32-byte area contains 16 system registers (d0h?dfh) and a 16-byte common working register area (c0h?cfh). you can use the common working register area as a ?scratch? area for data operations being performed in other areas of the register file. registers in set 1 locations are directly accessible at all times using register addressing mode. the 16-byte working register area can only be accessed using working register addressing (for more information about working register addressing, please refer to chapter 3, ?addressing modes.?) register set 2 the same 64-byte physical space that is used for set 1 locations c0h?ffh is logically duplicated to add another 64 bytes of register space. this expanded area of the register file is called set 2 . for the s3c821a, the set 2 address range (c0h?ffh) is accessible on pages 0-3. the logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. you can use only register addressing mode to access set 1 locations. in order to access registers in set 2, you must use register indirect addressing mode or indexed addressing mode. the set 2 register area on page 0 is commonly used for stack operations.
s3c821a/p821a address spaces 2- 7 prime register space the lower 192 bytes (00h ? bfh) of the s3c821a 's four 256 -byte register pages is called prime register area. prime registers can be accessed using any of the seven addressing modes (see chapter 3, "addressing modes . ") the prime register area on page 0 is immediately addressable following a reset. in order to address prime registers on pages 0, 1, 2, or 3 you must set the register page pointer (pp) to the appropriate source and destination values. bank 1 general-purpose cpu and system control peripherals and i/o lcd data register or not mapped area c0h ffh e0h d0h fch bank 0 set 1 ffh page 3 ffh page 2 ffh page 1 ffh 00h c0h set 2 prime space page 0 1 fh page 4 00h lcd data register area page 0 bf h figure 2-4. set 1, set 2, prime area register, and lcd data register map
address spaces s3c821a/p821a 2- 8 working registers instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. when 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of thirty-two 8-byte register groups or "slices." each slice comprises of eight 8-bit registers. using the two 8-bit register pointers, rp1 and rp0, two working register slices can be selected at any one time to form a 16-byte working register block. using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except for the set 2 area. the terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: ? one working register slice is 8 bytes (eight 8-bit working registers , r0 ? r7 or r8 ? r15) ? one working register block is 16 bytes (sixteen 8-bit working registers , r0 ? r15) all the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. this makes it possible for each register pointer to point to one of the 32 slices in the register file. the base addresses for the two selected 8-byte register slices are contained in register pointers rp0 and rp1. after a reset, rp0 and rp1 always point to the 16-byte common area in set 1 (c0h ? cfh). 1 1 1 1 1 x x x rp1 (registers r8?r15) 0 0 0 0 0 x x x rp0 (registers r0?r7) slice 1 slice 32 ffh f8h f7h f0h 10h fh 8h 7h 0h each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block . cfh c0h set 1 only ~ ~ slice 31 slice 2 figure 2-5. 8-byte working register areas (slices )
s3c821a/p821a address spaces 2- 9 using the register pointers register pointers rp0 and rp1, mapped to addresses d6h and d7h in set 1, are used to select two movable 8 -byte w orking register slices in the register file. after a reset, they point to the working register common area: rp0 points to addresses c0h ? c7h, and rp1 points to addresses c8h - cfh. to change a register pointer value, you load a new value to rp0 and/or rp1 using an srp or ld instruction (see figures 2-6 and 2-7). with working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by rp0 and rp1. you cannot, however, use the register pointers to select a working register space in set 2, c0h ? ffh, because these locations can be accessed only using the indirect register or indexed addressing modes. the selected 16-byte working register block usually consists of two contiguous 8-byte slices. as a general programming guideline, it is recommended that rp0 point to the "lower" slice and rp1 point to the "upper" slice (see figure 2-6). in some cases, it may be necessary to define working register areas in different (non- contiguous) areas of the register file. in figure 2-7, rp0 points to the "upper" slice and rp1 to the "lower" slice. because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area to support program requirements. + + programming tip ? setting the register pointers srp #70h ; rp0 ? 70h, rp1 ? 78h srp1 #48h ; rp0 ? no change, rp1 ? 48h, srp0 #0a0h ; rp0 ? a0h, rp1 ? no change clr rp0 ; rp0 ? 00h, rp1 ? no change ld rp1,#0f8h ; rp0 ? no change, rp1 ? f8h 0 0 0 0 1 x x x rp1 0 0 0 0 0 x x x rp0 fh 8h 7h 0h upper slice 8-byte slice 8-byte slice 16-byte contiguous working register block register file contains 32 8-byte slices (r15) (r0) ? ? ? figure 2-6. contiguous 16-byte working register block
address spaces s3c821a/p821a 2- 10 1 1 1 1 0 x x x rp0 0 0 0 0 0 x x x rp1 f7h f0h 7h 0h 8-byte slice 8-byte slice 16-byte non- contiguous working register block register file contains 32 8-byte slices (r7) (r0) | (r15) (r8) | figure 2-7. non-contiguous 16-byte working register block + + programming tip ? using the rps to calculate the sum of a series of registers calculate the sum of registers 80h - 85h using the register pointer. the register addresses from 80h through 85h contain the values 10h, 11h, 12h, 13h, 14h, and 15 h, respectively: srp0 #80h ; rp0 ? 80h add r0,r1 ; r0 ? r0 + r1 adc r0,r2 ; r0 ? r0 + r2 + c adc r0,r3 ; r0 ? r0 + r3 + c adc r0,r4 ; r0 ? r0 + r4 + c adc r0,r5 ; r0 ? r0 + r5 + c the sum of these six registers, 6fh, is located in the register r0 (80h). the instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. if the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used: add 80h,81h ; 80h ? (80h) + (81h) adc 80h,82h ; 80h ? ( 80h) + (82h) + c adc 80h,83h ; 80h ? ( 80h) + (83h) + c adc 80h,84h ; 80h ? ( 80h) + (84h) + c adc 80h,85h ; 80h ? ( 80h) + (85h) + c now, the sum of the six registers is also located in register 80h. however, this instruction string takes 15 bytes of instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.
s3c821a/p821a address spaces 2- 11 register addressing the s3c8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. with register (r) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2. with working register addressing, you use a register pointer to specify an 8 -byte working register space in the register file and an 8-bit register within that space. registers are addressed either as a single 8-bit register or as a paired 16-bit register space. in a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register, and the least significant byte is always stored in the next (+ 1) odd-numbered register. working register addressing differs from register addressing as it uses a register pointer to identify a specific 8 -byte working register space in the internal register file and a specific 8-bit register within that space. msb lsb rn rn + 1 n = even address figure 2-8. 16-bit register pair
address spaces s3c821a/p821a 2- 12 page 0-3 page 0-3 cfh bfh register addressing only all addressing modes indirect register, indexed addressing modes 00h register pointers rp1 rp0 d7h d6h set 2 ffh c0h c0h general-purpose registers each register pointer (rp) can independently point to one of the 256-byte "slices" of the register file (other than set 2). after a reset, rp0 points to locations c0h-c7h and rp1 to locations c8h- cfh (that is, to the common working register area). note : in the s3c821a microcontroller, pages 0-4 are implemented. pages 0-4 contain all of the addressable registers in the internal register file. special-purpose registers prime registers can be pointed to by register pointer lcd data registers can be pointed to by register pointer page 4 all addressing modes 1 fh lcd data registers or genernal purpose registers bank 1 bank 0 control registers system registers ffh d0h e 0h figure 2-9. register file addressing
s3c821a/p821a address spaces 2- 13 common working register area (c0h ? cfh ) after a reset, register pointers rp0 and rp1 automatically select two 8-byte register slices in set 1, locations c0h - cfh, as the active 16-byte working register block: rp0 ? c0h - c7h rp1 ? c8h - cfh this 16-byte address range is called common area . that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. typically, these working registers serve as temporary buffers for data operations between different pages. following a hardware reset, register pointers rp0 and rp1 point to the common working register area, locations c0h?cfh. 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 rp0 = rp1 = c0h ffh e0h cfh dfh fch set 1 ~ ~ ~ ffh 00h c0h bfh ~ prime area set 2 ~ page 2 page 1 page 0 ffh ffh ffh 00h 1 fh lcd data registers page 4 page 3 figure 2-10. common working register area
address spaces s3c821a/p821a 2- 14 + + programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h ? cfh, using working register addressing mode only. example s 1. ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: srp #0c0h ld r2,40h ; r2 (c2h) ? the value in location 40h 2. add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: srp #0c0h add r3,#45h ; r3 (c3h) ? r3 + 45h 4-bit working register add m ressing each register pointer defines a movable 8-byte slice of working register space. the address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. when an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: ? the high-order bit of the 4-bit address selects one of the register pointers ("0" selects rp0 , "1" selects rp1). ? the five high-order bits in the register pointer select an 8-byte slice of the register space . ? the three low-order bits of the 4-bit address select one of the eight registers in the slice. as shown in figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. as long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. figure 2-12 shows a typical example of 4-bit working register addressing . the high-order bit of the instruction " inc r6 " is "0", which selects rp0. the five high-order bits stored in rp0 (01110b) are concatenated with the three low-order bits of the instruction's 4-bit address (110b) to produce the register address 76h (01110110b).
s3c821a/p821a address spaces 2- 15 together they create an 8-bit register address register pointer provides five high-order bits selects rp0 or rp1 rp0 rp1 address opcode 4-bit address provides three low-order bits figure 2-11. 4-bit working register addressing 0 1 1 1 0 rp0 0 1 1 1 0 0 1 1 1 1 rp1 r6 opcode register address (76h) selects rp0 instruction: 'inc r6' q 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 0 0 figure 2-12. 4-bit working register addressing example
address spaces s3c821a/p821a 2- 16 8-bit working register addressing you can also use 8-bit working register addressing to access registers in a selected working register area. to initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value " 1100b. " this 4-bit value (1100b) indicates that the remaining four bits have the same effect as 4-bit working register addressing. as shown in figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4 -bit addressing: bit 3 selects either rp0 or rp1, which then supplies the five high-order bits of the final address; the three low-order bits of the complete address are provided by the original instruction. figure 2-14 shows an example of 8-bit working register addressing . the four high-order bits of the instruction address (1100b) specify 8-bit working register addressing. bit 4 ("1") selects rp1 and the five high-order bits in rp1 (10101b) become the five high-order bits of the register address. the three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. the five address bits from rp1 and the three address bits from the instruction are concatenated to form the complete register address, 0abh (10101011b). 8-bit physical address register pointer provides five high-order bits selects rp0 or rp1 rp0 rp1 address three low- order bits 8-bit logical address 1 1 0 0 these address bits indicate 8-bit working register addressing figure 2-13. 8-bit working register addressing
s3c821a/p821a address spaces 2- 17 rp0 rp1 r11 8-bit address from instruction 'ld r11, r2' specifies working register addressing selects rp1 register address (0abh) 1 1 0 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 figure 2-14. 8-bit working register addressing example
address spaces s3c821a/p821a 2- 18 system and user stacks the s 3c 8-series microcontrollers use the system stack for data storage, subroutine calls and returns. the push and pop instructions are used to control system stack operations. the s3c821a architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls , interrupts , and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address value is always decreased by one before a push operation and increased by one after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-15. stack contents after a call instruction pch pcl high address pch pcl flags stack contents after an interrupt top of stack low address top of stack figure 2-15. stack operations user-defined stacks you can freely define stacks in the internal register file as data storage locations. the instructions pushui, pushud, popui, and popud support user-defined stack operations. stack pointers (spl, sph) register locations d8h and d9h contain the 16-bit stack pointer (sp) that is used for system stack operations. the most significant byte of the sp address, sp15 - sp8, is stored in the sph register (d8h) , and the least significant byte, sp7 - sp0, is stored in the spl register (d9h). after a reset, the sp value is undetermined. if only internal memory space is implemented in the s3c821a , the spl must be initialized to an 8-bit value in the range 00h - ffh . t he sph register is not needed and can be used as a general-purpose register, if necessary. if external memory is implemented, both spl and sph must be initialized with a full 16-bit address. when the spl register contains the only stack pointer value (that is, when it points to a system stack in the register file), you can use the sph register as a general-purpose data register. however, if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the spl register during normal stack operations, the value in the spl register will overflow (or underflow) to the sph register, overwriting any other data that is currently stored there. to avoid overwriting data in the sph register, you can initialize the spl value to " ffh " instead of " 00h " .
s3c821a/p821a address spaces 2- 19 + + programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld spl,#0ffh ; spl ? ffh ; (normally, the spl is set to 0ffh by the initialization ; routine) ? ? ? push pp ; stack address 0feh ? pp push rp0 ; stack address 0fdh ? rp0 push rp1 ; stack address 0fch ? rp1 push r3 ; stack address 0fbh ? r3 ? ? ? pop r3 ; r3 ? stack address 0fbh pop rp1 ; rp1 ? stack address 0fch pop rp0 ; rp0 ? stack address 0fdh pop pp ; pp ? stack address 0feh
s3c821a/p821a addres sing modes 3- 1 3 addressing modes overview the program counter is used to fetch instructions that are stored in program memory for execution. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the s3c8-series instruction set supports seven explicit addressing modes. not all of these addressing modes are available for each instruction: ? register (r) ? indirect register (ir) ? indexed (x) ? direct address (da) ? indirect address (ia) ? relative address (ra) ? immediate (im)
addressing modes s3c821a/p82 1a 3- 2 register addressing mode (r) in register addressing mode, the operand is the content of a specified register or register pair (see figure 3-1). working register addressing differs from register addressing as it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see figure 3-2). program memory dst opcode 8-bit register file address one-operand instruction (example) register file operand points to one register in register file value used in instruction execution sample instruction: dec cntr ; where cntr is the label of an 8-bit register address figure 3-1. register addressing sample instruction: add r1,r2 ; where r1 and r2 are registers in the currently selected working register area program memory dst opcode 4-bit working register two- operand instruction (example) points to the working register (1 of 8) operand 3 lsbs src selected rp points to start of working register block register file rp0 or rp1 msb points to rp0 or rp1 figure 3-2. working register addressing
s3c821a/p821a addres sing modes 3- 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space, if implemented (see figures 3-3 through 3-6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. remember, however, that locations c0h?ffh in set 1 cannot be accessed using indirect register addressing mode. sample instruction: rl @shift ; where shift is the label of an 8-bit register address. 8-bit register file address one-operand instruction (example) points to one register in register file register file operand program memory dst opcode address address of operand used by instruction value used in instruction execution figure 3-3. indirect register addressing to register file
addressing modes s3c821a/p82 1a 3- 4 indirect register addressing mode ( continued ) program memory example instruction references program memory points to register pair register file 16-bit address points to program memory operand value used in instruction program memory register pair dst opcode sample instructions: call @rr2 jp @rr2 figure 3-4. indirect register addressing to program memory
s3c821a/p821a addres sing modes 3- 5 indirect register addressing mode ( continued ) program memory dst opcode 4-bit working register address points to the working register (1 of 8) register file rp0 or rp1 address 3 lsbs msb points to rp0 or rp1 src selected rp points to start of working register block operand value used in instruction sample instruction: or r3,@r6 ~ ~ ~ ~ figure 3-5. indirect working register addressing to register file
addressing modes s3c821a/p82 1a 3- 6 indirect register addressing mode ( continued ) sample instructions: ldc r5,@rr6 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4,r8 ; external data memory access next 2 bits point to working register pair (1 of 4) register file rp0 or rp1 register pair msb points to rp0 or rp1 selected rp points to start of working register block operand value used in instruction 4-bit working register address example instruction references either program memory or data memory program memory opcode dst src 16-bit address points to program memory or data memory program memory or data memory lsb selects figure 3-6. indirect working register addressing to program or data memory
s3c821a/p821a addres sing modes 3- 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3-7). you can use indexed addressing mode to access locations in the internal register file or in external memory (if implemented). you cannot, however, access locations c0h-ffh in set 1 using indexed addressing. in short offset indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range -128 to +127. this applies to external memory accesses only (see figure 3-8). for register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to the base address (see figure 3-9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program and for external data memory (if implemented). sample instruction: ld r0,#base[r1] ; where base is an 8-bit immediate value points to one of the working registers (1 of 8) msb points to rp0 or rp1 value used in instruction two- operand instruction example program memory opcode dst / src x 3 lsbs register file rp0 or rp1 operand selected rp points to start of working register block index base address + ~ ~ ~ ~ figure 3-7. indexed addressing to register file
addressing modes s3c821a/p82 1a 3- 8 indexed addressing mode ( continued ) sample instructions: ldc r4,#04h[rr2] ; the values in the program address (rr2 + 04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external data memory is accessed. msb points to rp0 or rp1 4-bit working register address program memory opcode dst / src x offset + register file rp0 or rp1 selected rp points to start of working register block operand register pair 16-bit address added to offset lsb selects 8 bits 16 bits 16 bits value used in instruction program memory or data memory next 2 bits point to working register pair (1 of 4) ~ ~ figure 3-8. indexed addressing to program or data memory with short offset
s3c821a/p821a addres sing modes 3- 9 indexed addressing mode ( continued ) sample instructions: ldc r4,#1000h[rr2] ; the values in the program address (rr2 + 1000h) are loaded into register r4. lde r4,#1000h[rr2] ; identical operation to ldc example, except that and external data memory is accessed. msb points to rp0 or rp1 4-bit working register address program memory opcode dst / src x offset + register file rp0 or rp1 selected rp points to start of working register block operand register pair 16-bit address added to offset lsb selects 16 bits 16 bits 16 bits value used in instruction program memory or data memory next 2 bits point to working register pair offset ~ ~ figure 3-9. indexed addressing to program or data memory
addressing modes s3c821a/p82 1a 3- 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external data memory is accessed. memory address used lsb selects program memory or data memory: "0" = program memory "1" = data memory program or data memory upper addr byte lower addr byte dst / src opcode "0" or "1" program memory figure 3-10. direct addressing for load instructions
s3c821a/p821a addres sing modes 3- 11 direct address mode (c ontinued ) sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address program memory next opcode lower addr byte program memory address used upper addr byte opcode figure 3-11. direct addressing for call and jump instructions
addressing modes s3c821a/p82 1a 3- 12 indirect address mode (ia) in indirect address (ia) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. the selected pair of memory locations contains the actual address of the next instruction to be executed. only the call instruction can use the indirect address mode. because the indirect address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros. sample instruction: call #40h ; the 16-bit value in program memory addresses 40h and 41h is the subroutine start address. program memory lower addr byte program memory locations 0?255 upper addr byte opcode dst lsb must be zero next instruction current instruction figure 3-12. indirect addressing
s3c821a/p821a addres sing modes 3- 13 relative address mode (ra) in relative address (ra) mode, a two's-complement signed displacement between -128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. several program control instructions use the relative address mode to perform conditional jumps. the instructions that support ra addressing are btjrf, btjrt, djnz, cpije, cpijne, and jr. program memory program memory address used displacement opcode signed displacement value + current pc value current instruction next opcode sample instruction: jr ult,$+offset ; where offset is a value in the range +127 to ?128 figure 3-13. relative addressing
addressing modes s3c821a/p82 1a 3- 14 immediate mode (im) in immediate (im) mode, the operand value used in the instruction is the value supplied in the operand field itself. the operand may be one byte or one word in length, depending on the instruction used. immediate addressing mode is useful for loading constant values into registers. program memory (the operand value is in the instruction.) opcode operand sample instruction: ld r0,#0aah figure 3-14. immediate addressing
s3c821a/p821a control registers 4 - 1 4 control registers overview in this chapter , deta iled descriptions of the s3c821a control registers are presented in an easy-to-read format. you can use this chapter as a quick-reference source when writing application programs. figure 4-1 illustrates the important features of the standard register description format. control register descriptions are arranged in alphabetical order according to register mnemonic. more detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in part ii of this manual. data and counter registers are not described in detail in this reference chapter . more information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in part ii of this manual. the locations and read/write characteristics of all mapped registers in the s3c821a register file are listed in table 4-1. the hardware reset value for each mapped register is described in chapter 8, ? reset and power- down ."
control registers s 3c821a/p821a 4- 2 table 4-1. set 1 registers register name mnemonic decimal hex r/w timer 0 counter t0cnt 208 d0h r ( n ote) timer 0 data register t0data 209 d1h r/w timer 0 control register t0con 210 d2h r/w basic timer control register btcon 211 d3h r/w clock control register clkcon 212 d4h r/w system flags register flags 213 d5h r/w register pointer 0 rp0 214 d6h r/w register pointer 1 rp1 215 d7h r/w stack pointer (high byte) sph 216 d8h r/w stack pointer (low byte) spl 217 d9h r/w instruction pointer (high byte) iph 218 dah r/w instruction pointer (low byte) ipl 219 dbh r/w interrupt request register irq 220 dch r ( n ote) interrupt mask register imr 221 ddh r/w system mode register sym 222 deh r/w register page pointer pp 223 dfh r/w note: you cannot use a read-only register as a destination for the instruction or, and, ld, or ldb.
s3c821a/p821a control registers 4 - 3 table 4- 2 . set 1, bank 0 registers register name mnemonic decimal hex r/w port 0 data register p0 224 e0h r/w port 1 data register p1 225 e1h r/w port 2 data register p2 226 e2h r/w port 3 data register p3 227 e3h r/w port 4 data register p 4 22 8 e 4 h r/w port 5 data register p 5 22 9 e 5 h r/w port 2 interrupt control register p2int 23 0 e 6 h r/w port 4 interrupt control register p4int 23 1 e 7 h r/w port 4 interrupt pending register p4pnd 23 2 e 8 h r/w port 4 interrupt edge select register p4edge 23 3 e 9 h r/w locations eah?edh are not mapped. timer b counter tbcnt 2 38 ee h r ( 2 ) timer a counter tacnt 2 39 ef h r ( 2 ) timer b data register tbdata 24 0 f 0 h r/w timer a data register tadata 24 1 f 1 h r/w timer b control register tbcon 24 2 f 2 h r/w timer 1/a control register tacon 24 3 f 3 h r/w sio data register sio 244 f4h r/w sio control register siocon 245 f5h r/w sio prescaler register siops 246 f6h r/w adc control register adcon 247 f7h r/w ( 1 ) adc data register addata 248 f8h r ( 2 ) location f9h is not mapped. lcd control register lcon 250 fah r/w watch timer control register wtcon 251 f b h r/w location fch is not mapped. basic timer counter btcnt 253 fdh r ( 2 ) external memory timing register emt 254 feh r/w interrupt priority register ipr 255 ffh r/w note s : 1. adcon.3 is a read-only bit. 2. you cannot use a read-only registe r as a destination for the instructions or, and, ld, or ldb.
control registers s 3c821a/p821a 4- 4 table 4- 3 . set 1, bank 1 registers register name mnemonic decimal hex r/w port 0 control register p0con 224 e0h r/w location e1h is not mapped. port 1 control register p1con 226 e2h r/w location e3h is not mapped. port 2 control register (high byte) p2conh 228 e4h r/w port 2 control register (low byte) p2conl 229 e5h r/w port 3 control register (high byte) p3conh 230 e6h r/w port 3 control register (low byte) p3conl 231 e7h r/w port 4 control register (high byte) p4conh 232 e8h r/w port 4 control register (low byte) p4conl 233 e9h r/w port 5 control register (high byte) p5conh 234 eah r/w port 5 control register (low byte) p5conl 235 ebh r/w locations ech?feh are not mapped. sub-clock control register sclkcon 255 ffh r/w
s3c821a/p821a control registers 4 - 5 flags ? system flags register d5h set 1 bit identifie r reset reset value read/write addressing mode .7 .6 carry flag (c) 0 1 operation does not generate a carry or borrow condition operation generates carry-out or borrow in high-order bit 7 register mnemonic full register name register address (hexadecimal) bit number: msb = bit 7 lsb = bit 0 r w r/w '?' = = = = read-only write-only read/write not used bit number(s) that is/are appended to the register name for bit addressing description of the effect of specific bit settings name of individual bit or bit function addressing mode or modes you can use to modify register values register addressing mode only .7 .6 .5 .4 .3 .2 .1 .0 x x x x x x 0 0 r/w r/w r/w r/w r/w r/w r/w r/w not used undetermined value logic zero logic one '?' 'x' '0' '1' = = = = reset value notation: register location in the internal register file zero flag (z) 0 1 operation result is a non-zero value operation result is zero sign flag (s) 0 1 operation generates positive number (msb = "0") operation generates negative number (msb = "1") .5 figure 4-1. register description format
control registers s 3c821a/p821a 4- 6 ad con ? a/d converter control register f7 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 0 0 0 0 0 0 0 read/write ? r/w r/w r/w r r/w r/w r/w addressing mode register addressing mode only .7 not used for the s3c821a . 6? . 4 a/d input pin selection bits 0 0 0 adc0 0 0 1 adc1 0 1 0 adc2 0 1 1 adc3 . 3 end-of-conversion bit (read-only) 0 conversion not complete 1 conversion complete .2 and .1 clock source selection bits 0 0 fxx/16 0 1 fxx/8 1 0 fxx/4 1 1 fxx .0 start or enable bit 0 no effect (when write) 1 start operation and auto cleared (when write)
s3c821a/p821a control registers 4 - 7 btcon ? basic timer control register d3h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 watchdog timer function disable code (for system reset) 1 0 1 0 disable watchdog timer function others enable watchdog timer function .3 and .2 basic timer input clock selection bits 0 0 fxx /4096 ( 3 ) 0 1 fxx /1024 1 0 fxx /128 1 1 fxx /16 .1 basic timer counter clear bit (1) 0 no effect 1 clear the basic timer counter value .0 clock frequency divider clear bit for basic timer and timer 0 (2) 0 no effect 1 clear both clock frequency dividers notes: 1. when you write a ?1? to btcon.1, the basic timer counter value is cleared to " 00h " . immediately following the write operation, the btcon. 1 value is automatically cleared to ?0?. 2. when you write a "1" to btcon.0, the corresponding frequency divider is cleared to " 00h " . immediately following the write operation, the btcon.0 value is automatically cleared to "0". 3. the fxx is selected clock for peripheral hardware (main system clock or sub system clock).
control registers s 3c821a/p821a 4- 8 clkcon ? system clock control register d4h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 oscillator irq wake-up enable bit 0 enable irq for main system oscillator wake-up in power-down mode 1 disable irq for main system oscillator wake-up in power-down mode .6 and .5 main oscillator stop control bits (3) 0 0 no effect 0 1 no effect 1 0 stop main oscillator (fx) 1 1 no effect .4 and .3 cpu clock selection bits ( 1 ) 0 0 fx/16 or fxt 0 1 fx/8 or fxt 1 0 fx/2 or fxt 1 1 fx (non-divided) or fxt .2?.0 subsystem clock selection bits (2) 1 0 1 select sub system clock (fxt) others select main system clock ( fx ) note s: 1. after a reset, the slowest clock (divided by 16) is selected as the cpu clock. to s elect faster clock speeds, load the appropriate v alues to clkcon.3 and clkcon.4. 2. although sub clock (fxt) is selected as cpu clock (fcpu), the selected clock (fxx) for basic timer, timer counter 0/1, watch timer, and a/d converter is main clock if the value of clkcon.6-.5 are not "10b (value to s top main clock)." 3. although the value of clkcon. 6-.5 are ?10b (value to stop main clock)?, main clock is not stopped if main system clock (fx) is selected as cpu clock (fcpu).
s3c821a/p821a control registers 4 - 9 emt ? external memory timing register ( n ote ) feh set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? ? 0 ? read/write ? ? ? ? ? ? r/w ? addressing mode register addressing mode only .7?.2 not used for the s3c821a .1 stack area selection bit 0 select internal register file area 1 select external data memory area .0 not used for the s3c821a note: the emt register is not used except emt.1 register bit . the program initialization routine should clear the emt register except the bit 1 to " 00h " following a reset. modification of emt values during normal operation may cause a system malfunction.
control registers s 3c821a/p821a 4- 10 flags ? system flags register d5h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x 0 0 read/write r/w r/w r/w r/w r/w r/w r r/w addressing mode register addressing mode only .7 carry flag (c) 0 operation does not generate a carry or borrow condition 1 operation generates a carry-out or borrow into high-order bit 7 .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is +127 or 3 ?128 1 operation result is > +127 or < ?128 .3 decimal adjust flag (d) 0 add operation completed 1 subtraction operation completed .2 half-carry flag (h) 0 no carry-out of bit 3 or no borrow into bit 3 by addition or subtraction 1 addition generated carry-out of bit 3 or subtraction generated borrow into bit 3 .1 fast interrupt status flag (fis) 0 interrupt return (iret) in progress (when read) 1 fast interrupt service routine in progress (when read) .0 bank address selection flag (ba) 0 bank 0 is selected 1 bank 1 is selected
s3c821a/p821a control registers 4 - 11 imr ? interrupt mask register ddh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x ? x x x read/write r/w r/w r/w r/w ? r/w r/w r/w addressing mode register addressing mode only . 7 interrupt level 7 (irq 7 ) enable bit; external interrupts p4.3?p4.0 0 disable (mask) 1 enable (un-mask) .6 interrupt level 6 (irq6) enable bit; external interrupts p4.7?p4.4 0 disable (mask) 1 enable (un-mask) .5 interrupt level 5 (irq5) enable bit; external interrupts p2.7?p2.4 0 disable (mask) 1 enable (un-mask) .4 interrupt level 4 (irq4) enable bit; watch timer overflow 0 disable (mask) 1 enable (un-mask) .3 not used for the s3c821a . 2 interrupt level 2 (irq 2 ) enable bit; sio interrupt 0 disable (mask) 1 enable (un-mask) .1 interrupt level 1 (irq1) enable bit; timer 1 match (timer a and b) 0 disable (mask) 1 enable (un-mask) .0 interrupt level 0 (irq0) enable bit; timer 0 match/capture or overflow 0 disable (mask) 1 enable (un-mask) note s : 1. when an interrupt level is masked, any interrupt requests that may be issued are not recognized by the cpu. 2. interrupt levels irq3 is not used in the s3c821a interrupt structure.
control registers s 3c821a/p821a 4- 12 iph ? instruction pointer (high byte ) dah set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (high byte) the high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (ip15 ? ip8). the lower byte of the ip address is located in the ipl register (dbh). ipl ? instruction pointer (low byte ) dbh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (low byte) the low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (ip7ip0). the upper byte of the ip address is located in the iph register (dah).
s3c821a/p821a control registers 4 - 13 ipr ? interrupt priority register ffh set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7, .4, and .1 priority control bits for interrupt groups a, b, and c 0 0 0 group priority undefined 0 0 1 b > c > a 0 1 0 a > b > c 0 1 1 b > a > c 1 0 0 c > a > b 1 0 1 c > b > a 1 1 0 a > c > b 1 1 1 group priority undefined .6 interrupt subgroup c priority control bit 0 irq6 > irq7 1 irq7 > irq6 .5 interrupt group c priority control bit 0 irq5 > ( irq6 , irq7) 1 ( irq6 , irq7) > irq5 .3 interrupt subgroup b priority control bit (note) 0 irq4 1 irq4 .2 interrupt group b priority control bit (note) 0 irq2 > irq4 1 irq4 > irq2 .0 interrupt group a priority control bit 0 irq0 > irq1 1 irq1 > irq0 note: the s3c821a interrupt structure uses only the seven levels: irq0?irq2, and irq4?irq7. because irq3 is not recognized, the interrupt b subgroup settings (ipr.2 and ipr.3) are not evaluated.
control registers s 3c821a/p821a 4- 14 irq ? interrupt request register dch set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r r r r r r r r addressing mode register addressing mode only . 7 level 7 (irq 7 ) request pending bit; external interrupts p4.3?p4.0 0 not pending 1 pending .6 level 6 (irq6) request pending bit; external interrupts p4.7?p4.4 0 not pending 1 pending .5 level 5 (irq5) request pending bit; external interrupts p2.7?p2.4 0 not pending 1 pending .4 level 4 (irq4) request pending bit; watch timer overflow 0 not pending 1 pending .3 not used for the s3c821a . 2 level 2 (irq 2 ) request pending bit; sio interrupt 0 not pending 1 pending .1 level 1 (irq1) request pending bit; timer 1 match (timer a and b) 0 not pending 1 pending .0 level 0 (irq0) request pending bit; timer 0 match/capture or overflow 0 not pending 1 pending note: interrupt level irq3 is not used in the s3c821a interrupt structure.
s3c821a/p821a control registers 4 - 15 lcon ? lcd control register fa h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 ? ? 0 0 0 0 read/write r/w r/w ? ? r/w r/w r/w r/w addressing mode register addressing mode only . 7 and .6 lcd duty and bias selection bits 0 0 display off, p-tr off 0 1 normal display (using v lc1 with external voltage), p-tr off 1 0 all dots off, p-tr on 1 1 normal display (using v lc1 with internal voltage), p-tr on . 5 and .4 not used for the s3c821a. . 3 and .2 lcd duty and bias selection bits 0 0 1/3 duty, 1/3 bias; com0?com2/seg0?seg31 0 1 1/4 duty, 1/3 bias; com0?com3/seg0?seg31 1 0 1/8 duty, 1/4 bias; com0?com7/seg4?seg31 1 1 1/8 duty, 1/5 bias; com0?com7/seg4?seg31 .1 and .0 lcd clock selection bits 0 0 fw/2 6 (512 hz when fw is 32.768 khz) 0 1 fw/2 5 (1,024 hz when fw is 32.768 khz) 1 0 fw/2 4 (2,048 hz when fw is 32.768 khz) 1 1 fw/2 3 (4,096 hz when fw is 32.768 khz)
control registers s 3c821a/p821a 4- 16 p0con ? port 0 control register e0h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? . 4 upper nibble port configuration (p0.7/a15?p0.4/a12) 0 0 x 0 input mode 0 1 x 0 pull-up input mode 0 0 0 1 push-pull output mode 0 0 1 1 open-drain output mode 0 1 x 1 lcd segment (seg23?seg20) 1 x x x external interface (a15?a12) . 3? . 0 lower nibble port configuration (p0.3/a11?p0.0/a8) 0 0 x 0 input mode 0 1 x 0 pull-up input mode 0 0 0 1 push-pull output mode 0 0 1 1 open-drain output mode 0 1 x 1 lcd segment (seg19?seg16) 1 x x x external interface (a11?a8) note: "x" means don't care.
s3c821a/p821a control registers 4 - 17 p 1 con ? port 1 control register e 2 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? . 4 upper nibble port configuration (p1.7/ad7?p1.4/ad4) 0 0 x 0 input mode 0 1 x 0 pull-up input mode 0 0 0 1 push-pull output mode 0 0 1 1 open-drain output mode 0 1 x 1 lcd segment (seg31?seg28) 1 x x x external interface (ad7?ad4) . 3? . 0 lower nibble port configuration (p1.3/ad3?p1.0/ad0) 0 0 x 0 input mode 0 1 x 0 pull-up input mode 0 0 0 1 push-pull output mode 0 0 1 1 open-drain output mode 0 1 x 1 lcd segment (seg27?seg24) 1 x x x external interface (ad3?ad0) note: "x" means don't care.
control registers s 3c821a/p821a 4- 18 p 2 conh ? port 2 control register (high byte ) e 4 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p2.7/tb mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 select alternate function for p2.7 (tb clock) .5 and .4 p2.6/ta mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 select alternate function for p2.6 (ta clock) .3 and .2 p2.5/t1ck mode selection bits 0 0 schmitt trigger input mode (t1ck) 0 1 schmitt trigger input, pull-up mode (t1ck) 1 0 push-pull output mode 1 1 p2.5 remains "0" state .1 and .0 p 2 .4 /t0ck mode selection bits 0 0 schmitt trigger input mode (t0ck) 0 1 schmitt trigger input, pull-up mode (t0ck) 1 0 push-pull output mode 1 1 p2.4 remains "0" state note: pins configured as input can be used as interrupt input with noise filter.
s3c821a/p821a control registers 4 - 19 p 2 conl ? port 2 control register (low byte ) e5 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p 2 .3 / dm dm mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 external memory interface line ( dm ) .5 and .4 p 2 .2 / dw dw mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 external memory interface line ( dw ) .3 and .2 p 2 .1 / dr dr mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 external memory interface line ( dr ) .1 and .0 p 2 .0 / as as mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 external memory interface line ( as)
control registers s 3c821a/p821a 4- 20 p2int ? port 2 interrupt control register e 6 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 port 2 interrupt request pending bit (p2.7/int3) 0 no interrupt request pending 0 clear pending bit (when write) 1 interrupt request is pending .6 interrupt control settings (p2.7/int3) 0 disable interrupt on p2.7 1 enable interrupt at falling edge on p2.7 .5 port 2 interrupt request pending bit (p2.6/int2) 0 no interrupt request pending 0 clear pending bit (when write) 1 interrupt request is pending .4 interrupt control settings (p2.6/int2) 0 disable interrupt on p2.6 1 enable interrupt at falling edge on p2.6 .3 port 2 interrupt request pending bit (p2.5/int1) 0 no interrupt request pending 0 clear pending bit (when write) 1 interrupt request is pending .2 interrupt control settings (p2.5/int1) 0 disable interrupt on p2.5 1 enable interrupt at falling edge on p2.5 .1 port 2 interrupt request pending bit (p2.4/int0) 0 no interrupt request pending 0 clear pending bit (when write) 1 interrupt request is pending .0 interrupt control settings (p2.4/int0) 0 disable interrupt on p2.4 1 enable interrupt at falling edge on p2.4
s3c821a/p821a control registers 4 - 21 p3 conh ? port 3 control register (high byte ) e 6 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p3.7/t0/t0pwm/t0cap mode selection bits 0 0 schmitt trigger input mode (t0cap input) 0 1 schmitt trigger input, pull-up mode (t0cap input) 1 0 push-pull output mode 1 1 select alternate function (t0pwm/t0) .5 and .4 p3.6 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 o utput , high-impedance .3 and .2 p3.5 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 o utput , high-impedance .1 and .0 p3. 4 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 o utput , high-impedance
control registers s 3c821a/p821a 4- 22 p3 conl ? port 3 control register (low byte ) e7 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p3. 3 /adc3 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 a/d converter input mode; schmitt trigger input off .5 and .4 p3. 2 /adc2 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 a/d converter input mode; schmitt trigger input off .3 and .2 p3. 1 /adc1 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 a/d converter input mode; schmitt trigger input off .1 and .0 p3. 0 /adc0 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 a/d converter input mode; schmitt trigger input off
s3c821a/p821a control registers 4 - 23 p4 conh ? port 4 control register (high byte ) e 8 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p4.7/int11 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 open-drain output mode .5 and .4 p4.6/int10 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 open-drain output mode .3 and .2 p4.5/int9 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 open-drain output mode .1 and .0 p4. 4 /int8 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 open-drain output mode note: pins configured as input can be used as interrupt input with noise filter.
control registers s 3c821a/p821a 4- 24 p4 conl ? port 4 control register (low byte ) e9 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p4. 3 /int7 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 open-drain output mode .5 and .4 p4. 2 /int6 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 open-drain output mode .3 and .2 p4. 1 /int5 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 open-drain output mode .1 and .0 p4. 0 /int4 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 open-drain output mode note: pins configured as input can be used as interrupt input with noise filter.
s3c821a/p821a control registers 4 - 25 p4 int ? port 4 interrupt control register e7 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 p4.7 external interrupt (int11 ) enable bit 0 disable interrupt 1 enable interrupt .6 p4.6 external interrupt (int10 ) enable bit 0 disable interrupt 1 enable interrupt .5 p4.5 external interrupt (int9 ) enable bit 0 disable interrupt 1 enable interrupt . 4 p4.4 external interrupt (int8 ) enable bit 0 disable interrupt 1 enable interrupt .3 p4.3 external interrupt (int7 ) enable bit 0 disable interrupt 1 enable interrupt .2 p4.2 external interrupt (int6 ) enable bit 0 disable interrupt 1 enable interrupt .1 p4.1 external interrupt (int5 ) enable bit 0 disable interrupt 1 enable interrupt .0 p4.0 external interrupt (int4 ) enable bit 0 disable interrupt 1 enable interrupt
control registers s 3c821a/p821a 4- 26 p4pnd ? port 4 interrupt pending register e8 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 p4.7 external interrupt (int11 ) pending flag 0 clear pending bit (when write) 1 p4.7 interrupt request is pending (when read) .6 p4.6 external interrupt (int10 ) pending flag 0 clear pending bit (when write) 1 p4.6 interrupt request is pending (when read) .5 p4.5 external interrupt (int9 ) pending flag 0 clear pending bit (when write) 1 p4.5 interrupt request is pending (when read) . 4 p4.4 external interrupt (int8 ) pending flag 0 clear pending bit (when write) 1 p4.4 interrupt request is pending (when read) .3 p4.3 external interrupt (int7 ) pending flag 0 clear pending bit (when write) 1 p4.3 interrupt request is pending (when read) .2 p4.2 external interrupt (int6 ) pending flag 0 clear pending bit (when write) 1 p4.2 interrupt request is pending (when read) .1 p4.1 external interrupt (int5 ) pending flag 0 clear pending bit (when write) 1 p4.1 interrupt request is pending (when read) .0 p4.0 external interrupt (int4 ) pending flag 0 clear pending bit (when write) 1 p4.0 interrupt request is pending (when read) note: writing a ?1? to an interrupt pending flag ( p4pnd.0?.7 ) has no effect.
s3c821a/p821a control registers 4 - 27 p4edge ? port 4 interrupt edge selection register e9 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 p4.7 external interrupt (int11) state bit 0 falling edge detection 1 rising edge detection .6 p4.6 external interrupt (int10) state bit 0 falling edge detection 1 rising edge detection .5 p4.5 external interrupt (int9) state bit 0 falling edge detection 1 rising edge detection .4 p4.4 external interrupt (int8) state bit 0 falling edge detection 1 rising edge detection .3 p4.3 external interrupt (int7) state bit 0 falling edge detection 1 rising edge detection .2 p4.2 external interrupt (int6) state bit 0 falling edge detection 1 rising edge detection .1 p4.1 external interrupt (int5) state bit 0 falling edge detection 1 rising edge detection .0 p4.0 external interrupt (int4) state bit 0 falling edge detection 1 rising edge detection
control registers s 3c821a/p821a 4- 28 p5 conh ? port 5 control register (high byte ) e a h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 not used for the s3c821a .5 and .4 p5.6 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 o utput , high-impedance .3 and .2 p5.5 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 o utput , high-impedance .1 and .0 p5. 4 mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 o utput , high-impedance
s3c821a/p821a control registers 4 - 29 p5 conl ? port 5 control register (low byte ) eb h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p5. 3 /buz mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 select alternate function (buz signal) .5 and .4 p5. 2 /so mode selection bits 0 0 schmitt trigger input mode 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 select alternate function (so) .3 and .2 p5. 1 /si mode selection bits 0 0 schmitt trigger input mode (si input) 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 output high-impedance .1 and .0 p5. 0 /sck mode selection bits 0 0 schmitt trigger input mode (sck input) 0 1 schmitt trigger input, pull-up mode 1 0 push-pull output mode 1 1 select alternate function (sck output) note: si and sck inputs have noise filter.
control registers s 3c821a/p821a 4- 30 pp ? register page pointer dfh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .4 destination register page selection bits 0 0 0 0 destination: page 0 0 0 0 1 destination: page 1 0 0 1 0 destination: page 2 0 0 1 1 destination: page 3 0 1 0 0 destination: page 4 .3 ? .0 source register page selection bits 0 0 0 0 source: page 0 0 0 0 1 source: page 1 0 0 1 0 source: page 2 0 0 1 1 source: page 3 0 1 0 0 source: page 4 note s : 1. in the s3c821a microcontroller, the internal register file is configured as five pages (pages 0?4). the pages 0?3 are used for general purpose register file, and page 4 is used for lcd data register or general purpose registers. 2. you should refer to page 6-39 and use djnz instruction properly when djnz instruction is used in your program.
s3c821a/p821a control registers 4 - 31 rp0 ? register pointer 0 d6h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 1 0 0 0 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing only .7 ? .3 register pointer 0 address value register pointer 0 can independently point to one of the 256 -byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp0 points to address c0h in register set 1, selecting the 8-byte working register slice c0h ? c7h. .2 ? .0 not used for the s3c821a rp1 ? register pointer 1 d7h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 1 0 0 1 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing only .7 ? .3 register pointer 1 address value register pointer 1 can independently point to one of the 256 -byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp1 points to address c8h in register set 1, selecting the 8-byte working register slice c8h ? cfh. .2 ? .0 not used for the s3c821a
control registers s 3c821a/p821a 4- 32 sclkcon ? sub-system clock control register ff h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? ? ? 0 read/write ? ? ? ? ? ? ? r/w addressing mode register addressing only .7 ? . 1 not used for the s3c821a . 0 sub-system clock stop enable bit 0 enable sub-system clock 1 disable sub-system clock notes: 1. the sub oscillator can be halted only by sclkcon.0. in sub-oscillation mode, sub-oscillation stop can be released only by a reset operation. 2. when sub and main oscillator are halted in main operating mode, stop mode can be released by an external interrupt or a reset operation.
s3c821a/p821a control registers 4 - 33 siocon ? sio control register f5 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 sio shift clock selection bit 0 external clock 1 cpu clock .6 sio interrupt pending bit 0 no interrupt pending 0 clear pending condition (when write) 1 interrupt is pending .5 sio interrupt enable bit 0 disable sio interrupt 1 enable sio interrupt . 4 sio start edge selection bit 0 falling edge start 1 rising edge start .3 sio counter clear and shifter start bit 0 no action (when write) 1 clear 3-bit counter and start shifting .2 sio shift operation enable bit 0 disable shifter and counter, retain irq status 1 enable shifter and clock counter, set irq flag to "1" .1 sio mode selection bit 0 receive only mode 1 transmit/receive mode .0 data direction control bit 0 msb first mode 1 lsb first mode
control registers s 3c821a/p821a 4- 34 sph ? stack pointer (high byte ) d8h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .0 stack pointer address (high byte) the high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (sp15 ? sp8). the lower byte of the stack pointer value is located in register spl (d9h). the sp value is undefined following a reset. spl ? stack pointer (low byte ) d9h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .0 stack pointer address (low byte) the low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer address (sp7 ? sp0). the upper byte of the stack pointer value is located in register sph (d8h). the sp value is undefined following a reset.
s3c821a/p821a control registers 4 - 35 sym ? system mode register deh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 ? ? x x x 0 0 read/write r/w ? ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 tri-state external interface enable bit 0 normal operation (disable tri-state operation) 1 set external interface lines to high impedance (enable tri-state operation) .6 and .5 not used for the s3c821a .4 ? .2 fast interrupt level selection bits ( 1 ) 0 0 0 irq0 0 0 1 irq1 0 1 0 irq2 0 1 1 not used for the s3c821a 1 0 0 irq4 1 0 1 irq5 1 1 0 irq6 1 1 1 irq7 .1 fast interrupt enable bit ( 2 ) 0 disable fast interrupt processing 1 enable fast interrupt processing .0 global interrupt enable bit ( 3 ) 0 disable all interrupt processing 1 enable all interrupt processing notes: 1 . you can select only one interrupt level at a time for fast interrupt processing. 2 . setting sym.1 to "1" enables fast interrupt processing for the interrupt level currently selected by sym.2 - sym.4. 3 . following a reset, you must enable global interrupt processing by executing an ei instruction (not by writing a "1" to sym.0).
control registers s 3c821a/p821a 4- 36 t0con ? timer 0 control register d2h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 timer 0 input clock selection bits 0 0 fxx /4 , 096 0 1 fxx /256 1 0 fxx /8 1 1 external cl ock input (t0ck ) .5 and .4 timer 0 operating mode selection bits 0 0 interval timer mode 0 1 capture mode (rising edges, counter running, ovf interrupt can occur) 1 0 capture mode (falling edges, counter running, ovf interrupt can occur) 1 1 pwm mode (ovf interrupt can occur) .3 timer 0 counter clear bit 0 no effect 1 clear t 0 counter (when write) .2 timer 0 overflow interrupt enable bit (note) 0 disable t0 overflow interrupt 1 enable t0 overflow interrupt .1 timer 0 interrupt enable bit 0 disable t0 interrupt 1 enable t0 interrupt .0 timer 0 interrupt pending bit 0 no t0 interrupt pending (when read) 0 clear t0 interrupt pending condition (when write) 1 t0 interrupt is pending note : a t imer 0 overflow interrupt pending condition is automatically cleared by har dware. however, the timer 0 match/ capture interrupt, irq0, vector fch, must be cleared by the interrupt service routine.
s3c821a/p821a control registers 4 - 37 t a con ? timer counter 1/a control register f3 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 timer 1 operating mode selection bit 0 two 8-bit timers mode (timer a/b) 1 one 16-bit timer mode (timer 1) . 6? .4 timer 1/a clock selection bits 0 0 0 fxx/1,024 0 0 1 fxx/512 0 1 0 fxx/8 0 1 1 fxx 1 x x t1ck (external clock at p2.5) .3 timer 1/a counter clear bit 0 no effect 1 clear the timer a counter (when write) .2 timer 1/a counter run enable bit 0 disable counter running 1 enable counter running .1 timer 1/a interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer 1/a interrupt pending bit 0 no interrupt pending (when read) 0 clear pending bit (when write) 1 i nterrupt is pending (when read) 1 no effect (when write) notes: 1. "x" means don't care. 2. fxx is a selected clock for peripheral hardware.
control registers s 3c821a/p821a 4- 38 t b con ? timer b control register f2 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 not used for the s3c821a .5 and .4 timer b clock selection bits 0 0 fxx/1,024 0 1 fxx/512 1 0 fxx/8 1 1 fxx .3 timer b counter clear bit 0 no effect 1 clear the timer b counter (when write) .2 timer b counter run enable bit 0 disable counter running 1 enable counter running .1 timer b interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer b interrupt pending bit 0 no interrupt pending (when read) 0 clear pending bit (when write) 1 i nterrupt is pending (when read) 1 no effect (when write) note: fxx is a selected clock for peripheral hardware.
s3c821a/p821a control registers 4 - 39 wt con ? watch timer control register fb h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only . 7 buzzer signal enable bit 0 disable buzzer signal output 1 enable buzzer signal output . 6 watch timer enable bit 0 disable watch timer; clear frequency dividing circuit 1 enable watch timer .5 and .4 buzzer signal selection bits 0 0 0.5 khz buzzer (buz) signal output 0 1 1 khz buzzer (buz) signal output 1 0 2 khz buzzer (buz) signal output 1 1 4 khz buzzer (buz) signal output .3 watch timer speed selection bit 0 fw/2 14 (0.5 sec) interval 1 fw/2 7 (3.91 ms) interval .2 watch timer clock selection bit 0 main system clock divided by 2 7 (fx/128) 1 sub system clock (fxt) .1 watch timer interrupt pending bit 0 no interrupt pending 0 clear pending bit (when write) 1 interrupt is pending .0 watch timer interrupt enable bit 0 disable interrupt 1 enable interrupt
s3c821a/p821a interrupt structure 5 - 1 5 interrupt structure overview the s3c8-series interrupt structure has three basic components: levels, vectors, and sources. the sam8 cpu recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. when a specific interrupt level has more than one vec t or address, the vector priorities are established in hardware . a vector address can be assigned to one or more sources. levels interrupt levels are the main unit for interrupt priority assignment and recognition. all peripherals and i/o blocks can issue interrupt requests. in other words, peripheral and i/o operations are interrupt-driven. there are eight possible interrupt levels: irq0 ? irq7, also called level 0 - level 7. each interrupt level directly corresponds to an interrupt request number (irqn). the total number of interrupt levels used in the interrupt structure varies fr om device to device. the s3c821a interrupt structure recognizes seven interrupt levels. the interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. they are just identifiers for the interrupt levels that are recognized by the cpu. the relative priority of different interrupt levels is determined by settings in the interrupt priority register, ipr. interrupt group and subgroup logic controlled by ipr settings lets you define more complex priority relationships between different levels. vectors each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. the maximum number of vectors that can be supported for a given level is 128 (the actual number of vectors used for s3c 8-series devices is always much smaller) . if an interrupt level has more than one vector address, the vector priorities are set in hardware. s3c821a uses nineteen vectors . sources a source is any peripheral that generates an interrupt. a source can be an external pin or a counter overflow . each vector can have several interrupt sources. in the s3c821a interrupt structure, there are nineteen possible interrupt sources. when a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually" by program software. the characteristics of the source's pending mechanism determine which method would be used to clear its respective pending bit.
interrupt structure s3c821a/p821a 5- 2 interrupt types the three components of the s3c8 interrupt structure described before ? levels, vectors, and sources ? are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. there are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. the types differ in the number of vectors and interrupt sources assigne d to each level (see figure 5-1): type 1: one level (irqn) + one vector (v 1 ) + one source (s 1 ) type 2: one level (irqn) + one vector (v 1 ) + multiple sources (s 1 ? s n ) type 3: one level (irqn) + multiple vectors (v 1 ? v n ) + multiple sources (s 1 ? s n , s n+1 ? s n+m ) in the s3c821a microcontroller, two interrupt types are implemented. notes : 1. the number of s n and v n values is expandable. 2. in the s3c821a implementation, interrupt types 1 and 3 are used. sources vectors levels s 1 v 1 s 1 s 2 s 3 s n v 1 irqn irqn irqn s 1 s 2 s 3 s n s n + 1 s n + 2 s n + m v 1 v 2 v 3 v n type 1: type 2: type 3: figure 5-1. s3c 8-series interrupt types
s3c821a/p821a interrupt structure 5 - 3 s3c821a interrupt structure the s3c821a microcontroller supports nineteen interrupt sources. all nineteen of the interrupt source s ha ve a corresponding interrupt vector address. seven interrupt levels are recognized by the cpu in this device-specific interrupt structure, as shown in figure 5-2. when multiple interrupt levels are active, the interrupt priority register (ipr) determines the order in which contending interrupts are to be serviced. if multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first (the relative priorities of multiple interrupts within a single level are fixed in hardware) . when the cpu grants an interrupt request, interrupt processing starts . all other interrupts are disabled and the program counter value and status flags are pushed to stack. the starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed.
interrupt structure s3c821a/p821a 5- 4 note : for interrupt levels with two or more vectors, the lowest vector address usually has the highest priority. for example, fah has higher priority (0) than fch (1) within the level irq0. these priorities are fixed in hardware. vector level source reset/clear irq0 1 0 timer 0 match/capture s/w irq4 irq1 1 0 timer 1/a match s/w timer 0 overflow timer b match s/w h/w reset basic timer overflow h/w p2.7 external interrupt s/w p2.6 external interrupt s/w 1 irq5 0 p2.5 external interrupt s/w p2.4 external interrupt s/w 2 3 p4.7 external interrupt s/w p4.6 external interrupt s/w 1 irq6 0 p4.5 external interrupt s/w p4.4 external interrupt s/w 2 3 watch timer overflow s /w fch f6h fah f4h 100h deh dch dah d8h d6 h d 4h d 2h d 0h f0h f2h irq2 sio interrupt s /w p4.3 external interrupt s/w p4.2 external interrupt s/w 1 irq7 0 p4.1 external interrupt s/w p4.0 external interrupt s/w 2 3 c 6 h c 4h c 2h c 0h figure 5-2. s3c821a interrupt structure
s3c821a/p821a interrupt structure 5 - 5 interrupt vector addresses all interrupt vector addresses for the s3c821a interrupt structure are stored in the vector address area of the internal 48 -k byte rom, 0h? b f ff h (see figure 5-3). you can allocate unused locations in the vector address area as normal program memory. if you do so, please be careful not to overwrite any of the stored vector addresses (table 5-1 lists all vector addresses) . the program reset address in the rom is 0100h. (decimal) (hex) 0 255 ffh b fffh 49,151 00h 100h reset address 48 -kbyte internal program memory (rom) area ~ ~ interrupt vector address area figure 5-3. rom vector address area
interrupt structure s3c821a/p821a 5- 6 table 5-1. s3c821a interrupt vectors vector address interrupt source request reset/clear decimal value hex value interrupt level priority in level h/w s/w 256 100h basic timer overflow reset reset ? ? 25 2 f c h timer 0 (match/capture) irq0 1 ? 250 f a h timer 0 overflow 0 ? 2 46 f6 h timer 1/a match irq1 1 ? 2 44 f 4 h timer b match 0 ? 240 f0h sio interrupt irq 2 ? ? 242 f2h watch timer overflow irq4 ? ? 222 deh p2.7 external interrupt irq5 3 ? 220 dch p2.6 external interrupt 2 ? 218 dah p2.5 external interrupt 1 ? 216 d8h p2.4 external interrupt 0 ? 214 d6h p4.7 external interrupt irq 6 3 ? 212 d4h p4.6 external interrupt 2 ? 210 d2h p4.5 external interrupt 1 ? 208 d0h p4.4 external interrupt 0 ? 198 c6h p4.3 external interrupt irq7 3 ? 196 c4h p4.2 external interrupt 2 ? 194 c2h p4.1 external interrupt 1 ? 192 c0h p4.0 external interrupt 0 ? notes: 1. interrupt priorities are identified in inverse order: " 0 " is the highest priority, " 1 " is the next highest, and so on. 2. if two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has pri ority over one with a higher vector address. the priorities within a given level are fixed in hardware.
s3c821a/p821a interrupt structure 5 - 7 enable/disable interrupt instructions (ei, di ) executing the enable interrupts (ei) instruction globally enables the interrupt structure. all interrupts are then serviced as they occur according to the established priorities. note the system initialization routine executed after a reset must always contain an ei instruction to globally enable the interrupt structure. during the normal operation, you can execute the di (disable interrupt) instruction at any time to globally disable interrupt processing. the ei and di instructions change the value of bit 0 in the sym register. system-level interrupt control registers in addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing: ? the interrupt mask register, imr, enables (un-masks) or disables (masks) interrupt levels. ? the interrupt priority register, ipr, controls the relative prioritie s of interrupt levels. ? the interrupt request register, irq, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source). ? the system mode register, sym, enables or disables global interrupt processing (sym settings also enable fast interrupts and control the activity of external interface, if implemented) . table 5-2. interrupt control register overview control register id r/w function description interrupt mask register imr r/w bit settings in the imr register enable or disable interrupt processing for each of the seven interrupt levels: irq0?irq2, and irq4?irq7 . interrupt priority register ipr r/w controls the relative processing priorities of the interrupt levels. the seven levels of s3c821a are organized into three groups: a, b, and c. group a is irq0 and irq1, group b is irq2 and irq4, and group c is irq5 , irq6 , and irq7 . interrupt request register irq r this register contains a request pending bit for each interrupt level. system mode register sym r/w this register enable s/ disable s fast interrupt processing, d ynamic global interrupt processing, and external interface control (an external memory interface is implemented in the s3c821a microcontroller).
interrupt structure s3c821a/p821a 5- 8 interrupt processing control points interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. t he system-level control points in the interr upt structure are : ? global interrupt enable and disable (by ei and di instructions or by direct manipulation of sym. 0 ) ? interrupt level enable/disable settings (imr register) ? interrupt level priority settings (ipr register) ? interrupt source enable/disable settings in the corresponding peripheral control registers note when writing an application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information. s q r ei polling cycle interrupt request register (read-only) irq0-irq2, and irq4-irq7 interrupts vector interrupt cycle interrupt mask register interrupt priority register global interrupt control (ei, di, or sym.0 manipulation) reset figure 5-4. interrupt function diagram
s3c821a/p821a interrupt structure 5 - 9 peripheral interrupt control registers for each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see table 5-3). table 5-3. interrupt source control and data registers interrupt source interrupt level register(s) location(s) in set 1 timer 0 match/capture timer 0 overflow irq0 t0con ( n ote) t0data d2h d1h timer 1/timer a match timer b match irq1 tacon, tbcon tadata, tbdata f3h, f2h, bank 0 f1h, f0h, bank 0 sio interrupt irq2 siops, siocon sio f6h, f5h, bank 0 f4h, bank 0 watch timer overflow irq4 wtcon fbh, bank 0 p2.7 external interrupt p2.6 external interrupt p2.5 external interrupt p2.4 external interrupt irq5 p2conh p2int e4h, bank 1 e6h, bank 0 p4.7 external interrupt p4.6 external interrupt p4.5 external interrupt p4.4 external interrupt irq6 p4conh p4int p4pnd p4edge e8h, bank 1 e7h, bank 0 e8h, bank 0 e9h, bank 0 p4.3 external interrupt p4.2 external interrupt p4.1 external interrupt p4.0 external interrupt irq7 p4conl p4int p4pnd p4edge e9h, bank 1 e7h, bank 0 e8h, bank 0 e9h, bank 0 note : b ecause the timer 0 overflow interrupt is cleared by hardware, the t0con register controls only the enable/disable function s . the t0con register contains enable/dis able and pending bits for the timer 0 match/capture interrupt.
interrupt structure s3c821a/p821a 5- 10 system mode register (sym ) the system mode register, sym (set 1, deh), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see figure 5-5). a reset clears sym.7, sym.1, and sym.0 to "0". the 3-bit value for fast interrupt level selection, sym.4 - sym.2, is undetermined. the instructions ei and di enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the sym register. i n order to enable interrupt processing , a n enable interrupt (ei) instruction must be included in the initialization routine, which follows a reset operation. although you can manipulate sym.0 directly to enable and disable interrupts during the normal operation, it is recommended to use the ei and di instructions for this purpose. system mode register (sym) deh, set 1, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 external interface tri-state enable bit: 0= normal operation (tri-state disabled) 1= set external interface lines to high impedance (tri-state enabled) not used for the s3c821a fast interrupt level selection bits: global interrupt enable bit: 0 = disable all interrupts processing 1 = enable all interrupts processing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 irq0 irq1 irq2 not used irq4 irq5 irq6 irq7 fast interrupt enable bit: 0 = disable fast interrupts processing 1 = enable fast interrupts processing figure 5-5. system mode register (sym )
s3c821a/p821a interrupt structure 5 - 11 interrupt mask register (imr ) the interrupt mask register, imr (set 1, ddh) is used to enable or disable interrupt processing for individual interrupt levels. after a reset, all imr bit values are undetermined and must therefore be written to their required settings by the initialization routine. each imr bit corresponds to a specific interrupt level: bit 1 to irq1, bit 2 to irq2, and so on. when the imr bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). when you set a level's imr bit to "1", interrupt processing for the level is enabled (not masked). the imr register is mapped to register location ddh in set 1. bit values can be read and written by instructions using the register addressing mode. interrupt mask register (imr) ddh, set 1, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 irq7 irq6 irq5 irq4 not used irq2 irq1 irq0 interrupt level enable bits (7?4, 2?0): 0 = disable (mask) interrupt level 1 = enable (un-mask) interrupt level figure 5-6. interrupt mask register (imr )
interrupt structure s3c821a/p821a 5- 12 interrupt priority register (ipr ) the interrupt priority register, ipr (set 1, bank 0, ffh), is used to set the relative priorities of the interrupt levels in the microcontroller?s interrupt structure. after a reset, all ipr bit values are undetermined and must therefore be written to their required settings by the initialization routine. when more than one interrupt source s are active, the source with the highest priority level is serviced first. if two sources belong to the same interrupt level, the source with the lowe r vector address usually has the priority (this priority is fixed in hardware) . to support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. please note that these groups (and subgroups) are used only by ipr logic for the ipr register priority definitions (see figure 5-7): group a irq0, irq1 group b irq 2, irq4 group c irq5, irq6 , irq7 irq0 irq1 irq2 a1 a2 ipr group a ipr group b irq4 b1 ipr group c b2 c1 irq5 irq6 irq7 c2 c3 figure 5-7. interrupt request priority groups as you can see in figure 5-8, ipr.7, ipr.4, and ipr.1 control the relative priority of interrupt groups a, b, and c. for example, the setting " 001b " for these bits would select the group relationship b > c > a . t he setting " 101b " would select the relationship c > b > a. the functions of the other ipr bit settings are as follows: ? ipr.5 controls the relative priorities of group c interrupts. ? interrupt group c includes a subgroup that has an additional priority relationship among the interrupt levels 5 , 6 , and 7 . ipr. 6 defines the subgroup c relationship . ipr. 5 controls the interrupt group c . in the s3c821a implementation, the interrupt level 3 is not used. therefore, ipr.3 setting is not evaluated. ? ipr.0 controls the relative priority setting of irq0 and irq1 interrupts.
s3c821a/p821a interrupt structure 5 - 13 group c 0 = irq5 > (irq6, irq7) 1 = (irq6, irq7) > irq5 interrupt priority register (ipr) ffh, set 1, bank 0, r/w group a 0 = irq0 > irq1 1 = irq1 > irq0 group b 0 = irq2 > irq4 1 = irq4 > irq2 subgroup b (note) 0 = irq4 1 = irq4 group priority: d7 0 0 0 0 1 1 1 1 d4 0 0 1 1 0 0 1 1 d1 0 1 0 1 0 1 0 1 = = = = = = = = undefined b > c > a a > b > c b > a > c c > a > b c > b > a a > c > b undefined msb lsb .7 .6 .5 .4 .3 .2 .1 .0 subgroup c 0 = irq6 > irq7 1 = irq7 > irq6 note : in the s3c821a interrupt structure, only the levels irq0-irq2, and irq4-irq7 are used. the setting for subgroup b, which controls relative priorities for the level irq3 is therefore not evaluated. figure 5-8. interrupt priority register (ipr )
interrupt structure s3c821a/p821a 5- 14 interrupt request register (irq ) you can poll bit values in the interrupt request register, irq (set 1, dch), to monitor interrupt request status for all levels in the microcontroller?s interrupt structure. each bit corresponds to the interrupt level of the same number: bit 0 to irq0, bit 1 to irq1, and so on. a "0" indicates that no interrupt request is currently being issued for that level . a "1" indicates that an interrupt request has been generated for that level. irq bit values are read-only addressable using register addressing mode. you can read (test) the contents of the irq register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. after a reset, all irq status bits are cleared to ?0?. you can poll irq register values even if a di instruction has been executed (that is, if global interrupt processing is disabled). if an interrupt occurs while the interrupt structure is disabled, the cpu will not service it. you can, however, still detect the interrupt request by polling the irq register. in this way, you can determine which events occurred while the interrupt structure was globally disabled. interrupt request register (irq) dch, set 1, read-only msb lsb .7 .6 .5 .4 .3 .2 .1 .0 irq7 irq6 irq5 irq4 not used irq2 irq1 irq0 0 = interrupt level is not pending 1 = interrupt level is pending interrupt level request pending bits: figure 5-9. interrupt request register (irq )
s3c821a/p821a interrupt structure 5 - 15 interrupt pending function types overview there are two types of interrupt pending bits: o ne type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine. pending bits cleared automatically by hardware for interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. it then issues an irq pulse to inform the cpu that an interrupt is waiting to be serviced. the cpu acknowledges the interrupt source by sending an iack, executes the service routine, and clears the pending bit to "0". this type of pending bit is not mapped and cannot, therefore, be read or written by application software. in the s3c821a interrupt structure, the timer 0 overflow interrupt (irq0 ) belongs to this category of interrupts in which pending condition is cleared automatically by hardware. pending bits cleared by the service routine the second type of pending bit is the one that should be cleared by program software. the service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (iret) occurs. to do this, a "0" must be written to the corresponding pending bit location in the source?s mode or control register. in the s3c821a interrupt structure, pending conditions for all interrupt sources , except the timer 0 overflow interrupt , must be cleared in the interrupt service routine.
interrupt structure s3c821a/p821a 5- 16 interrupt source polling sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by settin g the interrupt request bit to "1". 2. the cpu polling procedure identifies a pending condition for that source. 3. the cpu checks the source's interrupt level. 4. the cpu generates an interrupt acknowledge signal. 5. interrupt logic determines the interrupt's vector address. 6. the service routine starts and the source's pending bit is cleared to "0" (by hardware or by software). 7. the cpu continues polling for interrupt requests. interrupt service routines before an interrupt request is serviced, the following conditions must be met: ? interrupt processing must be globally enabled (ei, sym.0 = "1") ? the interrupt level must be enabled (imr register) ? the interrupt level must have the highest priority if more than one level s are currently requesting service ? the interrupt must be enabled at the interrupt's source (peripheral control register) when all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the interrupt enable bit in the sym register (sym.0) to disable all subsequent interrupts. 2. save the program counter (pc) and status flags to the system stack. 3. branch to the interrupt vector to fetch the address of the service routine. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, the cpu issues an interrupt return (iret). the iret restores the pc and status flags , set ting sym.0 to "1" . it allows the cpu to process the next interrupt request.
s3c821a/p821a interrupt structure 5 - 17 generating interrupt vector addresses the interrupt vector area in the rom (00h ? ffh) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to the stack. 2. push the program counter's high-byte value to the stack. 3. push the flag register values to the stack. 4. fetch the service routine 's high-byte address from the vector location. 5. fetch the service routine's low-byte address from the vector location. 6. branch to the service routine specified by the concatenated 16-bit vector address. note a 16-bit vector address always begins at an even-numbered rom address within the range of 00h ? ffh. nesting of vectored interrupts it is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. to do this, you must follow these steps: 1. push the current 8-bit interrupt mask register (imr) value to the stack (push imr). 2. load the imr register with a new mask value that enables only the higher priority interrupt. 3. execute an ei instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). 4. when the lower-priority interrupt service routine ends, restore the imr to its original value by returning the previous mask value from the stack (pop imr). 5. execute an iret. depending on the application, you may be able to simplify the procedure above to some extent. instruction pointer (ip ) the instruction pointer (ip) is adopted by all the s3c 8-series microcontrollers to control the optional high-speed interrupt processing feature called fast interrupts . the ip consists of register pair dah and dbh. the names of ip register s are iph (high byte, ip15 ? ip8) and ipl (low byte, ip7 ? ip0). fast interrupt processing the feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately six clock cycles rather than the usual 22 clock cycles. to select a specific interrupt level for fast interrupt processing, you write the appropriate 3-bit value to sym.4 ? sym.2. then, to enable fast interrupt processing for the selected level, you set sym.1 to ?1?.
interrupt structure s3c821a/p821a 5- 18 fast interrupt processing ( continued) two other system registers support fast interrupt processing: ? the instruction pointer (ip) contains the starting address of the service routine (and is later used to swap the program counter values), and ? when a fast interrupt occurs, the contents of the flags register is stored in an unmapped, dedicated register called flags' (?flags prime?). note for the s3c821a microcontroller, the service routine for any one of the seven interrupt levels: irq0? irq2, or irq4? irq 7 , can be selected for fast interrupt processing. procedure for initiating fast interrupts to initiate fast interrupt processing, follow these steps: 1. load the start address of the service routine into the instruction pointer (ip). 2. loa d the interrupt level number (irqn) into the fast interrupt selection field (sym.4 ? sym.2) 3. write a "1" to the fast interrupt enable bit in the sym register. fast interrupt service routine when an interrupt occurs in the level selected for fast interrupt processing, the following events occur: 1. the contents of the instruction pointer and the pc are swapped. 2. the flag register values are written to the flags' ( ?flags prime?) register. 3. the fast interrupt status bit in the flags register is set. 4. the interrupt is serviced. 5. assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction pointer and pc values are swapped back. 6. the content of flags' ( ?flags prime?) is copied automatically back to the flags register. 7. the fast interrupt status bit in flags is cleared automatically. relationship to interrupt pending bit types as described previously, there are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed ; the other that must be cleared by the application program's interrupt service routine. you can select fast interrupt processing for interrupts with either type of pending condition clear function ? by hardware or by software. programming guidelines remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the sym register, sym.1. executing an ei or di instruction globally enables or disables all interrupt processing, including fast interrupts. if you use fast interrupts, remember to load the ip with a new start address when the fast interrupt service routine ends.
s3c821a/p821a clock circuit s 7- 1 7 clock circuits overview the s3c821a microcontroller has two oscillator circuits: a main system clock, and a subsystem clock circuit. the cpu and peripheral hardware operate on the system clock frequency supplied through these circuits. the maximum cpu clock frequency is determined by clkcon register settings . system clock circuit the system clock circuit has the following components: ? external crystal , ceramic resonator , an external clock , or rc oscillation source ? oscillator stop and wake-up functions ? programmable frequency divider for the cpu clock (f x divided by 1, 2, 8, or 16 or fxt ) ? clock circuit control register, clkcon system clock notation in this document, the following notation is used for descriptions of the system clock: fx main system c lock fxt subsystem clock fxx selected system clock for peripheral hardware fcpu cpu clock
clock circuit s s3c821a/p821a 7- 2 main system oscillator circuits xin xout figure 7-1. crystal/ceramic oscillator xin xout external clock figure 7-2. external oscillator xin xout r figure 7-3. rc oscillator subsystem oscillator circuits xtin xtout 32.768 khz figure 7-4. crystal/ceramic oscillator xtin xtout figure 7-5. external oscillator
s3c821a/p821a clock circuit s 7- 3 clock status during power-down modes the two power-down modes, stop mode and idle mode, affect the system clock as follows: ? in stop mode, the main oscillator is halted. stop mode is released, and the oscillator is started, by a reset operation , by a watch timer overflow interrupt (when the watch timer clock source is subsystem clock) or by an external interrupt (when the fx is selected as cpu clock) . ? in idle mode, the internal clock signal is gated away from the cpu, but it continues to be supplied to the interrupt structure , basic timer, timer 0, timer 1, a/d converter, and watch timer . idle mode is released by a reset or by an interrupt ( external ly generated or internal ly generated) . clkcon.5,.6 main osc noise filter oscillator wake-up oscillator stop clkcon.7 int pin (1) clkcon.3,.4 stop instruction m u x fx clkcon.5,.6 (4) sub osc fxt m u x sclkcon.0 basic timer timer counter0, 1 watch timer a/d converter cpu clock sio fxx clkcon.0-.2 3-bit signature code (2) notes: 1. an external interrupt can be used to release stop mode and "wake up" the main oscillator. 2. the sub oscillator can be halted only by sclkcon.0. sub oscillation stop can be released only by a reset operation. 3. when sub and main oscillator are halted in main operation mode, stop mode can be released by an external interrupt, or a reset operation. 4. although sub clock (fxt) is selected as cpu clock (fcpu), the selected clock (fxx) for basic timer, timer counter 0/1, watch timer, and a/d converter is main clock if the value of clkcon.6-.5 are not "10b (value to stop main clock)". fcpu 1/2 1/8 1/16 m u x figure 7- 6 . system clock circuit diagram
clock circuit s s3c821a/p821a 7- 4 system clock control register (clkcon ) the system clock control register, clkcon , is located in set 1, address d4h. it is read/write addressable and has the following functions: ? oscillator irq wake-up function enable/disable ? oscillator frequency divide-by value ? system clock signal selection clkcon register settings control whether or not an external interrupt can be used to trigger a stop mode release (this is called the "irq wake-up" function) . the irq ?wake-up? enable bit is clkcon.7. after a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the f x /16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can raise the cpu clock speed to f x , f x /2, f x /8 , or fxt (subsystem clock) . for the s3c821a microcontroller, the clkcon.2 - clkcon.0 system clock signature code can be any value (the " 101b " setting selects subsystem clock as cpu clock ) . the reset value for the clock signature code is " 000b ". msb lsb .7 .6 .5 .4 .3 .2 .1 .0 system clock control register (clkcon) d4h, set 1, r/w subsystem clock selection bits: 101 b = select subsystem clock other value = select main system clock divide-by selection bits for cpu clock frequency: 00 = fx/16 or fxt 01 = f x /8 or fxt 10 = fx /2 or fxt 11 = fx or fxt (non-divided) oscillator irq wake-up enable bit: 0 = enable irq for main system oscillator wake-up function 1 = disable irq for main system oscillator wake-up function main oscillator stop control bits: 00 = no effect 01 = no effect 10 = stop main oscillator 11 = no effect note: although the value of clkcon.6-.5 are ?10b (value to stop main clock)?, main clock is not stopped if main system clock (fx) is selected as cpu clock (fcpu). (note) figure 7- 7 . system clock control register (clkcon )
s3c821a/p821a clock circuit s 7- 5 switching the cpu clock data loadings in the system clock control register, clkcon, determine whether a main or a sub clock is selected as the cpu clock, the system clock for peripheral hardware, and also how this frequency is to be divided. this makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies. clkcon.2?.0 select the main clock (fx) or a sub clock (fxt). clkcon.6?.5 start or stop main clock oscillation. clkcon.4?.3 control the frequency divider circuit, and divide the selected fx clock by 1, 2, 8, or 16, or fxt clock by 1. let's say that, you are using the default cpu clock (normal operating mode and a main clock of fx/16) and you want to switch from the fx clock to a sub clock and to stop the main clock. to do this, you need to set clkcon.2?.0 to "101b" and clkcon.6?.5 to "10b" simultaneously. this switches the clock from fx to fxt and stops main clock oscillation. the following steps must be taken to switch from a sub clock to the main clock: first, set clkcon.6?.5 to any value except "10b" to enable main system clock oscillation. then, after a certain number of machine cycles has elapsed, select the main clock by setting clkcon.2?.0 to any value except "101b". you must remember that the selected clock (fxx) for the basic timer, timer counter 0/1, watch timer, and a/d converter is the main clock during the interval time. refer to "figure 7-6. system clock circuit diagram." + + programming tip ? switching the cpu clock 1. this example shows how to change from the main clock to the sub clock: ma2sub ld clkcon,#5dh ; switches to the sub clock ; stop the main clock oscillation ret 2. this example shows how to change from the sub clock to the main clock: sub2ma and clkcon,#9fh ; start the main clock oscillation call dly20 ; delay 20 ms and clkcon,#98h ; switch to the main clock ret dly20 srp #0c0h ld r0,#1bh del nop nop djnz r0,del ret
clock circuit s s3c821a/p821a 7- 6 sub-system clock control register (sclkcon) the sub-system clock control register, sclkcon, is located in set 1, bank 1, address ffh. it is read/write addressable and has sub-system clock stop function. sclkcon register setting controls whether sub-system clock is halted or not. after a reset, all clkcon register and sclkcon register values are cleared to logic zero, both main-system clock and sub-system clock oscillation start, but main-system clock oscillation is selected as the cpu clock. main-system clock oscillation or sub-system clock oscillation can be halted by manipulating clkcon.6?.5 or sclkcon.0 respectively. at that time, oscillation stop can't be restarted by any interrupt but manipulating clkcon or sclkcon. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 sub-system clock control register (sclkcon) ffh, set 1, bank 1, r/w sub-system clock stop enable bit: 0 = enable sub-system clock 1 = disable sub-system clock not used for the notes : 1. the sub oscillator can be halted only by sclkcon.0. sub oscillation stop can be released only by a reset operation. 2. when sub and main oscillator are halted in main opearating mode, stop mode can be released by an external interrupt or a reset operation. figure 7-8. sub-system clock control register (sclkcon)
s3c821a/p821a reset reset and power-down 8- 1 8 reset reset and power-down system reset overview during a power-on reset, the voltage at v dd goes to high level and the reset pin is forced to low level. the reset signal is input through a s chmitt trigger circuit where it is then synchronized with the cpu clock. this procedure brings the s3c821a into a known operating status. to allow time for internal cpu clock oscillation to stabilize, the reset pin must be held to low level for a minimum time interval after the power supply comes within tolerance. the minimum required time of a reset operation for oscillation stabilization is 1 millisecond. whenever a reset occurs during normal operation (that is, when both v dd and reset are high level), the reset pin is forced low level and the reset operation starts. all system and peripheral control registers are then reset to their default hardware values (see table 8-1). in summary, the following sequence of events occurs during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? ports 0 , 1, 2, 3, 4, and 5 are set to input mode and all pull-up resistors are disabled for the i/o port pin circuits . ? perip heral control and data register settings are disabled and reset to the ir default hardware values (see table 8-1) . ? the program counter (pc) is loaded with the program reset address in the rom, 0100h. ? when the programmed oscillation stabilization time interval has elapsed, the instruction stored in rom location 0100h (and 0101h) is fetched and executed. note to program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing " 1010b " to the upper nibble of btcon.
reset reset and power-down s3c821a/p821a 8 - 2 hardware reset values table 8-1 list the reset values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation. the following notation is used to represent reset values: ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an " x " means that the bit value is undefined after a reset. ? a dash ( " ? " ) means that the bit is either not used or not mapped (but a ?0? is read from the bit position) . table 8-1. set 1 register values after reset register name mnemonic address bit values after reset dec hex 7 6 5 4 3 2 1 0 timer 0 counter t0cnt 208 d0h 0 0 0 0 0 0 0 0 timer 0 data register t0data 209 d1h 1 1 1 1 1 1 1 1 timer 0 control register t0con 210 d2h 0 0 0 0 0 0 0 0 basic timer control register btcon 211 d3h 0 0 0 0 0 0 0 0 clock control register clkcon 212 d4h 0 0 0 0 0 0 0 0 system flags register flags 213 d5h x x x x x x 0 0 register pointer 0 rp0 214 d6h 1 1 0 0 0 ? ? ? register pointer 1 rp1 215 d7h 1 1 0 0 1 ? ? ? stack pointer (high byte) sph 216 d8h x x x x x x x x stack pointer (low byte) spl 217 d9h x x x x x x x x instruction pointer (high byte) iph 218 dah x x x x x x x x instruction pointer (low byte) ipl 219 dbh x x x x x x x x interrupt request register irq 220 dch 0 0 0 0 0 0 0 0 interrupt mask register imr 221 ddh x x x x ? x x x system mode register sym 222 deh 0 ? ? x x x 0 0 register page pointer pp 223 dfh 0 0 0 0 0 0 0 0
s3c821a/p821a reset reset and power-down 8- 3 table 8 - 2 . set 1, bank 0 register values after reset register name mnemonic address bit values after reset dec hex 7 6 5 4 3 2 1 0 port 0 data register p0 224 e0h 0 0 0 0 0 0 0 0 port 1 data register p1 225 e1h 0 0 0 0 0 0 0 0 port 2 data register p2 226 e2h 0 0 0 0 0 0 0 0 port 3 data register p3 227 e3h 0 0 0 0 0 0 0 0 port 4 data register p 4 22 8 e 4 h 0 0 0 0 0 0 0 0 port 5 data register p 5 22 9 e 5 h ? 0 0 0 0 0 0 0 port 2 interrupt control register p2int 23 0 e 6 h 0 0 0 0 0 0 0 0 port 4 interrupt control register p4int 23 1 e 7 h 0 0 0 0 0 0 0 0 port 4 interrupt pending register p4pnd 232 e8h 0 0 0 0 0 0 0 0 port 4 interrupt edge select register p4edge 233 e9h 0 0 0 0 0 0 0 0 locations eah?edh are not mapped. timer b counter tbcnt 2 38 ee h 0 0 0 0 0 0 0 0 timer a counter tacnt 2 39 ef h 0 0 0 0 0 0 0 0 timer b data register tbdata 24 0 f 0 h 1 1 1 1 1 1 1 1 timer a data register tadata 24 1 f 1 h 1 1 1 1 1 1 1 1 timer b control register tbcon 24 2 f 2 h ? ? 0 0 0 0 0 0 timer a control register tacon 24 3 f 3 h 0 0 0 0 0 0 0 0 sio data register sio 244 f4h 0 0 0 0 0 0 0 0 sio control register siocon 245 f5h 1 0 0 0 0 0 0 0 sio prescaler register siops 246 f6h 0 0 0 0 0 0 0 0 adc control register adcon 247 f7h ? 0 0 0 0 0 0 0 adc data register addata 248 f8h x x x x x x x x location f9h is not mapped. lcd control register lcon 250 fah 0 0 ? ? 0 0 0 0 watch timer mode register wtcon 251 f b h 0 0 0 0 0 0 0 0 location fch is not mapped. basic timer counter btcnt 253 fdh x x x x x x x x external memory timing register emt 254 feh ? ? ? ? ? ? 0 ? interrupt priority register ipr 255 ffh x x x x x x x x notes: 1. except for t0cnt, irq, tacnt, tbcnt, adcon.3, addata, btcnt, and fis flag which are read-only, all registers in set 1 are read/write addressable. 2. you cannot use a read- only register as a destination field for the instructions or, and, ld, and ldb .
reset reset and power-down s3c821a/p821a 8 - 4 table 8 - 3 . set 1, bank 1 register values after reset register name mnemonic address bit values after reset dec hex 7 6 5 4 3 2 1 0 port 0 control register p0con 224 e0h 0 0 0 0 0 0 0 0 location e1h is not mapped. port 1 control register p1con 226 e2h 0 0 0 0 0 0 0 0 location e3h is not mapped. port 2 control register (high byte) p2conh 228 e4h 0 0 0 0 0 0 0 0 port 2 control register (low byte) p2conl 229 e5h 0 0 0 0 0 0 0 0 port 3 control register (high byte) p3conh 230 e6h 0 0 0 0 0 0 0 0 port 3 control register (low byte) p3conl 231 e7h 0 0 0 0 0 0 0 0 port 4 control register (high byte) p4conh 232 e8h 0 0 0 0 0 0 0 0 port 4 control register (low byte) p4conl 233 e9h 0 0 0 0 0 0 0 0 port 5 control register (high byte) p5conh 234 eah ? ? 0 0 0 0 0 0 port 5 control register (low byte) p5conl 235 ebh 0 0 0 0 0 0 0 0 locations ech?feh are not mapped. sub-clock control register sclkcon 255 ffh ? ? ? ? ? ? ? 0 note: you cannot use a read-only registe r as a destination for the instructions or, and, ld, or ldb.
s3c821a/p821a reset reset and power-down 8- 5 power-down modes stop mode stop mode is invoked by the instruction stop . in stop mode, the operation of the cpu and main oscillator is halted. al l peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops. that is, the watch timer and lcd controller will not halted in stop mode if the subsystem clock is selected as watch timer clock source. the data stored in the internal register file are retained in stop mode. stop mode can be released in one of three ways: by a system reset, by an internal watch timer interrupt (when subsystem clock is selected as clock source of watch timer), or by an external interrupt . example: stop nop nop nop using reset reset to release stop mode stop mode is released when the reset signal goes active ( low level): all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. when the programmed oscillation stabilization interval has elapsed, the cpu starts the system initialization routine by fetching the program instruction stored in rom location 0100h. using an external interrupt to release stop mode e xternal interrupts can be used to release s top mode . for the s3c821a microcontroller , we recommend using the int0 ?int11 interrupt though p2.4?p2.7, p4.0?p4.7. using an internal interrupt to release stop mode an internal interrupt, watch timer, can be used to release stop mode because, the watch timer operates in stop mode if the clock source of watch timer is subsystem clock. if system clock is subsystem clock, you can't use any interrupts to release stop mode. that is, you had batter use the idle instruction instead of stop one when subsystem clock is selected as the system clock. please note the following conditions for stop mode release: ? if you release s top mode using an internal or external interrupt, the current values in system and peripheral control registers are unchanged. ? if you use an internal or external interrupt for s top mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering s top mode. ? if you use an interrupt to release s top mode, the b it-pair setting for clkcon.4/clkcon.3 remains unchanged and the currently selected clock value is used. the internal or external interrupt is serviced when the s top mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated s top mode is executed. note do not use stop mode if you are using an external clock source because x in input must be cleared internally to v ss to reduce current leakage, and do not configure any pins to floating node in stop mode to reduce power consumption.
reset reset and power-down s3c821a/p821a 8 - 6 idle mode idle mode is invoked by the instruction idle. in idle mode, cpu operations are halted while some peripherals remain active. during idle mode, the internal clock signal is gated away from the cpu and from all but the following peripherals, which remain active: ? interrupt logic ? basic timer ? timer 0 ? timer 1 (timer a and b) ? watch timer ? lcd controller ? a/d converter i/o port pins retain the mode (input or output) they had at the time idle mode was entered. external interface pins are halted by high or low level, in the idle mode. idle mode release you can release idle mode in one of two ways: 1. execute a reset. all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects the slowest clock (1/16) because of the hardware reset value for the clkcon register. if all external interrupts are masked in the imr register, a reset is the only way you can release idle mode. 2. activate any enabled interrupt ? internal or external. when you use an interrupt to release idle mode, the 2 - bit clkcon.4/clkcon.3 value remains unchanged, and the currently selected clock value is used. the interrupt is then serviced. when the return-from-interrupt condition (iret) occurs, the instruction immediately following the one which i nitiated idle mode is executed.
s3c821a/p821a i/o ports 9- 1 9 i/o ports overview the s3c821a microcontroller has two nibble-programmable and four bit-programmable i/o ports , p0-p5. the ports from p0 to p4 are 8-bit ports and port 5 is a 7-bit port. this gives a total of 47 i/o pins . each port can be flexibly configured to meet application design requirements. the cpu accesses ports by directly writing or reading port registers. no special i/o instructions are required. table 9-1 gives y ou a general overview of the s3c821a i/o port functions. table 9-1. s3c821a port configuration overview port configuration options 0 4-bit -programmable i/o port . pull-up resistors and open-drain outputs are software assignable . pull-up resistors are automatically disabled for output pins . configurable as lcd segments/external interface address lines. 1 4-bit -programmable i/o port . pull-up resistors and open-drain outputs are software assignable . pull-up resistors are automatically disabled for output pins . configurable as lcd segment/external interface address and data lines. 2 1-b it-programmable i/o port . pull-up resistors are software assignable , and automatically disabled for output pins . p2.0? p2.3 can alternately be used as external interface lines. p2.4?p2.7 are configurable as alternate functions or external interrupts at falling edge with noise filters. 3 1-b it-programmable i/o port . pull-up resistors are software assignable , and automatically disabled for output pins . p3.0?p3.3 can alternately be used as adc. p3.7 is configurable as an alternate function. 4 1-b it-programmable i/o port . pull-up resistors and open-drain outputs are software assignable . pull-up resistors are automatically disabled for output pins . p4.0?p4.7 are configurable as external interrupts at a selectable edge with noise filters. 5 1-b it-programmable i/o port . pull-up resistors are software assignable , and automatically disabled for output pins . p5.0?p5.3 are configurable as alternate functions. when sck and si are used as input, these pins have noise filters.
i/o ports s3c821a/p8 21a 9- 2 port data registers table 9-2 gives you an overview of t he register locations of all four s3c821a i/o port data registers. data registers for ports 0 , 1, 2, 3, 4, and 5 have the general format shown in figure 9-1 . table 9-2. port data register summary register name mnemonic decimal hex location r/w port 0 data register p0 224 e0h set 1 , bank 0 r/w port 1 data register p1 225 e1h set 1 , bank 0 r/w port 2 data register p2 226 e2h set 1 , bank 0 r/w port 3 data register p3 227 e3h set 1 , bank 0 r/w port 4 data register p 4 228 e 4 h set 1 , bank 0 r/w port 5 data register p 5 229 e 5 h set 1 , bank 0 r/w i/o port data register format (n = 0-5) msb lsb .7 .6 .5 .4 .3 .2 .1 .0 pn.7 pn.6 pn.5 pn.4 pn.3 pn.2 pn.1 pn.0 note: when n=5, p5.7 does not exist. figure 9-1. s3c821a i/o port data register format
s3c821a/p821a i/o ports 9- 3 port 0 port 0 pins p0.0?p0.7 can be configured on a nibble basis for general data input or output. when configured as outputs, the pins in each nibble may optionally be set to open-drain. you can alternately configure port 0 as additional address lines (a8?a15) for the external peripheral interface. it is possible to configure the lower nibble as external interface address lines a8?a11, and to use the upper nibble pins for general i/o. to access port 0, you should write or read the port 0 data register, p0 (r224, e0h, bank 0) in set 1. the port 0 data register can't be written, however, when port 0 bits are configured as address lines for the external interface: writing has no effect and reading only loads p0 data register with the state of the pin. port 0 control register the port 0 control register, p0con (r224, e0h, set 1, bank 1), controls the direction of the i/o lines and allows an optional selection of pull-up resistor in input mode, and that of open-drain, or push-pull in output modes. the p0con setting "1xxxb" for each nibble configures the pins as external interface lines. the bits 4-7 control the upper nibble pins, p0.4?p0.7, and the bits 0-3 control the lower nibble pins, p0.0?p0.3. in normal operating mode, a reset operation clears all p0con register values to "0". if you want to configure an external memory area, you can use a routine to set the p0con value to "1xxx1xxxb". this setting correctly configures the address lines a8?a11 (lower nibble) and a12?a15 (upper nibble). i/o port 0 control register (p0con) r224, e0h, set 1, bank 1, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 upper nibble port configuration low er nibble port configuration 7 (3) 0 0 0 0 0 1 port mode selection input mode input, pull-up mode output, push-pull mode output, open-drain mode lcd segment (seg23-seg16) external interface (a15-a8) 6 (2) 0 1 0 0 1 x 4 (0) 0 0 1 1 1 x 5 (1) x x 0 1 x x (?x? means don?t care.) figure 9-2 . port 0 control register (p0con )
i/o ports s3c821a/p8 21a 9- 4 port 1 port 1 is basically identical to port 0, except for its alternate use as multiplexed address/data lines for the external interface. (port 0 can alternately be configure d as additional address lines a8 ? a15.) port 1 pins , p1.0 ? p1.7 , can be configured on a nibble basis for general data input or output. when configured as outputs, the pins in each nibble may optionally be set to open-drain. you can alternately configure port 0 as additional address/data lines (ad0 ?ad7) for external peripheral interface. to access port 1, you should write or read the port 1 data register, p1 (r225, e1h , bank 0 ) in set 1. the port 1 data register cannot be written, however, when the port 1 bits are configured as address lines for external interface: writing has no effect and reading only loads p1 data register with the state of the pin. port 1 control register the port 1 control register, p1con (r 226 , e2 h, set 1 , bank 1 ), controls the direction of the i/o lines and allows an optional selection of pull-up resistor in input mode, and that of open-drain, or push-pull in output mode . the p1con setting " 1xxxb " for each nibble configures the pins as external interface lines. the b its 4 ? 7 control the upper nibble pins, p1.4 ? p1.7, and the bits 0 ? 3 control the lower nibble pins, p1.0 ? p1.3. in normal operating mode a reset operation clears all p 1 con register values to "0". if you want to configure an external memory area, you can use a routine to set the p 1 con value to " 1xxx1xxxb " . this setting correctly configures the address/data lines ad0 ? ad7. i/o port 1 control register (p1con) r226, e2h, set 1, bank 1, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 upper nibble port configuration low er nibble port configuration 7 (3) 0 0 0 0 0 1 port mode selection input mode input, pull-up mode output, push-pull mode output, open-drain mode lcd segment (seg31 - seg24) external interface (ad7-ad0) 6 (2) 0 1 0 0 1 x 4 (0) 0 0 1 1 1 x 5 (1) x x 0 1 x x (?x? means don?t care.) figure 9- 3. port 1 control register (p1con)
s3c821a/p821a i/o ports 9- 5 port 2 port 2 is an 8-bit i/o port with individually configurable pins. it is accessed directly by writing or reading the port 2 data register, p2 (r226, e2h , bank 0 ) in set 1. you can use port 2 for general i/o, or for the following alternative functions: ? p2.0 ? p2. 3 can be configured as multiplexed external interface bus control lines for as (address strobe) signals , dr (data read) , d w (data write ), and dm (data memory). ? p2. 4? p2.7 can be configured, respectively, as t0ck (t0 clock input), t1ck (t1 clock input), ta, and tb output. the special functions that you can program using the port 2 high byte control register must also be enabled in the associated peripheral. also, when using port 2 pins for functions other than general i/o, you must still set the corresponding port 2 control register value to configure each bit to input or output mode. port 2 control register s two 8-bit control registers are used to configure port 2 pins: p2conh ( e4 h, set 1 , bank 1 ) for pins p2.4 ? p2.7 and p2conl ( e5 h, set 1 , bank 1 ) for pins p2.0 ? p2.3. each byte contains four bit-pairs and each bit-pair configures one port 2 pin. the p2conh and the p2conl registers also control the alternative functions described above. port 2 high-byte control register (p2conh) four bit-pairs in the port 2 control register (p 2conh) configure the port 2 pins, p2.4? p2.7 , to s chmitt trigger input , schmitt trigger input with pull-up resistor, or push-pull output mode. table 9 - 3. port 2 data register summary (high nibbles) p2con h bit-pair corresponding port 2 pin alternate pin function bits 0 and 1 p2.4 t0 output or capture input (t0ck) bits 2 and 3 p2.5 t0 clock input (t1ck) bits 4 and 5 p2.6 clock output (ta) bits 6 and 7 p2.7 clock output (tb)
i/o ports s3c821a/p8 21a 9- 6 port 2 control register, hitgh byte (p2conh) r228, e4h, set 1, bank 1, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 p2.7/tb p2.6/ta p2.5/t1ck p2.4/t0ck p2conh bit-pair pin configuration settings: 00 schmitt trigger input mode (or t0ck/t1ck input for p2.4/p2.5) 01 schmitt trigger input, pull-up mode (or t0ck/t1ck input for p2.4/p2.5) 10 output, push-pull mode 11 select alternative function for p2.6 and p2.7 p2.4 and p2.5 remain ?0? state figure 9 -4 . port 2 high-byte c ontrol register (p2conh) port 2 low-byte control register (p2conl) the low-byte port 2 pins, p2.0 ? p2.3, can be configured individually as s chmitt trigger inputs , schmitt trigger input with pull-up resistor, or as push-pull outputs. you can alternately configure these pins as multiplexed bus control signal lines for external interface. to select the bus signal function, you must set the related bit-pairs to " 11b " . table 9 - 4. port 2 data register summary (low nibbles) p2con l bit-pair corresponding port 2 pin alternate pin function bits 0 and 1 p2.0 address strobe ( as ) bits 2 and 3 p2.1 data read ( dr ) bits 4 and 5 p2.2 data write ( d w ) bits 6 and 7 p2.3 data memory ( dm )
s3c821a/p821a i/o ports 9- 7 port 2 control register, low byte (p2conl) r229, e5h, set 1, bank 1, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 p2.3/ dm p2.2/ dw p2.1/ dr p2.0/ as 00 schmitt trigger input mode 01 schmitt trigger input, pull-up mode 10 output, push-pull mode 11 external memory interface line p2conl bit-pair pin configuration settings: figure 9-5 . port 2 low-byte control register (p2con l ) interrupt control settings (n = 4, 5, 6, 7) 0 = disable interrupt on p2.n 1 = enable interrupt at falling edge on p2.n port 2 interrupt register (p2int) r230, e6h, set 1, bank 0, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 p2.7/int3 p2.6/int2 p2.5/int1 p2.4/int0 p2int bit-pair pin configuration settings: bits 0, 2, 4, 6 interrupt request pending bits 0 = no interrupt request pending 0 = clear pending bit (when write) 1 = interrupt request is pending bits 1, 3, 5, 7 figure 9-6. port 2 interrupt register (p2int)
i/o ports s3c821a/p8 21a 9- 8 port 3 port 3 can serve as a general-purpose 8-bit i/o port , or support alternative functions (t0cap input or t0pwm/t0 output for p3.7 and a/d converter inputs for p3.0?p3.3) . port 3 is accessed directly by writing or reading the port 3 data register, p 3 (r22 7 , e 3 h , bank 0 ) in set 1 . ? p3.0?p3.3 can be configured, respectively, as adc0?adc3 input. ? p3.7 can be configured as t0cap input, t0pwm, or t0 output. port 3 control registers the direction of each port pin is configured by bit-pair settings in two control registers: p3 conh (high byte, e6 h, set 1 , bank 1 ) and p3 conl (low byte, e7 h, set 1 , bank 1 ). p3 conh controls the pins , p3 . 4 ? p3 . 7, and p3 conl controls the pins , p3 . 0 ? p3 . 3 . both registers are read-write addressable using 1-bit or 8-bit instructions. there are two input modes: schmitt trigger input or schmitt trigger input with pull-up resistor. a reset clears all p3 conh and p3 conl bits to logic zero. this configures port 3 pins to s chmitt trigger input . port 3 control register, hitgh byte (p3conh) r230, e6h, set 1, bank 1, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 pin 3.7/t0/ t0pwm/t0cap pin 3.6 pin 3.5 pin 3.4 schmitt trigger input mode schmitt trigger input, pull-up mode output, push-pull mode output, high-impedance p3conh bit-pair pin configuration settings for pins 3.4-p3.6: 00 01 10 11 schmitt trigger input mode (or t0cap input for p3.7) schmitt trigger input, pull-up mode (or t0cap input for p3.7) output, push-pull mode select alternate function (t0pwm/t0) p3conh bit-pair pin configuration settings for pin 3.7: 00 01 10 11 figure 9-7 . port 3 high-byte control register (p3conh)
s3c821a/p821a i/o ports 9- 9 p3conl bit-pair pin configuration settings: 00 schmitt trigger input mode 01 schmitt trigger iput, pull-up mode 10 output, push-pull mode 11 a/d converter input mode (schmitt trigger input off) port 3 control register, low byte (p3conl) r231, e7h, set 1, bank 1, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 pin 3.3/adc3 pin 3.2/adc2 pin 3.1/adc1 pin 3.0/adc0 figure 9- 8 . port 3 low-byte control register (p3conl)
i/o ports s3c821a/p8 21a 9- 10 port 4 port 4 pins p4.0?p4.7 can be configured on a bit-pair setting basis for general data input or output. when configured as outputs, the pins may optionally be set to open-drain. all inputs are schmitt triggered. port 4 is accessed directly by writing or reading the port 4 data register, p 4 (r22 8 , e 4 h , bank 0 ) in set 1 . port 4 control registers the direction of each port pin is configured by bit-pair settings in two control registers: p4 conh (high byte, e8 h, set 1 , bank 1 ) and p4 conl (low byte, e9 h, set 1 , bank 1 ). p4 conh controls the pins , p4 . 4?p4 . 7, and p4 conl controls the pins , p4 . 0?p4 . 3 . both registers are read-write addressable using 1-bit or 8-bit instructions. there are two input modes: schmitt trigger input or schmitt trigger input with pull-up resistor. a reset clears all p4 conh and p4 conl bits to logic zero. this configures port 4 pins to s chmitt trigger input . port 4 control register, hitgh byte (p4conh) r232, e8h, set 1, bank 1, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 pin 4.7/int11 pin 4.6/int10 pin 4.5/int9 pin 4.4/int8 schmitt trigger input mode schmitt trigger input, pull-up mode push-pull output mode open-drain output mode p4conh bit-pair pin configuration settings: 00 01 10 11 figure 9-9. port 4 high-byte control register (p4conh)
s3c821a/p821a i/o ports 9- 11 port 4 control register, low byte (p4conl) r233, e9h, set 1, bank 1, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 pin 4.3/int7 pin 4.2/int6 pin 4.1/int5 pin 4.0/int4 schmitt trigger input mode schmitt trigger input, pull-up mode push-pull output mode open-drain output mode p4conl bit-pair pin configuration settings: 00 01 10 11 figure 9-10. port 4 low-byte control register (p4conl) port 4 interrupt enable and pending registers ( p4 int, p4 pnd) to process external interrupts, two additional control registers are provided: the port 4 interrupt enable register, p4 int (r2 31 , e7 h, set 1 , bank 0 ) and the port 4 interrupt pending register, p4 pnd (r2 32 , e8 h, set 1 , bank 0 ). by setting bits in the port 4 interrupt enable register p4 int to "1", you can use specific port 4 pins to generate interrupt requests when specific signal edges are detected. the interrupt names int 4 ?int 11 correspond to the pins , p4 .0? p4 .7. after a reset, p4 int bits are cleared to " 00h " , disabling all external interrupts. the port 4 interrupt pending register p4 pnd lets you check for interrupt pending conditions and clear the pending condition when the interrupt request has been serviced. incoming interrupt requests are detected by polling the p4 pnd bit values. when the interrupt enable bit of any port 4 pin is set to "1", a rising or falling signal edge at that pin generates an interrupt request. (remember that the port 4 interrupt pins must first be configured by setting them to input mode in the corresponding p4 conh or p4 conl register . ) the corresponding p4 pnd bit is then set to "1" and the irq pulse goes high to signal the cpu that an interrupt request is waiting. when a port 4 interrupt request has been serviced, the application program must clear the related interrupt pending register bit by writing a " 0 " to the pending bit in the p4 pnd register. please note that writing a " 1 " value has no effect. port 4 interrupt edge selection register (p4edge) p4 interrupt can be generated in falling edge or rising edge, depending on the value of the p4 interrupt edge selection register (r233, e9h, set 1, bank 0), p4edge. if the value is set to "1", p4 interrupt is generated in rising edge. if the value is set to "0", p4 interrupt is generated in falling edge.
i/o ports s3c821a/p8 21a 9- 12 port 4 interrupt control register (p4int) r231, e7h, set 1, bank 0, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 pin 4.3/int7 pin 4.2/int6 pin 4.1/int5 pin 4.0/int4 interrupt control settings: 0 = disable interrupt 1 = enable interrupt pin 4.7/int11 pin 4.6/int10 pin 4.5/int9 pin 4.4/int8 figure 9-11. port 4 interrupt control register (p4int) port 4 interrupt pending register (p4pnd) r232, e8h, set 1, bank 0, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 pin 4.3/int7 pin 4.2/int6 pin 4.1/int5 pin 4.0/int4 interrupt request pending bit s: 0 = no interrupt request pending 0 = clear pending bit (when write) 1 = interrupt request pending pin 4.7/int11 pin 4.6/int10 pin 4.5/int9 pin 4.4/int8 figure 9-12. port 4 interrupt pending register (p4pnd)
s3c821a/p821a i/o ports 9- 13 port 4 interrupt edge selection register (p4edge) r233, e9h, set 1, bank 0, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 pin 4.3/int7 pin 4.2/int6 pin 4.1/int5 pin 4.0/int4 interrupt control settings: 0 = falling edge interrupt 1 = rising edge interrupt pin 4.7/int11 pin 4.6/int10 pin 4.5/int9 pin 4.4/int8 figure 9-13. port 4 edge selection register (p4edge)
i/o ports s3c821a/p8 21a 9- 14 port 5 port 5 is a 7 -bit i/o port with individually configurable pins. it is accessed directly by writing or reading the port 5 data register, p 5 (r22 9 , e 5 h , bank 0 ) in set 1. you can use port 5 for general i/o, or for the following alternative functions: ? p 5 . 0? p 5 . 3 can be configured, respectively, as sck, output high impedance, so, and buz output. the special functions that you can program using the port 5 control register must also be enabled in the associated peripheral. also, when using port 5 pins for functions other than general i/o, you must still set the corresponding port 5 control register value to configure each bit to input or output mode. port 5 control register s two 8-bit control registers are used to configure port 5 pins: p 5 conh ( high byte, eah, set 1, bank 1 ) for the pins p 5 .4 ? p 5 . 6 and p 5 conl ( eb h, set 1 , bank 1 ) for the pins p 5 .0 ? p 5 .3. each byte contains four or three bit- pairs and each bit-pair configures one of port 5 pin s . the p 5 conl register also control s the alterna tive functions described below. port 5 high-byte control register (p5conh) three bit-pairs in the port 5 control register (p 5conh) configure the port 5 pins, p5.4? p 5 . 6 to s chmitt trigger input , schmitt trigger input with pull-up resistor, or push-pull output mode . port 5 low-byte control register (p5conl) the low-byte port 5 pins, p 5 .0 ? p 5 .3, can be configured individually as s chmitt trigger inputs , schmitt trigger input with pull-up resistor, or as push-pull outputs. you can alt ernately configure these pins . to select the alternative function s , you must set the related bit-pairs ? sck output, output high impedance, so, and buz output ? to " 11b " . table 9 -5 . port 5 data register summary (low nibbles) p 5 con l bit-pair corresponding port 5 pin alternate pin function bits 0 and 1 p 5 .0 sck output bits 2 and 3 p 5 .1 high impedance bits 4 and 5 p 5 .2 so bits 6 and 7 p 5 .3 buz
s3c821a/p821a i/o ports 9- 15 port 5 control register, hitgh byte (p5conh) r234, eah, set 1, bank 1, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 not used for the s3c821a pin 5.6 pin 5.5 pin 5.4 schmitt trigger input mode schmitt trigger input, pull-up mode output, push-pull mode output, high impedance p5conh bit-pair pin configuration settings: 00 01 10 11 figure 9-14. port 5 high-byte control register (p5conh) port 5 control register, low byte (p5conl) r235, ebh, set 1, bank 1, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 pin 5.3/buz pin 5.2/so pin 5.1/si pin 5.0/ sck schmitt trigger input mode (si, sck inputs for p5.1 and p5.0, respectively) schmitt trigger input, pull-up mode output, push-pull mode select alternative function (sck output, output high- impedance, so, buz for p5.0-p5.3) p5conl bit-pair pin configuration settings: 00 01 10 11 figure 9-15. port 5 low-byte control register (p5conl)
s3c821a/p821a basic timer and timer 0 10 - 1 10 basic timer and timer 0 overview s3c821a has two default timers: an 8-bit basic timer and an 8-bit gener al-purpose timer/counter. the 8 - bit timer/counter is called timer 0. basic timer (bt) you can use the basic timer (bt) in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction, or ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequency divider (f xx divided by 4096, 1024, 128, or 16 ) with multiplexer ? 8-bit basic timer counter, btcnt (set 1, bank 0, fdh, read-only) ? basic timer control register, btcon (set 1, d3h, read/write) timer 0 timer 0 offers three operating modes, which you can select by setting t0con appropriately : ? interval timer mode ? capture input mode with a rising or falling edge trigger at the p3.7 pin ? pwm mode timer 0 has the following functional components: ? clock frequency divider ( fxx divided by 4096 , 256, or 8 ) with multiplexer ? external clock input pin ( p2.4, t0ck) ? 8-bit counter (t0cnt), 8-bit comparator, and 8-bit reference data register (t0data) ? i/o pins for capture input ( p3.7 ) or match output ? timer 0 overflow interrupt (irq0, vector fah) and match/capture interrupt (irq0, vector fch) generation ? timer 0 control register, t0con (set 1, d2h, read/write)
basic timer and timer 0 s3c821a/p82 1a 10- 2 basic timer control register (btcon ) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. it is located in set 1, address d3h, and is read/write addressable using register addressing mode. a reset clears btcon to " 00h " . this enables the watchdog function and selects a basic timer clock frequency of f x /4096. to disable the watchdog function, you must write the signature code " 1010b " to the basic timer register control bits btcon.7 ? btcon.4. the 8-bit basic timer counter, btcnt (set 1, bank 0, fdh), can be cleared at any time during the normal operation by writing a "1" to btcon.1. to clear the frequency dividers for both the basic timer input clock and the timer 0 clock (unless timer 0 uses an external clock source), you should write a "1" to btcon.0. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 basic timer control register (btcon) d3h, set 1, r/w watchdog function enable bits: 1010b = disable watchdog timer others = enable watchdog timer divider clear bit for basic timer and timer 0: 0 = no effect 1 = clear both dividers basic timer counter clear bit: 0 = no effect 1 = clear btcnt basic timer input clock selection bits: 00 = fxx/4096 01 = fxx/1024 10 = fxx/128 11 = fxx/16 figure 10-1. basic timer control register (btcon )
s3c821a/p821a basic timer and timer 0 10 - 3 basic timer function description watchdog timer function you can program the basic timer overflow signal (btovf) to generate a reset by setting btcon.7 ? btcon.4 to any value other than " 1010b " . (the " 1010b " value disables the watchdog function.) a reset clears btcon to " 00h " , automatically enabling the watchdog timer function. a reset also selects fx/ 4096 as the bt clock. r eset occurs whenever a basic timer counter overflow s . during the normal operation, the application program must prevent the overflow , which causes a reset operation, from occurring. to do this, the btcnt value must be cleared (by writing a "1" to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the bt counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during the normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval after a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at the rate of f x /4096 (for reset), or at the rate of the preset clock source (for an internal and an external interrupt). when btcnt.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume the normal operation. in summary, the following events occur when stop mode is released: 1. during the stop mode, a power-on reset , or an external interrupt occurs to trigger the stop mode release and oscillation starts. 2. if a power-on reset occurred, the basic timer counter would increase at the rate of f x /4096. if an internal or an external interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows. 4. when a btcnt.3 overflow occurs, the normal cpu operation resumes. timer 0 control register (t0con ) you use the timer 0 control register, t0con, to ? select the timer 0 operating mode (interval timer, capture mode, or pwm mode) ? select the timer 0 input clock frequency ? clear the timer 0 counter, t0cnt ? enable the timer 0 overflow interrupt or timer 0 match/capture interrupt ? clear timer 0 match/capture interrupt pending conditions
basic timer and timer 0 s3c821a/p82 1a 10- 4 t0con is located in set 1, at address d2h, and is read/write addressable using register addressing mode. a reset clears t0con to " 00h " . this sets timer 0 to normal interval timer mode, selects an input clock frequency of f x /4096, and disables all timer 0 interrupts. you can clear the timer 0 counter at any time during the normal operation by writing a "1" to t0con.3. the timer 0 overflow interrupt (t0ovf) has interrupt level irq0 and the vector address fah. when a timer 0 overflow interrupt occurs and is serviced by the cpu, the pending condition is cleared automatically by hardware. to enable the timer 0 match/capture interrupt (irq0, vector fch), you must write t0con.1 to "1". to d etect a match/capture interrupt pending condition, the application program polls t0con.0. when a "1" is detected, a timer 0 match or capture interrupt is pending. after the interrupt request is serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, t0con.0. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 timer 0 control register (t0con) d2h, set 1, r/w timer 0 match/capture interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (write) 1 = interrupt is pending timer 0 match/capture interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer 0 overflow interrupt enable bit: 0 = disable overflow interrupt 1 = enable overflow interrupt timer 0 counter clear bit: 0 = no effect 1 = clear the timer 0 counter (when write) timer 0 input clock selection bits: 00 = fxx/4096 01 = fxx/256 10 = fxx/8 11 = external clock (p2.4/t0ck) timer 0 operating mode selection bits: 00 = interval mode 01 = capture mode (capture on rising edge, counter running, ovf can occur) 10 = capture mode (capture on falling edge, counter running, ovf can occur) 11 = pwm mode (ovf interrupt can occur) figure 10-2. timer 0 control register (t0con )
s3c821a/p821a basic timer and timer 0 10 - 5 timer 0 function description timer 0 interrupts (irq0, vectors fah and fch) the timer 0 module can generate two interrupts: the timer 0 overflow interrupt (t0ovf), and the timer 0 match/ capture interrupt (t0int). t0ovf is assigned the interrupt level irq0, vector fah. t0int also belongs to the interrupt level irq0, but is assigned a separate vector address, fch. a timer 0 overflow interrupt pending condition is automatically cleared by hardware after it is serviced. the t0int pending condition must, however, be cleared by the application?s interrupt service routine by writing a "0" to the t0con.0 interrupt pending bit. interval timer mode in interval timer mode, a match signal is generated when the counter value is identical to the value written to the t0 reference data register, t0data. the match signal generates a timer 0 match interrupt (t0int, vector fch) and clears the counter. if, for example, you write the value " 10h " to t0data and "0ah" to t0con , the counter will increment until it reaches " 10h " . at this point, the t0 interrupt request is generated, the counter value is reset, and counting resumes. with each match, the level of the signal at the timer 0 output pin is inverted (see figure 10-3). counter comparator clk r (clear) irq0 (t0int) interrupt enable/disable (t0con.1) match t0con.5 t0con.4 p3.7/t0 ctl pending ( t0con.0) buffer register data register match signal t0con.3 figure 10-3. simplified timer 0 function diagram: interval timer mode
basic timer and timer 0 s3c821a/p82 1a 10- 6 pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the t0 pwm pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register. in pwm mode, however, the match signal does not clear the counter. instead, it runs continuously, overflowing at " ffh " , and then continues incrementing from " 00h " . although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in pwm-type applications. instead, the pulse at the t0 pwm pin is held to low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to high level for as long as the data value is greater than ( > ) the counter value. the time period is equal to t clk 256 (see figure 10-4). counter comparator clk irq0 (t0ovf) match p3.7/ t0pwm t0con.5 t0con.4 ctl high level when data > counter; low level when data counter note : interrupts are usually not used when timer 0 is configured to operate in pwm mode. buffer register data register irq0 (t0int) interrupt enable/disable (t0con.1) t0con.3 t0ovf pnd t0con.0 figure 10-4. simplified timer 0 function diagram: pwm mode
s3c821a/p821a basic timer and timer 0 10 - 7 capture mode in capture mode, a signal edge that is detected at the t0cap pin opens a gate and loads the current counter value into the t0 data register. you can select rising or falling edge to trigger this operation. timer 0 also gives you capture input source: the signal edge at the t0cap pin. you select the capture input by setting the value s of the timer 0 capture input selection bit s in the port 3 control register, p3conh.7?6, (set 1, bank 1, e6 h). when p3conh.7?.6 is ? 00 ? or "01" , the t0cap input is selected. both kinds of timer 0 interrupts can be used in capture mode . t he timer 0 overflow interrupt is generated whenever a counter overflow occurs . t he timer 0 match/capture interrupt is generated whenever the counter value is loaded into the t0 data register. by reading the captured data value in t0data, and assuming a specific value for the timer 0 clock frequency, you can calculate the pulse width (duration) of the signal being input from the t0cap pin (see figure 10-5). counter data register clk irq0 (t0ovf) p3.7/t0cap interrupt enable / disable (t0con.1) irq0 (t0int) t0con.5 t0con.4 t0con.2 pending (t0con.0) figure 10-5. simplified timer 0 function diagram: capture mode
basic timer and timer 0 s3c821a/p82 1a 10- 8 1/4096 1/1024 1/128 1/16 bits 7, 6 notes: 1. in a power-on reset operation, the cpu is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). 2. it is available only in interval mode. div r bit 0 r div fxx mux 1/4096 1/256 1/8 mux t0ck bits 3, 2 8-bit basic counter (read-only) reset (1) or stop data bus basic timer control register (write '1010xxxxb' to disable.) reset ovf 8-bit up-counter (read-only) 8-bit comparator r t0cap bits 5, 4 t0pwm match bit 2 bit 3 t0ovf basic timer control register timer 0 control register data bus timer 0 buffer reg clear ovf p2.4 p3.7 p3.7 timer 0 data register (read/write) data bus clear bits 5, 4 t0ovf (2) bit 1 (x in or xt in ) t0int t0con.0 bit 1 bit 0 (2) t0clr match signal figure 10-6. basic timer and timer 0 block diagram
s3c821a/p821a basic timer and timer 0 10 - 9 + + programming tip ? configuring the basic timer this example shows how to configure the basic timer to sample specifications: org 0100h reset di ; disable all interrupts ld btcon,#0a b h ; disable the watchdog timer ld clkcon,#1 8h ; non-divided clock clr sym ; disable global and fast interrupts clr spl ; stack pointer low byte ? "0" ; stack area starts at 0ffh ? ? ? srp #0c0h ; set register poin ter ? 0c0h ei ; enable interrupts ? ? ? main ld btcon,#5 3 h ; enable the watchdog timer ; basic timer clock: f xx /4096 ; clear basic timer counter nop nop ? ? ? jp t,main ? ? ?
basic timer and timer 0 s3c821a/p82 1a 10- 10 + + programming tip ? programming timer 0 this sample program sets timer 0 to interval timer mode and the frequency of the oscillator clock, determin ing the execution sequence which follows a timer 0 interrupt. the program parameters are as follows: ? timer 0 is used in interval mode . t he timer interval is set to 4 milliseconds ? oscillation frequency is 6 mhz ? general register 6 4 h (page 0) ? 60h (page 0) + 62h (page 0) + 63h (page 0) + 64h (page 0) is executed after a timer 0 interrupt org 0fah ; timer 0 overflow interrupt vector t0over org 0fch ; timer 0 match/capture interrupt vector t0int org 0100h reset di ; disable all interrupts ld btcon,#0a b h ; disable the watchdog timer ld clkcon,#1 8h ; select non-divided clock clr sym ; disable global and fast interrupts clr spl ; stack pointer low byte ? "0" ; stack area starts at 0ffh ? ? ? ld t0con,#4a h ; write " 0100 1010 b " ; input clock is f xx /256 ; interval timer mode ; enable the timer 0 interrupt ; disable the timer 0 overflow interrupt ld t0data,#5 d h ; set timer interval to 4 milliseconds ; clear pending bit ; (6 mhz/256) + (93 + 1) = 0.25 k hz (4 ms) srp #60h ; rp ? 60h clr pp ; destination ? 0, source ? 0 clr r0 ; register 60h (page 0) = 00h bitr r1.2 ; bit reset (61.2h) srp #0c0h ; set register pointer ? 0c0h ei ; ena ble interrupts ? ? ? (continued on next page)
s3c821a/p821a basic timer and timer 0 10 - 11 + + programming tip ? programming timer 0 (cont inued ) t0int push rp0 ; save rp0 to stack push pp ; save pp to stack srp0 #60h ; rp0 ? 60h ld pp,#00h ; destination ? 0, source ? 0 inc r0 ; r0 ? r0 + 1 add r 2 ,r 0 ; r 2 ? r 2 + r 0 adc r 3 ,r 2 ; r 3 ? r 3 + r 2 + carry adc r 4 ,r 3 ; r 4 ? r 4 + r 3 + carry cp r0,#32h ; 50 4 = 200 ms jr ult,no_200ms_set bits r1.2 ; bit setting (61.2h) no_200ms_set: ld t0con,#4a h ; clear pending bit pop pp ; res tore page pointer value pop rp0 ; restore register pointer 0 value t0over iret ; return from interrupt service routine
s3c821a/p821a timer 1 11- 1 11 timer 1 one 16-bit timer mode (timer 1) the 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. when tacon.7 is set to "1", it is in one 16-bit timer mode. when tacon.7 is set to "0", the timer 1 is used as two 8-bit timers. ? one 16-bi t timer mode (timer 1) ? two 8-bit timers mode (timer a and b) overview the 16-bit timer 1 is an 16-bit general-purpose timer. timer 1 includes interval timer mode using appropriate tacon setting. timer 1 has the following functional components: ? clock frequency divider (fxx divided by 1024, 512, 8, or 1 and t1ck: external clock) with multiplexer ? 16-bit counter (tacnt, tbcnt), 16-bit comparator, and 16-bit reference data register (tadata, tbdata) ? timer 1 match interrupt (irq1, vector f6h) generation ? timer 1 control register, tacon (set 1, bank 0,f3h, read/write) function description interval timer function the timer 1 module can generate an interrupt, the timer 1 match interrupt (t1int). t1int belongs to the interrupt level irq1, and is assigned a separate vector address, f6h. the t1int pending condition should be cleared by software after irq1 is serviced. the t1int pending bit must be cleared by the application sub-routine by writing a "0" to the tacon.0 pending bit. in interval timer mode, a match signal is generated when the counter value is identical to the values written to the t1 reference data registers, tadata and tbdata. the match signal generates a timer 1 match interrupt (t1int, vector f6h) and clears the counter. if, for example, you write the value 10h and 32h to tadata and tbdata, respectively, and 8eh to tacon, the counter will increment until it reaches 3210h. at this point, the t1 interrupt request is generated, the counter value is reset, and counting resumes.
timer 1 s3c821a/p82 1a 11 - 2 timer 1 control register (tacon) you use the timer 1 control register, tacon, to ? enable the timer 1 operating (interval timer) ? select the timer 1 input clock frequency ? clear the timer 1 counter, tacnt and tbcnt ? enable the timer 1 interrupt ? clear timer 1 interrupt pending conditions tacon is located in set 1, bank 0, at address f3h, and is read/write addressable using register addressing mode. a reset clears tacon to "00h". this sets timer 1 to disable interval timer mode, selects an input clock frequency of fxx/1024, and disables timer 1 interrupt. you can clear the timer 1 counter at any time during the normal operation by writing a "1" to tacon.3. to enable the timer 1 interrupt (irq1, vector f6h), you must write tacon.7, tacon.2, and tacon.1 to "1". to generate the exact time interval, you should set tacon.3 and tacon.0 to ?10b?, which clear counter and interrupt pending bit. when the t1int sub-routine is serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 interrupt pending bit, tacon.0. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 timer 1 control register (tacon) f3h, set 1, bank 0, r/w timer 1 interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (when write) 1 = interrupt is pending (when read) 1 = no effect (when write) timer 1 interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer 1 counter run enable bit: 0 = disable counter running 1 = enable counter running timer 1 counter clear bit: 0 = no effect 1 = clear the timer a counter (when write) timer 1 operating mode selection bit : 0 = two 8-bit timers mode (timer a/b) 1 = one 16-bit timer mode (timer 1) timer 1 clock selection bits: 000 = fxx/1024 001 = fxx/512 010 = fxx/8 011 = fxx 1xx = t1ck (external clock) (?x? means don?t care.) figure 11-1. timer 1 control register (tacon)
s3c821a/p821a timer 1 11- 3 block diagram tacon.6-.4 mux comparator t1ck match tacon.3 clear p2.5 note: when tacon.7 is ?1?, one 16-bit timer 1. 1/1024 1/512 1/8 1/1 tbcnt tacnt tbdata tadata tacon.1 ta p2.6 t1int figure 11-2. timer 1 functional block diagram
timer 1 s3c821a/p82 1a 11 - 4 two 8-bit timers mode (timer a and b) overview the 8-bit timer a and b are the 8-bit general-purpose timers. timer a and b support interval timer mode using appropriate tacon and tbcon setting, respectively. timer a and b have the following functional components: ? clock frequency divider with multiplexer ? fxx divided by 1024, 512, 8, or 1 and t1ck (external clock) for timer a ? fxx divided by 1024, 512, 8, or 1 for timer b ? 8-bit counter (tacnt, tbcnt), 8-bit comparator, and 8-bit reference data register (tadata, tbdata) ? timer a match interrupt (irq1, vector f6h) generation ? timer a control register, tacon (set 1, bank 0, f3h, read/write) ? timer b match interrupt (irq1, vector f4h) generation ? timer b control register, tbcon (set 1, bank 0, f2h, read/write) function description interval timer function the timer a and b module can generate an interrupt: the timer a match interrupt (taint) and the timer b match interrupt (tbint). taint belongs to the interrupt level irq1, and is assigned a separate vector address, f6h. tbint belongs to the interrupt level irq1 and is assigned a separate vector address, f4h. the taint and tbint pending condition should be cleared by software after they are serviced. in interval timer mode, a match signal is generated when the counter value is identical to the values written to the ta or tb reference data registers, tadata or tbdata. the match signal generates corresponding match interrupt (taint, vector f6h; tbint, vector f4h) and clears the counter. if, for example, you write the value 10h to tbdata, "0" to tacon.7, and 0eh to tbcon, the counter will increment until it reaches 10h. at this point, the tb interrupt request is generated, the counter value is reset, and counting resumes. timer a and b control register (tacon, tbcon) you use the timer a and b control register, tacon and tbcon, to ? enable the timer a and b operating (interval timer) ? sele ct the timer a and b input clock frequency ? clear the timer a and b counter, tacnt and tbcnt ? enable the timer a and b interrupt ? clear timer a and b interrupt pending conditions
s3c821a/p821a timer 1 11- 5 tacon and tbcon are located in set 1, bank 0, at address f3h and f2h, and is read/write addressable using register addressing mode. a reset clears tacon and tbcon to "00h". this sets timer a and b to disable interval timer mode, selects an input clock frequency of fxx/1024, and disables timer a and b interrupt. you can clear the timer a and b counter at any time during normal operation by writing a "1" to tacon.3 and tbcon.3. to enable the timer a and b interrupt (irq1, vector f6h, f4h), you must write tacon.7 to "0", tacon.2 (tbcon.2) and tacon.1 (tbcon.1) to "1". to generate the exact time interval, you should set tacon.3 (tbcon.3) and tacon.0 (tbcon.0) to ?10b?, which clear counter and interrupt pending bit, respectively. when the taint or tbint sub-routine is serviced, the pending condition must be cleared by software by writing a "0" to the timer a or b interrupt pending bits, tacon.0 or tbcon.0. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 timer a control register (tacon) f3h, set 1, bank 0, r/w timer a interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (when write) 1 = interrupt is pending (when read) 1 = no effect (when write) timer a interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer a counter run enable bit: 0 = disable counter running 1 = enable counter running timer a counter clear bit: 0 = no effect 1 = clear the timer a counter (when write) timer 1 operating mode selection bit : 0 = two 8-bit timers mode (timer a/b) 1 = one 16-bit timer mode (timer 1) timer a clock selection bits: 000 = fxx/1024 001 = fxx/512 010 = fxx/8 011 = fxx 1xx = t1ck (external clock) (?x? means don?t care.) figure 11-3. timer a control register (tacon)
timer 1 s3c821a/p82 1a 11 - 6 msb lsb .7 .6 .5 .4 .3 .2 .1 .0 timer b control register (tbcon) f2h, set 1, bank 0, r/w timer b interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (when write) 1 = interrupt is pending (when read) 1 = no effect (when write) timer b interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer b counter run enable bit: 0 = disable counter running 1 = enable counter running timer b counter clear bit: 0 = no effect 1 = clear the timer a counter (when write) not used for the s3c821a. timer b clock selection bits: 00 = fxx/1024 01 = fxx/512 10 = fxx/8 11 = fxx figure 11-4. timer b control register (tbcon)
s3c821a/p821a timer 1 11- 7 match tb p2.7 note: when tacon.7 is ?0?, two 8-bit timer a/b. tacon.6-.4 mux comparator t1ck match tacon.3 clear p2.5 1/1024 1/512 1/8 1/1 tacnt tadata tacon.1 ta p2.6 irq1 tbcon.5-.4 mux 1/1024 1/512 1/8 1/1 comparator tbdata tbcon.3 clear tbcon.1 tbcnt r r figure 11-5. timer a and b function block diagram
s3c821a/p821a watch timer 12- 1 12 watch timer overview watch timer functions include real-time and watch-time measurement and interval timing for the system clock. after the watch timer starts and elapses a time, the watch timer interrupt is automatically set to "1", and interrupt requests commence in 3.91 ms or 0.5 second. the watch timer can generate a steady 0.5 khz, 1 khz, 2 khz, or 4 khz signal to the buz output. by setting wtcon.3 and wtcon.0 to "11b", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. high-speed mode is useful for timing events for program debugging sequences. the watch timer supplies the clock frequency for the lcd controller (f lcd ). therefore, if the watch timer is disabled, the lcd controller does not operate. ? real-time an d watch-time measurement ? using a main system or subsystem clock source ? clock source generation for lcd controller ? buzzer output frequency generator ? timing tests in high-speed mode
watch timer s3c821a/ p821a 12- 2 watch timer control register (wtcon: r/w) fbh wtcon.7 wtcon.6 wtcon.5 wtcon.4 wtcon.3 wtcon.2 wtcon.1 wtcon.0 reset "0" "0" "0" "0" "0" "0" "0" "0" table 12-1. watch timer control register (wtcon): 8-bit r/w bit name values function address wtcon.7 0 disable buzzer (buz) signal output fbh, 1 enable buzzer (buz) signal output bank 0 wtcon.6 0 disable watch timer (clear frequency dividing circuits) 1 enable watch timer wtcon.5?.4 0 0 0.5 khz buzzer (buz) signal output 0 1 1 khz buzzer (buz) signal output 1 0 2 khz buzzer (buz) signal output 1 1 4 khz buzzer (buz) signal output wtcon.3 0 fw/2 14 (0.5 sec) interval 1 fw/2 7 (3.91 ms) interval wtcon.2 0 main system clock divided by 2 7 (fx/128) 1 sub system clock (fxt) wtcon.1 0 no interrupt pending 0 clear pending bit (when write) 1 interrupt is pending wtcon.0 0 disable interrupt 1 enable interrupt
s3c821a/p821a watch timer 12- 3 watch timer circuit diagram wt con.5-.4 fx/128 fxt mux frequency dividing circuit wt con.2 m u x fw 32.768 khz (note) fw/2 7 wt con.3 m u x fw/2 14 wt con.7 irq 4 buz fx : main system clock fxt: sub system clock fw: watch timer clock f lcd : lcd clock fxx: selected clock for peripheral hardware note: when the fxt (subsystem clock) is selected as watch timer clock. wt con.6 p5.3 0.5 khz 1 khz 2 khz 4 khz f lcd figure 12- 1 . watch timer circuit diagram
s3c821a/p821a lcd controller/driv er 13- 1 13 lcd controller/driver overview the s3c821a microcontroller can directly drive an up-to- 224 -dot ( 28 segments x 8 commons) lcd panel. its lcd block has the following components: ? lcd controller/d river ? display ram for storing display data ? 4 common/segment output pins (com4/seg0?com7/seg3) ? 28 segment output pins (seg 4? seg 31 ) ? 4 common output pins (com0 ? com 3 ) ? internal resistor circuit for lcd bias ? v lc 1 pin for controlling the driver and bias voltage the lcd control register, lcon, is used to turn the lcd display on and off, switch the current to the dividing resistors for the lcd displ ay, and frame frequency . data written to the lcd display ram can be automatically transferred to the segment signal pins without any program control. when a subsystem clock is selected as the lcd clock source, the lcd display is enabled even in the main clock stop or idle mode. 4 1 28 4 8 data bus lcd controller / driver com0?com3 vlc1 seg4?seg31 com4?com7/ seg0?seg3 figure 13- 1. lcd function diagram
lcd controller/driver s3c821a/p821a 13- 2 lcd circuit diagram data bus display ram (page 4) lcon selector timing controller com control or selector com control lcd voltage control seg31 seg4 com7/seg3 com6/seg2 com5/seg1 com4/seg0 com3 com2 com1 com0 v cl 1 f lcd 32 figure 13- 2. lcd circuit diagram
s3c821a/p821a lcd controller/driv er 13- 3 lcd ram address area ram addresses of page 4 are used as lcd data memory. these locations can be addressed by 1-bit or 8 -bit instructions. if the bit value of a display segment is "1", the lcd display is turned on . if the bit value is "0", the display is turned off. display ram data are sent out through the segment pins , seg0 ? seg 31, using the direct memory access (dma) method that is synchronized with the f lcd signal. ram addresses in this location that are not used for lcd display can be allocated to general-purpose use. com0 com1 com2 com3 com4 com5 com6 com7 .0 .1 .2 .3 .4 .5 .6 .7 com bit seg0 seg1 seg2 seg3 seg4 seg30 seg31 ....... ....... 00h 01h 02h 03h 04h 30h 31h figure 13- 3. lcd display data ram organization
lcd controller/driver s3c821a/p821a 13- 4 lcd control register (lcon) the lcd control register (lcon) is used to turn the lcd display on and off , lcd frame frequency, and control the flow of the current to the dividing resistors in the lcd circuit. after a reset , all lcon values are cleared to "0". this turns the lcd display off and stops the flow of the current to the dividing resistors. lcd control register (lcon) fah, set 1, bank 0, r/w msb lsb .7 .6 .5 .4 .3 .2 .1 .0 lcd clock select bits: 00 = fw/2 6 01 = fw/2 5 10 = fw/2 4 11 = fw/2 3 not used for the s3c821a. lcd duty and bias selection bits: 00 = display off, p-tr off 01 = normal display (using vlc1 with external voltage), p-tr off 10 = all dots off, p-tr on 11 = normal display, p-tr on (p-tr is transistor between vdd and vlc1) lcd duty and bias selection bits: 00 = 1/3 duty, 1/3 bias; com0-2/seg0-31 01 = 1/4 duty, 1/3 bias; com0-3/seg0-31 10 = 1/8 duty, 1/4 bias; com0-7/seg4-31 11 = 1/8 duty, 1/5 bias; com0-7/seg4-31 figure 13-4. lcd control register (lcon)
s3c821a/p821a lcd controller/driv er 13- 5 lcd voltage dividing resistors on-chip voltage dividing resistors for the lcd drive power supply are fixed to the v lc1? v lc5 pins. figure 13-5 shows the bias connections for the s3c821a lcd drive power supply. to cut off the flow of current through the dividing resistor, manipulate bits 7 and 6 of the lcon register. v dd s3c821a v lc1 v lc2 v lc3 v lc4 v lc5 r lcon.7 r r r r v ss v lc1 1/4 bias v dd s3c821a v lc1 v lc2 v lc3 v lc4 v lc5 r lcon.7 r r r r v ss v lc1 1/3 bias v dd s3c821a v lc1 v lc2 v lc3 v lc4 v lc5 r lcon.7 r r r r v ss v lc1 1/5 bias figure 13-5. lcd bias circuit connection
lcd controller/driver s3c821a/p821a 13- 6 v dd s3c821a v lc1 v lc2 v lc3 v lc4 v lc5 r lcon.7 r r r r note: for lcd-off, lcon.7, .6 must be set to 00b or 10b. for power-saving, lcd.7, .6 must be set to 00b when lcd is off. for a normal display, lcon.7, .6 must be set to 11b. on in case of internal v dd figure 13-6 . example 1 for the usage of lcon.7, lcon.6
s3c821a/p821a lcd controller/driv er 13- 7 off s3c821a v lc1 v lc2 v lc3 v lc4 v lc1 v lc5 r lcon.7 r r r r v dd note: for lcd-off, lcon.7, .6 must be set to 00b. for a normal display, lcon.7, .6 must be set to 01b. v dd in case of external v for contrast dd figure 13-7. example 2 for the usage of lcon.7, lcon.6
lcd controller/driver s3c821a/p821a 13- 8 p a.b s3c821a v lc1 v lc2 v lc3 v lc4 v lc1 v lc5 r lcon.7 r r r r v dd off in case of using a port for contrast control for lcd-off, lcon.7, .6 must be set to 00b. for power-saving, pa.b must be in low level when lcs is off. for a normal disaplay, pa.b must be in high level and lcon.7, .6 must be set to 01b. note: figure 13-8. example 3 for the usage of lcon.7, lcon.6
s3c821a/p821a lcd controller/driv er 13- 9 1 2 0 1 frame 0 1 2 fr v lc1 v ss seg0 - com 0 + v lc1 + 1/3 v lc1 com0 v lc1 v lc2 ( v lc3 ) v lc4 ( v lc5 ) v ss com1 v lc1 v lc2 ( v lc3 ) v lc4 ( v lc5 ) v ss com2 v lc1 v lc2 ( v lc3 ) v lc4 ( v lc5 ) v ss seg0 v lc1 v lc2 ( v lc3 ) v lc4 ( v lc5 ) v ss seg1 v lc1 v lc2 ( v lc3 ) v lc4 ( v lc5 ) v ss - 1/3 v lc1 - v lc1 com0 com1 com2 seg1 seg0 seg2 0 v figure 13-9. lcd signal waveforms (1/3 duty, 1/ 3 bias)
lcd controller/driver s3c821a/p821a 13- 10 1 2 0 1 frame 0 1 2 fr v lc1 v ss v ss com0 v lc1 v lc2 ( v lc3 ) v lc4 ( v lc5 ) v ss com1 v lc1 v lc2 ( v lc3 ) v lc4 ( v lc5 ) v ss com2 v lc1 v lc2 ( v lc3 ) v lc4 ( v lc5 ) seg0 v lc1 v lc2 ( v lc3 ) v lc4 ( v lc5 ) v ss seg1 v lc1 v lc2 ( v lc3 ) v lc4 ( v lc5 ) v ss seg0 - com 0 + v lc1 + 1/3 v lc1 - 1/3 v lc1 - v lc1 com0 com1 com2 seg0 seg1 com3 3 3 com3 v lc1 v lc2 ( v lc3 ) v lc4 ( v lc5 ) 0 v figure 13-10. lcd signal waveforms (1/4 duty, 1/ 3 bias)
s3c821a/p821a lcd controller/driv er 13- 11 com0 v lc1 v lc2 v lc3 ( v lc4 ) v lc5 v ss fr 1 frame com1 v lc1 v lc2 v lc3 ( v lc4 ) v lc5 v ss com2 v lc1 v lc2 v lc3 ( v lc4 ) v lc5 v ss seg5 v lc1 v lc2 v lc3 ( v lc4 ) v lc5 v ss seg5 - com0 v lc1 v lc2 v lc3 ( v lc4 ) v lc5 0v - v lc5 - v lc3 ( - v lc4 ) - v lc2 - v lc1 v lc1 0 1 2 3 7 v ss 4 5 6 7 0 1 2 3 7 4 5 6 com0 com1 com2 com3 com4 com5 com6 com7 s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 figure 13-11. lcd signal waveforms (1/8 duty, 1/ 4 bias)
lcd controller/driver s3c821a/p821a 13- 12 seg6 v lc1 v lc2 v lc3 ( v lc4 ) v lc5 v ss seg6 - com0 v lc1 v lc2 v lc3 ( v lc4 ) v lc5 0v - v lc5 - v lc3 ( - v lc4 ) - v lc2 - v lc1 fr 1 frame v lc1 0 1 2 3 7 v ss 4 5 6 0 7 0 1 2 3 7 4 5 6 0 7 figure 13-11. lcd signal waveforms (1/8 duty, 1/ 4 bias) (continued)
s3c821a/p821a lcd controller/driv er 13- 13 1 2 com0 com1 com2 com3 com4 com5 com6 com7 fr v lc1 0 3 7 1 frame v ss com0 v lc1 v lc2 v lc3 v lc4 v lc5 0 1 2 3 7 com1 com2 seg5 vss v lc1 v lc2 v lc3 v lc4 v lc5 v ss v lc1 v lc2 v lc3 v lc4 v lc5 v ss v lc1 v lc2 v lc3 v lc4 v lc5 v ss s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 figure 13-12. lcd signal waveforms (1/8 duty, 1/5 bias)
lcd controller/driver s3c821a/p821a 13- 14 fr v lc1 0 1 2 3 7 1 frame v ss 0 1 2 3 7 seg6 v lc1 v lc2 v lc3 v lc4 v lc5 v ss seg5 - com0 v lc1 v lc2 v lc3 v lc4 v lc5 0v - v lc5 - v lc4 - v lc3 - v lc2 - v lc1 seg6 - com0 v lc1 v lc2 v lc3 v lc4 v lc5 0v - v lc5 - v lc4 - v lc3 - v lc2 - v lc1 figure 13-12 . lcd signal waveforms (1/ 8 duty, 1/5 bias) (continued)
s3c821a/p821a a/d converter 14- 1 14 analog-to-digital converter overview the 8-bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 8 -bit digital values. the analog input level must lie between the av ref and av ss values. the a/d converter has the following components: ? analog comparator with s uccessive approximation logic ? d/a converter logic (resistor string type) ? adc control register (adcon) ? four multiplexed analog data input pins (adc0 ? adc 3 ) ? 8-bit a/d conversion data output register (ad data ) ? av ref and av ss input pins to initiate an analog-to-digital conversion procedure, you should load a value in analog input pin selection bits in the a/d converter control register adcon to select one of the four analog input pins (adcn, n = 0? 3 ) and set the conversion start or enable bit, adcon.0 . the read-write adcon register is located in set 1, bank 0 , at address f 7 h. during a normal conversion, adc block initially set s the successive approximation register to 80h (the approximate half-way point of an 8 -bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 8-bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value ( adcon.6? adcon.4 ) in the adcon register. to start t he a/d conversion , you should set the enable bit, adcon.0. when a conversion is completed, adcon.3, the end-of-conversion (eoc) bit is automatically set to 1 and the result is dumped into the addata register where it can be read. the a/d converter then enters an idle state. remember to read the contents of addata before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note as the a/d converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the adc0 ? adc 3 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to noise, will invalidate the result. if the chip enters to stop or idle mode in conversion process, there will be a leakage current path in a/d block. you must use stop or idle mode after adc operation is finished.
a/d converter s3c821a/p821a 14- 2 conversion timing the a/d conversion process requires 4 clocks to convert each bit. therefore, a total of 34 clocks are required to complete an 8-bit conversion (17 s?170 s). with an 4 mhz fxx clock frequency and fxx/4 clock source selected , one clock cyc l e is 1 s . if each bit conversion requires 4 clocks, the conversion rate is calculated as follows: (start 1 clock + (4 clock/bit 8 bits ) + eoc clock) = 34 clocks, 1 s 34 = 34 s at 4 mhz (fxx/4) adcon.0 (adc enable) adcon.0 (adc enable) adcon.2 - .1 conversion result ( addata f8h, set1, bank0) to data bus analog comparator to adcon.3 (eoc flag) f xx /n (n = 1, 4, 8, 16) input pins adc3 - adc0 mux adcon.6 - .4 (input pin select) av ss av ref 8-bit d/a converter + - clock select successive approximation logic and register figure 14- 1. a/d converter functional block diagram
s3c821a/p821a a/d converter 14- 3 a/d converter control register (adcon) the a/d converter control register, adcon, is located at address f 7 h in set 1, bank 0. it has four functions: ? a nalog input pin selection (b its 4 , 5, and 6 ) ? end-of-conversion status detection (bit 3) ? clock source selection (bits 2 and 1) ? a/d operation start or enable (bit 0) after a reset, the adc0 pin is automatically selected as the analog data input pin, and the start bit is turned off. you can select only one analog input channel at a time. other analog input pins (adc0 ? adc 3 ) can be selected dynamically by manipulating the adcon.4?.6 bits. . 7 .6 .5 .4 .3 .2 .1 .0 not used for the s3c821a a/d converter control register (adcon) f7h, set 1, bank 0, r/w (eoc bit is read-only) msb lsb end-of-conversion bit (read-only): 0 = conversion not complete 1 = conversion complete clock source select bits: 00 = fxx/16 01 = fxx/8 10 = fxx/4 11 = fxx start or enable bit: 0 = disable operation 1 = start operation a/d input pin selection bits: 0 00 = adc0 0 01 = adc1 0 10 = adc2 0 11 = adc3 figure 14- 2. a/d converter control register (adcon) internal reference voltage levels in the adc function block, the analog input voltage level is logically compared to a reference voltage. for the s3c821a , the analog input level must be within the range of av ss to av ref , where av ref = v dd . different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first bit conversion is always 1/2 av ref .
s3c821a/p821a serial i/o interface 1 5- 1 1 5 serial i/o interface overview serial i/o module, sio can interface with various types of external device that require serial data transfer. the components of each sio function block are: ? 8-bit control register (s iocon ) ? clock selector logic ? 8-bit data buffer (siodata) ? 8-bit prescaler (siops) ? 3-bit serial clock counter ? serial data i/o pins (si, so) ? external clock input/output pins (sck) the sio module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. to ensure flexible data transmission rates, you can select an internal or external clock source. programming procedure to program the sio modules, follow these basic steps: 1. configure the i/o pins at port (so, sck, si) by loading the appropriate value to the p5conl register if necessary. 2. load an 8-bit value to the siocon control register to properly configure the serial i/o module. in this operation, siocon.2 must be set to "1" to enable the data shifter. 3. for interrupt generation, set the serial i/o interrupt enable bit (siocon.5) to "1". 4. when you transmit data to the serial buffer, write data to siodata and set siocon.3 to 1, the shift operation starts. 5. when the shift operation (transmit/receive) is completed, the sio pending bit (siocon.6) is set to "1" and an sio interrupt request is generated.
serial i/o interface s3c821a/p821a 1 5- 2 sio control register (siocon) the control register for serial i/o interface module, siocon, is located at f5h in set 1, bank 0. it has the control settings for sio module. ? clock source selection (internal or external) for shift clock ? interrupt enable ? edge selection for shift operation ? clear 3-bit counter and start shift operation ? shift operation (transmit) enable ? mode selection (transmit/receive or receive-only) ? data direction selection (msb first or lsb first) a reset sets the siocon value to "80h". this configures the corresponding module with a cpu clock source at the sck, selects receive-only operating mode, and falling edge start. the data shift operation and the interrupt are disabled. the selected data direction is msb-first. msb lsb .7 .6 .5 .4 .3 .2 .1 .0 sio control register (siocon) f5h, set 1, bank 0, r/w sio shift clock selection: 0 = external clock 1 = cpu clock sio counter clear and shifter start bit: 0 = no action (when write) 1 = clear 3-bit counter and start shifting sio mode selection bit: 0 = receive-only mode 1 = transmit/receive mode sio interrupt pending bit: 0 = no interrupt pending 0 = clear pending condition (when write) 1 = interrupt is pending data direction control bit: 0 = msb-first mode 1 = lsb-first mode sio interrupt enable bit: 0 = disable interrupt 1 = enable interrupt sio start edge selection bit: 0 = falling edge start 1 = rising edge start sio shift operation enable bit: 0 = disable shifter and counter, retain irq status 1 = enable shifter and clock counter, set irq flag to ?1? figure 1 5- 1. serial i/o port control register (siocon)
s3c821a/p821a serial i/o interface 1 5- 3 sio pre-scaler register (siops) sio prescaler register, siops, is located at f6h in set 1, bank 0. the value stored in the sio prescaler registers, siops, lets you determine the sio clock rate (baud rate) as follows: baud rate = input clock (cpu clock) / 2 (prescaler value + 1), or sck input clock msb lsb .7 .6 .5 .4 .3 .2 .1 .0 sio prescaler register (siops) f6h, set 1, bank 0, r/w baud rate = (cpu clock) / 2 x (siops + 1) figure 15-2. sio prescaler register (siops) block diagram 8 8-bit sio shift buffer (siodata) clk siocon.7 (shift clock source select) cpu clock 8-bit p.s. siops (f6h, set 1, bank 0) m u x sck/p5.0 so/p5.2 si/p5.1 data bus clk 3-bit counter sioint (irq2) siocon.5 (interrupt enable) siocon.0 (lsb/msb first mode select) clear siocon.3 siocon.1 (mode select) siocon.2 (shift enable) siocon.4 (edge select) prescaled value = 1 / 2(siops + 1) siocon.6 pending figure 15-3. sio functional block diagram
serial i/o interface s3c821a/p821a 1 5- 4 serial i/o timing diagrams data output transmit complete irq2 start d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 data input shift clock figure 15-4 . sio timing in transmit/receive mode (falling edge start) data output transmit complete irq2 start d7 d6 d5 d4 d3 d2 d1 d0 data input shift clock high impedance figure 15-5 . sio timing in receive-only mode (falling edge start)
s3c821a/p821a serial i/o interface 1 5- 5 serial i/o timing diagrams (continued) data output transmit complete irq2 start d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 data input shift clock figure 15-6. timing in transmit/receive mode (rising edge start) data output transmit complete irq2 start d7 d6 d5 d4 d3 d2 d1 d0 data input shift clock high impedance figure 15-7. timing in receive-only mode (rising edge start)
s3c821a/p821a external interface 16- 1 1 6 external interface overview the sam8 architecture supports an external memory interface. d ata memory areas in external devices can be accessed over the 16-bit multiplexed address/data bus. the s3c821a microcontroller has a total of 80 pins, 47 of which are for programmable i/o. of these 47 i/o pins, up to 2 0 can be configured as an external interface that supports access to external memory and other peripheral devices. since memory addresses that are carried over the address/data bus are 16 bits long, up to 64 k bytes of memory space can be addressed .
external interface s3c821a/p821a 16- 2 external interface control registers this subsection presents an overview of the s3c821a system registers which are used to configure and control the external peripheral interface: ? system mode register (sym, r222, deh, set 1) ? port 0 control register (p0con, r 224 , e0 h, set 1 , bank 1 ) ? port 1 control register (p1con, r2 26 , e2 h, set 1 , bank 1 ) ? port 2 low-byte control register (p 2 con l , r2 29 , e5 h, set 1 , bank 1 ) detailed descriptions of each of these registers can be found in part i, chapter 4, "control registers . " port 0 control register (p0con) the port 0 control register p0con ( e0 h, set 1 , bank 1 ) controls the upper and lower nibble configuration for port 0 pins. when p0con bit 7 = "1", the upper nibble pins p0.7 ? p0.4 are configured as lines for the external memory interface. when p0con bit 3 = "1", the lower nibble pins p0.3 ? p0.0 are configured for external memory. after a reset, p0con is cleared to 00h. bits 7 and/or 3 must then be set to "1" by program software to enable the external memory interface function for port 0. port 1 control register (p1con) the port 1 control register p1con ( e2 h, set 1 , bank 1 ) functions identically to the p0con register, except that it controls the upper and lower nibble configuration for port 1 pins: p1.7 ? p1.4 and p1.3 ? p1.0, respectively. p1con is also cleared to 00h by a reset. port 2 control register (p2conl) the pins of i/o port 2, p2. 3? p2.0, can alternately be used as lines for the signal outputs that are required to control the activity of the multiplexed external memory interface bus. you manipulate the bit-pairs in the control register, p2conl ( e5 h, set 1 , bank 1 ) to configure the pins individually for general-purpose use or as external memory bus control lines. if the external memory interface is implemented, you must configure all four pins as memory lines. when bit pairs 7/6, 5/4, 3/2, and 1/0 are set to " 11b " , the corresponding memory signal outputs are activated: bit-pair pin symbol function 7/6 p2.3 dm data memory pin 5/4 p2.2 d w data write pin 3/2 p2.1 dr data read pin 1/0 p2.0 as address strobe pin in normal operating mode, a reset operation clears p2conl to 00h, configuring p2. 3? p2.0 as normal input pins.
s3c821a/p821a external interface 16- 3 how to configure the external interface the 3-state external memory interface is enabled or disabled by manipulating bit 7 of the system mode register sym (r222, deh). a reset clears sym.7 to logic zero, disabling the high impedance levels of the interface bus lines and enabling the external interface. to access the external memory, its port must be selected to external interface lines. table 16- 1. control register overview for the external memory interface register location bit (s) description sym deh 7 external 3-state interface enable bit p0con e0 h , bank 1 3 if "1", enable port 0 pins p0.0 ? p0.3 for external memory interface 7 if "1", enable port 0 pins p0.4 ? p0.7 for external memory interface p1con e2 h , bank 1 3 if "1", enable port 1 low nibble pins (p1.0 ? p1.3) for external memory interface 7 if "1", external memory interface enable for port 1 high nibble pins (p1.4 ? p1.7) p2conl e5 h , bank 1 1, 0 if both "1", address strobe ( as ) enabled at p2.0 3, 2 if both "1", data read signal ( dr ) enabled at p2. 1 5, 4 if both "1", data write signal ( d w ) enabled at p2. 2 7, 6 if both "1", data memory signal ( dm ) enabled at p2.3 table 16- 2. external interface control register values after a reset reset (normal mode) register name mnemonic address bit values after reset reset dec hex 7 6 5 4 3 2 1 0 system mode register sym r222 deh 0 ? ? x x x 0 0 port 0 control register p0con r2 24 e0 h , bank 1 0 0 0 0 0 0 0 0 port 1 control register p1con r2 26 e 2 h , bank 1 0 0 0 0 0 0 0 0 port 2 control register (low byte) p2conl r2 29 e 5 h , bank 1 0 0 0 0 0 0 0 0 note: a dash ( ?) indicates that the bit is not mapped . a n " x " means that the value is undefined after a reset .
external interface s3c821a/p821a 16- 4 using an external system stack sam8 microcontrollers use the system stack to implement subroutine calls and returns for interrupt processing and for dynamic data storage. stack operations are supported in either the internal register file or in externally configured data memory. the push and pop instructions support external system stack operations. the instructions pushui, pushud, popui, and popud support user-defined stack operations in the register file only. after a reset, the stack pointer value is undetermined. for external stack operations, a 16-bit stack pointer value (in other words, both spl and sph) must be used. an external stack holds return addresses for procedure calls and interrupts, as well as dynamically-generated data. the contents of the pc are saved on the external stack during a call instruction and restored during a ret instruction. during interrupts, the contents of the pc and the flags register are saved on the external stack and then restored by the iret instruction. to select the external stack area option, bit 1 in the external memory timing register (emt, feh, set 1, bank 0) must be set to logic one. the instruction used to change the stack selection bit in the emt register should not be immediately followed by an instruction that uses the stack, since this will cause indeterminate program flow. also, interrupts should be disabled with a di instruction before changing the stack selection bit.
s3c821a/p821a external interface 16- 5 machine cycle (mn) t1 t2 t3 clock write cycle dm as dr dw a8?a15 port a d0?d7 output a0?a7 port ad figure 16-1 . s3c821a external bus write cycle timing diagram
external interface s3c821a/p821a 16- 6 machine cycle (mn) t1 t2 t3 clock read cycle dm as d0?d7 input a0?a7 port ad a8?a15 port a d r d w figure 16-2 . s3c821a external bus read cycle timing diagram
s3c821a/p821a external interface 16- 7 sram (64 kb) cs s3c821a 74hct374 74hct574 clk d0-d7 a0-a7 a8-a15 ad0-ad7 port ad oe we dw dr dm as a8-a15 port a 8 8 8 8 figure 16-3 . external interface function diagram ( s3c821a , sram, eprom, eeprom)
s3c821a/p821a electrical data 17- 1 1 7 electrical data overview in this section, s3c821a electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. electrical characteristics ? data retention supply voltage in stop mode ? stop mode release timing when initiated by an external interrupt ? stop mode release timing when initiated by a reset ? i/o capacitance ? a.c. electrical characteristics ? a /d converter electrical characteristics ? input timing for external interrupts (p4, p2.4?p2.7) ? input timing for reset ? serial data transfer timing ? oscillation characteristics ? oscillation stabilization time ? operating voltage range
electrical data s3c821a/p821a 17- 2 table 17- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v in all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 18 ma all i/o ports active ? 60 output current low i ol one i/o port active + 30 (peak value) ma + 15 (note) ports 0, 1, 2, and 3 + 100 (peak value) + 60 (note) ports 4 and 5 + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low (i ol ) are calculated as peak value duty .
s3c821a/p821a electrical data 17- 3 table 17- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd f osc = 8 mhz (instruction clock = 1.33 mhz) 2.2 ? 5.5 v f osc = 6 mhz (instruction clock = 1 mhz) 2.0 input high voltage v ih1 p0 and p1 0.7 v dd ? v dd v v ih2 reset , p2, p3, p4, and p5 0.8 v dd v dd v ih3 x in , x t in v dd ? 0.1 v dd input low voltage v il1 p0 and p1 0 ? 0.3 v dd v il2 reset , p2, p3, p4, and p5 0.2 v dd v il3 x in , x t in 0.1 output high voltage v oh v dd = 3 v; i oh = ? 200 m a all output pins v dd ? 1.0 ? ? output low voltage v ol v dd = 3 v; i o l = 1 ma all output pins ? 0.4 1.0 input high leakage current i lih1 v i n = v dd all input pins except those specified below for i lih2 ? ? 1 a i lih2 v in = v dd x in , x out , xt in , and xt out 20 input low leakage current i lil1 v i n = 0 v all input pins except those specified below for i lil2 and reset ? ? ? 1 i lil2 v i n = 0 v x in , x out , xt in , and xt out ? 20 output high leakage current i loh v out = v dd all output pins ? ? 1 output low leakage current i lol v out = 0 v all output pins ? ? ? 1 | v dd ? comi | voltage drop (i = 0?7) v dc v dd = 2.7 v to 5.5 v ? 15 m a per common pin ? ? 120 mv | v dd ? segx | voltage drop (x = 0?31) v ds v lcd = 2.7 v to 5.5 v ? 15 m a per segment pin ? ? 120
electrical data s3c821a/p821a 17- 4 table 17- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit v lc2 output voltage v lc2 v dd = 2.7 v to 5.5 v lcd clock = 0 hz 0.8 v dd ? 0.15 0.8 v dd 0.8 v dd + 0.15 v v lc3 output voltage v lc3 v lc1 = v dd 0.6 v dd ? 0.15 0.6 v dd 0.6 v dd + 0.15 v lc4 output voltage v lc4 0.4 v dd ? 0.15 0.4 v dd 0.4 v dd + 0.15 v lc5 output voltage v lc5 0.2 v dd ? 0.15 0.2 v dd 0.2 v dd + 0.15 pull-up resistors r l1 v in = 0 v; t a = 25 c v dd = 3.0 10 %; ports 0?5 30 80 200 k w r l2 v in = 0 v; t a = 25 c v dd = 3.0 10 % reset only 200 450 800 lcd voltage dividing resistor r lcd v lcd = 2.7 v to 5.5 v t a = 25 c 45 65 80 k w supply current i dd1 run mode; v dd = 5 .0v 10% 6.0 mhz ? 6.0 12 ma ( n ote) c rystal oscillator c1 = c2 = 22 pf 4.19 mhz 4.5 9.0 v dd = 3 .0 v 10 % 6.0 mhz 2.9 5.8 4.19 mhz 2.0 4.0 i dd2 idle mode; v dd = 5 .0 v 0 % 6.0 mhz 1.3 2.6 c rystal oscillator c1 = c2 = 22 pf 4.19 mhz 1.2 2.4 v dd = 3 .0 v 10 % 6.0 mhz 0.6 1.2 4.19 mhz 0.4 0.8 i dd 3 run mode; v dd = 3 .0 v 10 % 32 k hz crystal oscillator 20 40 a i dd 4 idle mode; v dd = 3 .0 v 10 % 32 k hz crystal oscillator 7 14 i dd 5 stop mode; v dd = 5 .0 v 10 % 0.5 3 stop mode; v dd = 3 .0 v 10 % 0.3 2 note s : 1. supply current does not include current drawn through internal pull-up resistors , lcd voltage dividing resistors, and adc . 2. i dd1 and i dd2 include power consumption for subsystem clock oscillation. 3. i dd3 and i dd4 are current when main system clock oscillation stops and the subsystem clock is used. 4. i dd5 is current when main system clock and subsystem clock oscillation stops.
s3c821a/p821a electrical data 17- 5 table 17- 3. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2.2 ? 3.4 v data retention supply current i dddr v dddr = 1.0 v stop mode ? ? 1 a oscillator stabilization t wait released by reset ? 2 16 /fx (1) ? ms wait time released by interrupt ? (2) ? notes: 1. fx is the main oscillator frequency. 2. the duration of the oscillation stabilization time (t wait ) when it is released by an interrupt is determined by the setting in the basic timer control register, btcon. v dd interrupt request execution of stop instruction v dddr data retention mode stop mode normal operating mode t wait idle mode (basic timer active) ~ ~ 0.8 v dd ~ ~ figure 17- 1. stop mode release timing when initiated by a n external interrupt
electrical data s3c821a/p821a 17- 6 v dd reset execution of stop instruction v dddr data retention mode stop mode normal operating mode t wait oscillation stabilization time reset occurs 0.2 v dd 0.8 v dd ~ ~ ~ ~ figure 17-2 . stop mode release timing when initiated by a reset reset
s3c821a/p821a electrical data 17- 7 table 17-4. input/ o utput capacitance (t a = ? 25 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 17- 5. a.c. electrical characteristics (t a = ? 40 c to + 85 c , v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit sck cycle time t kcy external sck source 1,000 ? ? ns internal sck source 1,000 sck high, low t kh, t kl external sck source 500 width internal sck source t kcy /2?50 si setup time to t sik external sck source 250 sck high internal sck source 250 si hold time to t ksi external sck source 400 sck high internal sck source 400 output delay for t kso external sck source ? ? 300 ns sck to so internal sck source 250 interrupt input, high, low width t int h , t int l all interrupt v dd = 3 v 500 700 ? ns reset input low width t rsl input v dd = 3 v 2,0 00 ? ?
electrical data s3c821a/p821a 17- 8 table 17-6 . a/d converter electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 2.7 v to 5 . 5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? 8 ? bit total accuracy v dd = 5.12 v ? ? 2 lsb av ref = 5 .12 v av ss = 0 v conversion time ( 1 ) t con 8 bit conversion 34 x n/fxx (2) , n=1,4,8,16 17 ? 170 m s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 1,000 ? m w analog reference voltage av ref ? 2.5 ? v dd v analog ground av ss ? v ss ? v ss + 0.3 v analog input current i adin av ref = v dd = 5 v ? ? 10 m a notes: 1. " conversion time " is the time required from the moment a conversion operation starts until it ends . 2 . fxx is a selected system clock for peripheral hardware.
s3c821a/p821a electrical data 17- 9 0.8 v dd 0.2 v dd t int l t int h note : the unit t cpu means one cpu clock period. figure 17-3 . input timing for external interrupts t rsl 0.2 v dd reset figure 17-4 . input timing for reset reset sck t kl t kh t kcy 0.8 v dd input data output data 0.2 v dd 0.8 v dd 0.2 v dd si so t kso t sik t ksi figure 17-5 . serial data transfer timing
electrical data s3c821a/p821a 17- 10 table 17-7 . main system osc illation characteristics (t a = ? 40 c + 85 c) oscillator clock circuit parameter condition (v dd ) min typ max unit crystal c2 c1 x in x out main oscillation frequency 2.2 v?5.5 v 0.4 ? 8 mhz 2.0 v?5.5 v 0.4 ? 6 ceramic c2 c1 x in x out main oscillation frequency 2.2 v?5.5 v 0.4 ? 8 2.0 v?5.5 v 0.4 ? 6 external clock x in x out x in input frequency 2.2 v?5.5 v 0.4 ? 8 2.0 v?5.5 v 0.4 ? 6 rc x in x out r frequency 3.0 v 0.4 ? 2 table 17-8 . subsystem oscillation characteristics (t a = ? 40 c + 85 c) oscillator clock circuit parameter condition (v dd ) min typ max unit crystal c2 c1 xt in xt out sub oscillation frequency 2.0 v?5.5 v 32 32.768 35 k hz external clock xt in xt out xt in input frequency 2.0 v?5.5 v 32 ? 500 k hz
s3c821a/p821a electrical data 17- 11 table 17-9 . main oscillation stabilization time (t a = ? 40 c + 85 c, v dd = 2.0 v to 5.5 v) oscillator test condition min typ max unit c rystal fx > 400 khz ? ? 20 ms c eramic oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 10 ms external clock x in input high and low width (t xh , t xl ) 25 ? 500 ns x in t xl t xh 1 / f x v dd ? 0.1 v 0.1 v figure 17-6. clock timing measurement at x in table 17-10 . sub oscillation stabilization time (t a = ? 40 c + 85 c, v dd = 2.0 v to 5.5 v) oscillator test condition min typ max unit c rystal ? ? ? 10 s external clock xt in input high and low width (t xh , t xl ) 1 ? 18 m s xt in t xtl t xth 1 / f xt v dd ? 0.1 v 0.1 v figure 17-7. clock timing measurement at xt in
electrical data s3c821a/p821a 17- 12 instruction clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16) supply voltage (v) 1.00 mhz 8.33 khz instruction clock 2 3 7 f x (main oscillation frequency) 6 mhz 400 khz 8 mhz 2.2 5.5 1.33 mhz 1 5 4 6 figure 17-8. operating voltage range
s3c821a/p821a mecha nical data 18 - 1 1 8 mechanical data overview the s3c821a micr ocontroller is currently available in 80 -pin qfp and tqfp package. note : dimensions are in millimeters. 0.80 0.20 0.10 max 0.15 +0.10 - 0.05 0 - 8 2.65 0.10 3.00 max 0.05 min 17.90 0.3 14.00 0.2 (1.00) 80-qfp-1420c 23.90 0.3 #80 (0.80) #1 0.35 0.1 0.15 max 20.00 0.2 0.80 0.80 0.20 figure 18-1. 80- pin qf p package demensions
mechanical data s3c821a/p821a 18 - 2 note : dimensions are in millimeters. 14.00bsc 12.00bsc 80-tqfp-1212 14.00bsc 12.00bsc #80 (1.25) #1 0.17 - 0.27 0.60 0.15 0.09 - 0.20 0 - 7 1.00 0.05 1.20 max 0.05-0.15 0.08 max m 0.50 figure 18-2. 80- pin tqf p package demensions
s3c821a/p821a customer notice 19 - 1 1 9 customer notice dnjz instruction when djnz instruction is used in a program, the working register being used as a counter should be set at the one of location 0c0h to 0cfh with srp, srp0, or srp1 instruction. + + programming tip ? using djnz instruction to transport ram data from page 0 to page 1 ld pp,#10h ; destination ? 1, source ? 0 srp #0c0h ld r0,#0ffh ; transportation starts ramtrn ld r1,@r0 ld @r0,r1 djnz r0,ramtrn ld r1,@r0 ; r0 = 00h ld @r0,r1
s3c821a/p821a s3p821 a otp 20- 1 20 S3P821A otp overview the S3P821A single-chip cmos microcontroller is the otp (one time programmable) version of the s3c821a microcontroller. it has an on-chip otp rom instead of a masked rom. the eprom is accessed by serial data format. the S3P821A is fully compatible with the s3c821a, both in function and in pin configuration. because of its simple programming requirements, the S3P821A is ideal as an evaluation chip for the s3c821a.
S3P821A otp s3c821a/ p821a 20- 2 p1.1/seg25/ad1 p1.2/seg26/ad2 p1.3/seg27/ad3 p1.4/seg28/ad4 p1.5/seg29/ad5 p1.6/seg30/ad6 p1.7/seg31/ad7 sdat /p2.0/ as sclk /p2.1/ dr v dd1 /v dd1 v ss1 /v ss1 x out x in v pp /test xt in xt out reset/reset p2.2/ dw p2.3/ dm p2.4/int0/t0ck S3P821A (80-tqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 65 64 63 62 61 60 p2.5/int1/t1ck p2.6/int2/ta p2.7/int3/tb av ref p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3/adc3 av ss p3.4 p3.5 p3.6 p3.7/t0/t0pwm/t0cap p4.0/int4 p4.1/int5 p4.2/int6 p4.3/int7 p4.4/int8 p4.5/int9 p4.6/int10 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 seg4 seg3/com7 seg2/com6 seg1/com5 seg0/com4 com3 com2 com1 com0 v dd2 (ext) v ss2 v lc1 p5.6 p5.5 p5.4 p5.3/buz p5.2/so p5.1/si p5.0/sck p4.7/int11 p1.0/seg24/ad0 p0.7/seg23/a15 p0.6/seg22/a14 p0.5/seg21/a13 p0.4/seg20/a12 p0.3/seg19/a11 p0.2/seg18/a10 p0.1/seg17/a9 p0.0/seg16/a8 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 figure 20-1. S3P821A pin assignments (80-tqfp-1212 package)
s3c821a/p821a s3p821 a otp 20- 3 p0.6/seg22/a14 p0.5/seg21/a13 p0.4/seg20/a12 p0.3/seg19/a11 p0.2/seg18/a10 p0.1/seg17/a9 p0.0/seg16/a8 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 p0.7/seg23/a15 p1.0/seg24/ad0 p1.1/seg25/ad1 p1.2/seg26/ad2 p1.3/seg27/ad3 p1.4/seg28/ad4 p1.5/seg29/ad5 p1.6/seg30/ad6 p1.7/seg31/ad7 sdat /p2.0/ as sclk /p2.1/ dr v dd1 /v dd1 v ss1 /v ss1 x out x in v pp /test xt in xt out reset reset /reset p2.2/ dw p2.3/ dm p2.4/int0/t0ck p2.5/int1/t1ck p2.6/int2/ta S3P821A (80-qfp) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p2.7/int3/tb av ref p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3/adc3 av ss p3.4 p3.5 p3.6 p3.7/t0/t0pwm/t0cap p4.0/int4 p4.1/int5 p4.2/int6 p4.3/int7 p4.4/int8 seg6 seg5 seg4 seg3/com7 seg2/com6 seg1/com5 seg0/com4 com3 com2 com1 com0 v dd2 (ext) v ss2 v lc1 p5.6 p5.5 p5.4 p5.3/buz p5.2/so p5.1/si p5.0/sck p4.7/int11 p4.6/int10 p4.5/int9 figure 20-2. S3P821A pin assignments (80-qfp-1420c package)
S3P821A otp s3c821a/ p821a 20- 4 table 20-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p2.0 sdat 8 (10) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p2.1 sclk 9 (11) i/o serial clock pin. input only pin. v pp test 14 (16) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 17 (19) i chip initialization v dd1 /v ss1 v dd1 /v ss1 10 (12)/11 (13) ? logic power supply pin. v dd should be tied to + 5 v during programming. note: ( ) means 80 qfp package. table 20-2. comparison of S3P821A and s3c821a features characteristic S3P821A s3c821a program memory 48-k byte eprom 48-k byte mask rom operating voltage (v dd ) 2.0 v to 5.5 v 2.0 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v pin configuration 80 qfp/80 tqfp 80 qfp/80 tqfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the S3P821A, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 20-3 below. table 20-3. operating mode selection criteria v dd v pp ( test ) reg/ mem mem address (a15?a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level ; "1" means high level.
s3c821a/p821a s3p821 a otp 20- 5 table 20-4 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd f osc = 8 mhz (instruction clock = 1.33 mhz) 2.2 ? 5.5 v f osc = 6 mhz (instruction clock = 1 mhz) 2.0 input high voltage v ih1 p0 and p1 0.7 v dd ? v dd v v ih2 reset, p2, p3, p4, and p5 0.8 v dd v dd v ih3 x in , x t in v dd ? 0.1 v dd input low voltage v il1 p0 and p1 0 ? 0.3 v dd v il2 reset, p2, p3, p4, and p5 0.2 v dd v il3 x in , x t in 0.1 output high voltage v oh v dd = 3 v; i oh = ? 200 m a all output pins v dd ? 1.0 ? ? output low voltage v ol v dd = 3 v; i o l = 1 ma all output pins ? 0.4 1.0 input high leakage current i lih1 v i n = v dd all input pins except those specified below for i lih2 ? ? 1 a i lih2 v in = v dd x in , x out , xt in , and xt out 20 input low leakage current i lil1 v i n = 0 v all input pins except those specified below for i lil2 and reset ? ? ? 1 i lil2 v i n = 0 v x in , x out , xt in , and xt out ? 20 output high leakage current i loh v out = v dd all output pins ? ? 1 output low leakage current i lol v out = 0 v all output pins ? ? ? 1 | v dd ? comi | voltage drop (i = 0-7) v dc v dd = 2.7 v to 5.5 v ? 15 m a per common pin ? ? 120 mv | v dd ? segx | voltage drop (x = 0-31) v ds v lcd = 2.7 v to 5.5 v ? 15 m a per segment pin ? ? 120
S3P821A otp s3c821a/ p821a 20- 6 table 20-4 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit v lc2 output voltage v lc2 v dd = 2.7 v to 5.5 v lcd clock = 0 hz 0.8 v dd ? 0.15 0.8 v dd 0.8 v dd + 0.15 v v lc3 output voltage v lc3 v lc1 = v dd 0.6 v dd ? 0.15 0.6 v dd 0.6 v dd + 0.15 v lc4 output voltage v lc4 0.4 v dd ? 0.15 0.4 v dd 0.4 v dd + 0.15 v lc5 output voltage v lc5 0.2 v dd ? 0.15 0.2 v dd 0.2 v dd + 0.15 pull-up resistors r l1 v in = 0 v; t a = 25 c v dd = 3.0 10%; ports 0?5 30 80 200 k w r l2 v in = 0 v; t a = 25 c v dd = 3.0 10 % reset only 300 500 800 lcd voltage dividing resistor r lcd v lcd = 2.7 v to 5.5 v t a = 25 c 45 65 80 k w supply current i dd1 run mode; v dd = 5 .0v 10% 6.0 mhz ? 6.0 12 ma ( n ote) c rystal oscillator c1 = c2 = 22 pf 4.19 mhz 4.5 9.0 v dd = 3 .0 v 10 % 6.0 mhz 2.9 5.8 4.19 mhz 2.0 4.0 i dd2 idle mode; v dd = 5 .0 v 0% 6.0 mhz 1.3 2.6 c rystal oscillator c1 = c2 = 22 pf 4.19 mhz 1.2 2.4 v dd = 3 .0 v 10 % 6.0 mhz 0.6 1.2 4.19 mhz 0.4 0.8 i dd 3 run mode; v dd = 3 .0 v 10 % 32 k hz crystal oscillator 20 40 a i dd 4 idle mode; v dd = 3 .0 v 10 % 32 k hz crystal oscillator 7 14 i dd 5 stop mode; v dd = 5 .0 v 10 % 0.5 3 stop mode; v dd = 3 .0 v 10 % 0.3 2 note s : 1. supply current does not include current drawn through internal pull-up resistors , lcd voltage dividing resistors, and adc . 2. i dd1 and i dd2 include power consumption for subsystem clock oscillation. 3. i dd3 and i dd4 are current when main system clock oscillation stops and the subsystem clock is used. 4. i dd5 is current when main system clock and subsystem clock oscillation stops.
s3c821a/p821a s3p821 a otp 20- 7 instruction clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16) supply voltage (v) 1.00 mhz 8.33 khz instruction clock 2 3 7 f x (main oscillation frequency) 6 mhz 400 khz 8 mhz 2.2 5.5 1.33 mhz 1 5 4 6 figure 20-3. operating voltage range
s3c821a/p821a development tools 21- 1 21 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7 , s3c 6, s3c 8 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, as s embler, and a program for setting options. shine samsung host interface for in - c ircuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm88 the sasm88 is a relocatable assembler for samsung's s3c 8-series microcontrollers. the sasm88 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm88 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value " ff " is filled into the unused rom area up to the maximum rom size of the target device automatically. target boards target boards are available for all s3c 8-series microcontrollers. all required target system cables and adapters are included with the device-specific target board.
development tools s3c821a/p821a 21- 2 ram break/ display unit target application system probe adapter tb821a target board prom/otp writer unit trace/timer unit sam8 base unit power supply unit pod rs-232c ibm-pc at or compatible bus smds2+ eva chip figure 21-1. smds product configuration (smds2+)
s3c821a/p821a development tools 21- 3 tb821a target board the tb821a target board is used for the s3c821a microcontroller. it is supported with the smds2+. sm1317a tb821a 1 25 off on to user_vcc rese + stop + idle 100-pin connector j10 144 qfp s3e8210 eva chip 40 -pin connector 1 2 39 40 40 -pin connector 41 42 79 80 j10 7411 mds xtal xi gnd vcc figure 21-2 . tb821a target board configuration
development tools s3c821a/p821a 21- 4 table 21-1. power selection settings for tb821a " to user_vcc " settings operating mode comments to user_vcc on off v cc tb821a target system smds2/smds2+ v ss v cc the smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_vcc on off v cc tb821a target system smds2/smds2+ v ss external v cc the smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. note : the following symbol in the " to user_vcc " setting column indicates the electrical short (off) configuration: a table 21-2. main-clock selection settings for tb821a sub clock settings operating mode comments xtal mds xin x i n smds2/ smds2+ eva chip s3e8210 x out no connection 100 pin connector set the xi switch to ?mds? when the target board is connected to the smds2/smds2+. xtal mds xin x in target board eva chip s3e8210 x out xtal set the xi switch to ?xtal? when the target board is used as a standalone unit, and is not connected to the smds2/smds2+.
s3c821a/p821a development tools 21- 5 smds2+ selection (sam8) in order to write data into program memory that is available in smds2+, the target board should be selected to be for smds2+ through a switch as follows. otherwise, the program memory writing function is not available. table 21-3 . the smds2+ tool selection setting "sw1" setting operating mode smds smds2+ smds2+ target board r/w* r/w* idle led the yellow led is on when the evaluation chip ( s3e8210 ) is in idle mode. stop led the red led is on when the evaluation chip ( s3e8210 ) is in stop mode.
development tools s3c821a/p821a 21- 6 j101 40 -pin dip connector 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 p0.7/seg23/a15 p1.1/seg25/ad1 p1.3/seg27/ad3 p1.5/seg29/ad5 p1.7/seg31/ad7 p2.1/ dr v s s1 x in xt in reset p2.3/ dm p2.5/int1/t1ck p2.7/int3/tb p3.0/adc0 p3.2/adc2 av ss p3.5 p3.7/t0/t0pwm/t0cap p4.1/int5 p4.3/int7 p1.0/seg24/ad0 p1.2/seg26/ad2 p1.4/seg28/ad4 p1.6/seg30/ad6 p2.0/ as v dd1 (int) x out test xt out p2.2/ dw p2.4/int0/t0ck p2.6/int2/ta av ref p3.1/adc1 p3.3/adc3 p3.4 p3.6 p4.0/int4 p4.2/int6 p4.4/int8 j102 40 -pin dip connector 41 4 3 4 5 4 7 4 9 51 53 55 57 59 61 63 65 6 7 69 71 73 75 77 79 42 4 4 4 6 4 8 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 p4.6/int10 p5.0/ sck p5.2/so p5.4 p5.6 v ss2 com0 com2 seg0/com4 seg2/com6 seg4 seg6 seg8 seg10 seg12 seg14 p0.0/seg16/a8 p0.2/seg18/a10 p0.4/seg20/a12 p0.6/seg22/a14 p4.5/int9 p4.7/int11 p5.1/si p5.3/buz p5.5 vlc1 v dd2 (ext) com1 com3 seg1/com5 seg3/com7 seg5 seg7 seg9 seg11 seg13 seg15 p0.1/seg17/a9 p0.3/seg19/a11 p0.5/seg21/a13 figure 21-3 . 40 -pin connector s (j101, j102) for tb821a
s3c821a/p821a development tools 21- 7 40 -pin dip connectors target board target system target cable for 40 pin connector part name: as40d-a order code: sm6306 j102 41 42 79 80 1 2 39 40 j101 j101 j102 1 2 39 40 41 42 79 80 40 -pin dip connectors figure 21-4 . s3c821a cables for 80 - qf p package

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