october 2011 FDD86110 n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 1 www.fairchildsemi.com FDD86110 rev.c FDD86110 n-channel powertrench ? mosfet 100 v, 50 a, 10.2 m features ? max r ds(on) = 10.2 m at v gs = 10 v, i d = 12.5 a ? max r ds(on) = 16 m at v gs = 6 v, i d = 9.8 a ? 100% uil tested ? rohs compliant general description this n-channel mosfet is produced using fairchild semiconductor?s advanced power trench ? process that has been especially tailored to minimi ze the on-state resistance and yet maintain superior switching performance. application ? dc - dc conversion g s d to-252 d-pak (to-252) d g s mosfet maximum ratings t c = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 100 v v gs gate to source voltage 20 v i d drain current -continuous (package limited) t c = 25 c 50 a -continuous (silicon limited) t c = 25 c 80 -continuous t a = 25 c (note 1a) 12.5 -pulsed 60 e as single pulse avalanche energy (note 3) 135 mj p d power dissipation t c = 25 c 127 w power dissipation t a = 25 c (note 1a) 3.1 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case 0.98 c/w r ja thermal resistance, junction to ambient (note 1a) 40 device marking device package reel size tape width quantity FDD86110 FDD86110 d-pak(to-252) 13 ?? 12 mm 2500 units
FDD86110 n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 2 www.fairchildsemi.com FDD86110 rev.c electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 100 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 72 mv/c i dss zero gate voltage drain current v ds = 80 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 20 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a22.84v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -10 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 12.5 a 8.5 10.2 m v gs = 6 v, i d = 9.8 a 11.3 16 v gs = 10 v, i d = 12.5 a,t j = 125c 15 18 g fs forward transconductance v ds = 10 v, i d = 12.5 a 38 s c iss input capacitance v ds = 50 v, v gs = 0 v, f = 1mhz 1702 2265 pf c oss output capacitance 379 505 pf c rss reverse transfer capacitance 17 30 pf r g gate resistance 0.5 t d(on) turn-on delay time v dd = 50 v, i d = 12.5 a, v gs = 10 v, r gen = 6 12 20 ns t r rise time 5.4 10 ns t d(off) turn-off delay time 19 35 ns t f fall time 3.9 10 ns q g total gate charge v gs = 0 v to 10 v v dd = 50 v, i d = 12.5 a 25 35 nc q gs gate to source charge 7.1 nc q gd gate to drain ?miller? charge 5.2 nc v sd source-drain diode forward voltage v gs = 0 v, i s = 12.5 a (note 2) 0.80 1.3 v v gs = 0 v, i s = 2.6 a (note 2) 0.72 1.2 t rr reverse recovery time i f = 12.5 a, di/dt = 100 a/ s 52 83 ns q rr reverse recovery charge 60 96 nc notes : 1: r ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the s older mounting surface of the drain pins. r jc is guaranteed by design while r ja is determined by the user?s board design. 2: pulse test: pulse width < 300 s, duty cycle < 2.0%. 3: starting t j = 25 c, l = 0.3 mh, i as = 30 a, v dd = 90 v, v gs = 10 v. 40 c/w when mounted on a 1 in 2 pad of 2 oz copper 96 c/w when mounted on a minimum pad a) b)
FDD86110 n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 3 www.fairchildsemi.com FDD86110 rev.c typical characteristics t j = 25 c unless otherwise noted figure 1. 012345 0 15 30 45 60 v gs = 5.5 v v gs = 5 v v gs = 10 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 6 v v gs = 4.5 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 15304560 0 1 2 3 4 5 v gs = 5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4.5 v v gs = 6 v v gs = 5.5 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i d = 12.5 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 45678910 0 10 20 30 40 50 t j = 125 o c i d = 12.5 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 234567 0 15 30 45 60 t j = 25 o c t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 100 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDD86110 n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 4 www.fairchildsemi.com FDD86110 rev.c figure 7. 0 5 10 15 20 25 0 2 4 6 8 10 i d = 12.5 a v dd = 50 v v dd = 25 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 75 v gate charge characteristics figure 8. 0.1 1 10 100 10 100 1000 5000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.1 1 10 100 1 10 100 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 20 40 60 80 limited by package v gs = 6 v r t jc = 0.98 o c/w v gs = 10 v i d , drain current (a) t c , c ase temperature ( o c ) maximum continous drain current vs. case temperature figure 11. 0.1 1 10 100 400 0.5 1 10 80 10 ms 100 p s dc 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t jc = 0.98 o c/w t c = 25 o c forward bias safe operating area figure 12. 10 -5 10 -4 10 -3 10 -2 10 -1 1 50 100 1000 10000 single pulse r t jc = 0.98 o c/w t c = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) single pulse maximum power dissipation typical characteristics t j = 25 c unless otherwise noted
FDD86110 n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 5 www.fairchildsemi.com FDD86110 rev.c figure 13. 10 -5 10 -4 10 -3 10 -2 10 -1 1 0.01 0.1 1 single pulse r t jc = 0.98 o c/w duty cycle-descending order normalized thermal impedance, z t jc t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t jc x r t jc + t c junction-to-case transient thermal response curve typical characteristics t j = 25 c unless otherwise noted
FDD86110 n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 6 www.fairchildsemi.com FDD86110 rev.c trademarks the following includes registered and unregistered trademarks and se rvice marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical co mponents in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used here in: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi ficant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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