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  innovative power tm - 1 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. act8342 three channel integrated power management ic for handheld portable equipment rev 3, 11-sep-09 system blo ck diagram features ? multiple patents pending ? three integrated regulators ? 350ma pwm step-down dc/dc ? 80ma low noise ldo ? 150ma low noise ldo ? independent enable/disable control ? minimal external components ? 3 3mm, thin-qfn (tqfn33-16) package ? only 0.75mm height ? rohs compliant applications ? portable devices and pdas ? mp3/mp4 players ? wireless handhelds ? gps receivers, etc. general description the patent-pending act8342 is a complete, cost effective, highly-efficient activepmu tm power management solution that is ideal for a wide range of portable handheld equipment. this device integrates one pwm step-down dc/dc converter and two low noise, low dropout linear regulators (ldos) in a single, thin, space-saving package. this device is ideal for a wide range of portable handheld equipment that can benefit from the advantages of activepmu tm technology but does not require a high level of integration. reg1 is a fixed-frequency, current-mode pwm step-down dc/dc converter that is optimized for high efficiency and is capable of supplying up to 350ma output current. reg1?s output is available in a variety of factory-preset output voltage options, and an adjustable output voltage mode is also available. reg2 and reg3 are low noise, high psrr linear regulators that are capable of supplying up to 80ma and 150ma, respectively. the act8342 is available in a tiny 3mm 3mm 16-pin thin-qfn package that is just 0.75mm thin. out1 adjustable, or 1.2v to 3.3v up to 350ma out2 1.4v to 3.7v up to 80ma out3 1.4v to 3.7v up to 150ma on2 on3 system control reg3 ldo reg2 ldo battery reg1 step-down dc/dc act8342 tm pmu pmu active nirq nmstr nrsto on1 pb pb-free
act8342 rev 3, 11-sep-09 innovative power tm - 2 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. functional block diagram reg1 vp1 gp1 sw1 out1 out1 ga to battery act8342 reg2 ldo to battery or out1 on1 on3 reg3 ldo inl out2 out3 nrsto nmstr push button nirq inl out2 out2 on2 system control refbp reference a ctive- semi
act8342 rev 3, 11-sep-09 innovative power tm - 3 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. ordering information cd pin configuration thin-qfn (tqfn33-16) 7 8 5 6 11 12 9 10 15 16 13 14 3 4 1 2 nirq nmstr out1 nrsto act8342 on1 on2 inl out3 refbp ga ga on3 out2 gp1 vp1 sw1 part number v out1 v out2 v out3 pins temperature range act8342qkcqi-t 1.2v 2.85v 2.85v 16 -40c to +85c package tqfn33-16 ACT8342QKP2D-T 1.2v 2.2v 2.6v tqfn33-16 16 -40c to +85c c : output voltage options detailed in this table represent st andard voltage options, and are available for samples or production orders. additional output voltage options, as detailed in the output voltage codes table, are available for pro duction subject to minimum order quantities. contact active-semi for more informatio n regarding semi-custom output voltage combinations. d : all active-semi components are rohs compliant and with pb-free plating unless specified differently. the term pb-free means semiconductor products that are in compliance with current rohs (restriction of haza rdous substances) standards. reg1 output voltage codes a d e f i g adjustable 1.5v 1.8v 2.5v 2.8v 3.0v c 1.2v p 1.3v j 1.4v q 2.85v h 3.3v top view reg2 output voltage codes j d l e 2 f i q 1.4v 1.5v 1.7v 1.8v 2.2v 2.5v 2.8v 2.85v g 3.0v h 3.3v reg3 output voltage codes e g k m b d h i 1.4v 1.5v 1.7v 1.8v 2.5v 2.6v 2.8v 2.85v l 3.0v r 3.3v
act8342 rev 3, 11-sep-09 innovative power tm - 4 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. pin descriptions pin name description 1 nirq open-drain push-button status ou tput. nirq is an open-drain ou tput which sinks current when nmstr is asserted or when a fault-condit ion occurs. if interrupts are not masked. 2 nmstr master enable input. drive nmstr to ga or to a logic low to enable the ic. 3 nrsto open-drain reset output. nrsto asserts low for the reset timeout period of 300ms whenever the ic is enabled. 4 out1 output feedback sense. for fixed output voltage options reg1, connect this pin directly to the output node to connect the internal feedback netwo rk to the output voltage. for adjustable output voltage options reg1. the voltage at this pin is regulated to 0.625v. connect this pin to the center point of the output voltage feedback netwo rk between output node and ga to set the output voltage. 5 vp1 power input for reg1. bypass to gp1 with a high quality ceramic capacitor placed as close as possible to the ic. 6 sw1 switching node output for reg1. connect th is pin to the switching end of the inductor. 7 gp1 power ground for reg1. connect ga, gp1 together at a single point as close to the ic as possible. 8 out2 output voltage for reg2. capable of delivering up to 80ma of output current. output is discharged to ground with 650 ? resistor when disabled. 9 inl power input for reg2, reg3. bypass to ga with a high quality ceramic capacitor placed as close as possible to the ic. 10 out3 output voltage for reg3. capable of deliveri ng up to 150ma of output current. output is discharged to ground with 650 ? resistor when disabled. 11 on2 enable control input for reg2. drive on2 to inl or to a logic high for normal operation, drive to ga or a logic low to disable reg2. 12 on1 enable control input for reg1. drive on1 to the vp1 or a logic high for normal operation, drive to ga or a logic low to disable reg1. 13 refbp reference noise bypass. connect a 0.01f ceramic capacitor from refbp to ga. this pin is discharged to ga in shutdown. 14, 16 ga analog ground. connect ga directly to a quiet ground node. connect ga, gp1 together at a single point as close to the ic as possible. 15 on3 enable control input for reg3. drive on3 to the in l or a logic high for normal operation, drive to ga or a logic low to disable reg3.
act8342 rev 3, 11-sep-09 innovative power tm - 5 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. c : do not exceed these limits to prevent damage to the device. exposure to absolute maximum rati ng conditions for long periods m ay affect device reliability. absolute maximum ratings c parameter value unit sw1 to gp1, inl, vp1, out1, out2, out3, on1, on2, on3, nmstr, nrsto, nirq, refbp to ga -0.3 to +6 v sw1 to vp1 -6 to +0.3 v gp1 to ga -0.3 to +0.3 v junction to ambient thermal resistance ( ja ) 33 c/w operating temperature range -40 to 85 c junction temperature 125 c storage temperature -55 to 150 c lead temperature (soldering, 10 sec) 300 c
act8342 rev 3, 11-sep-09 system management innovative power tm - 6 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. electrical characteristics (v inl = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit inl operating voltage range 2.7 5.5 v inl uvlo threshold inl voltage rising 2.25 2.5 2.7 v inl uvlo hysteresis inl voltage falling 90 mv oscillator frequency 1.35 1.6 1.85 mhz inl supply current on1 = on2 = on3 = ga 1.5 a nmstr internal pull-up resistance 250 500 k ? logic high input voltage on1, on2, on3, nmstr 1.4 v logic low input voltage on1, on2, on3, nmstr 0.4 v logic low output voltage i sink = 5ma 0.3 v thermal shutdown temperature temperature rising 160 c thermal shutdown hysteresis temperature falling 20 c leakage current nirq, nrsto, v nrsto = v nirq = 4.2v 1 a nrsto delay 240 300 360 ms
act8342 rev 3, 11-sep-09 system management innovative power tm - 7 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. functional description general description the act8342 offers an array of system management functions that allow it to provide optimal performance in a wide range of applications. system startup and shutdown the act8342 features a flexible control architecture that supports a variety of software- controlled enable/disable functions that make it a simple yet flexible and highly configurable solution. the act8342 is automatically enabled when any of the following conditions exists: 1) nmstr is asserted low, or 2) on1 is asserted high, or 3) on2 is asserted high, or 4) on3 is asserted high. if any of these conditions is true, the act8342 enables and on1 drives reg1, on2 drives reg2, and on3 drives reg3. manual enable due to asserting nmstr low system startup is initiated when the user presses the push-button, assertin g nmstr low. when this occurs, reg1 is enabled, which in turn enables the processor to allow it to control the system power up sequence. once the power-up routine is successfully completed, the microprocessor must assert on1 so that the act8342 remains enabled after the push-button is released by the user. upon completion of the start-up sequence the processor assumes control of the power system and all further operation is software-controlled. manual enable due to asserting on1 high the act8342 is compatible with applications that do not utilize it?s push-butt on control function, and may be enabled by simply driving on1 to a logic- high. in this case, the signal driving on1 controls enable/disable timing, although software-controlled enable/disable sequences are still supported if the processor assumes control of the power system once the startup sequence is completed. shutdown sequence once a successful power-up routine is completed, the system processor contro ls the operation of the power system, including the system shutdown timing and sequence. the act8342 asserts nirq low when nmstr is asserted low, providing a simple means of alerting the system processor when the user wishes to shut the system down. asserting nirq interrupts the system processor, initiating an interrupt service routine in the processor which will reveal that the user pressed the push-button. the microprocessor may validate the input, such as by ensuring that the push-button is asserted for a minimum amount of time, then initiates a software-controlled power-down routine, the final step of which is to de-assert the on1 input, disabling reg1 and reg2 and shutting the system down. nmstr enable input in most applications, connect nmstr to an active low, momentary push-butt on switch to utilize the act8342?s closed-loop enable/disable functionality. if a momentary-on switch is not used, drive nmstr to ga or to a logic low to initiate a startup sequence. enable/disable inputs the act8342 provides three manual enable/disable inputs. w hen driven high, on1 enables reg1, on2 enables reg2, and on3 enables out3. nirq output the act8342 provides an active-low, open-drain push-button status output t hat sinks current when nmstr is driven to a logic-low. connect a pull-up resistor from nirq to an appropriate voltage supply. nirq is typically used to dr ive the interrupt input of the system processor, and is useful in a variety of software-controlled enable/disable control routines. thermal shutdown the act8342 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. this circuitry disables all regulators if the act8342 die temperature exceeds 160c, and prevents the regulators from being enabled until the ic temperature drops by 20c (typ).
act8342 rev 3, 11-sep-09 system management innovative power tm - 8 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. typical performanc e characteristics (v inl = 3.6v, t a = 25c, unless otherwise specified.) oscillator frequency vs. temperature frequency (mhz) temperature (c) 1.71 1.50 act8342-001 1.68 1.65 1.62 1.59 1.56 1.53 85 -20 -40 0 20 40 60 startup sequence act8342-002 ch1 ch2 ch3 ch1: v nmstr , 5v/div ch2: v nrsto , 2v/div ch3: v on1 , 5v/div ch4: v out1 , 2v/div ch4 time: 100ms/div shutdown sequence act8342-003 ch1 ch2 ch3 ch4 ch1: v nmstr , 5v/div ch2: v nirq , 2v/div ch3: v on1 , 5v/div ch4: v out1 , 2v/div time: 100ms/div
act8342 rev 3, 11-sep-09 step-down dc/dc converter innovative power tm - 9 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. electrical characteristics (reg1) (v vp1 = 3.6v, t a = 25c, unless otherwise specified.) c : v nom1 refers to the nominal output voltage level for v out1 as defined by the ordering information section. parameter test conditions min typ max unit vp1 operating voltage range 3.1 5.5 v vp1 uvlo threshold input vo ltage rising 2.9 3 3.1 v vp1 uvlo hysteresis input voltage falling 90 mv standby supply current 130 200 a shutdown supply current on1 = ga, v vp1 = 4.2v 0.1 1 a adjustable output option regulation voltage 0.625 v output voltage regulation accuracy v nom1 < 1.3v, i out1 = 10ma -2.4% v nom1 c +1.8% v v nom1 1.3v, i out1 = 10ma -1.2% v nom1 +1.8% line regulation v vp1 = max(v nom1 + 1v, 3.2v) to 5.5v 0.15 %/v load regulation i out1 = 10ma to 350ma 0.0017 %/ma current limit 0.45 0.6 a oscillator frequency v out1 20% of v nom1 1.35 1.6 1.85 mhz v out1 = 0v 530 khz pmos on-resistance i sw1 = -100ma 0.52 0.88 ? nmos on-resistance i sw1 = 100ma 0.27 0.46 ? sw1 leakage current v vp1 = 5.5v, v sw1 = 5.5v or 0v 1 a power good threshold 94 %v nom1 minimum on-time 70 ns
act8342 rev 3, 11-sep-09 step-down dc/dc converter innovative power tm - 10 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. typical performanc e characteristics (act8342qkcqi, v vp1 = 3.6v, l = 3.3h, c vp1 = 2.2 f, c out1 = 10 f, t a = 25c, unless otherwise specified.) reg1 transient peak inductor current peak inductor current (ma) 650 vp1 voltage (v) 5.5 act8342-005 3.5 4.0 4.5 5.0 630 610 590 570 3.0 550 reg1 mosfet resistance r dson (m ? ) vp1 voltage (v) 600 0 act8342-006 5.5 5.0 4.5 4.0 3.5 3.0 2.5 500 400 300 200 100 reg1 load regulation load regulation error (%) 0.2 0 400 output current (ma) act8342-007 50 100 150 200 250 300 350 0.0 -0.2 -0.4 -0.6 -0.8 pmos nmos 3.6v 4.2v -1.0 reg1 efficiency vs. load current efficiency (%) 50 1000 output current (ma) 95 80 70 60 1 10 100 v out1 = 1.2v v in = 4.2v 85 75 65 55 90 v in = 3.6v out1 regulation voltage out1 voltage (%) 0.67 -0.67 temperature (c) act8342-008 -20 -40 0 20 40 60 0.44 0.22 0.00 -0.22 -0.44 i out1 = 35ma 85 -0.11 -0.33 -0.56 0.11 0.33 0.56 act8342-004
act8342 rev 3, 11-sep-09 step-down dc/dc converter innovative power tm - 11 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. functional description general description reg1 is a fixed-frequency, current-mode, synchronous pwm step-down converters that achieves a peak efficiency of up to 97%. reg1 is capable of supplying up to 350ma of output current and operates with a fixed frequency of 1.6mhz, minimizing noise in sensitive applications and allowing the use of small external components. reg1 is available with a variety of standard and custom output voltages, as well as an adjustable output voltage option. 100% duty cycle operation reg1 is capable of operating at up to 100% duty cycle. during 100% duty-cycle operation, the high-side power mosfet is held on continuously, providing a direct connection from the input to the output (through the inducto r), ensuring the lowest possible dropout voltage in battery-powered applications. synchronous rectification reg1 features an integrated n-channel synchronous rectifier, which maximizes efficiency and minimizes the total solution size and cost by eliminating the need for an external rectifier. enabling and disabling reg1 reg1 is enabled or disabled using on1. drive on1 to a logic-high to enable reg1. drive on1 to a logic-low to disable reg1, reducing supply current to less than 1a. soft-start reg1 includes internal soft-start circuitry, and enabled its output voltage tracks an internal 80s soft-start ramp so that it powers up in a monotonic manner that is independent of loading. compensation reg1 utilizes current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over its full operating range. no compensation design is required, simply follow a few simple guidelines described below when choosing external components. input capacitor selection the input capacitor reduces peak currents and noise induced upon the voltage source. a 2.2f ceramic input capacitor is recommended for most applications. output capacitor selection for most applications, a 10f ceramic output capacitor is recommended. although reg1 was designed to take advantage of the benefits of ceramic capacitors, namely small size and very-low esr, low-esr tantalum capacitors can provide acceptable results as well. inductor selection reg1 utilizes current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over its full operating range. reg1 was optimized for operation with a 3.3h inductor, although inductors in the 2.2h to 4.7h range can be used. choose an inductor with a low dc-resistance, and avoid inductor saturation by choosing inductors with dc ratings that exceed the maximum output current of the application by at least 30%. thermal shutdown the act8342 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. this circuitry disables all regulators if the act8342 die temperature exceeds 160c, and prevents the regulators from being enabled until the ic temperature drops by 20c (typ). output voltage programming figure 4 shows the feedback network necessary to set the output voltage when using the adjustable output voltage option. se lect components as follows: set r fb2 = 51k ? , then calculate r fb1 using the following equation: where v fb is 0.625v ? ? ? ? ? ? ? ? ? = 1 v v r r fb 1 out 2 fb 1 fb (1)
act8342 rev 3, 11-sep-09 step-down dc/dc converter innovative power tm - 12 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. r fb1 r fb2 out1 act8342 out1 c ff v fb figure 4: output voltage programming finally choose c ff using the following equation: where r fb1 = 47k ? , use 47pf. pcb layout considerations high switching frequencies and large peak currents make pc board layout an important part of step- down dc/dc converter design. a good design minimizes excessive emi on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. step-down dc/dcs exhibit discontinuous input current, so the input capacitors should be placed as close as possible to the ic, and avoiding the use of vias if possible. the inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. the ground nodes for each regulator's power loops should be connected at a single point in a star-ground configuration, and this point should be connected to the backside ground plane with multiple vias. for fixed output voltage options, connect the output node directly to the out1 pin. for adjustable output voltage options, connect the feedback resistors and feed-forward capacitor to the out1 pin through the s hortest possible route. in both cases, the feedback path should be routed to maintain sufficient distance from switching nodes to prevent noise injection. finally, the exposed pad should be directly connected to the backside ground plane using multiple vias to achieve low electrical and thermal resistance. (2) 1 fb 6 ff r 10 2 . 2 c ? =
act8342 rev 3, 11-sep-09 low-dropout line ar regulators innovative power tm - 13 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. electrical characteristics (reg2) (v inl = 3.6v, c out2 = 1f, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit inl operating voltage range 3.1 5.5 v inl uvlo threshold v inl input rising 2.9 3 3.1 v uvlo hysteresis v inl input falling 0.1 v output voltage accuracy t a = 25c -1.2 v nom2 1 +2 % t a = -40c to 85c -2.5 v nom2 +3 line regulation error v inl = max(v out2 + 0.5v, 3.6v) to 5.5v 0 mv load regulation error i out2 = 1ma to 80ma -0.004 %/ma power supply rejection ratio f = 1khz, i out2 = 80ma, c out2 = 1f 70 db f = 10khz, i out2 = 80ma, c out2 = 1f 60 supply current per output regulator enabled 50 a regulator disabled 0 dropout voltage 2 i out2 = 40ma, v out2 > 3.1v 100 200 mv output current 80 ma current limit e v out2 = 95% of regulation voltage 90 ma internal soft-start 100 s power good flag high threshold v out2 , hysteresis = -4% 89 % output noise c out2 = 10f, f = 10hz to 100khz 40 v rms stable c out2 range 1 20 f discharge resistor in shutdown ldo disabled 650 ? c : v nom2 refers to the nominal output voltage level for v out2 as defined by the ordering information section. d : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below the regulation voltage at 1v differential voltage. e : ldo current limit is defined as the output current at which t he output voltage drops to 95% of the respective regulation volt age. under heavy overload conditions the output current limit folds back by 30% (typ)
act8342 rev 3, 11-sep-09 low-dropout line ar regulators innovative power tm - 14 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. electrical characteristics (reg3) (v inl = 3.6v, c out3 = 1f, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit inl operating voltage range 3.1 5.5 v inl uvlo threshold v inl input rising 2.9 3 3.1 v uvlo hysteresis v inl input falling 0.1 v output voltage accuracy t a = 25c -1.2 v nom3 1 +2 % t a = -40c to 85c -2.5 v nom3 +3 line regulation error v inl = max(v out3 + 0.5v, 3.6v) to 5.5v 0 mv load regulation error i out3 = 1ma to 150ma -0.004 %/ma power supply rejection ratio f = 1khz, i out3 = 150ma, c out3 = 1f 70 db f = 10khz, i out3 = 150ma, c out3 = 1f 60 supply current per output regulator enabled 50 a regulator disabled 0 dropout voltage 2 i out3 = 80ma, v out3 > 3.1v 100 200 mv output current 150 ma current limit e v out3 = 95% of regulation voltage 170 ma internal soft-start 100 s power good flag high threshold v out3 , hysteresis = -4% 89 % output noise c out3 = 10f, f = 10hz to 100khz 40 v rms stable c out3 range 1 20 f discharge resistor in shutdown ldo disabled 650 ? c : v nom3 refers to the nominal output voltage level for v out2 as defined by the ordering information section. d : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below the regulation voltage at 1v differential voltage. e : ldo current limit is defined as the output current at which t he output voltage drops to 95% of the respective regulation volt age. under heavy overload conditions the output current limit folds back by 30% (typ)
act8342 rev 3, 11-sep-09 low-dropout line ar regulators innovative power tm - 15 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. typical performanc e characteristics (act8342qkcqi, v inl = 5v, t a = 25c, unless otherwise specified.) load regulation output voltage (%) load current (ma) 0.20 -0.20 act8342-009 0 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 dropout voltage (mv) output current (ma) ldo2 dropout voltage vs. output current act8342-011 250 20 0 60 40 ldo output voltage noise ch1 act8342-014 ch1: v outx , 200v/div (ac coupled) time: 200ms/div region of stable c out esr vs. output current 20 40 60 100 120 300 200 150 100 50 0 80 1 0.1 0.01 0 50 100 150 esr ( ? ) 100 120 140 160 output current (ma) stable esr 80 ldo2 ldo3 output voltage deviation (%) temperature (c) -40 85 act8342-010 -15 10 35 60 -0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 i load = 0ma output voltage deviation vs. temperature 0.5 dropout voltage (mv) output current (ma) act8342-012 160 20 0 60 40 200 120 80 40 0 100 120 160 80 140 ldo3 dropout voltage vs. output current 3.1v 3.7v 3.1v 3.7v act8342-013
act8342 rev 3, 11-sep-09 low-dropout line ar regulators innovative power tm - 16 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. functional description general description reg2 and reg3 are low-noise, low-dropout linear regulators (ldos) that ar e optimized for low-noise and high-psrr operation, achieving more than 60db psrr at frequencies up to 10khz. output current capability reg2 supplies up to 80ma while reg3 supplies up to 150ma of load current. excellent performance is achieved over each regulat or's entire load current ranges. output current limit in order to ensure safe operation under over-load conditions, each ldo features current-limit circuitry with current fold-back. the current-limit circuitry limits the current that can be drawn from the output, providing protection in over-load conditions. for additional protection under extreme over current conditions, current-fold-back protection reduces the current-limit by approximately 30% under extreme overload conditions. enabling and disabling the ldos reg2 and reg3 are enabled or disabled using on2 and on3. drive on2 and on3 to a logic-high to enable reg2 and reg3. drive on2 and on3 to a logic-low to disable reg2 and reg3, reducing supply current to less than 1a. output capacitor selection reg2 and reg3 each require only a small ceramic capacitor for stability. for best performance, each output capacitor should be connected directly between the out2 and out3 and g pins as possible, with a short and direct connection. to ensure best performance fo r the device, the output capacitor should have a minimum capacitance of 1f, and esr value between 10m ? and 200m ? . high quality ceramic capacitors such as x7r and x5r dielectric types are strongly recommended. pcb layout considerations the act8342?s ldos provide good dc, ac, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. when designing a pcb, however, careful layout is necessary to prevent other circuitry from degrading ldo performance. a good design places input and output capacitors as close to the ldo inputs and output as possible, and utilizes a star-ground configuration for all regulators to prevent noise-coupling through ground. output traces should be routed to avoid close proximity to noisy nodes, particularly the sw nodes of the dc/dcs.
act8342 rev 3, 11-sep-09 package information innovative power tm - 17 - www.active-semi.com copyright ? 2008 active-semi, inc. activepmu tm is a trademark of active-semi. active-semi, inc. reserves the right to modify the circuitry or spec ifications without notice. users should evaluate each produ ct to make sure that it is suitable for their applications. active-semi pr oducts are not intended or authorized for use as critical compon ents in life- support devices or systems. active-semi, inc. does not assume an y liability arising out of the use of any product or circuit de scribed in this datasheet, nor does it convey any patent license. active-semi and its logo are trademarks of active-semi, inc. for more information on this and other products, contact sales@active- semi.com or visit http://www.active-semi.com. for other inquiri es, please send to: 1270 oakmead parkway, suite 310, sunnyvale, california 94085-4044, usa package outline tqfn33-16 package outline and dimensions d e a3 a a1 e1 e b l d1 k symbol dimension in millimeters dimension in inches min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.153 d 2.900 3.100 0.114 0.122 e 2.900 3.100 0.114 0.122 d2 1.600 1.800 0.063 0.071 e2 1.600 1.800 0.063 0.071 b 0.180 0.300 0.007 0.012 e 0.500 typ 0.020 typ l 0.300 0.500 0.012 0.020 k 0.200 0.400 0.008 0.016 0.006 0.253 0.010


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