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| august 2010 ? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7nz04 ? rev. 1.0.2 nc7nz04 ? tinylogic ? uhs inverter nc7nz04 tinylogic ? uhs inverter features ? ultra-high speed: t pd 2.4ns (typical) into 50pf at 5v v cc ? high output drive: 24ma at 3v v cc ? broad v cc operating range: 1.65v to 5.5v ? power-down, high-impedance inputs / outputs ? over-voltage tolerance inputs facilitate 5v to 3v translation ? proprietary noise / emi reduction circuitry ? space-saving micropak? and us8 surface mount packages description the nc7nz04 is a triple inverter from fairchild?s ultra- high speed (uhs) series of tinylogic?. the device is fabricated with advanced cmos technology to achieve ultra-high speed with high output drive while maintaining low static power dissipation over a broad v cc operating range. the device is specifi ed to operate over the 1.65v to 5.5v v cc operating range. the inputs and output are high impedance when v cc is 0v. inputs tolerate voltages up to 7v, independent of v cc operating voltage. ieec/iec figure 1. logic symbol figure 2. connection diagram ordering information part number top mark package packing method NC7NZ04K8X nz04 8-lead us8, jedec mo-187, variation ca 3.1mm wide 3000 units on tape & reel nc7nz04l8x t3 8-lead micropak?, 1.6mm wide 5000 units on tape & reel micropak? is a trademarks of fairchild semiconductor corporation.
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7nz04 ? rev. 1.0.2 2 nc7nz04 ? tinylogic ? uhs inverter pin configurations figure 3. us8 notes: 1. aaa represents product code t op mark (see ordering table). 2. orientation of top mark determines pin one location. reading the top product code mark left to right, pin one is the lower left pin. figure 4. micropak? (top through view) pin definitions pin # us8 pin # micropak? name description 1 7 1a input 2 6 3y output 3 5 2a input 4 4 gnd ground 5 3 2y output 6 2 3a input 7 1 1y output 8 8 v cc supply voltage function table y= /a inputs output a y l h h l ? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7nz04 ? rev. 1.0.2 3 nc7nz04 ? tinylogic ? uhs inverter absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 7.0 v v in dc input voltage -0.5 7.0 v v out dc output voltage -0.5 7.0 v i ik dc input diode current v in < -0.5v -50 ma v in > 6.0v +20 i ok dc output diode current v out < -0.5v -50 ma v out > 6v, v cc =gnd +20 i out dc output current 50 ma i cc or i gnd dc v cc or ground current 50 ma t stg storage temperature range -65 +150 c t j junction temperature under bias +150 c t l junction lead temperature (sol dering, 10 seconds) +260 c p d power dissipation at +85c 250 mw esd human body model, jedec:jesd22-a114 4000 v charge device model, jedec:jesd22-c101 2000 recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc supply voltage operating 1.65 5.50 v supply voltage data retention 1.5 5.5 v in input voltage 0 5.5 v v out output voltage 0 v cc v t a operating temperature -40 +85 c t r , t f input rise and fall times v cc at 1.8v, 2.5v 0.2v 0 20 ns/v v cc at 3.3v 0.3v 0 10 v cc at 5.0v 0.5v 0 5 ja thermal resistance us8 250 c/w micropak? 287 note: 3. unused inputs must be held high or low. they may not float. ? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7nz04 ? rev. 1.0.2 4 nc7nz04 ? tinylogic ? uhs inverter dc electrical characteristics symbol parameter v cc conditions t a =25c t a =-40 to 85c units min. typ. max. min. max. v ih high level input voltage 1.80 0.15 0.75v cc 0.75v cc v 2.30 to 5.50 0.70v cc 0.70v cc v il low level input voltage 1.80 0.15 0.25v cc 0.25v cc v 2.30 to 5.50 0.30v cc 0.30v cc v oh high level output voltage 1.65 v in =v il , i oh =-100a 1.55 1.65 1.55 v 2.30 2.20 2.30 2.20 3.00 2.90 3.00 2.90 4.50 4.40 4.50 4.40 1.65 i oh =-4ma 1.29 1.52 1.29 2.30 i oh =-8ma 1.90 2.15 1.90 3.00 i oh =-16ma 2.40 2.80 2.40 3.00 i oh =-24ma 2.30 2.68 2.30 4.50 i oh =-32ma 3.80 4.20 3.80 v ol low level output voltage 1.65 v in =v ih , i ol =100a 0.00 0.10 0.10 v 2.30 0.00 0.10 0.10 3.00 0.00 0.10 0.10 4.50 0.00 0.10 0.10 1.65 i ol =4ma 0.80 0.24 0.24 2.30 i ol =8ma 0.10 0.30 0.30 3.00 i ol =16ma 0.15 0.40 0.40 3.00 i ol =24ma 0.22 0.55 0.55 4.50 i ol =32ma 0.22 0.55 0.55 i in input leakage current 0 to 5.5 0 v in 5.5v 1 1 a i off power-off leakage current 0 v in or v out =5.5v 1 10 a i cc quiescent supply current 1.65 to 5.50 v in =5.5v, gnd 1 10 a ? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7nz04 ? rev. 1.0.2 5 nc7nz04 ? tinylogic ? uhs inverter ac electrical characteristics symbol parameter v cc conditions t a =25c t a =-40 to 85c units figure min. typ. max. min. max. t plh , t phl propagation delay 1.80 0.15 c l =15pf, r l =1m 1.8 4.4 9.5 2.0 10.0 ns figure 5 figure 6 2.50 0.20 0.8 2.9 5.1 0.8 5.6 3.30 0.30 0.5 2.1 3.4 0.5 3.8 5.00 0.50 0.5 1.8 2.8 0.5 3.1 3.30 0.30 c l =50pf, r l =500 1.2 2.9 4.5 1.2 5.0 5.00 0.50 0.8 2.4 3.6 0.8 4.0 c in input capacitance 0 2.5 pf c pd power dissipation capacitance (4) 3.30 9 pf figure 7 5.00 11 note: 4. c pd is defined as the value of the internal equivalent capacitance which is deriv ed from dynamic operating current consumption (i ccd ) at no output lading and operating at 50% duty cycle. c pd is related to i ccd dynamic operating current by the expression: i ccd =(c pd )(v cc )(f in )+(i cc static). dynamic switching characteristics symbol parameter conditions v cc t a =25c unit typ. v olp quiet output dynamic peak v ol c l =50pf, v ih =5.0v, v il =0v 5.0 0.8 v v olv quiet output dynamic valley v ol 5.0 -0.8 v note: 5. c l includes load and stray capacitance; inputs prr=1.0mhz, t w =500ns. figure 5. ac test circuit figure 6. ac waveforms note: 6. input=ac waveform; t r =t f =1.8ns; prr=10mhz; duty cycle =50%. figure 7. i ccd test circuit ? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7nz04 ? rev. 1.0.2 6 nc7nz04 ? tinylogic ? uhs inverter physical dimensions side view top view recommended land pattern a b 0.50 seating plane 0.10-0.18 0.13 ab c 0.50 detail a 0.4 typ all lead tips 0.2 c b a pin 1 ident all lead tips 0.1 c 8 1 4 5 (8x) 0.70 2.70 3.40 1.00 detail a 1.80 gage plane 0.12 c. dimensions are exclusive of burrs, d. dimensions and tolerances per mold flash, and tie bar extrusions. b. dimensions are in millimeters. a. conforms to jedec registration mo-187 ansi y14.5m, 1994. 2.10 1.90 2.40 2.20 0.15 3.20 3.00 1.55 0.90 max 0.10 0.00 0.80 0.60 0.17-0.27 (8x) 0.30 (8x) 0.20-0.35 0-8 c seating plane e. file drawing name : mkt-mab08arev4 figure 8. 8-lead us8, jedec mo-187, variation ca, 3.1mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/us8_pack_tnr.pdf package designator tape section cavity number cavity status cover type status k8x leader (start end) 125 (typical) empty sealed carrier 3000 filled sealed trailer (hub end) 75 (typical) empty sealed ? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7nz04 ? rev. 1.0.2 7 nc7nz04 ? tinylogic ? uhs inverter physical dimensions (0.09) (0.1) (0.2) 1.6 2x 0.05 0.00 1.6 2x c 0.05 c 4 3. drawing conforms to asme y.14m-1994 2. dimensions are in millimeters 1. package conforms to jedec mo-255 variation uaad bottom view 4. pin 1 flag, end of package offset mac08arev4 1 23 5 6 7 8 notes: 8x 0.25 0.35 3x 8x 1.0 4 0.5 8x 0.25 0.15 0.10 cab 0.05 c 0.10 c top view index area b recommended landpattern a 0.10 c 0.55 max 0.05 c detail a 0.35 0.25 (0.15) (0.20) 0.35 0.25 detail a pin #1 terminal scale: 2x 5. drawing file name: mkt-mac08arev4 figure 9. 8-lead, micropak?, 1.0mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf package designator tape section cavity number cavity status cover type status l8x leader (start end) 125 (typical) empty sealed carrier 3000 filled sealed trailer (hub end) 75 (typical) empty sealed ? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7nz04 ? rev. 1.0.2 8 nc7nz04 ? tinylogic ? uhs inverter |
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