march 1996 ndc651n n -channel logic level enhancement mode field effect transistor general description features __________ __________________________________________________________________________________ absolute maximum ratings t a = 25c unless otherwise note symbol parameter ndc651n units v dss drain-source voltage 30 v v gss gate-source voltage - continuous 20 v i d drain current - continuous (note 1a) 3.2 a - pulsed 15 p d maximum power dissipation (note 1a) 1.6 w (note 1b) 1 (note 1c) 0.8 t j ,t stg operating and storage temperature range -55 to 15 0 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 78 c/w r q jc thermal resistance, junction-to-case (note 1) 30 c/w ndc651n rev. d1 3 5 6 4 1 2 these n -channel logic level enhancement mode power field effect transistors are produced using fairchild's proprietary, high cell density, dmos technology. this very high density process is tailored to minimize on-state resistance. these devices are particularly suited for low voltage applications in notebook computers, portable phones, pcmica cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. 3.2 a, 30v. ?r ds(on ) = 0.09 w @ v gs = 4.5v r ds(on ) = 0.06 w @ v gs = 10v . proprietary supersot tm -6 package design using copper lead frame for superior thermal and electrical capabilities. high density cell design for extremely low r ds(on) . exceptional on-resistance and maximum dc current capability. ? 1997 fairchild semiconductor corporation
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 30 v i dss zero gate voltage drain current v ds = 24 v , v gs = 0 v 1 a t j = 55 o c 10 a i gssf gate - body leakage, forward v gs = 20 v, v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = -20 v, v ds = 0 v -100 na on characteristics (note 2) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a 1 1.7 3 v t j = 125 o c 0.7 1.3 2.2 r ds(on) static drain-source on-resistance v gs = 4.5 v, i d = 3.2 a 0.068 0.09 w t j = 125 o c 0.095 0.18 v gs = 10 v, i d = 4 a 0.042 0.06 i d (on) on-state drain current v gs = 4.5 v, v ds = 5 v 10 a g fs forward transconductance v ds = 10 v, i d = 3.2 a 6 s dynamic characteristics c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1.0 mhz 290 pf c oss output capacitance 180 pf c rss reverse transfer capacitance 60 pf switching ch aracteristics (note 2 ) t d(on ) turn - on delay time v dd = 10 v, i d = 1 a, v gen = 4.5 v, r gen = 6 w 9 20 ns t r turn - on rise time 19 30 ns t d(off) turn - off delay time 15 30 ns t f turn - off fall time 7 20 ns q g total gate charge v ds = 15 v, i d = 3.2 a, v gs = 10 v 10 20 nc q gs gate-source charge 1.2 nc q gd gate-drain charge 2.6 nc ndc651n rev. d1
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units drain-source diode characteristics i s continuous source diode current 1.3 a v sd drain-source diode forward voltage v gs = 0 v, i s = 1.3 a (note 2 ) 0.8 1.2 v notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. p d ( t ) = t j - t a r q j a ( t ) = t j - t a r q j c + r q c a ( t ) = i d 2 ( t ) r d s ( o n ) t j typical r q ja using the board layouts shown below on 4.5"x5" fr-4 pcb in a still air environment : a. 78 o c/w when mounted on a 1 in 2 pad of 2oz cpper. b. 125 o c/w when mounted on a 0.01 in 2 pad of 2oz cpper. c. 156 o c/w when mounted on a 0.003 in 2 pad of 2oz cpper. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. ndc651n rev. d1 1a 1b 1c
ndc651n rev. d1 0 0.5 1 1.5 2 2.5 3 0 3 6 9 12 15 v , drain-source voltage (v) i , drain-source current (a) 6.0 5.0 4.5 4.0 3.5 v =10v gs ds 3.0 d 0 3 6 9 12 15 0.5 1 1.5 2 2.5 i , drain current (a) drain-source on-resistance d v = 3v gs r , normalized ds(on) 6.0 3.5 10 4.5 5.0 4.0 figure 1. on-region characteristics figure 2. on-resistance variation with drain current and gate voltage typical electrical characteristics -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j v = 4.5v gs i = 3.2a d r , normalized ds(on) 0 3 6 9 12 15 0.5 1 1.5 2 2.5 i , drain current (a) drain-source on-resistance t = 125c j 25c d v = 4.5v gs -55c r , normalized ds(on) figure 3. on-resistance variation with temperature figure 4. on-resistance variation with drain current and temperature 1 2 3 4 5 0 3 6 9 12 15 v , gate to source voltage (v) i , drain current (a) 25c 125c v = 10v ds gs d t = -55c j -50 -25 0 25 50 75 100 125 150 0.6 0.7 0.8 0.9 1 1.1 1.2 t , junction temperature (c) gate-source threshold voltage j i = 250a d v = v ds gs v , normalized th figure 5. transfer characteristics figure 6. gate threshold variation with temperature
ndc651n rev. d1 -50 -25 0 25 50 75 100 125 150 0.88 0.92 0.96 1 1.04 1.08 1.12 1.16 t , junction temperature (c) drain-source breakdown voltage i = 250a d bv , normalized dss j 0.2 0.4 0.6 0.8 1 1.2 0.001 0.01 0.1 0.5 1 5 10 v , body diode forward voltage (v) i , reverse drain current (a) t = 125c j 25c -55c v = 0v gs sd s figure 7. breakdown voltage variation with temperature figure 8. body diode forward voltage variation with source current and temperature typical electrical characteristics (continued) 0 2 4 6 8 10 0 2 4 6 8 10 q , gate charge (nc) v , gate-source voltage (v) g gs i = 3.2a d 15v 10v v = 5v ds 0.1 0.2 0.5 1 2 5 10 30 30 50 100 200 500 800 1000 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0v gs c oss c rss g d s v dd r l v v in out v gs dut r gen 10% 50% 90% 10% 90% 90% 50% v in v out on off d(off) f r d(on) t t t t t t inverted 10% pulse width figure 9. capacitance characteristics figure 10. gate charge characteristics figure 11. switching test circuit figure 12. switching waveforms
ndc651n rev. d1 0 2 4 6 8 10 0 2 4 6 8 10 12 i , drain current (a) g , transconductance (siemens) t = -55c j 25c d fs v = 10v ds 125c figure 13. transconductance variation with drain current and temperature figure 16. maximum safe operating area typical electrical and thermal characteristics (continued) 0 0.2 0.4 0.6 0.8 1 2 2.5 3 3.5 2oz copper mounting pad area (in ) i , steady-state drain current (a) 2 1c 1b 1a 4.5"x5" fr-4 board t = 25 c still air v = 4.5v a o gs d 0 0.2 0.4 0.6 0.8 1 0 0.5 1 1.5 2 2oz copper mounting pad area (in ) steady-state power dissipation (w) 2 1c 1b 1a 4.5"x5" fr-4 board t = 25 c still air a o 0.1 0.2 0.5 1 2 5 10 30 50 0.01 0.03 0.1 0.3 1 3 10 30 v , drain-source voltage (v) i , drain current (a) ds d rds(on) limit v = 4.5v single pulse r = see note 1c t = 25c gs a q ja 1s 100us dc 10ms 1ms 100ms figure 14. sot-6 maximum steady-state power dissipation versus copper mounting pad area. figure 15 . maximum steady-state drain current versus copper mounting pad area. 0.00001 0.0001 0.001 0.01 0.1 1 10 100 300 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t / t 1 2 r (t) = r(t) * r r = see note 1c q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2 r(t), normalized effective figure 17 . transient thermal response curve . note: thermal characterization performed using the conditions described in note 1c. transient thermal response will change depending on the circuit board design.
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