cmos-ccd 1h delay line for pal description the cxl5508m/p are cmos-ccd delay line ics that provide 1h delay time for pal signals, including the external low-pass filter. features single 5v power supply low power consumption 60mw (typ.) built-in peripheral circuits functions 565-bit ccd register clock driver auto-bias circuit input clamp circuit sample-and-hold circuit structure cmos-ccd absolute maximum ratings (ta = 25?) supply voltage v dd 6v operating temperature topr ?0 to +60 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d cxl5508m 350 mw cxl5508p 480 mw recommended operating condition (ta = 25?) supply voltage v dd 5 5% v recommended clock conditions (ta = 25?) input clock amplitude v clk 0.3 to 1.0 vp-p (0.5vp-p typ.) clock frequency f clk 8.867238 mhz input clock waveform sine wave input signal amplitude v sig 500mvp-p (typ.), 527mvp-p (max.) (at internal clamp condition) ?1 e91101a7x-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxl5508m/p blook diagram and pin configuration (top view) (s/h 1bit) clk 1 2 3 4 5 7 8 ccd (565bit) 6 vga v dd ab v ss out vgb in output circuit auto-bias circuit timing circuit bias circuit clock driver bias circuit (a) bias circuit (b) clamp circuit cxl5508m 8 pin sop (plastic) cxl5508p 8 pin dip (plastic)
electrical characteristics (ta = 25 c, v dd = 5v, f clk = 8.867238mhz, v clk = 500mvp-p, sine wave) see "electrical characteristics test circuit" ? 2 cxl5508m/p description of i/o signals input signals are low level clamped and output signals are inverted in relation to the input signals. also, the clamp condition of input signals are controlled by vgb (pin 2) conditions. 0v ........ internal clamp condition 5v ........ non internal clamp condition center biased to approx. 2.1v by means of the ic internal resistance (approx. 10k ). in this mode, the input signal is limited to apl 50% and the maximum input signal amplitude is 200mvp-p. c l a m p l e v e l i n p u t w a v e f o r m o u t p u t w a v e f o r m pin description pin no. symbol description impedance 1 2 3 4 5 6 7 8 in vgb out v ss clk vga v dd ab signal input gate control b signal output gnd clock input gate control a power supply (5v) auto-bias dc output > 10k at no clamp 40 to 500 > 100k 600 to 200k i i o i o o i/o a a b c b b b 7 ? ?.8 54 37 18 56 12 0 ?.8 56 40 20 60 17 2 0 350 43 22 64 ma db db mvp-p db % 1 2 3 4 5 6 unit note max. min. typ. item symbol test condition sw condition 1 a a a b b a a a 2 b b a a a b b b a a b b b a a a b b a c a a a 3 4 5 200khz, 500mvp-p, sine wave 200khz ? ? 2mhz, 150mvp-p, sine wave no signal input no signal input 5-staircase wave (for luminance signals only) i dd gl fg cp sn lis lil lic supply current low frequency gain frequency response s/h pulse coupling s/n ratio linearity 2.1 2.1 bias condition v1 (v)
? 3 cxl5508m/p notes (1) this is the ic supply current value during clock and signal input. (2) gl is the output gain of out pin when a 500mvp-p, 200khz sine wave is fed to in pin. gl = 20 log [db] (3) indicates the dissipation at 2mhz in relation to 200khz. from the output voltage at out pin when a 150mvp-p, 200khz sine wave is fed to in pin, and from the output voltage at out pin when a 150mvp-p, 2mhz sine wave is fed to same, cal culation is made according to the following formula. input bias is tested at 2.1v. fg = 20 log [db] (4) the internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. input bias is tested at 2.1v. out pin output voltage [mvp-p] 500 [mvp-p] out pin otuput voltage (2mhz) [mvp-p] out pin output voltage (200khz) [mvp-p] t e s t v a l u e ( m v p - p ) (5) input no signal noise components are tested with the video noise meter at bpf 10khz to 3mhz. this is calculated from the output gain (gl), at the input of 200khz, 500mvp-p and according to the following formula. s/n = ?0 iog [db] (6) respective outputs are tested at the input of the 5-staircase waves seen in the figure below (iuminance signals only) and calculated according to the formula below. (however, output signals become inverted with regards to input.) noise (mvrms) 0.5 10 gl/20 4 0 i r e 1 0 0 i r e 5 0 0 m v v s v p v c v a l i s = 1 0 0 [ % ] v s v a l i l = 1 0 0 [ % ] v p v a l i c = 1 0 0 [ % ] v c v a
? 4 cxl5508m/p 0 . 3 t o 1 . 0 v p - p ( 0 . 5 v p - p t y p . ) 2 f s c ( 8 . 8 6 7 2 3 8 m h z ) s i n e w a v e clock
? 5 cxl5508m/p electrical characteristics test circuit 1 a b v d d v g a c l k 1 0 0 0 p 1 0 0 0 p 3 . 3 0 . 1 c l k 2 f s c ( 8 . 8 6 7 2 3 8 m h z ) 0 . 5 v p - p s i n e w a v e i n v g b o u t v s s a b s w 4 a b 1 m 1 k 5 v 1 s w 2 b s w 1 c a b d a s w 5 2 . 1 k 9 v 2 3 4 5 6 7 1 b c n o t e ) 3 b p f n o t e ) b p f f r e q u e n c y r e s p o n s e 3 m 8 . 9 m f r e q u e n c y [ h z ] 1 0 k 8 s w 3 v 1 a 1 0 0 0 p 0 3 5 0 [ d b ] o s c i l l o s c o p e s p e c t r u m a n a l y z e r n o i s e m e t e r 2 0 0 k h z 5 0 0 m v p - p s i n e w a v e 2 0 0 k h z 1 5 0 m v p - p s i n e w a v e 2 m h z 1 5 0 m v p - p s i n e w a v e 5 - s t a i r c a s e w a v e
? 6 cxl5508m/p application circuit 1 0 0 0 p 3 . 3 0 . 1 1 2 f s c 0 . 5 v p - p s i n e w a v e 1 m 1 8 1 0 1 2 5 v 2 3 4 6 7 1 i n p u t l p f 2 . 2 k 2 . 2 k 5 v 2 . 2 k o u t p u t p n p : 2 s a 1 1 7 5 d e l a y t i m e 1 4 0 n s 5 1 0 0 0 p 2 . 2 k n p n : 2 s c 2 7 8 5 o u t p u t application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 7 cxl5508m/p example of representative characteristics 5 4 . 7 5 5 1 0 1 5 2 0 0 5 . 2 5 5 4 . 7 5 1 0 . 5 0 0 . 5 1 . 5 5 . 2 5 5 4 . 7 5 1 0 . 5 0 0 . 5 1 . 5 5 . 2 5 5 4 . 7 5 3 6 4 0 3 2 5 . 2 5 4 4 5 4 . 7 5 5 4 6 2 6 6 7 0 5 0 5 . 2 5 5 8 5 4 . 7 5 1 5 2 0 2 5 3 0 1 0 5 . 2 5 s u p p l y v o l t a g e [ v ] s u p p l y c u r r e n t v s . s u p p l y v o l t a g e s u p p l y c u r r e n t [ m a ] s u p p l y v o l t a g e [ v ] l o w f r e q u e n c y g a i n v s . s u p p l y v o l t a g e l o w f r e q u e n c y g a i n [ d b ] s u p p l y v o l t a g e [ v ] f r e q u e n c y r e s p o n s e v s . s u p p l y v o l t a g e f r e q u e n c y r e s p o n s e [ d b ] s u p p l y v o l t a g e [ v ] l i n e a r i t y ( l i s ) v s . s u p p l y v o l t a g e l i n e a r i t y ( l i s ) [ % ] s u p p l y v o l t a g e [ v ] l i n e a r i t y ( l i c ) v s . s u p p l y v o l t a g e l i n e a r i t y ( l i c ) [ % ] s u p p l y v o l t a g e [ v ] l i n e a r i t y ( l i l ) v s . s u p p l y v o l t a g e l i n e a r i t y ( l i l ) [ % ]
? 8 cxl5508m/p 5 4 6 2 6 6 7 0 5 0 5 8 2 0 2 0 7 0 1 0 0 1 0 3 0 4 0 5 0 6 0 1 5 2 0 2 5 3 0 1 0 2 0 2 0 7 0 1 0 0 1 0 3 0 4 0 5 0 6 0 1 0 . 5 0 0 . 5 1 . 5 2 0 2 0 7 0 1 0 0 1 0 3 0 4 0 5 0 6 0 3 6 4 0 3 2 4 4 2 0 2 0 7 0 1 0 0 1 0 3 0 4 0 5 0 6 0 1 0 . 5 0 0 . 5 1 . 5 2 0 2 0 7 0 1 0 0 1 0 3 0 4 0 5 0 6 0 2 0 2 0 5 1 0 1 5 2 0 0 7 0 1 0 0 1 0 3 0 4 0 5 0 6 0 a m b i e n t t e m p e r a t u r e [ c ] s u p p l y c u r r e n t v s . a m b i e n t t e m p e r a t u r e s u p p l y c u r r e n t [ m a ] a m b i e n t t e m p e r a t u r e [ c ] l o w f r e q u e n c y g a i n v s . a m b i e n t t e m p e r a t u r e l o w f r e q u e n c y g a i n [ d b ] a m b i e n t t e m p e r a t u r e [ c ] f r e q u e n c y r e s p o n s e v s . a m b i e n t t e m p e r a t u r e f r e q u e n c y r e s p o n s e [ d b ] a m b i e n t t e m p e r a t u r e [ c ] l i n e a r i t y ( l i s ) v s . a m b i e n t t e m p e r a t u r e l i n e a r i t y ( l i s ) [ % ] a m b i e n t t e m p e r a t u r e [ c ] l i n e a r i t y ( l i c ) v s . a m b i e n t t e m p e r a t u r e l i n e a r i t y ( l i c ) [ % ] a m b i e n t t e m p e r a t u r e [ c ] l i n e a r i t y ( l i l ) v s . a m b i e n t t e m p e r a t u r e l i n e a r i t y ( l i l ) [ % ]
? 9 cxl5508m/p package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y 8 p i n s o p ( p l a s t i c ) 6 . 1 + 0 . 4 0 . 1 5 . 3 + 0 . 3 0 . 1 1 . 8 5 + 0 . 4 0 . 1 5 0 . 1 + 0 . 2 0 . 0 5 0 . 2 + 0 . 1 0 . 0 5 0 . 4 5 0 . 1 1 . 2 7 4 1 7 . 9 0 . 4 6 . 9 0 . 5 0 . 2 0 . 2 4 m 0 . 1 g s o p - 8 p - l 0 1 s o p 0 0 8 - p - 0 3 0 0 8 5 0 . 1 5 s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g c o p p e r a l l o y 8 p i n d i p ( p l a s t i c ) 9 . 4 0 . 1 + 0 . 4 2 . 5 4 1 4 5 8 1 . 2 0 . 1 5 0 . 5 0 . 1 3 . 0 m i n 0 . 5 m i n 3 . 7 0 . 1 + 0 . 4 7 . 6 2 6 . 4 0 . 1 + 0 . 3 0 . 2 5 0 . 0 5 + 0 . 1 0 t o 1 5 0 . 5 g d i p - 8 p - 0 1 d i p 0 0 8 - p - 0 3 0 0 cxl5508m cxl5508p
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