View CXP845P60_5823114.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXP845P60 cmos 8-bit single chip microcomputer description the CXP845P60 is a cmos 8-bit microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time-base timer, capture timer/counter, pwm output and the like besides the basic configurations of 8-bit cpu, prom, ram and i/o port. the CXP845P60 also provides a sleep/stop functions that enable to execute the power-on reset function or lower the power consumption. the CXP845P60 is the prom-incorporated version of the cxp84548 with built-in mask rom. this provides the additional feature of being able to write directly into the program. thus, it is most suitable for evaluation use during system development and for small-quantity production. features a wide instruction set (213 instructions) which covers various types of data ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 143ns at 28mhz operation (4.5 to 5.5v) 200ns at 20khz operation (3.0 to 5.5v) incorporated prom capacity 60k bytes incorporated ram capacity 1472 bytes peripheral functions ?a/d converter 8 bits, 8 channels, successive approximation method (conversion time of 1.93s at 28mhz, 2.7s at 20mhz) ?serial interface incorporated 8-bit, 8-stage fifo (auto transfer for 1 to 8 bytes, latch output function, msb/lsb first selectable), 1 channel 8-bit clock sync type, 1 channel ?timer 8-bit timer 8-bit timer/counter 19-bit time-base timer 16-bit capture time/counter ?pwm output 8 bits, 2 channels interruption 14 factors, 14 vectors, multi-interruption possible standby mode sleep/stop package 80-pin plastic qfp/lqfp 80-pin plastic lflga structure silicon gate cmos ic ?1 e96825c1y-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 80 pin qfp (plastic) 80 pin lqfp (plastic) 80 pin lflga (plastic)
?2 CXP845P60 8 an0 to an7 pwm0 pwm1 cs0 si0 so0 sck0 si1 so1 sck1 to cint ec1 ec0 a/d converter avss av ref 8-bit pwm generator 0 serial interface unit 0 fifo serial interface unit 1 8-bit timer/counter 0 8-bit timer 1 16-bit capture timer/counter 2 interrupt controller int0 int1 int2 int3 nmi spc700 cpu core prom 60k bytes clock generator/ system control ram 1472 bytes prescaler/ time-base timer extal xtal v dd vss port a 8 8 8 4 4 8 pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe3 pe4 to pe7 pf0 to pf7 pg0 to pg7 pi0 to pi7 rst 8 8 8 port b port c port d port e port f port g port i ph0 to ph7 8 port h 2 2 lat0 8-bit pwm generator 1 block diagram
3 CXP845P60 pin assignment (top view) 80-pin qfp package 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 1 pe1/ec1 pi4 pi3/int3 pi2/int2 pi1/int1 pi0/int0 pe5/to/pwm1 pe4/pwm0 pe3/nmi pe2/cint pe0/ec0 pb7/so1 pb6/si1 pb5/sck1 pb4/so0 pb3/si0 pb2/sck0 pb1/cs0 pb0/lat0 pa7/an7 pa6/an6 pa5/an5 pa4/an4 pa3/an3 ph3 ph4 ph5 ph6 ph7 rst extal xtal v ss pe6 pe7 av ss av ref pa0/an0 pa1/an1 pa2/an2 pf3 pf4 pf5 pf6 pf7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ph0 ph1 ph2 pf2 pf1 pf0 pg7 pg6 pg5 pg4 vpp v dd pg3 pg2 pg1 pg0 pi7 pi6 pi5 note) vpp (pin 73) should be left open. (internally connected to v dd .) however, this pin is used for the flash eeprom-incorporated version (cxp845f60).
4 CXP845P60 pin assignment (top view) 80-pin lqfp package pi2/int2 pi1/int1 pi0/int0 pe5/to/pwm1 pe4/pwm0 pe3/nmi pe2/cint pe1/ec1 pe0/ec0 pb7/so1 pb6/si1 pb5/sck1 pb4/so0 pb3/si0 pb2/sck0 pb1/cs0 pb0/lat0 pa7/an7 pa6/an6 pa5/an5 ph1 ph2 ph3 ph4 ph5 ph6 ph7 rst extal xtal v ss pe6 pe7 av ss av ref pa0/an0 pa1/an1 pa2/an2 pa3/an3 pa4/an4 pf4 pf3 pf2 pf1 pf0 pg7 pg6 pg5 pg4 vpp v dd pg3 pg2 pg1 pg0 pi7 pi6 pi5 pi4 pi3/int3 pf5 pf6 pf7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ph0 18 19 20 5 16 17 6 4 3 2 1 11 12 10 9 8 7 13 14 15 27 35 34 31 32 24 23 22 21 40 39 38 33 37 36 30 29 25 26 28 52 53 54 55 56 57 60 59 58 51 50 49 48 47 46 45 44 43 42 41 70 71 80 79 78 77 76 75 74 73 72 69 68 67 66 65 64 63 62 61 note) vpp (pin 71) should be left open. (internally connected to v dd .) however, this pin is used for the flash eeprom-incorporated version (cxp845f60).
5 CXP845P60 pin assignment (top view) 80-pin lflga package 80 78 75 72 69 67 65 62 2 1 79 76 73 70 66 63 61 60 5 3 4 77 74 71 68 64 59 58 7 6 8 57 56 55 9 10 11 54 53 52 12 13 14 51 50 49 15 16 17 48 46 47 18 19 24 28 31 34 37 44 43 45 20 21 23 26 30 33 36 39 41 42 22 25 27 29 32 35 38 40 pf4 pf2 pg7 pg4 pg3 pg1 pi7 pi4 pf5 pf6 pf3 pf0 pg5 v dd pg0 pi5 pi3 pi2 pf7 pd1 pd0 pf1 pg6 vpp pg2 pi6 pi1 pi0 pd2 pd3 pd4 pe5 pe4 pe3 pd6 pd5 pd7 pe2 pe1 pe0 pc1 pc0 pc2 pb7 pb6 pb5 pc4 pc3 pc5 pb4 pb2 pb3 pc7 pc6 ph4 rst v ss av ss pa1 pb0 pa7 pb1 ph1 ph0 ph3 ph6 xtal pe7 pa0 pa3 pa5 pa6 ph2 ph5 ph7 extal pe6 avref pa2 pa4 note) vpp (pin 71) should be left open. (internally connected to v dd .) however, this pin is used for the flash eeprom-incorporated version (cxp845f60).
6 CXP845P60 pin description symbol i/o description i/o/analog input pa0/an0 to pa7/an7 (port a) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of the pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) analog inputs to a/d converter. (8 pins) i/o pc0 to pc7 (port c) 8-bit i/o port. i/o can be set in a unit of single bits. can drive 12ma sync current. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) i/o pd0 to pd7 (port d) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull- up resistor can be set through the software in a unit of 4 bits. (8 pins) i/o pf0 to pf7 (port f) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) input/input input/input input/input input/input output/output output/output/ output output output pe0/ec0 pe1/ec1 pe2/cint pe3/nmi pe4/pwm0 pe5/to/ pwm1 pe6 pe7 (port e) 8-bit port. lower 4 bits are for inputs; upper 4 bits are for outputs. (8 pins) external event inputs for timer/counter. (2 pins) capture trigger input. non-maskable interruption request input. 8-bit pwm0 output. rectangular wave output for 16-bit timer/ counter and 8-bit pwm1 output. i/o/output i/o/input i/o/i/o i/o/input i/o/output i/o/i/o i/o/input i/o/output pb0/lat0 pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 (port b) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) latch output for serial interface (ch0). chip select input for serial interface (ch0). serial clock i/o (ch0). serial data input (ch0). serial data output (ch0). serial clock i/o (ch1). serial data input (ch1). serial data output (ch1).
7 CXP845P60 symbol i/o description i/o pg0 to pg7 (port g) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull- up resistor can be set through the software in a unit of 4 bits. (8 pins) i/o ph0 to ph7 (port h) 8-bit i/o port. i/o and standby release input function can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) i/o/input pi0/int0 to pi3/int3 i/o pi4 to pi7 input connects a crystal for system clock oscillation. when the clock is supplied externally, input to extal; opposite phase clock should be input to xtal. extal output xtal i/o system reset for active at low level. this pin is i/o pin, and outputs low level at the power on with the power-on reset function executed. rst positive power supply for incorporated prom writing. leave this pin open (internally connected to v dd ). this is used for the flash eeprom-incorporated version (cxp845f60). vpp input reference voltage input for a/d converter. av ref a/d converter gnd. avss positive power supply. v dd gnd vss (port i) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) external interruption request inputs. (4 pins)
8 CXP845P60 data bus rd (port b) aaa aaa aa port b direction ip aa aa aaa aaa port b data aaa aaa pull-up resistor "0" when reset "0" when reset lat0 latch output enable ? pull-up transistor approx. 100k ? (v dd = 4.5 to 5.5v) approx. 300k ? (v dd = 3.0 to 3.6v) ? data bus rd (port b) aaaa aaaa a a port b direction ip aa aa aaaa aaaa port b data aaaa pull-up resistor "0" when reset "0" when reset schmitt input cs0 si0 si1 ? pull-up transistor approx. 100k ? (v dd = 4.5 to 5.5v) approx. 300k ? (v dd = 3.0 to 3.6v) ? port b 8 pins hi-z hi-z when reset pa0/an0 to pa7/an7 pb0/lat0 port b 1 pin 3 pins hi-z pb1/cs0 pb3/si0 pb6/si1 data bus rd (port a) aaa aaa aa aa port a direction ip aa aaa port a data aaa aaa pull-up resistor aaa aaa port a function selection input protection circuit "0" when reset "0" when direction "0" when reset input multiplexer a/d converter ? pull-up transistor approx. 100k ? (v dd = 4.5 to 5.5v) approx. 300k ? (v dd = 3.0 to 3.6v) ? input/output circuit formats for pins port a pin circuit format
9 CXP845P60 data bus rd (port b) aa ip aa aa aaa aaa port b function selection "0" when reset aaa aaa port b data aaa aaa port b direction "0" when reset aaa aaa pull-up resistor serial data output enable so ? pull-up transistor approx. 100k ? (v dd = 4.5 to 5.5v) approx. 300k ? (v dd = 3.0 to 3.6v) ? data bus rd (port c) aaaa aaaa a a port c direction ip aa aa aaaa aaaa port c data aaaa pull-up resistor "0" when reset "0" when reset ? 2 * 1 ? 1 large current drive 12ma (v dd = 4.5 to 5.5v) 5ma (v dd = 3.0 to 3.6v) ? 2 pull-up transistor approx. 100kw (v dd = 4.5 to 5.5v) approx. 300kw (v dd = 3.0 to 3.6v) port b 2 pins hi-z hi-z pb2/sck0 pb5/sck1 pb4/so0 pb7/so1 port c 2 pins 8 pins hi-z pc0 to pc7 data bus rd (port b) aa ip aa aa aaaa port b function selection "0" when reset schmitt input sck0, sck1 in aaaa aaaa port b data aaaa aaaa port b direction "0" when reset aaaa pull-up resistor "0" when reset sck out serial clock output enable ? pull-up transistor approx. 100k ? (v dd = 4.5 to 5.5v) approx. 300k ? (v dd = 3.0 to 3.6v) ? port b when reset pin circuit format
10 CXP845P60 aaaaa a aaa a aaaaa aa aa aaaa aaaa port e data "1" when reset port e function selection (lower) "00" when reset to port e function selection (upper) pwm1 aaaa a aa a a aa a aaaa mpx 00 01 1x internal reset signal to output enable ? pull-up transistor approx. 150k ? (v dd = 4.5 to 5.5v) approx. 400k ? (v dd = 3.0 to 3.6v) ? high level with resistor of pull-up transistor on for reset 4 pins 1 pin pe0/ec0 pe1/ec1 pe2/cint pe3/nmi pe4/pwm0 pe5/to/ pwm1 1 pin low level pe6, pe7 2 pins data bus rd (port e) aa aa aaaa aaaa port e data "0" when reset aa aa ip aa aa schmitt input rd (port e) data bus ec0, ec1 cint, nmi data bus aa aa aaaa aaaa port e function selection pwm0 aaaa aaaa port e data "0" when reset "1" when reset rd (port e) port e port e port e port e hi-z high level () when reset pin circuit format
11 CXP845P60 28 pins pd0 to pd7 pf0 to pf7 pg0 to pg7 pi4 to pi7 aa aa ip a a aaaaaa aaaaaa ports d, f, g, i data "0" when reset aaaaaa aaaaaa ports d, f, g, i direction aaaa aaaa pull-up resistor "0" when reset rd data bus ? pull-up transistor approx. 100k ? (v dd = 4.5 to 5.5v) approx. 300k ? (v dd = 3.0 to 3.6v) ? port i 8 pins hi-z ph0 to ph7 data bus rd (port h) aaaa aaaa a a port h direction ip aa aa aaaa aaaa port h data aaaa pull-up resistor "0" when reset "0" when reset standby release a a edge detection ? pull-up transistor approx. 100k ? (v dd = 4.5 to 5.5v) approx. 300k ? (v dd = 3.0 to 3.6v) ? port h 4 pins hi-z pi0/int0 to pi3/int3 port d port f port g port i hi-z data bus aa aa ip a a aaaa aaaa port i data "0" when reset ? pull-up transistor approx. 100k ? (v dd = 4.5 to 5.5v) approx. 300k ? (v dd = 3.0 to 3.6v) ? aaaa aaaa port i direction aaaa aaaa pull-up resistor "0" when reset int0 int1 int2 int3 rd schmitt input when reset pin circuit format
12 CXP845P60 2 pins oscillation extal xtal 1 pin rst low level aa aa a a ip aa aa extal xtal diagram shows the circuit composition during oscillation. feedback resistor is removed during stop mode and xtal becomes high level. aa aa ip aa schmitt input pull-up resistor aa ip from power-on reset circuit when reset pin circuit format
13 CXP845P60 ? 1 v in and v out must not exceed v dd + 0.3v. ? 2 the large current drive transistor is the n-ch transistor of port c (pc). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. input voltage output voltage high level output current high level total output current low level total output current operating temperature storage temperature allowable power dissipation v dd av ss v in v out i oh i oh i ol i olc i ol topr tstg p d supply voltage low level output current 0.3 to +7.0 0.3 to +0.3 0.3 to +7.0 ? 1 0.3 to +7.0 ? 1 5 50 15 20 100 20 to +75 55 to +150 600 380 500 v v v v ma ma ma ma ma c c mw mw mw output (value per pin) total for all output pins all pins excluding large current outputs (value per pin) large current outputs (value per pin ? 2 ) total for all output pins qfp-80p-l01 lqfp-80p-l01 lflga-80p-02 item symbol ratings unit remarks absolute maximum ratings (vss = 0v reference) high level input voltage low level input voltage operating temperature supply voltage ? 1 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.1v dd +75 v v v v v v c v item symbol min. max. unit remarks 4.5 (3.0) 3.5 (2.7) 2.0 0.7v dd 0.8v dd 0.9v dd 0 0 0.3 20 v ih v ihs v ihex v il v ils v ilex topr guaranteed operation range for 1/2 and 1/4 frequency dividing modes guaranteed operation range for 1/16 frequency dividing and sleep modes guaranteed data hold range during stop mode ? 2 hysteresis input ? 3 extal ? 4 ? 2 hysteresis input ? 3 extal ? 4 v dd ? 1 specifies values in parenthesis for 1 to 20mhz system clock operation. ? 2 normal input ports (pa, pb0, pb4, pb7, pc, pe0 to pe3, pd, pf to ph, pi4 to pi7) ? 3 rst, cint, cs0, sck0, sck1, ec0, ec1, si0, si1, nmi, int0, int1, int2, int3 ? 4 specifies only during external clock input. recommended operating conditions (vss = 0v reference)
14 CXP845P60 electrical characteristics dc characteristics (v dd = 4.5 to 5.5v) (ta = 20 to +75 c, vss = 0v reference) v dd = 4.5v, i oh = 0.5ma v dd = 4.5v, i oh = 1.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 4.0v high level output voltage 4.0 3.5 0.1 0.1 1.5 2.78 v v v v v a a a a a a pc pa to pd, pe4 to pe7, pf to pi, rst (only v ol ) extal rst pa to pd ? 1 pf to pi ? 1 item symbol pins conditions min. clock 1mhz 0v for all pins excluding measured pins v dd i dd1 i iz i dd2 i dds1 i dds2 i dds3 c in v oh v ol i ihe i ile i ilr i il low level output voltage input current typ. 0.4 0.6 1.5 25 25 400 50 10 max. unit ? 1 for pa to pd and pf to pi pins, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. ? 2 when all pins are open. v dd = 5.5v, 28mhz crystal oscillation (c 1 = c 2 = 1pf) sleep mode supply current ? 2 input capacity v dd = 4.5v, v il = 4.0v v dd = 5.5v, v i = 0, 5.5v for 1/2 frequency dividing mode i/o leakage current pa to pd ? 1 pf to pi ? 1 pe0 to pe3 35 2.5 10 64 10 30 20 ma ma a pf v dd = 5.5v, 28mhz crystal oscillation (c 1 = c 2 = 1pf) stop mode v dd = 5.5v, termination of 28mhz crystal oscillation pa to pd, pe0 to pe3, pf to pi, extal, rst
15 CXP845P60 dc characteristics (v dd = 3.0 to 3.6v) (ta = 20 to +75 c, v ss = 0v reference) v dd = 3.0v, i oh = 0.15ma v dd = 3.0v, i oh = 0.5ma v dd = 3.0v, i ol = 1.2ma v dd = 3.0v, i ol = 1.6ma v dd = 3.0v, i ol = 5ma v dd = 3.6v, v ih = 3.6v v dd = 3.6v, v il = 0.3v v dd = 3.6v, v il = 0.3v high level output voltage 2.7 2.3 0.05 0.05 0.7 1.0 v v v v v a a a a a a pc pa to pd, pe4 to pe7, pf to pi, rst (only v ol ) extal rst pa to pd ? 1 pf to pi ? 1 v dd i dd1 i iz i dd2 i dds1 i dds2 i dds3 v oh v ol i ihe i ile i ilr i il low level output voltage input current 0.3 0.5 1.0 15 15 200 30 5 v dd = 3.6v, 20mhz crystal oscillation (c 1 = c 2 = 10pf) sleep mode supply current ? 2 v dd = 3.0v, v il = 2.7v v dd = 3.6v, v i = 0, 3.6v for 1/2 frequency dividing mode i/o leakage current pa to pd ? 1 pf to pi ? 1 pe0 to pe3 14.5 0.85 30 4.0 5 ma ma a v dd = 3.6v, 20mhz crystal oscillation (c 1 = c 2 = 10pf) stop mode v dd = 3.6v, termination of 20mhz crystal oscillation ? 1 for pa to pd and pf to pi pins, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. ? 2 when all pins are open. item symbol pins conditions min. typ. max. unit
16 CXP845P60 ? 1 t sys indicates the three values according to the contents of the clock control register (clc: 00feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") extal t xh t xl t cf t cr 0.4v v dd 0.4v 1/fc aaaaa a aaa a aaaaa aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal external clock extal xtal 74hc04 c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise time, fall time event count input clock pulse width event count input clock rise time, fall time f c t xl , t xh t cr , t cf t eh , t el t er , t ef xtal extal extal extal ec0 ec1 ec0 ec1 mhz ns ns ns ns item symbol pin conditions min. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 1 1 15.6 23 t sys + 50 ? 1 typ. max. 28 20 100 20 (ta = 20 to +75 c, v dd = 3.0 to 5.5v, vss = 0v reference) fig. 2. clock applied conditions fig. 1. clock timing t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr ec0 ec1 fig. 3. event count clock timing v dd = 4.5 to 5.5v v dd = 4.5 to 5.5v
17 CXP845P60 chip select transfer mode (sck0 = output mode) chip select transfer mode (sck0 = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates the three values according to the contents of the clock control register (clc: 00feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) the load condition for the sck0 output mode, so0 output delay time is 50pf + 1ttl. (2) serial transfer (ch0) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item cs0 sck0 delay time cs0 sck0 float delay time cs0 so0 delay time cs0 so0 float delay time cs0 high level width sck0 cycle time sck0 high, low level width si0 input setup time (for sck0 ) si0 input hold time (for sck0 ) sck0 so0 delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso t ladly t lapls sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 lat0 lat0 input mode output mode input mode output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode latch output mode (sck0 = output mode) latch output mode (sck0 = output mode) ns ns ns ns ns symbol pin min. 1.5 t sys + 100 1.5 t sys + 100 1.5 t sys + 100 1.5 t sys + 100 t sys + 150 2 t sys + 200 8000/fc t sys + 90 4000/fc 25 50 100 t sys + 100 50 t kcy t kcy 10 ns ns ns ns ns ns ns ns ns ns ns ns t sys + 100 50 t kcy + 50 t kcy + 50 max. unit condition sck0 lat0 output delay time lat0 data pulse width
18 CXP845P60 chip select transfer mode (sck0 = output mode) chip select transfer mode (sck0 = output mode) chip select transfer mode chip select transfer mode chip select transfer mode serial transfer (ch0) (ta = 20 to +75 c, v dd = 3.0 to 3.6v, vss = 0v reference) cs0 sck0 delay time cs0 sck0 float delay time cs0 so0 delay time cs0 so0 float delay time cs0 high level width sck0 cycle time sck0 high, low level width si0 input setup time (for sck0 ) si0 input hold time (for sck0 ) sck0 so0 delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso t ladly t lapls sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 lat0 lat0 input mode output mode input mode output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode latch output mode (sck0 = output mode) latch output mode (sck0 = output mode) ns ns ns ns ns 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 t sys + 200 2 t sys + 200 8000/fc t sys + 80 4000/fc 50 80 150 t sys + 120 70 t kcy t kcy 10 ns ns ns ns ns ns ns ns ns ns ns ns t sys + 200 80 t kcy + 100 t kcy + 100 sck0 lat0 output delay time lat0 data pulse width item symbol pin min. max. unit condition note 1) t sys indicates the three values according to the contents of the clock control register (clc: 00feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) the load condition for the sck0 output mode, so0 output delay time is 50pf.
19 CXP845P60 sck0 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 t sik input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0 cs0 t ksi t lapls lat0 t ladly 0.8v dd 0.8v dd 0.8v dd fig. 4. serial transfer ch0 timing
20 CXP845P60 (3) serial transfer (ch1) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v reference) item sck1 cycle time t kcy sck1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 500 8000/fc 200 4000/fc 25 50 100 100 50 100 50 ns ns ns ns ns ns ns ns ns ns sck1 si1 si1 so1 t kh t kl t sik t ksi t kso sck1 high, low level width si1 input setup time (for sck1 ) si1 input hold time (for sck1 ) sck1 so1 delay time symbol pin condition min. max. unit note) the load condition for the sck1 output mode, so1 output delay time is 50pf + 1ttl. (ta = 20 to +75 c, v dd = 3.0 to 3.6v, v ss = 0v reference) item sck1 cycle time t kcy sck1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 700 8000/fc 300 4000/fc 50 70 150 150 70 150 80 ns ns ns ns ns ns ns ns ns ns sck1 si1 si1 so1 t kh t kl t sik t ksi t kso sck1 high, low level width si1 input setup time (for sck1 ) si1 input hold time (for sck1 ) sck1 so1 delay time symbol pin condition min. max. unit note) the load condition for the sck1 output mode, so1 output delay time is 50pf.
21 CXP845P60 0.2v dd 0.8v dd t kl t kh so1 t kcy t sik t ksi 0.2v dd 0.8v dd t kso 0.2v dd 0.8v dd output data input data si1 sck1 fig. 5. serial transfer ch1 timing
22 CXP845P60 conversion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian v zt ? 1 v ft ? 2 i ref av ref an0 to an7 ta = 25 c v dd = av ref = 5.0v v ss = av ss = 0v operation mode sleep mode stop mode linearity error zero transition voltage full-scale transition voltage resolution av ref current av ref i refs s s v v v dd av ref 1.0 ma 10 a 0.6 27/f adc ? 3 6/f adc ? 3 v dd 0.5 0 item symbol pin condition min. typ. max. unit bits (4) a/d converter characteristics (ta = 20 to +75 c, v dd = 4.5 to 5.5v, av ref = 4.0 to v dd , vss = av ss = 0v reference) 8 lsb 70 mv 5030 10 4970 10 4910 mv analog input linearity error v ft v zt 00h 01h feh ffh digital conversion value 4 conversion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian v zt ? 1 v ft ? 2 i ref av ref an0 to an7 ta = 25 c v dd = av ref = 3.3v v ss = av ss = 0v operation mode sleep mode stop mode linearity error zero transition voltage full-scale transition voltage resolution av ref current av ref i refs s s v v v dd av ref 0.7 ma 5a 0.4 27/f adc ? 3 6/f adc ? 3 v dd 0.3 0 item symbol pin condition min. typ. max. unit bits (ta = 20 to +75 c, v dd = 3.0 to 3.6v, av ref = 2.7 to v dd , vss = av ss = 0v reference) 8 lsb 70 mv 3345 6.5 3280.5 10 3216 mv 5 ? 1 v zt : value at which the digital conversion value changes from 00h to 01h and vice versa. ? 2 v ft : value at which the digital conversion value changes from feh to ffh and vice versa. ? 3 f adc indicates the values below due to the contents of bit 6 (cks) of the a/d control register (adc: 00f9h). f adc = fc (cks = "0"), fc/2 (cks = "1") however, the selection for f adc = fc (cks = "0") is limited in the clock range of fc = 1 to 14mhz (v dd 4.5 to 5.5v) and fc = 1 to 10mhz (v dd = 3.0 to 4.5v). fig. 6. definition of a/d converter terms
23 CXP845P60 external interruption high, low level width reset input low level width int0 int1 int2 int3 nmi rst 1 32/fc s s item symbol pin condition min. max. unit t ih t il t rsl (5) interruption, reset input (ta = 20 to +75 c, v dd = 3.0 to 5.5v, vss = 0v reference) 0.2v dd 0.8v dd t ih t il int0 int1 int2 int3 nmi (specifies nmi only for the falling edge.) t il t ih 0.2v dd 0.8v dd fig 7. interruption input timing t rsl 0.2v dd rst fig. 8. rst input timing power supply rise time power supply cut-off time v dd 0.05 1 50 ms ms item symbol pin condition min. max. unit t r t off power-on reset repetitive power-on reset (6) power-on reset (ta = 20 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v reference) v dd t r t off 0.2v 0.2v 4.5v turn the power on smoothly. fig. 9. power-on reset
24 CXP845P60 appendix c 1 aaaa a aa a aaaa extal xtal c 2 rd aaaa a aa a aaaa extal xtal (i) main clock aaaa a aa a aaaa extal xtal c 1 c 2 rd (ii) main clock models with an asterisk ( ? ) have the built-in ground capacitance (c 1 , c 2 ). manufacturer murata mfg co., ltd. tdk corporation. kinseki ltd. model csa8.00mtz csa10.0mtz csa12.00mtz cst8.00mtw ? cst10.0mt ? cst12.0mtw ? csa16.00mxz040 cst16.00mxz0c1 ? csa20.00mxz040 csa24.00mxz040 csa28.00mxz040 ccr20.0mc6 ? ccr24.0mc6 ? hc49/u-s cx-11f fc (mhz) 8.00 10.00 12.00 8.00 10.00 12.00 16.00 16.00 20.00 24.00 28.00 20.00 24.00 28.00 28.00 30 5 5 open 3 3 16 16 1 1 30 5 5 open 3 3 16 16 1 1 0 0 0 0 0 0 0 0 220 220 c 1 (pf) c 2 (pf) rd ( ? ) circuit example (i) (ii) (i) (ii) (i) (ii) (i) selection guide ? 1 when the otp product with the power-on reset function is used outside the range of v dd = 4.5 to 5.5v, be sure to keep the external reset (setting the rst pin to low) for the oscillation stable time or more. CXP845P60q-1- CXP845P60r-1- CXP845P60ga-1- fig. 10. spc700 series recommended oscillation circuit mask package rom capacitance reset pin pull-up resistor power-on reset function ? 1 existent/non-existent otp cxp84540 cxp84548 80-pin plastic qfp 80-pin plastic lqfp 80-pin plastic lflga 40k bytes 48k bytes prom 60k bytes existent/non-existent existent existent option item product name 80-pin plastic qfp/lqfp/lflga
25 CXP845P60 characteristics curves 20 (100a) 3 45 6 0.1 5.0 1.0 v dd supply voltage [v] i dd supply current [ma] i dd vs. v dd (fc = 28mhz, ta = 25 c, typical) 7 2 0.05 (50a) 0.01 (10a) 0.5 10.0 20.0 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode 0 15 10 5 fc system clock [mhz] i dd supply current [ma] i dd vs. fc (v dd = 5v, ta = 25 c, typical) 10 30 20 20 (100a) 3 45 6 0.1 5.0 1.0 v dd supply voltage [v] i dd supply current [ma] i dd vs. v dd (fc = 20mhz, ta = 25 c, typical) 7 2 0.05 (50a) 0.01 (10a) 0.5 10.0 20.0 0 15 10 5 fc system clock [mhz] i dd supply current [ma] i dd vs. fc (v dd = 3.3v, ta = 25 c, typical) 10 30 20 1/16 dividing mode 1/4 dividing mode sleep mode stop mode 1/2 dividing mode 30 1/16 dividing mode 1/4 dividing mode sleep mode 1/2 dividing mode sleep mode 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode
26 CXP845P60 package outline unit: mm package structure sony code eiaj code jedec code qfp-80p-l01 qfp080-p-1420 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 1.6g 23.9 0.4 20.0 ?0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 ?0.1 + 0.15 14.0 ?0.1 + 0.4 17.9 0.4 16.3 0.1 ?0.05 + 0.2 2.75 ?0.15 + 0.35 0.8 0.2 0.15 ?0.05 + 0.1 80pin qfp (plastic) m 0.2 0.15 0? to 10? detail a a package structure sony code eiaj code jedec code qfp-80p-l01 qfp080-p-1420 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 1.6g 23.9 0.4 20.0 0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 0.1 + 0.15 14.0 0.1 + 0.4 17.9 0.4 16.3 0.1 0.05 + 0.2 2.75 0.15 + 0.35 0.8 0.2 0.15 0.05 + 0.1 80pin qfp (plastic) m 0.2 0.15 0 ? to 10 ? detail a a lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec.
27 CXP845P60 package outline unit: mm 20 21 40 41 60 61 80 1 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy package structure 14.0 0.2 ? 12.0 0.1 (0.22) b a 1.5 0.1 + 0.2 0.5 0.2 (13.0) 80pin lqfp (plastic) 0.5g lqfp-80p-l01 p-lqfp80-12x12-0.5 0.1 note: dimension " ? " does not include mold protrusion. 0.13 m 0.5 b = 0.18 0.03 ( 0.18 ) (0.127) + 0.08 0.127 0.02 + 0.05 detail b : solder detail a 0 ? to 10 ? 0.1 0.1 0.5 0.2 b 20 21 40 41 60 61 80 1 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy package structure 14.0 0.2 ? 12.0 0.1 (0.22) b a 1.5 0.1 + 0.2 0.5 0.2 (13.0) 80pin lqfp (plastic) 0.5g lqfp-80p-l01 p-lqfp80-12x12-0.5 0.1 note: dimension " ? " does not include mold protrusion. 0.13 m 0.5 b = 0.18 0.03 ( 0.18 ) (0.127) + 0.08 0.127 0.02 + 0.05 detail b : solder detail a 0 ? to 10 ? 0.1 0.1 0.5 0.2 b lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec.
28 CXP845P60 package outline unit: mm so ny c o de eia j code jedec code pa cka ge ma ss pac kage struc ture lflg a - 8 0 p - 0 2 orga nic substra te 0.3g package material terminal treatment terminal material gold pla ting nickel plating 80pin lflga detail x 1.4m ax s s 0.2 s 0.10 x pin 1 in dex 9.0 0.2 a s 9.0 0.2 b s 0.15 x4 p-lflga 80-9x9-0.8 123456789 10 a b a b c d e f g h j k 80 0.40 0.05 0.08 m s ab 0.5 3 0.50 0.5 0.9 0.8 0.3 0.3 0.8 0.9 0.3 0.3 0.4 0.4 0.10m ax sony corporation

▲Up To Search▲

Price & Availability of CXP845P60

	To Download CXP845P60 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .