|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
rev.4.00, oct.02. 2003, page 1 of 11 HD74ALVCH16820 3.3-v 10-bit flip flops with dual outputs rej03d0034-0400z (previous ade-205-170b(z)) rev.4.00 oct.02.2003 description the flip flops of the HD74ALVCH16820 are edge triggere d d-type flip flops. on the positive transition of the clock (clk) input, the device provides true data at the q outputs. a buffered output enable ( oe ) input can be used to place the ten outputs in either a norm al logic state (high or low logic level) or a high impedance state. in the high impedance state, the ou tputs neither load nor drive the bus lines significantly. the high impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. oe input does not affect th e internal operation of the flip flops. old data can be retained or new data can be entered while the outputs are in the high impedance state. active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. features ? v cc = 2.3 v to 3.6 v ? typical v ol ground bounce < 0.8 v (@v cc = 3.3 v, ta = 25c) ? typical v oh undershoot > 2.0 v (@v cc = 3.3 v, ta = 25c) ? high output current 24 ma (@v cc = 3.0 v) ? bus hold on data inputs eliminates the need for external pullup / pulldown resistors d d-type flip flops. on the positive transition of the clock (clk) input, the device provides true data at the q outputs. a buffered output enable ( al logic state (high or low logic level) or a high tputs neither load nor drive the bus lines significantly. the high impedance state and increased drive provide the capability to drive bus lines without need for input does not affect th e internal operation of the flip flops. old data can be retained or new data can be entered while the outputs are in the high impedance state. active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. ground bounce < 0.8 v (@v cc = 3.3 v, ta = 25c) undershoot > 2.0 v (@v cc = 3.3 v, ta = 25c) high output current 24 ma (@v cc = 3.0 v) bus hold on data inputs eliminates the need for external pullup / pulldown resistors
HD74ALVCH16820 rev.4.00, oct.02. 2003, page 2 of 11 function table inputs output qn *1 o e n *2 clk d l hh l ll llxq 0 *1 hxxz h : high level l : low level x : immaterial z : high impedance : low to high transition notes: 1. output level before t he indicated steady state input conditions were established. 2. n = 1, 2 conditions were established. HD74ALVCH16820 rev.4.00, oct.02. 2003, page 3 of 11 pin arrangement (top view) 1 2 3 4 5 6 7 8 9 10 v cc v cc 1q1 1q2 gnd 2q1 2q2 3q1 3q2 4q1 gnd 4q2 5q1 5q2 6q1 6q2 7q1 gnd 7q2 8q1 8q2 9q1 9q2 1oe 11 12 13 14 15 16 17 18 19 20 21 22 23 24 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 nc gnd 25 32 gnd 10q1 26 31 d10 10q2 27 30 nc 2oe 28 29 nc d9 nc d8 nc d7 gnd nc d6 nc d5 nc gnd d4 nc d3 nc d2 nc clk gnd d1 v cc v cc v cc v cc v gnd 7q2 8q1 8q2 9q1 9q2 17 18 19 20 21 22 23 24 41 42 43 44 45 46 47 48 49 gnd 25 10q1 d6 nc d5 nc gnd d4 nc d3 v cc v cc v HD74ALVCH16820 rev.4.00, oct.02. 2003, page 4 of 11 absolute maximum ratings item symbol ratings unit conditions supply voltage v cc ?0.5 to 4.6 v input voltage *1 v i ?0.5 to 4.6 v output voltage *1, 2 v o ?0.5 to v cc +0.5 v input clamp current i ik ?50 ma v i < 0 output clamp current i ok 50 ma v o < 0 or v o > v cc continuous output current i o 50 ma v o = 0 to v cc v cc , gnd current / pin i cc or i gnd 100 ma maximum power dissipation at ta = 55c (in still air) *3 p t 1w t ss o p storage temperature tstg ?65 to 150 c notes: stresses beyond those listed under ?absolut e maximum ratings? may cause permanent damage to the device. these are stress ratings only, and f unctional operation of t he device at these or any other conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. this value is limited to 4.6 v maximum. 3. the maximum package power dissipation is calculated using a junction temperature of 150c and a board trace length of 750 mils. recommended operating conditions item symbol min max unit conditions supply voltage v cc 2.3 3.6 v input voltage v i 0v cc v output voltage v o 0v cc v high level output current i oh ? ?12 ma v cc = 2.3 v ? ?12 v cc = 2.7 v ? ?24 v cc = 3.0 v low level output current i ol ?1 2m av cc = 2.3 v ?1 2v cc = 2.7 v ?2 4v cc = 3.0 v input transition rise or fall rate ? t / ? v 0 10 ns / v operating temperature ta ?40 85 c note: unused control inputs must be held hi gh or low to prevent them from floating. 1w c e maximum ratings? may cause permanent damage to unctional operation of t he device at these or any ?recommended operating conditions? is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. the input and output negative voltage ratings may be exceeded if the input and output clamp 2. this value is limited to 4.6 v maximum. 3. the maximum package power dissipation is calculated using a junction temperature of 150c and a board trace length of 750 mils. recommended operating conditions symbol min max unit conditions v cc v i v o high level output current i oh HD74ALVCH16820 rev.4.00, oct.02. 2003, page 5 of 11 logic diagram 1oe 2oe 1 55 clk d1 56 28 1q2 3 1q1 2 1d c1 to nine other channels to nine other channels HD74ALVCH16820 rev.4.00, oct.02. 2003, page 6 of 11 electrical characteristics (ta = ?40 to 85c) item symbol v cc (v) *1 min max unit test conditions input voltage v ih 2.3 to 2.7 1.7 ? v 2.7 to 3.6 2.0 ? v il 2.3 to 2.7 ? 0.7 2.7 to 3.6 ? 0.8 output voltage v oh min to max v cc ?0.2 ? v i oh = ?100 a 2.3 2.0 ? i oh = ?6 ma, v ih = 1.7 v 2.3 1.7 ? i oh = ?12 ma, v ih = 1.7 v 2.7 2.2 ? i oh = ?12 ma, v ih = 2.0 v 3.0 2.4 ? i oh = ?12 ma, v ih = 2.0 v 3.0 2.0 ? i oh = ?24 ma, v ih = 2.0 v v ol min to max ? 0.2 i ol = 100 a 2.3 ? 0.4 i ol = 6 ma, v il = 0.7 v 2.3 ? 0.7 i ol = 12 ma, v il = 0.7 v 2.7 ? 0.4 i ol = 12 ma, v il = 0.8 v 3.0 ? 0.55 i ol = 24 ma, v il = 0.8 v input current i in 3.6 ? 5 av in = v cc or gnd i in (hold) 2.3 45 ? v in = 0.7 v 2.3 ?45 ? v in = 1.7 v 3.0 75 ? v in = 0.8 v 3.0 ?75 ? v in = 2.0 v 3.6 ? 500 v in = 0 to 3.6 v off state output current *2 i oz 3.6 ? 10 av out = v cc or gnd quiescent supply current i cc 3.6 ? 40 av in = v cc or gnd ? i cc 3.0 to 3.6 ? 750 av in = one input at (v cc ?0.6) v, other inputs at v cc or gnd notes: 1. for conditions shown as min or max, use the appropriate values under recommended operating conditions. 2. for i/o ports, the parameter i oz includes the input leakage current. i oh = ?6 ma, v i oh = ?12 ma, v i oh = ?12 ma, v i oh = ?12 ma, v 3.0 2.0 ? i oh = ?24 ma, v min to max ? 0.2 i ol = 100 a 2.3 ? 0.4 i ol = 6 ma, v 2.3 ? 0.7 i ol = 12 ma, v 2.7 ? 0.4 i 3.0 ? 0.55 3.6 ? 5 in (hold) 2.3 45 ? 2.3 ?45 ? 3.0 75 ? 3.0 ?75 ? 3.6 ? 500 off state output current *2 i oz 3.6 ? 10 quiescent supply current i cc 3.6 ? 40 ? i cc 3.0 to 3.6 ? 750 notes: 1. for conditions shown as min or max, use HD74ALVCH16820 rev.4.00, oct.02. 2003, page 7 of 11 switching characteristics (ta = -40 to 85c) item symbol v cc (v) min typ max unit from (input) to (output) maximum clock frequency f max 2.50.2 150 ? ? mhz 2.7 150 ? ? 3.30.3 150 ? ? propagation delay time t plh 2.50.2 1.0 ? 5.9 ns clk q t phl 2.7 ? ? 5.5 3.30.3 1.0 ? 4.8 output enable time t zh 2.50.2 1.0 ? 6.4 ns oe q t zl 2.7 ? ? 6.1 3.30.3 1.0 ? 5.0 output disable time t hz 2.50.2 1.3 ? 5.7 ns oe q t lz 2.7 ? ? 5.0 3.30.3 1.0 ? 4.5 setup time t su 2.50.2 1.7 ? ? ns 2.7 1.8 ? ? 3.30.3 1.4 ? ? hold time t h 2.50.2 1.1 ? ? ns 2.7 1.1 ? ? 3.30.3 1.0 ? ? pulse width t w 2.50.2 3.3 ? ? ns 2.7 3.3 ? ? 3.30.3 3.3 ? ? input capacitance c in 3.3 ? 3.5 ? pf control inputs 3.3 ? 6.0 ? data inputs output capacitance c o 3.3 ? 7.0 ? pf outputs 2.50.2 1.0 ? 6.4 ns 2.7 ? ? 6.1 3.30.3 1.0 ? 5.0 2.50.2 1.3 ? 5.7 ns oe 2.7 ? ? 5.0 3.30.3 1.0 ? 4.5 2.50.2 1.7 ? ? ns 2.7 1.8 ? ? 3.30.3 1.4 ? ? 2.50.2 1.1 ? ? ns 2.7 1.1 ? ? 3.30.3 1.0 ? ? t w 2.50.2 3.3 ? ? ns 2.7 3.3 ? ? 3.30.3 3.3 ? ? input capacitance c in 3.3 ? 3.5 ? pf control inputs 3.3 ? 6.0 ? output capacitance c o HD74ALVCH16820 rev.4.00, oct.02. 2003, page 8 of 11 500 ? c = 50 pf l l 500 ? s1 *1 see under table gnd open load circuit for outputs note: 1. c includes probe and jig capacitance. symbol t / t plh phl open gnd 4.6 v 6.0 v t / t zh hz t / t zl lz t / t / t su h w open gnd vcc = 2.7 v, 3.30.3 v vcc=2.50.2 v ? test circuit load circuit for outputs note: 1. c includes probe and jig capacitance. l note: 1. c includes probe and jig capacitance. l open gnd 4.6 v 6.0 v lz open gnd vcc = 2.7 v, 3.30.3 v vcc = 2.7 v, 3.30.3 v vcc = 2.7 v, vcc=2.50.2 v HD74ALVCH16820 rev.4.00, oct.02. 2003, page 9 of 11 t plh t phl t su t h v oh v ol t w gnd v ih gnd v ih gnd v ih gnd v ih v ref v ref v ref v ref v ref v ref v ref v ref v ref input output timing input data input input ? waveforms C 1 ? waveforms C 2 10 % 90 % tr tf 10 % 90 % 10 % 90 % tr t h t w v ref v ref v ref 90 % HD74ALVCH16820 rev.4.00, oct.02. 2003, page 10 of 11 v ? 0.3 v oh v + 0.3 v ol t zl t lz t zh t hz v oh v ol waveform - a output control waveform - b gnd v ih v ol1 v oh1 v ref v ref v ref v ref test v ih v ref v oh1 v ol1 1.2 v 1.5 v 2.3 v 3.0 v gnd 2.3 v 2.7 v gnd vcc = 2.7 v, 3.30.3 v vcc=2.50.2 v notes: 1. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, zo = 50 ?, tr 2.5 ns, tf 2.5 ns. 2. waveform ? a is for an output with internal conditions such that the output is low except when disabled by the output control. 3. waveform ? b is for an output with internal conditions such that the output is high except when disabled by the output control. 4. the output are measured one at a time with one transition per measurement. ? waveforms C 3 tr tf 10 % 10 % 90 % 90 % v ? 0.3 v oh 1.2 v 1.5 v test v ih v ref 2.3 v 3.0 v v oh1 v ol1 2.3 v 2.7 v 2.3 v 2.7 v vcc=2.50.2 v notes: 1. all input pulses are supplied by generators having the following characteristics: 10 mhz, zo = 50 ? , tr 2.5 ns, tf 2.5 ns. 2. waveform ? a is for an output with internal conditions such that the output is low except when disabled by the output control. 3. waveform ? b is for an output with internal conditions such that the output is high except when disabled by the output control. 4. the output are measured one at a time with one transition per measurement. HD74ALVCH16820 rev.4.00, oct.02. 2003, page 11 of 11 package dimensions package code jedec jeita mass (reference value) ttp-56dav ? ? 0.23 g *ni/pd/au plating 0.08 m 0.10 *0.15 0.05 8.10 0.20 0.50 0.1 0.65 max 12 8 29 56 14.0 6.10 0? C 8? 0.50 1.20 max 0.10 0.05 14.2 max 1.0 *0.19 0.05 as of january, 2003 unit: mm package code jedec jeita mass *0.15 0.05 8.10 0.20 0.50 0.1 0? C 8? 0.10 0.05 1.0 ? 2003. renesas technolo gy corp., all ri g hts reserved. printed in japan . colo p hon 1.0 keep safet y first in y our circuit desi g ns ! 1. renesas technolo gy corp. puts the maximum effort into makin g semiconductor products better and more reliable, but there is alwa y s the possibilit y that trouble m a y occur with them. trouble with semiconductors ma y lead to personal in j ur y , fire or propert y dama g e . remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placem ent of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technolo gy corp. is necessar y to reprint or reproduce in whole or in part these materials . 7 . if these products or technolo g ies are sub j ect to the japanese export control restrictions, the y must be exported under a license from the japanese g overnment and cannot b e imported into a countr y other than the approved destination. an y diversion or reexport contrar y to the export control laws and re g ulatio n s of japan and/or the countr y of destination is prohibited . 8. please contact renesas technolo gy corp. for further details on these materials or the products contained therein . s ales strate g ic plannin g div. nippon bld g ., 2-6-2, ohte-machi, chi y oda-ku, tok y o 100-0004, japa n htt p ://www.renesas.co m renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices semiconductor products better and more reliable, but there is alwa remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placem 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a evaluate all information as a total system before making a final decision on the applicability of the information and products. no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp corp. is necessar y to reprint or reproduce in whole or in part these materials ect to the japanese export control restrictions, the y must be exported under a license from the japanese other than the approved destination. to the export control laws and re g ulatio n s of japan and/or the countr corp. for further details on these materials or the products contained therein renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 dornacher str. 3, d-85622 feldkirchen, germany renesas sales offices |
Price & Availability of HD74ALVCH16820 |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |