S1C17F13 16-bit single chip microcontroller for active epd descriptions the S1C17F13 is an ultra low-power mcu equipped with a display memory and an epd timing controller to send display data for using the active epd panels. this ic includes the synchronous serial interface, parallel interface, uart, and i2c to communicate with an epd panel and other devices. this ic allows measurement of various environmental conditions such as a temperatur e and humidity measurement using the r/f converter, and a supply voltage measurement using the suppl y voltage detector and brownout reset circuits. ? features cpu cpu core seiko epson original 16-bit risc cpu core s1c17 16-bit 16-bit multiplier 16-bit 16-bit + 32-bit multiply and accumulation unit multiplier/divider (copro) 16-bit 16-bit divider other on-chip debugger embedded flash memory capacity 128k bytes (for both instructions and data) *1 erase/program count 50 times (min.) * programming by the debugging tool icdmini security function to protect from reading/programming by icdmini on-board programming function using icdmini other embedded flash voltage booster to generate t he flash erasing/programming voltage embedded ram 6k bytes (area accessed by cpu only) capacity 14k bytes (area accessed by cpu and epd tcon) clock generator (clg) system clock source 5 sources (osc 3b, osc3a, osc1b, osc1a, and exosc) system clock frequency (operating frequency) 20 mhz (max.) osc3b internal high-speed oscillator circuit (boot clock source) 20/16/12/8 mhz (typ.) selectable via software osc1b internal low-speed oscillator circuit 32 khz (typ.) osc3a high-speed oscillator circuit 20 mhz (max .) crystal or ceramic oscillator circuit osc1a low-speed oscillator circuit 32.768 kh z (typ.) crystal oscillator circuit exosc clock input 20 mhz (max.) square or sine wave input configurable system clock division ratio configurable system clock (except for osc1a and osc1b) used at wake up from sleep state other operating clock frequency for the cpu and a ll peripheral circuits is selectable. i/o port (pport) number of general-purpose i/o ports 37 bits (max.) (pins are shared with the peripheral i/o.) number of input interrupt ports 8 bits all pins contain a pull-up/down resistor that can be enabled/disabled via software other 16 bits contain an interrupt function and a chattering filter function. display control controls display on the active-matrix epd via the embedded spi or pio. includes a display data read function fr om the embedded ram (area for both cpu and epd tcon). epd timing controller (epd tcon) can be controlled with the dedicated api library. communication interfaces 1 channel irda1.0 supported uart (uart) embedded baud-rate generator 3 channels synchronous serial interface (spi) configurable as the communication in terface for epd tcon (spi ch.1) 1 channel master and slave operations supported i 2 c (i2c) embedded baud-rate generator address length: 8 bits (max.) data width: 8 bits (max.) parallel interface (pio) control signals: #ce, #rd, #wr
S1C17F13 configurable as the communica tion interface for epd tcon timers 1 channel watchdog timer (wdt) generates nmi or watchdog timer reset. 4 channels 16-bit timer (t16) generates the spi master clocks. (ch.1 to ch.3) 1 channel clock timer (ct) 128?1 hz counter real-time clock (rtc) hour, minute, and second counters time adjustment function in -31/32,768 to + 32/32,768 second units (applied to t16a3, ct, and rtc clocks) theoretical regulation function (tr) supports correction value alteration according to temperature variations. 2 channels 16-bit pwm timer (t16a3) pwm output, event counter, and count capture functions supply voltage detector (svd) detection level 19 values (1.8 to 3.6 v) intermittent operation mode other generates an interrupt or reset accord ing to the detection level evaluation. r/f converter (rfc) conversion method cr oscillation type with 24-bit counters number of conversion channels 2 channels (u p to four sensors can be connected.) supported sensors dc-bias resistive s ensors and ac-bias resistive sensors temperature detection circuit (tem) resolution/accuracy 1 c steps, 5 c accuracy reset #reset pin reset when the reset pin is set to low. power-on reset reset at power-on. brownout reset reset when brownout (vdd = 1.45 v typ.) is detected. key entry reset reset when the p00 to p01/p02/ p03 keys are pressed simultaneously (can be enabled/ disabled using a register). watchdog timer reset reset when the watchdog timer ov erflows (can be enabled/disabl ed using a register). supply voltage detector reset reset when the supply volt age detector detects the set voltage level (can be enabled/ disabled using a register). interrupt non-maskable interrupt 4 systems (rese t, address misaligned interrupt, debug, nmi) external interrupt: 1 system (8 levels) programmable interrupt internal interrupt: 19 systems (8 levels) power supply voltage vdd operating voltage 2.0 to 3.6 v operating temperature operating temperature range -20 to 70 c current consumption sleep mode 0.35 a osc1 = off, rtc = off, osc3b = off, osc3a = off 0.78 a osc1 = 32 khz (osc1a), rtc = off, osc3b = off, osc3a = off halt mode 0.80 a osc1 = 32 khz (osc1a), rtc = on, osc3b = off, osc3a = off 11.9 a osc1 = 32 khz (osc1a), rtc = off, osc3b = off, osc3a = off 5.43 ma osc1 = off, rtc = off, osc3b = off, osc3a = 20 mhz ceramic run mode 5.5 ma osc1 = off, rtc = off, osc3b = 20 mhz, osc3a = off shipping form 1 tqfp13-64pin (lead pitch: 0.5 mm) 2 chip (pad pitch: 90 m) *1 when using the epd timing controller (epd tcon), an area for storing the timing parameters must be allocated in the flash me mory. when using the internal flash voltage booster as the flash programing power supply, an area for storing the control program must be allocated in the flash memory. 2 seiko epson corporation
S1C17F13 ? block diagram cpu core & debugger (s1c17) internal ram 6k bytes internal ram 14k bytes flash memory 128k bytes osc3b oscillator osc1b oscillator osc1a oscillator osc3a oscillator exosc input circuit power-on reset (por) brownout reset (bor) power generator (pwg) interrupt controller (itc) i/o port (pport) watchdog timer (wdt) clock timer (ct) real-time clock (rtc) theoretical regulation (tr) supply voltage detector (svd) 16-bit timer (t16) ch.0-3 16-bit pwm timer (t16a3) ch.0-1 uart (uart) epd timing controller (epd tcon) synchro- nous serial interface (spi) ch.1 parallel interface (pio) synchronous serial interface (spi) ch.0, 2 i 2 c (i2c) r/f converter (rfc) ch.0-1 temperature detection circuit (tem) 16-bit internal bus clock generator (clg) system reset controller (src) microdevices operations division ic sales & marketing department 421-8 hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 http://www.epson.jp/device/semicon_e/ epson semiconductor website document code: 412501500 first issue feb., 2013 in j apan notice: no part of this material may be reproduced or duplicated in any fo rm or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kin d arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there i s no representation that this material is applicable to produc ts requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. when exporting the products or technology des cribed in this material, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you are requested not to use, to resell, to export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the development and/or manufacture of weapon of mass destruction or for other military purposes. all brands or product names mentioned herein are trademarks and/ or registered trademarks of t heir respective companies. ? seiko epson corporation 2013, all rights reserved 32- bit ram bus 32-bit ram bus instruction bus interrupt request system clock dclk dsio dst2 fout osc1 osc2 osc3 osc4 exosc #reset v dd v ss v d1 v osc v pp c 1n ,c 1p ,c 1h c 2n ,c 2p iref_m usout0 usin0 toutb0/capb0-1 touta0/capa0-1 excl0-1 exsvd p00-07, p10-17, p20-27, p30-37, p40-41, pd0-d2 regmon interrupt signal sdi1 sdo1 spiclk1 #spiss1 pioa[7:0] piod[7:0] #pioce #piord #piowr sdi0, 2 sdo0, 2 spiclk0, 2 #spiss0, 2 sda0 scl0 rfin0-1 ref0-1 sena0-1 senb0-1 rfclko0-1 vm1-2 internal ram 6k bytes cpu core & debugger (s1c17) internal ram 14k bytes flash memory 128k bytes osc3b oscillator osc1b oscillator osc1a oscillator osc3a oscillator exosc input circuit power-on reset (por) brownout reset (bor) power generator (pwg) interrupt controller (itc) i/o port (pport) watchdog timer (wdt) clock timer (ct) real-time clock (rtc) theoretical regulation (tr) supply voltage detector (svd) 16-bit timer (t16) ch.0-3 16-bit pwm timer (t16a3) ch.0-1 uart (uart) epd timing controller (epd tcon) synchro- nous serial interface (spi) ch.1 parallel interface (pio) synchronous serial interface (spi) ch.0, 2 i 2 c (i2c) r/f converter (rfc) ch.0-1 temperature detection circuit (tem) 16-bit internal bus clock generator (clg) system reset controller (src) bit ram bus 32-bit ram bus instruction bus interrupt request system clock dclk dsio dst2 fout osc1 osc2 osc3 osc4 exosc #reset v dd v ss v d1 v osc v pp c 1n ,c 1p ,c 1h c 2n ,c 2p iref_m usout0 usin0 toutb0/capb0-1 touta0/capa0-1 excl0-1 exsvd p00-07, p10-17, p20-27, p30-37, p40-41, pd0-d2 regmon interrupt signal sdi1 sdo1 spiclk1 #spiss1 pioa[7:0] piod[7:0] #pioce #piord #piowr sdi0, 2 sdo0, 2 spiclk0, 2 #spiss0, 2 sda0 scl0 rfin0-1 ref0-1 sena0-1 senb0-1 rfclko0-1 vm1-2 32- seiko epson corporation 3
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