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data sheet v2.0 2009-03 microcontrollers 16/32-bit architecture xc2361a, xc2363a, xc2364a, XC2365A 16/32-bit single-chip microcontroller with 32-bit performance xc2000 family derivatives / base line free datasheet http:///
edition 2009-03 published by infineon technologies ag 81726 munich, germany ? 2009 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms an d conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life -support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or ef fectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. free datasheet http:///
data sheet v2.0 2009-03 microcontrollers 16/32-bit architecture xc2361a, xc2363a, xc2364a, XC2365A 16/32-bit single-chip microcontroller with 32-bit performance xc2000 family derivatives / base line free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line data sheet v2.0, 2009-03 trademarks c166 ? , tricore ? , and dave ? are trademarks of infineon technologies ag. xc236xa revision history: v2.0, 2009-03 previous version(s): v1.31, 2008-11 v1.3, 2008-11 v1.2, 2008-09 v1.1, 2008-06 preliminary v1.0, 2008-06 (intermediate version) page subjects (major changes since last revisions) 17 ff overlaid analog input channels specified (adc0/adc1) 21 signal u3c1_selo1 added 81 , 83 current through power domain dmp_a specified 89 specification of wakeup clock frequencies improved 101 f section ?pad properties? added 111 f ssc interface timing improved 114 ff debug interface timing detailled we listen to your comments is there any information in this document that you feel is wrong, unclear or missing? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line table of contents data sheet 5 v2.0, 2009-03 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 basic device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 special device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 definition of feature variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 pin configuration and definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.1 memory subsystem and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2 external bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3 central processing unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5 memory checker module (mchk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.7 on-chip debug support (ocds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.8 capture/compare unit (capcom2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.9 capture/compare units ccu6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.10 general purpose timer (gpt12e) unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.11 real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.12 a/d converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.13 universal serial interface channel modules (usic) . . . . . . . . . . . . . . . . . 61 3.14 multican module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.15 system timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.16 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.17 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.18 parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.19 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.2.1 dc parameters for upper voltage area . . . . . . . . . . . . . . . . . . . . . . . . 76 4.2.2 dc parameters for lower voltage area . . . . . . . . . . . . . . . . . . . . . . . . 78 4.2.3 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.3 analog/digital converter parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.4 system parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.5 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.6 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.6.1 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.6.2 definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.6.3 external clock input parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table of contents free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line table of contents data sheet 6 v2.0, 2009-03 4.6.4 pad properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.6.5 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.6.6 synchronous serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.6.7 debug interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5 package and reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.1 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.2 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line summary of features data sheet 7 v2.0, 2009-03 16/32-bit single-chip microcontroller with 32-bit performance xc236xa (xc2000 family) 1 summary of features for a quick overview and easy reference, the features of the xc236xa are summarized here. ? high-performance cpu with five-stage pipeline and mpu ? 12.5 ns instruction cycle at 80 mhz cpu clock (single-cycle execution) ? one-cycle 32-bit addition and subtraction with 40-bit result ? one-cycle multiplication (16 16 bit) ? background division (32 / 16 bit) in 21 cycles ? one-cycle multiply-and-accumulate (mac) instructions ? enhanced boolean bit manipulation facilities ? zero-cycle jump execution ? additional instructions to support hll and operating systems ? register-based design with multiple variable register banks ? fast context switching support with two additional local register banks ? 16 mbytes total linear address space for code and data ? 1024 bytes on-chip special function r egister area (c166 family compatible) ? integrated memory protection unit (mpu) ? interrupt system with 16 priority levels for up to 96 sources ? selectable external inputs for interrupt generation and wake-up ? fastest sample-rate 12.5 ns ? eight-channel interrupt-driven single-cycle data transfer with peripheral event controller (pec), 24-bit pointers cover total address space ? clock generation from internal or external clock sources, using on-chip pll or prescaler ? hardware crc-checker with programmable polynomial to supervise on-chip memory areas ? on-chip memory modules ? 8 kbytes on-chip stand-by ram (sbram) ? 2 kbytes on-chip dual-port ram (dpram) ? 16 kbytes on-chip data sram (dsram) ? up to 32 kbytes on-chip program/data sram (psram) ? up to 832 kbytes on-chip program memory (flash memory) ? memory content protection through error correction code (ecc) ? on-chip peripheral modules ? multi-functional general purpose timer unit with 5 timers ? 16-channel general purpose capture/compare unit (capcom2) free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line summary of features data sheet 8 v2.0, 2009-03 ? two capture/compare units for flexible pwm signal generation (ccu6x) ? two synchronizable a/d converters with a total of up to 16 channels, 10-bit resolution, conversion time below 1 s, optional data preprocessing (data reduction, range check), broken wire detection ? up to 6 serial interface channels to be used as uart, lin, high-speed synchronous channel (spi/qspi), iic bus interface (10-bit addressing, 400 kbit/s), iis interface ? on-chip multican interface (rev. 2.0b active) with 64 message objects (full can/basic can) on up to 3 can nodes and gateway functionality ? on-chip system timer and on-chip real time clock ? up to 12 mbytes external address space for code and data ? programmable external bus characteristics for different address ranges ? multiplexed or demultiplexed external address/data buses ? selectable address bus width ? 16-bit or 8-bit data bus width ? four programmable chip-select signals ? single power supply from 3.0 v to 5.5 v ? programmable watchdog timer and oscillator watchdog ? up to 76 general purpose i/o lines ? on-chip bootstrap loaders ? supported by a full range of development tools including c compilers, macro- assembler packages, emulators, evaluation boards, hll debuggers, simulators, logic analyzer disassemblers, programming boards ? on-chip debug support via device access port (dap) or jtag interface ? 100-pin green lqfp package, 0.5 mm (19.7 mil) pitch free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line summary of features data sheet 9 v2.0, 2009-03 ordering information the ordering code for an infineon microcont roller provides an exact reference to a specific product. this ordering code identifies: ? the function set of the corresponding product type ? the temperature range: ? saf- : -40c to 85c ? sak- : -40c to 125c ? the package and the type of delivery. for ordering codes for the xc236xa please c ontact your sales representative or local distributor. this document describes several derivatives of the xc236xa group: basic device types are readily available and special device types are only available on request. as this document refers to all of these derivatives, some descriptions may not apply to a specific product, in particular to the special device types. for simplicity the term xc236xa is used for all derivatives throughout this document. 1.1 basic device types basic device types are available and can be ordered through infineon?s direct and/or distribution channels. table 1 synopsis of xc236xa basic device types derivative 1) 1) this data sheet is valid for devices starting with and including design step aa. xx is a placeholder for the available speed grade (in mhz). program memory 2) 2) specific information about the on-chip flash memory in table 3 . psram 3) 3) all derivatives additionally provide 8 kbytes sbram, 2 kbytes dpram, and 16 kbytes dsram. capt./comp. modules adc 4) chan. 4) specific information about the available channels in table 4 . analog input channels are listed for each analog /digital converter module separately (adc0 + adc1). interfaces 4) sak-XC2365A- 104fxxl 832 kbytes flash 32 kbytes cc2 ccu60/1 11 + 5 3 can nodes, 6 serial chan. sak-xc2364a- 104fxxl 832 kbytes flash 32 kbytes cc2 ccu60/1 11 + 5 2 can nodes, 4 serial chan. sak-xc2364a- 72fxxl 576 kbytes flash 32/16 kbytes cc2 ccu60/1 11 + 5 2 can nodes, 4 serial chan. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line summary of features data sheet 10 v2.0, 2009-03 1.2 special device types special device types are only available fo r high-volume applications on request. table 2 synopsis of xc236xa special device types derivative 1) 1) this data sheet is valid for devices starting with and including design step aa. xx is a placeholder for the available speed grade (in mhz). program memory 2) 2) specific information about the on-chip flash memory in table 3 . psram 3) capt./comp. modules adc 4) chan. interfaces 4) saf-XC2365A- 104fxxl 832 kbytes flash 32 kbytes cc2 ccu60/1 11 + 5 3 can nodes, 6 serial chan. sak-XC2365A- 72fxxl 576 kbytes flash 32/16 kbytes cc2 ccu60/1 11 + 5 3 can nodes, 6 serial chan. saf-XC2365A- 72fxxl 576 kbytes flash 32/16 kbytes cc2 ccu60/1 11 + 5 3 can nodes, 6 serial chan. sak-XC2365A- 56fxxl 448 kbytes flash 32/16 kbytes cc2 ccu60/1 11 + 5 3 can nodes, 6 serial chan. saf-XC2365A- 56fxxl 448 kbytes flash 32/16 kbytes cc2 ccu60/1 11 + 5 3 can nodes, 6 serial chan. saf-xc2364a- 104fxxl 832 kbytes flash 32 kbytes cc2 ccu60/1 11 + 5 2 can nodes, 4 serial chan. sak-xc2364a- 56fxxl 448 kbytes flash 32/16 kbytes cc2 ccu60/1 11 + 5 2 can nodes, 4 serial chan. saf-xc2364a- 56fxxl 448 kbytes flash 32/16 kbytes cc2 ccu60/1 11 + 5 2 can nodes, 4 serial chan. sak-xc2363a- 72fxxl 576 kbytes flash 32/16 kbytes cc2 ccu60/1 4 + 4 2 can nodes, 2 serial chan. saf-xc2363a- 72fxxl 576 kbytes flash 32/16 kbytes cc2 ccu60/1 4 + 4 2 can nodes, 2 serial chan. sak-xc2363a- 56fxxl 448 kbytes flash 32/16 kbytes cc2 ccu60/1 4 + 4 2 can nodes, 2 serial chan. saf-xc2363a- 56fxxl 448 kbytes flash 32/16 kbytes cc2 ccu60/1 4 + 4 2 can nodes, 2 serial chan. sak-xc2361a- 56fxxl 448 kbytes flash 16 kbytes cc2 ccu60/1 11 + 5 2 can nodes, 6 serial chan. sak-xc2361a- 72fxxl 576 kbytes flash 32 kbytes cc2 ccu60/1 11 + 5 2 can nodes, 6 serial chan. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line summary of features data sheet 11 v2.0, 2009-03 1.3 definition of feature variants the xc236xa types are offered with several flash memory sizes. table 3 describes the location of the available memory areas for each flash memory size. the xc236xa types are offered with different interface options. table 4 lists the available channels for each option. 3) all derivatives additionally provide 8 kbytes sbram, 2 kbytes dpram, and 16 kbytes dsram. 4) specific information about the available channels in table 4 . analog input channels are listed for each analog /digital converter module separately (adc0 + adc1). table 3 flash memory allocation total flash size flash area a 1) 1) the uppermost 4-kbyte sector of the first flash segment is reserved for internal use (c0?f000 h to c0?ffff h ). flash area b flash area c 832 kbytes c0?0000 h c0?efff h c1?0000 h cc?ffff h n.a. 576 kbytes c0?0000 h c0?efff h c1?0000 h c7?ffff h cc?0000 h cc?ffff h 448 kbytes c0?0000 h c0?efff h c1?0000 h c5?ffff h cc?0000 h cc?ffff h table 4 interface channel association total number available channels 11 adc0 channels ch0, ch2 ch5, ch8 ch11, ch13, ch15 4 adc0 channels ch0, ch2, ch3, ch4 5 adc1 channels ch0, ch2, ch4, ch5, ch6 (overlay: ch8 ch11) 4 adc1 channels ch0, ch2, ch4, ch5 3 can nodes can0, can1, can2 2 can nodes can0, can1 6 serial channels u0c0, u0c1, u1c0, u1c1, u2c0, u2c1 4 serial channels u0c0, u0c1, u1c0, u1c1 2 serial channels u0c0, u0c1 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 12 v2.0, 2009-03 2 general device information the xc236xa series (16/32-bit single-chip microcontroller with 32-bit performance) is a part of the infineon xc2000 family of full-feature single-chip cmos microcontrollers. these devices extend the functionality and performance of the c166 family in terms of instructions (mac unit), peripherals, and sp eed. they combine high cpu performance (up to 80 million instructions per second) with extended peripheral functionality and enhanced io capabilities. optimized peripherals can be adapted flexibly to meet the application requirements. these derivatives utilize clock generation via pll and internal or external clock sources. on-chip memory modules include program flash, program ram, and data ram. figure 1 logic symbol mc_xy_ logsymb100 port 0 8 bit port 1 8 bit port 2 14 bit port 4 4 bit port 6 3 bit port 7 5 bit v agnd (1) v aref (1) v ddp (9) v ss (4) v ddi (4) xtal1 xtal2 esr0 esr1 port 10 16 bit port 15 5 bit port 5 11 bit via port pins dap/jtag 2 / 4 bit trst debug 2 bit testm porst free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 13 v2.0, 2009-03 2.1 pin configuration and definition the pins of the xc236xa are described in detail in table 5 , which includes all alternate functions. for further explanations please refer to the footnotes at the end of the table. figure 2 summarizes all pins, showing their locations on the four sides of the package. figure 2 pin configuration (top view) mc_xy_pin100 v ddpb 25 p5.3 24 p5.2 23 p5.0 22 v agn d 21 20 19 p15 .5 18 v ddpa 17 16 p15 .0 15 p15 .4 14 p6.2 13 p6.1 12 p6.0 11 v ddim 10 9 8 p7.3 7 6 5 p7.2 4 testm 3 v ddpb 2 v ss 1 p7.0 trst v ar ef p15 .6 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 v ddpb esr0 esr1 porst xtal1 xtal2 p1.7 p1.6 p1.5 p 10.1 5 p1.4 p 10.1 4 v ddi1 p1.3 p 10.1 3 p 10.1 2 p1.2 p 10.1 1 p 10.1 0 p1.1 p 10.9 p 10.8 p1.0 v ddpb v ss 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 p2. 4 46 47 48 49 50 v ss v dd pb p5. 8 p5. 9 p5.10 p5.11 p5.13 p5 .15 p2.12 p2.11 v ddi1 p2. 0 p2. 1 p2. 2 p4. 0 p2. 3 p4. 1 p2. 5 p4. 2 p2. 6 p4. 3 v dd pb 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 v ss v ddpb p0. 0 p2. 7 p0. 1 p2. 8 p2. 9 p0. 2 p10 .0 p10 .1 p10 .2 p0. 4 v ddi1 p2. 13 p2. 10 p10 .3 p0. 5 p10 .4 p10 .5 p0. 6 p10 .6 p10 .7 p0. 7 v ddpb lqfp-100 p7.4 p7.1 p15 .2 p0 .3 p5. 4 p5. 5 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 14 v2.0, 2009-03 key to pin definitions ? ctrl. : the output signal for a port pin is selected by bitfield pc in the associated register px_iocry. output o0 is selected by setting the respective bitfield pc to 1x00 b , output o1 is selected by 1x01 b , etc. output signal oh is controlled by hardware. ? type : indicates the pad type and its power supply domain (a, b, m, 1) ? st: standard pad ? sp: special pad ? dp: double pad - can be used as standard or high-speed pad ? in: input only pad ? ps: power supply pad table 5 pin definitions and functions pin symbol ctrl. type function 3 testm iin/b testmode enable enables factory test modes, must be held high for normal operation (connect to v ddpb ). an internal pullup device will hold this pin high when nothing is driving it. 4 p7.2 o0 / i st/b bit 2 of port 7, general purpose input/output emux0 o1 st/b external analog mux control output 0 (adc1) tdi_c i st/b jtag test data input 5trst iin/b test-system reset input for normal system operation, pin trst should be held low. a high level at this pin at the rising edge of porst activates the xc236xa?s debug system. in this case, pin trst must be driven low once to reset the debug system. an internal pulldown device will hold this pin low when nothing is driving it. 6 p7.0 o0 / i st/b bit 0 of port 7, general purpose input/output t3out o1 st/b gpt12e timer t3 toggle latch output t6out o2 st/b gpt12e timer t6 toggle latch output tdo_a oh / i st/b jtag test data output / dap1 input/output esr2_1 i st/b esr2 trigger input 1 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 15 v2.0, 2009-03 7 p7.3 o0 / i st/b bit 3 of port 7, general purpose input/output emux1 o1 st/b external analog mux control output 1 (adc1) u0c1_dout o2 st/b usic0 channel 1 shift data output u0c0_dout o3 st/b usic0 channel 0 shift data output tms_c i st/b jtag test mode selection input u0c1_dx0f i st/b usic0 channel 1 shift data input 8 p7.1 o0 / i st/b bit 1 of port 7, general purpose input/output extclk o1 st/b programmable clock signal output brkin_c i st/b ocds break signal input 9 p7.4 o0 / i st/b bit 4 of port 7, general purpose input/output emux2 o1 st/b external analog mux control output 2 (adc1) u0c1_dout o2 st/b usic0 channel 1 shift data output u0c1_sclk out o3 st/b usic0 channel 1 shift clock output tck_c i st/b dap0/jtag clock input u0c0_dx0d i st/b usic0 channel 0 shift data input u0c1_dx1e i st/b usic0 channel 1 shift clock input 11 p6.0 o0 / i st/a bit 0 of port 6, general purpose input/output emux0 o1 st/a external analog mux control output 0 (adc0) txdc2 o2 st/a can node 2 transmit data output brkout o3 st/a ocds break signal output adcx_reqg tyg i st/a external request gate input for adc0/1 u1c1_dx0e i st/a usic1 channel 1 shift data input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 16 v2.0, 2009-03 12 p6.1 o0 / i st/a bit 1 of port 6, general purpose input/output emux1 o1 st/a external analog mux control output 1 (adc0) t3out o2 st/a gpt12e timer t3 toggle latch output u1c1_dout o3 st/a usic1 channel 1 shift data output adcx_reqt rye i st/a external request trigger input for adc0/1 rxdc2e i st/a can node 2 receive data input esr1_6 i st/a esr1 trigger input 6 13 p6.2 o0 / i st/a bit 2 of port 6, general purpose input/output emux2 o1 st/a external analog mux control output 2 (adc0) t6out o2 st/a gpt12e timer t6 toggle latch output u1c1_sclk out o3 st/a usic1 channel 1 shift clock output u1c1_dx1c i st/a usic1 channel 1 shift clock input 15 p15.0 i in/a bit 0 of port 15, general purpose input adc1_ch0 i in/a analog input channel 0 for adc1 16 p15.2 i in/a bit 2 of port 15, general purpose input adc1_ch2 i in/a analog input channel 2 for adc1 t5ina i in/a gpt12e timer t5 count/gate input 17 p15.4 i in/a bit 4 of port 15, general purpose input adc1_ch4 i in/a analog input channel 4 for adc1 t6ina i in/a gpt12e timer t6 count/gate input 18 p15.5 i in/a bit 5 of port 15, general purpose input adc1_ch5 i in/a analog input channel 5 for adc1 t6euda i in/a gpt12e timer t6 external up/down control input 19 p15.6 i in/a bit 6 of port 15, general purpose input adc1_ch6 i in/a analog input channel 6 for adc1 20 v aref - ps/a reference voltage for a/d converters adc0/1 21 v agnd - ps/a reference ground for a/d converters adc0/1 table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 17 v2.0, 2009-03 22 p5.0 i in/a bit 0 of port 5, general purpose input adc0_ch0 i in/a analog input channel 0 for adc0 23 p5.2 i in/a bit 2 of port 5, general purpose input adc0_ch2 i in/a analog input channel 2 for adc0 tdi_a i in/a jtag test data input 24 p5.3 i in/a bit 3 of port 5, general purpose input adc0_ch3 i in/a analog input channel 3 for adc0 t3ina i in/a gpt12e timer t3 count/gate input 28 p5.4 i in/a bit 4 of port 5, general purpose input adc0_ch4 i in/a analog input channel 4 for adc0 t3euda i in/a gpt12e timer t3 external up/down control input tms_a i in/a jtag test mode selection input 29 p5.5 i in/a bit 5 of port 5, general purpose input adc0_ch5 i in/a analog input channel 5 for adc0 ccu60_t12 hrb iin/a external run control input for t12 of ccu60 30 p5.8 i in/a bit 8 of port 5, general purpose input adc0_ch8 i in/a analog input channel 8 for adc0 adc1_ch8 i in/a analog input channel 8 for adc1 ccu6x_t12h rc iin/a external run control input for t12 of ccu60/1 ccu6x_t13h rc iin/a external run control input for t13 of ccu60/1 u2c0_dx0f i in/a usic2 channel 0 shift data input 31 p5.9 i in/a bit 9 of port 5, general purpose input adc0_ch9 i in/a analog input channel 9 for adc0 adc1_ch9 i in/a analog input channel 9 for adc1 cc2_t7in i in/a capcom2 timer t7 count input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 18 v2.0, 2009-03 32 p5.10 i in/a bit 10 of port 5, general purpose input adc0_ch10 i in/a analog input channel 10 for adc0 adc1_ch10 i in/a analog input channel 10 for adc1 brkin_a iin/a ocds break signal input u2c1_dx0f i in/a usic2 channel 1 shift data input ccu61_t13 hra iin/a external run control input for t13 of ccu61 33 p5.11 i in/a bit 11 of port 5, general purpose input adc0_ch11 i in/a analog input channel 11 for adc0 adc1_ch11 i in/a analog input channel 11 for adc1 34 p5.13 i in/a bit 13 of port 5, general purpose input adc0_ch13 i in/a analog input channel 13 for adc0 35 p5.15 i in/a bit 15 of port 5, general purpose input adc0_ch15 i in/a analog input channel 15 for adc0 rxdc2f i in/a can node 2 receive data input 36 p2.12 o0 / i st/b bit 12 of port 2, general purpose input/output u0c0_selo 4 o1 st/b usic0 channel 0 select/control 4 output u0c1_selo 3 o2 st/b usic0 channel 1 select/control 3 output txdc2 o3 st/b can node 2 transmit data output ready i st/b external bus interface ready input 37 p2.11 o0 / i st/b bit 11 of port 2, general purpose input/output u0c0_selo 2 o1 st/b usic0 channel 0 select/control 2 output u0c1_selo 2 o2 st/b usic0 channel 1 select/control 2 output bhe /wrh oh st/b external bus interf. high-byte control output can operate either as byte high enable (bhe ) or as write strobe for high byte (wrh ). table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 19 v2.0, 2009-03 39 p2.0 o0 / i st/b bit 0 of port 2, general purpose input/output ad13 oh / i st/b external bus interface address/data line 13 rxdc0c i st/b can node 0 receive data input t5inb i st/b gpt12e timer t5 count/gate input 40 p2.1 o0 / i st/b bit 1 of port 2, general purpose input/output txdc0 o1 st/b can node 0 transmit data output ad14 oh / i st/b external bus interface address/data line 14 t5eudb i st/b gpt12e timer t5 external up/down control input esr1_5 i st/b esr1 trigger input 5 41 p2.2 o0 / i st/b bit 2 of port 2, general purpose input/output txdc1 o1 st/b can node 1 transmit data output ad15 oh / i st/b external bus interface address/data line 15 esr2_5 i st/b esr2 trigger input 5 42 p4.0 o0 / i st/b bit 0 of port 4, general purpose input/output cc2_cc24 o3 / i st/b capcom2 cc24io capture inp./ compare out. cs0 oh st/b external bus interface chip select 0 output 43 p2.3 o0 / i st/b bit 3 of port 2, general purpose input/output u0c0_dout o1 st/b usic0 channel 0 shift data output cc2_cc16 o3 / i st/b capcom2 cc16io capture inp./ compare out. a16 oh st/b external bus interface address line 16 esr2_0 i st/b esr2 trigger input 0 u0c0_dx0e i st/b usic0 channel 0 shift data input u0c1_dx0d i st/b usic0 channel 1 shift data input rxdc0a i st/b can node 0 receive data input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 20 v2.0, 2009-03 44 p4.1 o0 / i st/b bit 1 of port 4, general purpose input/output txdc2 o2 st/b can node 2 transmit data output cc2_cc25 o3 / i st/b capcom2 cc25io capture inp./ compare out. cs1 oh st/b external bus interface chip select 1 output t4eudb i st/b gpt12e timer t4 external up/down control input esr1_8 i st/b esr1 trigger input 8 45 p2.4 o0 / i st/b bit 4 of port 2, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output txdc0 o2 st/b can node 0 transmit data output cc2_cc17 o3 / i st/b capcom2 cc17io capture inp./ compare out. a17 oh st/b external bus interface address line 17 esr1_0 i st/b esr1 trigger input 0 u0c0_dx0f i st/b usic0 channel 0 shift data input rxdc1a i st/b can node 1 receive data input 46 p2.5 o0 / i st/b bit 5 of port 2, general purpose input/output u0c0_sclk out o1 st/b usic0 channel 0 shift clock output txdc0 o2 st/b can node 0 transmit data output cc2_cc18 o3 / i st/b capcom2 cc18io capture inp./ compare out. a18 oh st/b external bus interface address line 18 u0c0_dx1d i st/b usic0 channel 0 shift clock input esr1_10 i st/b esr1 trigger input 10 47 p4.2 o0 / i st/b bit 2 of port 4, general purpose input/output txdc2 o2 st/b can node 2 transmit data output cc2_cc26 o3 / i st/b capcom2 cc26io capture inp./ compare out. cs2 oh st/b external bus interface chip select 2 output t2ina i st/b gpt12e timer t2 count/gate input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 21 v2.0, 2009-03 48 p2.6 o0 / i st/b bit 6 of port 2, general purpose input/output u0c0_selo 0 o1 st/b usic0 channel 0 select/control 0 output u0c1_selo 1 o2 st/b usic0 channel 1 select/control 1 output cc2_cc19 o3 / i st/b capcom2 cc19io capture inp./ compare out. a19 oh st/b external bus interface address line 19 u0c0_dx2d i st/b usic0 channel 0 shift control input rxdc0d i st/b can node 0 receive data input esr2_6 i st/b esr2 trigger input 6 49 p4.3 o0 / i st/b bit 3 of port 4, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output cc2_cc27 o3 / i st/b capcom2 cc27io capture inp./ compare out. cs3 oh st/b external bus interface chip select 3 output rxdc2a i st/b can node 2 receive data input t2euda i st/b gpt12e timer t2 external up/down control input 53 p0.0 o0 / i st/b bit 0 of port 0, general purpose input/output u1c0_dout o1 st/b usic1 channel 0 shift data output ccu61_cc6 0 o3 st/b ccu61 channel 0 ioutput a0 oh st/b external bus interface address line 0 u1c0_dx0a i st/b usic1 channel 0 shift data input ccu61_cc6 0ina i st/b ccu61 channel 0 input esr1_11 i st/b esr1 trigger input 11 table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 22 v2.0, 2009-03 54 p2.7 o0 / i st/b bit 7 of port 2, general purpose input/output u0c1_selo 0 o1 st/b usic0 channel 1 select/control 0 output u0c0_selo 1 o2 st/b usic0 channel 0 select/control 1 output cc2_cc20 o3 / i st/b capcom2 cc20io capture inp./ compare out. a20 oh st/b external bus interface address line 20 u0c1_dx2c i st/b usic0 channel 1 shift control input rxdc1c i st/b can node 1 receive data input esr2_7 i st/b esr2 trigger input 7 55 p0.1 o0 / i st/b bit 1 of port 0, general purpose input/output u1c0_dout o1 st/b usic1 channel 0 shift data output txdc0 o2 st/b can node 0 transmit data output ccu61_cc6 1 o3 st/b ccu61 channel 1 output a1 oh st/b external bus interface address line 1 u1c0_dx0b i st/b usic1 channel 0 shift data input ccu61_cc6 1ina i st/b ccu61 channel 1 input u1c0_dx1a i st/b usic1 channel 0 shift clock input 56 p2.8 o0 / i dp/b bit 8 of port 2, general purpose input/output u0c1_sclk out o1 dp/b usic0 channel 1 shift clock output extclk o2 dp/b programmable clock signal output 1) cc2_cc21 o3 / i dp/b capcom2 cc21io capture inp./ compare out. a21 oh dp/b external bus interface address line 21 u0c1_dx1d i dp/b usic0 channel 1 shift clock input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 23 v2.0, 2009-03 57 p2.9 o0 / i st/b bit 9 of port 2, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output txdc1 o2 st/b can node 1 transmit data output cc2_cc22 o3 / i st/b capcom2 cc22io capture inp./ compare out. a22 oh st/b external bus interface address line 22 clkin1 i st/b clock signal input 1 tck_a i st/b dap0/jtag clock input 58 p0.2 o0 / i st/b bit 2 of port 0, general purpose input/output u1c0_sclk out o1 st/b usic1 channel 0 shift clock output txdc0 o2 st/b can node 0 transmit data output ccu61_cc6 2 o3 st/b ccu61 channel 2 output a2 oh st/b external bus interface address line 2 u1c0_dx1b i st/b usic1 channel 0 shift clock input ccu61_cc6 2ina i st/b ccu61 channel 2 input 59 p10.0 o0 / i st/b bit 0 of port 10, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output ccu60_cc6 0 o2 st/b ccu60 channel 0 output ad0 oh / i st/b external bus interface address/data line 0 ccu60_cc6 0ina i st/b ccu60 channel 0 input esr1_2 i st/b esr1 trigger input 2 u0c0_dx0a i st/b usic0 channel 0 shift data input u0c1_dx0a i st/b usic0 channel 1 shift data input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 24 v2.0, 2009-03 60 p10.1 o0 / i st/b bit 1 of port 10, general purpose input/output u0c0_dout o1 st/b usic0 channel 0 shift data output ccu60_cc6 1 o2 st/b ccu60 channel 1 output ad1 oh / i st/b external bus interface address/data line 1 ccu60_cc6 1ina i st/b ccu60 channel 1 input u0c0_dx1a i st/b usic0 channel 0 shift clock input u0c0_dx0b i st/b usic0 channel 0 shift data input 61 p0.3 o0 / i st/b bit 3 of port 0, general purpose input/output u1c0_selo 0 o1 st/b usic1 channel 0 select/control 0 output u1c1_selo 1 o2 st/b usic1 channel 1 select/control 1 output ccu61_cou t60 o3 st/b ccu61 channel 0 output a3 oh st/b external bus interface address line 3 u1c0_dx2a i st/b usic1 channel 0 shift control input rxdc0b i st/b can node 0 receive data input 62 p10.2 o0 / i st/b bit 2 of port 10, general purpose input/output u0c0_sclk out o1 st/b usic0 channel 0 shift clock output ccu60_cc6 2 o2 st/b ccu60 channel 2 output ad2 oh / i st/b external bus interface address/data line 2 ccu60_cc6 2ina i st/b ccu60 channel 2 input u0c0_dx1b i st/b usic0 channel 0 shift clock input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 25 v2.0, 2009-03 63 p0.4 o0 / i st/b bit 4 of port 0, general purpose input/output u1c1_selo 0 o1 st/b usic1 channel 1 select/control 0 output u1c0_selo 1 o2 st/b usic1 channel 0 select/control 1 output ccu61_cou t61 o3 st/b ccu61 channel 1 output a4 oh st/b external bus interface address line 4 u1c1_dx2a i st/b usic1 channel 1 shift control input rxdc1b i st/b can node 1 receive data input esr2_8 i st/b esr2 trigger input 8 65 p2.13 o0 / i st/b bit 13 of port 2, general purpose input/output u2c1_selo 2 o1 st/b usic2 channel 1 select/control 2 output rxdc2d i st/b can node 2 receive data input 66 p2.10 o0 / i st/b bit 10 of port 2, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output u0c0_selo 3 o2 st/b usic0 channel 0 select/control 3 output cc2_cc23 o3 / i st/b capcom2 cc23io capture inp./ compare out. a23 oh st/b external bus interface address line 23 u0c1_dx0e i st/b usic0 channel 1 shift data input capina i st/b gpt12e register caprel capture input 67 p10.3 o0 / i st/b bit 3 of port 10, general purpose input/output ccu60_cou t60 o2 st/b ccu60 channel 0 output ad3 oh / i st/b external bus interface address/data line 3 u0c0_dx2a i st/b usic0 channel 0 shift control input u0c1_dx2a i st/b usic0 channel 1 shift control input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 26 v2.0, 2009-03 68 p0.5 o0 / i st/b bit 5 of port 0, general purpose input/output u1c1_sclk out o1 st/b usic1 channel 1 shift clock output u1c0_selo 2 o2 st/b usic1 channel 0 select/control 2 output ccu61_cou t62 o3 st/b ccu61 channel 2 output a5 oh st/b external bus interface address line 5 u1c1_dx1a i st/b usic1 channel 1 shift clock input u1c0_dx1c i st/b usic1 channel 0 shift clock input 69 p10.4 o0 / i st/b bit 4 of port 10, general purpose input/output u0c0_selo 3 o1 st/b usic0 channel 0 select/control 3 output ccu60_cou t61 o2 st/b ccu60 channel 1 output ad4 oh / i st/b external bus interface address/data line 4 u0c0_dx2b i st/b usic0 channel 0 shift control input u0c1_dx2b i st/b usic0 channel 1 shift control input esr1_9 i st/b esr1 trigger input 9 70 p10.5 o0 / i st/b bit 5 of port 10, general purpose input/output u0c1_sclk out o1 st/b usic0 channel 1 shift clock output ccu60_cou t62 o2 st/b ccu60 channel 2 output u2c0_dout o3 st/b usic2 channel 0 shift data output ad5 oh / i st/b external bus interface address/data line 5 u0c1_dx1b i st/b usic0 channel 1 shift clock input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 27 v2.0, 2009-03 71 p0.6 o0 / i st/b bit 6 of port 0, general purpose input/output u1c1_dout o1 st/b usic1 channel 1 shift data output txdc1 o2 st/b can node 1 transmit data output ccu61_cou t63 o3 st/b ccu61 channel 3 output a6 oh st/b external bus interface address line 6 u1c1_dx0a i st/b usic1 channel 1 shift data input ccu61_ctr apa i st/b ccu61 emergency trap input u1c1_dx1b i st/b usic1 channel 1 shift clock input 72 p10.6 o0 / i st/b bit 6 of port 10, general purpose input/output u0c0_dout o1 st/b usic0 channel 0 shift data output u1c0_selo 0 o3 st/b usic1 channel 0 select/control 0 output ad6 oh / i st/b external bus interface address/data line 6 u0c0_dx0c i st/b usic0 channel 0 shift data input u1c0_dx2d i st/b usic1 channel 0 shift control input ccu60_ctr apa i st/b ccu60 emergency trap input 73 p10.7 o0 / i st/b bit 7 of port 10, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output ccu60_cou t63 o2 st/b ccu60 channel 3 output ad7 oh / i st/b external bus interface address/data line 7 u0c1_dx0b i st/b usic0 channel 1 shift data input ccu60_ccp os0a i st/b ccu60 position input 0 t4inb i st/b gpt12e timer t4 count/gate input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 28 v2.0, 2009-03 74 p0.7 o0 / i st/b bit 7 of port 0, general purpose input/output u1c1_dout o1 st/b usic1 channel 1 shift data output u1c0_selo 3 o2 st/b usic1 channel 0 select/control 3 output a7 oh st/b external bus interface address line 7 u1c1_dx0b i st/b usic1 channel 1 shift data input ccu61_ctr apb i st/b ccu61 emergency trap input 78 p1.0 o0 / i st/b bit 0 of port 1, general purpose input/output u1c0_mclk out o1 st/b usic1 channel 0 master clock output u1c0_selo 4 o2 st/b usic1 channel 0 select/control 4 output a8 oh st/b external bus interface address line 8 esr1_3 i st/b esr1 trigger input 3 t6inb i st/b gpt12e timer t6 count/gate input 79 p10.8 o0 / i st/b bit 8 of port 10, general purpose input/output u0c0_mclk out o1 st/b usic0 channel 0 master clock output u0c1_selo 0 o2 st/b usic0 channel 1 select/control 0 output u2c1_dout o3 st/b usic2 channel 1 shift data output ad8 oh / i st/b external bus interface address/data line 8 ccu60_ccp os1a i st/b ccu60 position input 1 u0c0_dx1c i st/b usic0 channel 0 shift clock input brkin_b i st/b ocds break signal input t3eudb i st/b gpt12e timer t3 external up/down control input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 29 v2.0, 2009-03 80 p10.9 o0 / i st/b bit 9 of port 10, general purpose input/output u0c0_selo 4 o1 st/b usic0 channel 0 select/control 4 output u0c1_mclk out o2 st/b usic0 channel 1 master clock output ad9 oh / i st/b external bus interface address/data line 9 ccu60_ccp os2a i st/b ccu60 position input 2 tck_b i st/b dap0/jtag clock input t3inb i st/b gpt12e timer t3 count/gate input 81 p1.1 o0 / i st/b bit 1 of port 1, general purpose input/output u1c0_selo 5 o2 st/b usic1 channel 0 select/control 5 output u2c1_dout o3 st/b usic2 channel 1 shift data output a9 oh st/b external bus interface address line 9 esr2_3 i st/b esr2 trigger input 3 u2c1_dx0c i st/b usic2 channel 1 shift data input 82 p10.10 o0 / i st/b bit 10 of port 10, general purpose input/output u0c0_selo 0 o1 st/b usic0 channel 0 select/control 0 output ccu60_cou t63 o2 st/b ccu60 channel 3 output ad10 oh / i st/b external bus interface address/data line 10 u0c0_dx2c i st/b usic0 channel 0 shift control input u0c1_dx1a i st/b usic0 channel 1 shift clock input tdi_b i st/b jtag test data input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 30 v2.0, 2009-03 83 p10.11 o0 / i st/b bit 11 of port 10, general purpose input/output u1c0_sclk out o1 st/b usic1 channel 0 shift clock output brkout o2 st/b ocds break signal output ad11 oh / i st/b external bus interface address/data line 11 u1c0_dx1d i st/b usic1 channel 0 shift clock input rxdc2b i st/b can node 2 receive data input tms_b i st/b jtag test mode selection input 84 p1.2 o0 / i st/b bit 2 of port 1, general purpose input/output u1c0_selo 6 o2 st/b usic1 channel 0 select/control 6 output u2c1_sclk out o3 st/b usic2 channel 1 shift clock output a10 oh st/b external bus interface address line 10 esr1_4 i st/b esr1 trigger input 4 ccu61_t12 hrb i st/b external run control input for t12 of ccu61 u2c1_dx0d i st/b usic2 channel 1 shift data input u2c1_dx1c i st/b usic2 channel 1 shift clock input 85 p10.12 o0 / i st/b bit 12 of port 10, general purpose input/output u1c0_dout o1 st/b usic1 channel 0 shift data output txdc2 o2 st/b can node 2 transmit data output tdo_b oh / i st/b jtag test data output / dap1 input/output ad12 oh / i st/b external bus interface address/data line 12 u1c0_dx0c i st/b usic1 channel 0 shift data input u1c0_dx1e i st/b usic1 channel 0 shift clock input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 31 v2.0, 2009-03 86 p10.13 o0 / i st/b bit 13 of port 10, general purpose input/output u1c0_dout o1 st/b usic1 channel 0 shift data output u1c0_selo 3 o3 st/b usic1 channel 0 select/control 3 output wr /wrl oh st/b external bus interface write strobe output active for each external write access, when wr , active for ext. writes to the low byte, when wrl . u1c0_dx0d i st/b usic1 channel 0 shift data input 87 p1.3 o0 / i st/b bit 3 of port 1, general purpose input/output u1c0_selo 7 o2 st/b usic1 channel 0 select/control 7 output u2c0_selo 4 o3 st/b usic2 channel 0 select/control 4 output a11 oh st/b external bus interface address line 11 esr2_4 i st/b esr2 trigger input 4 89 p10.14 o0 / i st/b bit 14 of port 10, general purpose input/output u1c0_selo 1 o1 st/b usic1 channel 0 select/control 1 output u0c1_dout o2 st/b usic0 channel 1 shift data output rd oh st/b external bus interface read strobe output esr2_2 i st/b esr2 trigger input 2 u0c1_dx0c i st/b usic0 channel 1 shift data input 90 p1.4 o0 / i st/b bit 4 of port 1, general purpose input/output u1c1_selo 4 o2 st/b usic1 channel 1 select/control 4 output u2c0_selo 5 o3 st/b usic2 channel 0 select/control 5 output a12 oh st/b external bus interface address line 12 u2c0_dx2b i st/b usic2 channel 0 shift control input table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 32 v2.0, 2009-03 91 p10.15 o0 / i st/b bit 15 of port 10, general purpose input/output u1c0_selo 2 o1 st/b usic1 channel 0 select/control 2 output u0c1_dout o2 st/b usic0 channel 1 shift data output u1c0_dout o3 st/b usic1 channel 0 shift data output ale oh st/b external bus interf. addr. latch enable output u0c1_dx1c i st/b usic0 channel 1 shift clock input 92 p1.5 o0 / i st/b bit 5 of port 1, general purpose input/output u1c1_selo 3 o2 st/b usic1 channel 1 select/control 3 output brkout o3 st/b ocds break signal output a13 oh st/b external bus interface address line 13 u2c0_dx0c i st/b usic2 channel 0 shift data input 93 p1.6 o0 / i st/b bit 6 of port 1, general purpose input/output u1c1_selo 2 o2 st/b usic1 channel 1 select/control 2 output u2c0_dout o3 st/b usic2 channel 0 shift data output a14 oh st/b external bus interface address line 14 u2c0_dx0d i st/b usic2 channel 0 shift data input 94 p1.7 o0 / i st/b bit 7 of port 1, general purpose input/output u1c1_mclk out o2 st/b usic1 channel 1 master clock output u2c0_sclk out o3 st/b usic2 channel 0 shift clock output a15 oh st/b external bus interface address line 15 u2c0_dx1c i st/b usic2 channel 0 shift clock input 95 xtal2 o sp/m crystal oscillator amplifier output 96 xtal1 i sp/m crystal oscillator amplifier input to clock the device from an external source, drive xtal1, while leaving xtal2 unconnected. voltages on xtal1 must comply to the core supply voltage v ddim . esr2_9 i st/b esr2 trigger input 9 table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 33 v2.0, 2009-03 97 porst iin/b power on reset input a low level at this pin resets the xc236xa completely. a spike filter suppresses input pulses <10 ns. input pulses >100 ns safely pass the filter. the minimum duration for a safe recognition should be 120 ns. an internal pullup device will hold this pin high when nothing is driving it. 98 esr1 o0 / i st/b external service request 1 rxdc0e i st/b can node 0 receive data input u1c0_dx0f i st/b usic1 channel 0 shift data input u1c0_dx2c i st/b usic1 channel 0 shift control input u1c1_dx0c i st/b usic1 channel 1 shift data input u1c1_dx2b i st/b usic1 channel 1 shift control input u2c1_dx2c i st/b usic2 channel 1 shift control input 99 esr0 o0 / i st/b external service request 0 note: after power-up, esr0 operates as open- drain bidirectional reset with a weak pull-up. u1c0_dx0e i st/b usic1 channel 0 shift data input u1c0_dx2b i st/b usic1 channel 0 shift control input 10 v ddim - ps/m digital core supply voltage for domain m decouple with a ceramic capacitor, see table 13 for details. 38, 64, 88 v ddi1 - ps/1 digital core supply voltage for domain 1 decouple with a ceramic capacitor, see table 13 for details. all v ddi1 pins must be connected to each other. 14 v ddpa - ps/a digital pad supply voltage for domain a connect decoupling capacitors to adjacent v ddp / v ss pin pairs as close as possible to the pins. note: the a/d_converters and ports p5, p6 and p15 are fed from supply voltage v ddpa . table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line general device information data sheet 34 v2.0, 2009-03 2, 25, 27, 50, 52, 75, 77, 100 v ddpb - ps/b digital pad supply voltage for domain b connect decoupling capacitors to adjacent v ddp / v ss pin pairs as close as possible to the pins. note: the on-chip voltage regulators and all ports except p5, p6 and p15 are fed from supply voltage v ddpb . 1, 26, 51, 76 v ss - ps/-- digital ground all v ss pins must be connected to the ground-line or ground-plane. note: also the exposed pad is connected internally to v ss . to improve the emc behavior, it is recommended to connect the exposed pad to the board ground. for thermal aspects, please refer to section 5.1 . board layout examples are given in an application note. 1) to generate the reference clock output for bus timing measurement, f sys must be selected as source for extclk and p2.8 must be selected as output pin. also the high-speed clock pad must be enabled. this configuration is referred to as reference clock output signal clkout. table 5 pin definitions and functions (cont?d) pin symbol ctrl. type function free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 35 v2.0, 2009-03 3 functional description the architecture of the xc236xa combines advantages of risc, cisc, and dsp processors with an advanced peripheral subsystem in a well-balanced design. on-chip memory blocks allow the design of comp act systems-on-silicon with maximum performance suited for computing, control, and communication. the on-chip memory blocks (program code memory and sram, dual-port ram, data sram) and the generic peripherals are connected to the cpu by separate high-speed buses. another bus, the lxbus, connects additional on-chip resources and external resources (see figure 3 ). this bus structure enhances overall system performance by enabling the concurrent operation of several subsystems of the xc236xa. the block diagram gives an overview of the on-chip components and the advanced internal bus structure of the xc236xa. figure 3 block diagram multi can dpram cpu pmu dmu brgen adc1 8-bit 10-bit rtc mchk interrupt & pec ebc lxbus control external bus control dsram psram system functions clock , reset, power control, standby ram ocds debug support interrupt bus periph eral data bu s analog and digital general purpose io (gpio) ports mc_xy _ blockdi agram flash memory gpt t6 t5 t4 t3 t2 adc0 8-bit 10 -bit cc2 t8 t7 lxbus im b wdt ccu6x t13 t12 usic0 2 ch., 64 x buffer rs232, lin, spi, iic , iis mac unit mpu ccu60 t13 t12 .. .. usicx 2 ch., 64 x buffer rs232, lin, spi, iic, iis .. .. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 36 v2.0, 2009-03 3.1 memory subsystem and organization the memory space of the xc236xa is confi gured in the von neumann architecture. in this architecture all internal and external resources, including code memory, data memory, registers and i/o ports, are organized in the same linear address space. this common memory space consists of 16 mbytes organized as 256 segments of 64 kbytes; each segment contains four data pages of 16 kbytes. the entire memory space can be accessed bytewise or wordwise. portions of the on-chip dpram and the register spaces (esfr/ sfr) additionally are directly bit addressable. the internal data memory areas and the special function register areas (sfr and esfr) are mapped into segment 0, the system segment. the program management unit (pmu) handles all code fetches and, therefore, controls access to the program memories such as flash memory and psram. the data management unit (dmu) handles all data transfers and, therefore, controls access to the dsram and the on-chip peripherals. both units (pmu and dmu) are connected to the high-speed syst em bus so that they can exchange data. this is required if operands are read from program memory, code or data is written to the psram, code is fetched from external memory, or data is read from or written to external resources. these include peripherals on the lxbus such as usic or multican. the system bus allows concurrent two-way communication for maximum transfer performance. table 6 xc236xa memory map address area start loc. end loc. area size 1) notes imb register space ff?ff00 h ff?ffff h 256 bytes ? reserved (access trap) f0?0000 h ff?feff h <1 mbyte minus imb registers reserved for epsram e8?8000 h ef?ffff h 480 kbytes mirrors epsram emulated psram e8?0000 h e8?7fff h 32 kbytes flash timing reserved for psram e0?8000 h e7?ffff h 480 kbytes mirrors psram program sram e0?0000 h e0?7fff h 32 kbytes maximum speed reserved for flash cd?0000 h df?ffff h <1.25 mbytes ? program flash 3 cc?0000 h cc?ffff h 64 kbytes ? program flash 2 c8?0000 h cb?ffff h 256 kbytes ? program flash 1 c4?0000 h c7?ffff h 256 kbytes ? program flash 0 c0?0000 h c3?ffff h 256 kbytes 2) external memory area 40?0000 h bf?ffff h 8 mbytes ? available ext. io area 3) 21?0000 h 3f?ffff h < 2 mbytes minus usic/can free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 37 v2.0, 2009-03 up to 32 kbytes of on-chip program sram (psram) are provided to store user code or data. the psram is accessed via the pmu and is optimized for code fetches. a section of the psram with programmable size can be write-protected. note: the actual size of the psram depends on the quoted device type. 16 kbytes of on-chip data sram (dsram) are used for storage of general user data. the dsram is accessed via a separate interface and is optimized for data access. 2 kbytes of on-chip dual-port ram (dpram) provide storage for user-defined variables, for the system stack, and for general purpose register ban ks. a register bank can consist of up to 16 word-wide (r0 to r15) and/or byte-wide (rl0, rh0, ?, rl7, rh7) general purpose registers (gprs). the upper 256 bytes of the dpram are directly bit addressable. when used by a gpr, any location in the dpram is bit addressable. reserved 20?c000 h 20?ffff h 16 kbytes ? multican/usic regs. 20?8000 h 20?bfff h 16 kbytes alternate location 4) reserved 20?6000 h 20?7fff h 8 kbytes ? usic registers 20?4000 h 20?5fff h 8 kbytes accessed via ebc multican registers 20?0000 h 20?3fff h 16 kbytes accessed via ebc external memory area 01?0000 h 1f?ffff h < 2 mbytes minus segment 0 sfr area 00?fe00 h 00?ffff h 0.5 kbyte ? dual-port ram 00?f600 h 00?fdff h 2 kbytes ? reserved for dpram 00?f200 h 00?f5ff h 1 kbyte ? esfr area 00?f000 h 00?f1ff h 0.5 kbyte ? xsfr area 00?e000 h 00?efff h 4 kbytes ? data sram 00?a000 h 00?dfff h 16 kbytes ? reserved for dsram 00?8000 h 00?9fff h 8 kbytes ? external memory area 00?0000 h 00?7fff h 32 kbytes ? 1) the areas marked with ? xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 38 v2.0, 2009-03 8 kbytes of on-chip stand-by sram (sbram) provide storage for system-relevant user data that must be preserved while the major part of the device is powered down. the sbram is accessed via a specific interface and is powered in domain m. 1024 bytes (2 512 bytes) of the address space are reserved for the special function register areas (sfr space and esfr space) . sfrs are word-wide registers which are used to control and monitor functions of the different on-chip units. unused sfr addresses are reserved for future members of the xc2000 family. in order to to ensure upward compatibility they should either not be accessed or written with zeros. in order to meet the requirements of designs where more memory is required than is available on chip, up to 12 mbytes (approximately, see table 6 ) of external ram and/or rom can be connected to the microcontroller. the external bus interface also provides access to external peripherals. the on-chip flash memory stores code, constant data, and control data. the on-chip flash memory consists of one 64-kbyte module (preferably for data storage) and modules with a maximum capacity of 256 kbyt es each. each module is organized in sectors of 4 kbytes. the uppermost 4-kbyte sector of segment 0 (located in flash module 0) is used internally to store operation control parameters and protection information. note: the actual size of the flash me mory depends on the chosen device type. each sector can be separately write protected 1) , erased and programmed (in blocks of 128 bytes). the complete flash area can be read-protected. a user-defined password sequence temporarily unlocks protected area s. the flash modules combine 128-bit read access with protected and efficient writing algorithms for programming and erasing. dynamic error correction provides extremely high read data security for all read access operations. access to different flash modules can be executed in parallel. for flash parameters, please see section 4.5 . memory content protection the contents of on-chip memories can be pr otected against soft errors (induced e.g. by radiation) by activating the parity mechanism or the error correction code (ecc). the parity mechanism can detect a single-bit error and prevent the software from using incorrect data or executing incorrect instructions. the ecc mechanism can detect and automatically correct single-bit errors. this supports the stable oper ation of the system. it is strongly recommended to activate the ecc mechanism wherever possible because this dramatically increases the robustness of an application against such soft errors. 1) to save control bits, sectors are clustered for protection purposes, they remain separate for programming/erasing. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 39 v2.0, 2009-03 3.2 external bus controller all external memory access operations are performed by a special on-chip external bus controller (ebc). the ebc also controls a ccess to resources connected to the on-chip lxbus (multican and the usic modules). the lxbus is an internal representation of the external bus that allows access to integrated peripherals and modules in the same way as to external components. the ebc can be programmed either to single chip mode, when no external memory is required, or to an external bus mode with the following selections 1) : ? address bus width with a range of 0 ? 24-bit ? data bus width 8-bit or 16-bit ? bus operation multiplexed or demultiplexed the bus interface uses port 10 and port 2 for addresses and data. in the demultiplexed bus modes, the lower addresses are output separately on port 0 and port 1. the number of active segment address lines is selectabl e, restricting the external address space to 8 mbytes ? 64 kbytes. this is required when interface lines shall be assigned to port 2. external cs signals (address windows plus default) can be generated and output on port 4 in order to save external glue logic. external modules can be directly connected to the common address/data bus and their individual select lines. important timing characteristics of the external bus interface are programmable (with registers tconcsx/fconcsx) to allow the user to adapt it to a wide range of different types of memories and external peripherals. access to very slow memories or modules with varying access times is supported by a special ?ready? function. the ac tive level of the control input signal is selectable. in addition, up to four independent address windows may be defined (using registers addrselx) to control access to resources with different bus characteristics. these address windows are arranged hierarchically where window 4 overrides window 3, and window 2 overrides window 1. all accesses to locations not covered by these four address windows are controlled by tconcs0/fconcs0. the currently active window can generate a chip select signal. the external bus timing is based on the rising edge of the reference clock output clkout. the external bus protocol is compat ible with that of the standard c166 family. 1) bus modes are switched dynamically if several address windows with different mode settings are used. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 40 v2.0, 2009-03 3.3 central processing unit (cpu) the core of the cpu consists of a 5-stage execution pipeline with a 2-stage instruction- fetch pipeline, a 16-bit arithmetic and logic unit (alu), a 32-bit/40-bit multiply and accumulate unit (mac), a register-file providing three register banks, and dedicated sfrs. the alu features a multiply-and-divide unit, a bit-mask generator, and a barrel shifter. figure 4 cpu block diagram dpram cpu ipip rf r0 r1 gprs r14 r15 r0 r1 gprs r14 r15 ifu injection/ exception handler adu mac mca04917_x.vsd cpucon1 cpucon2 csp ip return stack fifo branch unit prefetch unit vecseg tfr +/- idx0 idx1 qx0 qx1 qr0 qr1 dpp0 dpp1 dpp2 dpp3 spseg sp stkov stkun +/- mrw mcw msw mal +/- mah multiply unit alu division unit multiply unit bit-mask-gen. barrel-shifter +/- mdc psw mdh zeros mdl ones r0 r1 gprs r14 r15 cp wb buffer 2-stage prefetch pipeline 5-stage pipeline r0 r1 gprs r14 r15 pmu dmu dsram ebc peripherals psram flash/rom free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 41 v2.0, 2009-03 with this hardware most xc236xa instructions can be executed in a single machine cycle of 12.5 ns with an 80-mhz cpu clock. for example, shift and rotate instructions are always processed during one machine cycle, no matter how many bits are shifted. also, multiplication and most mac instructions execute in one cycle. all multiple-cycle instructions have been optimized so that they can be executed very fast; for example, a 32-/16-bit division is started within 4 cycles while the remaining cycles are executed in the background. another pipeline optimization, the branch target prediction, eliminates the execution time of branch instructions if the prediction was correct. the cpu has a register context consisting of up to three register banks with 16 word- wide gprs each at its disposal. one of these register banks is physically allocated within the on-chip dpram area. a context pointer (cp) register determines the base address of the active register bank accessed by t he cpu at any time. the number of these register bank copies is only restricted by the available internal ram space. for easy parameter passing, a register bank may overlap others. a system stack of up to 32 kwords is prov ided for storage of temporary data. the system stack can be allocated to any location within the address space (preferably in the on-chip ram area); it is accessed by the cpu with the stack pointer (sp) register. two separate sfrs, stkov and stkun, are implicitly compared with the stack pointer value during each stack access to detect stack overflow or underflow. the high performance of the cpu hardware implementation can be best utilized by the programmer with the highly efficient xc236xa instruction set. this includes the following instruction classes: ? standard arithmetic instructions ? dsp-oriented arithmetic instructions ? logical instructions ? boolean bit manipulation instructions ? compare and loop control instructions ? shift and rotate instructions ? prioritize instruction ? data movement instructions ? system stack instructions ? jump and call instructions ? return instructions ? system control instructions ? miscellaneous instructions the basic instruction length is either 2 or 4 bytes. possible operand types are bits, bytes and words. a variety of direct, indirect or immediate addressing modes are provided to specify the required operands. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 42 v2.0, 2009-03 3.4 memory protection unit (mpu) the xc236xa?s memory protection unit (mpu) protects user-specified memory areas from unauthorized read, write, or instruct ion fetch accesses. the mpu can protect the whole address space including the peripheral area. this completes establisched mechanisms such as the register security mechanism or stack overrun/underrun detection. four protection levels support flexible system programming where operating system, low level drivers, and applications run on s eparate levels. each protection level permits different access restrictions for instructions and/or data. every access is checked (if the mpu is enabled) and an access violating the permission rules will be marked as invalid and leads to a protection trap. a set of protection registers for each protection level specifies the address ranges and the access permissions. applications requiring more than 4 protection levels can dynamically re-program the protection registers. 3.5 memory checker module (mchk) the xc236xa?s memory checker module calculates a checksum (fractional polynomial division) on a block of data, often called cyclic redundancy code (crc). it is based on a 32-bit linear feedback shift register and may, therefore, also be used to generate pseudo-random numbers. the memory checker module is a 16-bit paral lel input signature compression circuitry which enables error detection within a block of data stored in memory, registers, or communicated e.g. via serial communicatio n lines. it reduces the probability of error masking due to repeated error patterns by calculating the signature of blocks of data. the polynomial used for operation is configurable, so most of the commonly used polynomials may be used. also, the block size for generating a crc result is configurable via a local counter. an interrupt may be generated if testing the current data block reveals an error. an autonomous crc compare circuitry is included to enable redundant error detection, e.g. to enable higher safety integrity levels. the memory checker module provides enhanced fault detection (beyond parity or ecc) for data and instructions in volatile and non volatile memories. this is especially important for the safety and reliability of embedded systems. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 43 v2.0, 2009-03 3.6 interrupt system with a minimum interrupt response time of 7/11 1) cpu clocks (in the case of internal program execution), the xc236xa can reac t quickly to the occurrence of non- deterministic events. the architecture of the xc236xa supports se veral mechanisms for fast and flexible response to service requests; these can be generated from various sources internal or external to the microcontroller. any of these interrupt requests can be programmed to be serviced by the interrupt controller or by the peripheral event controller (pec). where in a standard interrupt service the current program execution is suspended and a branch to the interrupt vector table is per formed, just one cycle is ?stolen? from the current cpu activity to perform a pec service. a pec service implies a single byte or word data transfer between any two memory locations with an additional increment of either the pec source pointer, the destination pointer, or both. an individual pec transfer counter is implicitly decremented for each pec service except when performing in the continuous transfer mode. when this counter reaches zero, a standard interrupt is performed to the corresponding source-related vector location. pec services are particularly well suited to supp orting the transmission or reception of blocks of data. the xc236xa has eight pec channels, each whith fast interrupt-driven data transfer capabilities. each of the possible interrupt nodes has a separate control register containing an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield. each node can be programmed by its related register to one of sixteen interrupt priority levels. once accepted by the cpu, an interrupt service can only be interrupted by a higher-priority service request. for standard interrupt processing, each possible interrupt node has a dedicated vector location. fast external interrupt inputs can service external interrupts with high-precision requirements. these fast interrupt inputs feature programmable edge detection (rising edge, falling edge, or both edges). software interrupts are supported by the ?trap? instruction in combination with an individual trap (interrupt) number. table 7 shows all of the possible xc236xa interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. note: interrupt nodes which are not assigned to peripherals (unassigned nodes) may be used to generate software-controlled interrupt requests by setting the respective interrupt request bit (xir). 1) depending if the jump cache is used or not. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 44 v2.0, 2009-03 table 7 xc236xa interrupt nodes source of interrupt or pec service request control register vector location 1) trap number capcom register 16 cc2_cc16ic xx?0040 h 10 h / 16 d capcom register 17 cc2_cc17ic xx?0044 h 11 h / 17 d capcom register 18 cc2_cc18ic xx?0048 h 12 h / 18 d capcom register 19 cc2_cc19ic xx?004c h 13 h / 19 d capcom register 20, or usic0 channel 0, request 3 cc2_cc20ic xx?0050 h 14 h / 20 d capcom register 21, or usic0 channel 1, request 3 cc2_cc21ic xx?0054 h 15 h / 21 d capcom register 22, or usic1 channel 0, request 3 cc2_cc22ic xx?0058 h 16 h / 22 d capcom register 23, or usic1 channel 1, request 3 cc2_cc23ic xx?005c h 17 h / 23 d capcom register 24 cc2_cc24ic xx?0060 h 18 h / 24 d capcom register 25 cc2_cc25ic xx?0064 h 19 h / 25 d capcom register 26 cc2_cc26ic xx?0068 h 1a h / 26 d capcom register 27 cc2_cc27ic xx?006c h 1b h / 27 d capcom register 28, or usic2 channel 0, request 3 cc2_cc28ic xx?0070 h 1c h / 28 d capcom register 29, or usic2 channel 1, request 3 cc2_cc29ic xx?0074 h 1d h / 29 d capcom register 30, or scu request 2 cc2_cc30ic xx?0078 h 1e h / 30 d capcom register 31, or scu request 3 cc2_cc31ic xx?007c h 1f h / 31 d gpt1 timer 2 gpt12e_t2ic xx?0080 h 20 h / 32 d gpt1 timer 3 gpt12e_t3ic xx?0084 h 21 h / 33 d gpt1 timer 4 gpt12e_t4ic xx?0088 h 22 h / 34 d gpt2 timer 5 gpt12e_t5ic xx?008c h 23 h / 35 d gpt2 timer 6 gpt12e_t6ic xx?0090 h 24 h / 36 d gpt2 caprel register gpt12e_cric xx?0094 h 25 h / 37 d capcom timer 7 cc2_t7ic xx?0098 h 26 h / 38 d capcom timer 8 cc2_t8ic xx?009c h 27 h / 39 d free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 45 v2.0, 2009-03 a/d converter request 0 adc_0ic xx?00a0 h 28 h / 40 d a/d converter request 1 adc_1ic xx?00a4 h 29 h / 41 d a/d converter request 2 adc_2ic xx?00a8 h 2a h / 42 d a/d converter request 3 adc_3ic xx?00ac h 2b h / 43 d a/d converter request 4 adc_4ic xx?00b0 h 2c h / 44 d a/d converter request 5 adc_5ic xx?00b4 h 2d h / 45 d a/d converter request 6 adc_6ic xx?00b8 h 2e h / 46 d a/d converter request 7 adc_7ic xx?00bc h 2f h / 47 d ccu60 request 0 ccu60_0ic xx?00c0 h 30 h / 48 d ccu60 request 1 ccu60_1ic xx?00c4 h 31 h / 49 d ccu60 request 2 ccu60_2ic xx?00c8 h 32 h / 50 d ccu60 request 3 ccu60_3ic xx?00cc h 33 h / 51 d ccu61 request 0 ccu61_0ic xx?00d0 h 34 h / 52 d ccu61 request 1 ccu61_1ic xx?00d4 h 35 h / 53 d ccu61 request 2 ccu61_2ic xx?00d8 h 36 h / 54 d ccu61 request 3 ccu61_3ic xx?00dc h 37 h / 55 d xx?00e0 h 38 h / 56 d xx?00e4 h 39 h / 57 d xx?00e8 h 3a h / 58 d xx?00ec h 3b h / 59 d xx?00f0 h 3c h / 60 d xx?00f4 h 3d h / 61 d xx?00f8 h 3e h / 62 d xx?00fc h 3f h / 63 d can request 0 can_0ic xx?0100 h 40 h / 64 d can request 1 can_1ic xx?0104 h 41 h / 65 d can request 2 can_2ic xx?0108 h 42 h / 66 d can request 3 can_3ic xx?010c h 43 h / 67 d can request 4 can_4ic xx?0110 h 44 h / 68 d can request 5 can_5ic xx?0114 h 45 h / 69 d table 7 xc236xa interrupt nodes (cont?d) source of interrupt or pec service request control register vector location 1) trap number free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 46 v2.0, 2009-03 can request 6 can_6ic xx?0118 h 46 h / 70 d can request 7 can_7ic xx?011c h 47 h / 71 d can request 8 can_8ic xx?0120 h 48 h / 72 d can request 9 can_9ic xx?0124 h 49 h / 73 d can request 10 can_10ic xx?0128 h 4a h / 74 d can request 11 can_11ic xx?012c h 4b h / 75 d can request 12 can_12ic xx?0130 h 4c h / 76 d can request 13 can_13ic xx?0134 h 4d h / 77 d can request 14 can_14ic xx?0138 h 4e h / 78 d can request 15 can_15ic xx?013c h 4f h / 79 d usic0 channel 0, request 0 u0c0_0ic xx?0140 h 50 h / 80 d usic0 channel 0, request 1 u0c0_1ic xx?0144 h 51 h / 81 d usic0 channel 0, request 2 u0c0_2ic xx?0148 h 52 h / 82 d usic0 channel 1, request 0 u0c1_0ic xx?014c h 53 h / 83 d usic0 channel 1, request 1 u0c1_1ic xx?0150 h 54 h / 84 d usic0 channel 1, request 2 u0c1_2ic xx?0154 h 55 h / 85 d usic1 channel 0, request 0 u1c0_0ic xx?0158 h 56 h / 86 d usic1 channel 0, request 1 u1c0_1ic xx?015c h 57 h / 87 d usic1 channel 0, request 2 u1c0_2ic xx?0160 h 58 h / 88 d usic1 channel 1, request 0 u1c1_0ic xx?0164 h 59 h / 89 d usic1 channel 1, request 1 u1c1_1ic xx?0168 h 5a h / 90 d usic1 channel 1, request 2 u1c1_2ic xx?016c h 5b h / 91 d usic2 channel 0, request 0 u2c0_0ic xx?0170 h 5c h / 92 d usic2 channel 0, request 1 u2c0_1ic xx?0174 h 5d h / 93 d usic2 channel 0, request 2 u2c0_2ic xx?0178 h 5e h / 94 d usic2 channel 1, request 0 u2c1_0ic xx?017c h 5f h / 95 d usic2 channel 1, request 1 u2c1_1ic xx?0180 h 60 h / 96 d usic2 channel 1, request 2 u2c1_2ic xx?0184 h 61 h / 97 d xx?0188 h 62 h / 98 d xx?018c h 63 h / 99 d table 7 xc236xa interrupt nodes (cont?d) source of interrupt or pec service request control register vector location 1) trap number free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 47 v2.0, 2009-03 note: vector locations without an associated interrupt control register are not assigned and are reserved. xx?0190 h 64 h / 100 d xx?0194 h 65 h / 101 d xx?0198 h 66 h / 102 d xx?019c h 67 h / 103 d scu external request 0 scu_eru_0ic xx?01a0 h 68 h / 104 d scu external request 1 scu_eru_1ic xx?01a4 h 69 h / 105 d scu external request 2 scu_eru_2ic xx?01a8 h 6a h / 106 d scu request 1 scu_1ic xx?01ac h 6b h / 107 d scu request 0 scu_0ic xx?01b0 h 6c h / 108 d scu external request 3 scu_eru_3ic xx?01b4 h 6d h / 109 d rtc rtc_ic xx?01b8 h 6e h / 110 d end of pec subchannel eopic xx?01bc h 6f h / 111 d 1) register vecseg defines the segment where the vector table is located. bitfield vecsc in register cpucon1 defines the distance between two adjacent vectors. this table represents the default setting with a distance of 4 (two words) between two vectors. table 7 xc236xa interrupt nodes (cont?d) source of interrupt or pec service request control register vector location 1) trap number free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 48 v2.0, 2009-03 the xc236xa includes an excellent mechanism to identify and process exceptions or error conditions that arise during run-time, the so-called ?hardware traps?. a hardware trap causes an immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). the occurrence of a hardware trap is also indicated by a single bit in the trap flag register (tfr). unless another higher- priority trap service is in progress, a hardware trap will interrupt any ongoing program execution. in turn, hardware trap services can normally not be interrupted by standard or pec interrupts. table 8 shows all possible exceptions or error conditions that can arise during runtime: table 8 trap summary exception condition trap flag trap vector vector location 1) 1) register vecseg defines the segment where the vector table is located to. bitfield vecsc in register cpucon1 defines the distance between two adjacent vectors. this table represents the default setting, with a distance of 4 (two words) between two vectors. trap number trap priority reset functions ? reset xx?0000 h 00 h iii class a hardware traps: ? system request 0 ? stack overflow ? stack underflow ? software break sr0 stkof stkuf softbrk sr0trap stotrap stutrap sbrktrap xx?0008 h xx?0010 h xx?0018 h xx?0020 h 02 h 04 h 06 h 08 h ii ii ii ii class b hardware traps: ? system request 1 ? memory protection ? undefined opcode ? memory access error ? protected instruction fault ? illegal word operand access sr1 mpr/w/x undopc acer prtflt illopa btrap btrap btrap btrap btrap btrap xx?0028 h xx?0028 h xx?0028 h xx?0028 h xx?0028 h xx?0028 h 0a h 0a h 0a h 0a h 0a h 0a h i i i i i i reserved ? ? [2c h - 3c h ][0b h - 0f h ] ? software traps: ? trap instruction ?? any [xx?0000 h - xx?01fc h ] in steps of 4 h any [00 h - 7f h ] current cpu priority free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 49 v2.0, 2009-03 3.7 on-chip debug support (ocds) the on-chip debug support system built into the xc236xa provides a broad range of debug and emulation features. user software running on the xc236xa can be debugged within the target system environment. the ocds is controlled by an external debugging device via the debug interface. this either consists of the 2-pin device access port (dap) or of the jtag port conforming to ieee-1149. the debug interface can be completed with an optional break interface. the debugger controls the ocds with a set of dedicated registers accessible via the debug interface (dap or jtag). in addition the ocds system can be controlled by the cpu, e.g. by a monitor program. an injection interface allows the execution of ocds- generated instructions by the cpu. multiple breakpoints can be triggered by on-chip hardware, by software, or by an external trigger input. single stepping is supported, as is the injection of arbitrary instructions and read/write access to the complete internal address space. a breakpoint trigger can be answered with a cpu halt, a monitor call, a data transfer, or/and the activation of an external signal. tracing data can be obtained via the debug interf ace, or via the external bus interface for increased performance. the dap interface uses two interface signals , the jtag interface uses four interface signals, to communicate with external circuitry. the debug interface can be amended with two optional break lines. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 50 v2.0, 2009-03 3.8 capture/compare unit (capcom2) the capcom2 unit supports generation an d control of timing sequences on up to 16 channels with a maximum resolution of one system clock cycle (eight cycles in staggered mode). the capcom2 unit is typically used to handle high-speed i/o tasks such as pulse and waveform generation, pulse width modulation (pwm), digital to analog (d/a) conversion, software timing, or time recording with respect to external events. two 16-bit timers (t7/t8) with reload registers provide two independent time bases for the capture/compare register array. the input clock for the timers is programmable to a number of prescaled values of the internal system clock. it may also be deri ved from an over flow/underflow of timer t6 in module gpt2. this provides a wide range for the timer period and resolution while allowing precise adjustments for application- specific requirements. an external count input for capcom2 timer t7 allows event scheduling for the capture/compare registers with respect to external events. the capture/compare register array contains 16 dual purpose capture/compare registers. each may be individually allocated to either capcom2 timer t7 or t8 and programmed for a capture or compare function. each register of the capcom2 module has one port pin associated with it.a port pin is associated with 12 registers of the capcom2 module. this serves as an input pin to trigger the capture function or as an output pin to indicate the occurrence of a compare event. table 9 compare modes (capcom2) compare modes function mode 0 interrupt-only compare mode; several compare interrupts per timer period are possible mode 1 pin toggles on each compare match; several compare events per timer period are possible mode 2 interrupt-only compare mode; only one compare interrupt per timer period is generated mode 3 pin set ?1? on match; pin reset ?0? on compare timer overflow; only one compare event per timer period is generated double register mode two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible single event mode generates single edges or pulses; can be used with any compare mode free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 51 v2.0, 2009-03 when a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (?captured?) into the capture/compare register in response to an external event at t he port pin associated with this register. in addition, a specific interrupt request for this capture/compare register is generated. either a positive, a negative, or both a pos itive and a negative external signal transition at the pin can be selected as the triggering event. the contents of all registers selected for one of the five compare modes are continuously compared with the contents of the allocated timers. when a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the compare mode selected. figure 5 capcom2 unit block diagram sixteen 16-bit capture/ compare registers mode control (capture or compare) t7 input control t8 input control mc_capcom2_blockdiag cc16irq cc31irq cc17irq t7irq t8irq cc16io cc17io t7in t6ouf f cc t6ouf f cc reload reg. t7rel timer t7 timer t8 reload reg. t8rel cc31io free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 52 v2.0, 2009-03 3.9 capture/compare units ccu6x the xc236xa types feature several ccu6 units (ccu60, ccu61). the ccu6 is a high-resolution capture and compare unit with application-specific modes. it provides inputs to start the timers synchronously, an important feature in devices with several ccu6 modules. the module provides two independent timers (t12, t13), that can be used for pwm generation, especially for ac motor control. ad ditionally, special c ontrol modes for block commutation and multi-phase machines are supported. timer 12 features ? three capture/compare channels, where each channel can be used either as a capture or as a compare channel. ? supports generation of a three-phase pwm (six outputs, individual signals for high- side and low-side switches) ? 16-bit resolution, maximum count frequency = peripheral clock ? dead-time control for each channel to avoid short circuits in the power stage ? concurrent update of the required t12/13 registers ? center-aligned and edge-aligned pwm can be generated ? single-shot mode supported ? many interrupt request sources ? hysteresis-like control mode ? automatic start on a hw event (t12hr, for synchronization purposes) timer 13 features ? one independent compare channel with one output ? 16-bit resolution, maximum count frequency = peripheral clock ? can be synchronized to t12 ? interrupt generation at period match and compare match ? single-shot mode supported ? automatic start on a hw event (t13hr, for synchronization purposes) additional features ? block commutation for brushless dc drives implemented ? position detection via hall sensor pattern ? automatic rotational speed measurement for block commutation ? integrated error handling ? fast emergency stop without cpu load via external signal (ctrap ) ? control modes for multi-channel ac drives ? output levels can be selected and adapted to the power stage free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 53 v2.0, 2009-03 figure 6 mod_name block diagram timer t12 can work in capture and/or compare mode for its three channels. the modes can also be combined. timer t13 can work in compare mode only. the multi-channel control unit generates output patterns that c an be modulated by timer t12 and/or timer t13. the modulation sources can be selected and combined for signal modulation. mc_ccu6_blockdiagram. vsd channel 0 channel 1 channel 2 t12 dead- time control input / output control cc62 cout62 cc61 cout61 cc60 cout60 cout63 ctrap channel 3 t13 ccpos0 1 1 1 2 2 2 1 start compare capt ure 3 multi- channel control trap control com pare compa re compa re compa re 1 t rap i nput ccpos1 ccpos2 output select output select 3 hal l i nput ccu6 module kernel f sys interrupts txhr free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 54 v2.0, 2009-03 3.10 general purpose timer (gpt12e) unit the gpt12e unit is a very flexible multifun ctional timer/counter structure which can be used for many different timing tasks such as event timing and counting, pulse width and duty cycle measurements, pulse gener ation, or pulse multiplication. the gpt12e unit incorporates five 16-bit timers organized in two separate modules, gpt1 and gpt2. each timer in each module may either operate independently in a number of different modes or be concatenated with another timer of the same module. each of the three timers t2, t3, t4 of module gpt1 can be configured individually for one of four basic modes of operation: timer, gated timer, counter, and incremental interface mode. in timer mode, the input clock for a timer is derived from the system clock and divided by a programmable prescaler. counter mode allows timer clocking in reference to external events. pulse width or duty cycle measurement is supported in gated timer mode, where the operation of a timer is controlled by the ?gat e? level on an external input pin. for these purposes each timer has one associated port pi n (txin) which serves as a gate or clock input. the maximum resolution of the timers in module gpt1 is 4 system clock cycles. the counting direction (up/down) for each timer can be programmed by software or altered dynamically by an external signal on a port pin (txeud), e.g. to facilitate position tracking. in incremental interface mode the gpt1 timers can be directly connected to the incremental position sensor signals a and b through their respective inputs txin and txeud. direction and counting signals are internally derived from these two input signals, so that the contents of the respective timer tx corresponds to the sensor position. the third position sensor signal to p0 can be connected to an interrupt input. timer t3 has an output toggle latch (t3otl ) which changes its state on each timer overflow/underflow. the state of this latch may be output on pin t3out e.g. for time out monitoring of external hardware components. it may also be used internally to clock timers t2 and t4 for measuring long time periods with high resolution. in addition to the basic operating modes, t2 and t4 may be configured as reload or capture register for timer t3. a timer used as capture or reload register is stopped. the contents of timer t3 is captured into t2 or t4 in response to a signal at the associated input pin (txin). timer t3 is reloaded with the contents of t2 or t4, triggered either by an external signal or a selectable state transition of its toggle latch t3otl. when both t2 and t4 are configured to alternately reload t3 on opposite state transitions of t3otl with the low and high times of a pwm signal, this signal can be continuously generated without software intervention. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 55 v2.0, 2009-03 figure 7 block diagram of gpt1 mc_gpt_block1 aux. timer t2 2 n :1 t2 mode control capture u/d basic clock f gpt t3con.bps1 t3otl t3out toggle latch t2in t2eud reload core timer t3 t3 mode control t3in t3eud u/d interrupt request (t3irq) t4 mode control u/d aux. timer t4 t4eud t4in reload capture interrupt request (t4irq) interrupt request (t2irq) free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 56 v2.0, 2009-03 with its maximum resolution of 2 system clock cycles, the gpt2 module provides precise event control and time measurement. it includes two timers (t5, t6) and a capture/reload register (caprel). both time rs can be clocked with an input clock which is derived from the cpu clock via a programmabl e prescaler or with external signals. the counting direction (up/down) for each timer can be programmed by software or altered dynamically with an external signal on a port pin (txeud 1) ). concatenation of the timers is supported with the output toggle latch (t6o tl) of timer t6, which changes its state on each timer overflow/underflow. the state of this latch may be used to clock timer t5, and/or it may be output on pin t6out. the overflows/underflows of timer t6 can also be used to clock the capcom2 timers and to initiate a reload from the caprel register. the caprel register can capture the contents of timer t5 based on an external signal transition on the corresponding port pin (capin); timer t5 may optionally be cleared after the capture procedure. this allows the xc236xa to measure absolute time differences or to perform pulse multiplication without software overhead. the capture trigger (timer t5 to caprel) can also be generated upon transitions of gpt1 timer t3 inputs t3in and/or t3eud. this is especially advantageous when t3 operates in incremental interface mode. 1) exception: t5eud is not connected to a pin. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 57 v2.0, 2009-03 figure 8 block diagram of gpt2 mc_gpt_block2 gpt2 timer t5 2 n :1 t5 mode control gpt2 caprel t3in/ t3eud caprel mode control t6 mode control reload clear u/d capture clear u/d t5in capin interrupt request (t5irq) interrupt request (t6irq) interrupt request (crirq) basic clock f gpt t6con.bps2 t6in gpt2 timer t6 t6otl t6out t6ouf toggle ff t6eud t5eud free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 58 v2.0, 2009-03 3.11 real time clock the real time clock (rtc) module of the xc236xa can be clocked with a clock signal selected from internal sources or external sources (pins). the rtc basically consists of a chain of divider blocks: ? selectable 32:1 and 8:1 dividers (on - off) ? the reloadable 16-bit timer t14 ? the 32-bit rtc timer block (accessible via registers rtch and rtcl) consisting of: ? a reloadable 10-bit timer ? a reloadable 6-bit timer ? a reloadable 6-bit timer ? a reloadable 10-bit timer all timers count up. each timer can generate an interrupt request. all requests are combined to a common node request. figure 9 rtc block diagram note: the registers associated with the rtc are only affected by a power reset. cnt-register rel-register 10 bits 6 bits 6 bits 10 bits t14 mcb05568b t14-register interrupt sub node rtcint mux 32 pre run cnt int3 cnt int2 cnt int1 cnt int0 f cnt f rtc t14rel 10 bits 6 bits 6 bits 10 bits : mux 8 : refclk free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 59 v2.0, 2009-03 the rtc module can be used for different purposes: ? system clock to determine the current time and date ? cyclic time-based interrupt, to provide a system time tick independent of cpu frequency and other resources ? 48-bit timer for long-term measurements ? alarm interrupt at a defined time free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 60 v2.0, 2009-03 3.12 a/d converters for analog signal measurement, up to two 10-bit a/d converters (adc0, adc1) with 11 + 5 multiplexed input channels and a sample and hold circuit have been integrated on-chip. 4 inputs can be converted by bot h a/d converters. conversions use the successive approximation method. the sample time (to charge the capacitors) and the conversion time are programmable so that they can be adjusted to the external circuit. the a/d converters can also operate in 8- bit conversion mode, further reducing the conversion time. several independent conversion result registers, selectable interrupt requests, and highly flexible conversion sequences prov ide a high degree of programmability to meet the application requirements. both modules can be synchronized to allow parallel sampling of two input channels. for applications that require more analog input channels, external analog multiplexers can be controlled automatically. for appl ications that require fewer analog input channels, the remaining channel inputs can be used as digital input port pins. the a/d converters of the xc236xa support two types of request sources which can be triggered by several internal and external events. ? parallel requests are activated at the same time and then executed in a predefined sequence. ? queued requests are executed in a user-defined sequence. in addition, the conversion of a specific channel can be inserted into a running sequence without disturbing that sequence. all requests are arbitrated according to the priority level assigned to them. data reduction features reduce the number of required cpu access operations allowing the precise evaluation of analog inputs (high conversion rate) even at a low cpu speed. result data can be reduced by limit checking or accumulation of results. the peripheral event controller (pec) can be used to control the a/d converters or to automatically store conversion results to a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. each a/d converter contains eight result registers which can be concatenated to build a result fifo. wait-for-read mode can be enabled for each result register to prevent the loss of conversion data. in order to decouple analog inputs from digi tal noise and to avoid input trigger noise, those pins used for analog input can be disc onnected from the digital input stages. this can be selected for each pin separately with the port x digital input disable registers. the auto-power-down feature of the a/d converters minimizes the power consumption when no conversion is in progress. broken wire detection for each channel and a multiplexer test mode provide information to verify the proper operation of the anal og signal sources (e.g. a sensor system). free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 61 v2.0, 2009-03 3.13 universal serial interface channel modules (usic) the xc236xa features several usic modules (usic0, usic1, usic2), each providing two serial communication channels. the universal serial interface channel (usic) module is based on a generic data shift and data storage structure which is identical for all supported serial communication protocols. each channel supports complete full-duplex operation with a basic data buffer structure (one transmit buffer and two receive buffer stages). in addition, the data handling software can use fifos. the protocol part (generation of shift clock/data/control signals) is independent of the general part and is handled by protocol-specific preprocessors (ppps). the usic?s input/output lines are connected to pins by a pin routing unit. the inputs and outputs of each usic channel can be assigned to different interface pins, providing great flexibility to the application software. all assignments can be made during runtime. figure 10 general structure of a usic module the regular structure of the usic module brings the following advantages: ? higher flexibility through configuration with same look-and-feel for data management ? reduced complexity for low-level drivers serving different protocols ? wide range of protocols with improved performances (baud rate, buffer handling) usic_basic.vsd bus interface dbu 0 dbu 1 control 0 control 1 dsu 0 dsu 1 ppp_a ppp_b ppp_c ppp_d ppp_a ppp_b ppp_c ppp_d pin routing shell buffer & shift structure protocol preprocessors pins bus f sys fractional dividers baud rate generators free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 62 v2.0, 2009-03 target protocols each usic channel can receive and transmit data frames with a selectable data word width from 1 to 16 bits in each of the following protocols: ? uart (asynchronous serial channel) ? module capability: maximum baud rate = f sys / 4 ? data frame length programmable from 1 to 63 bits ? msb or lsb first ? lin support (local interconnect network) ? module capability: maximum baud rate = f sys / 16 ? checksum generation under software control ? baud rate detection possible by built-in capture event of baud rate generator ? ssc/spi/qspi (synchronous serial channel with or without data buffer) ? module capability: maximum baud rate = f sys / 2, limited by loop delay ? number of data bits programmable from 1 to 63, more with explicit stop condition ? msb or lsb first ? optional control of slave select signals ? iic (inter-ic bus) ? supports baud rates of 100 kbit/s and 400 kbit/s ? iis (inter-ic sound bus) ? module capability: maximum baud rate = f sys / 2 note: depending on the selected functions (such as digital filters, input synchronization stages, sample point adjustment, etc.), the maximum achievable baud rate can be limited. please note that there may be additional delays, such as internal or external propagation delays and driver delays (e.g. for collision detection in uart mode, for iic, etc.). free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 63 v2.0, 2009-03 3.14 multican module the multican module contains independently operating can nodes with full-can functionality which are able to exchange data and remote frames using a gateway function. transmission and reception of can fr ames is handled in accordance with can specification v2.0 b (active). each can node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. all can nodes share a common set of message objects. each message object can be individually allocated to one of the can nodes. besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the can nodes or to set up a fifo buffer. note: the number of can nodes and message objects depends on the selected device type. the message objects are organized in double-chained linked lists, where each can node has its own list of message objects. a can node stores frames only into message objects that are allocated to its own mess age object list and it transmits only messages belonging to this message object list. a powerful, command-driven list controller performs all message object list operations. figure 11 block diagram of multican module mc_multican_block.vsd multican module kernel interrupt control f can port control can control message object buffer can node 0 linked list control clock control address decoder can node n txdcn rxdcn txdc0 rxdc0 ... ... ... free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 64 v2.0, 2009-03 multican features ? can functionality conforming to can spec ification v2.0 b active for each can node (compliant to iso 11898) ? independent can nodes ? set of independent message objects (shared by the can nodes) ? dedicated control registers for each can node ? data transfer rate up to 1 mbit/s, individually programmable for each node ? flexible and powerful message transfer control and error handling capabilities ? full-can functionality for message objects: ? can be assigned to one of the can nodes ? configurable as transmit or receive objects, or as message buffer fifo ? handle 11-bit or 29-bit identifiers with programmable acceptance mask for filtering ? remote monitoring mode, and frame counter for monitoring ? automatic gateway mode support ? 16 individually programmable interrupt nodes ? analyzer mode for can bus monitoring 3.15 system timer the system timer consists of a progra mmable prescaler and two concatenated timers (10 bits and 6 bits). both timers can generate interrupt requests. the clock source can be selected and the timers can also run during power reduction modes. therefore, the system timer enables the software to maintain the current time for scheduling functions or for the implementation of a clock. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 65 v2.0, 2009-03 3.16 watchdog timer the watchdog timer is one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. the watchdog timer is always enabled after an application reset of the chip. it can be disabled and enabled at any time by executing the instructions diswdt and enwdt respectively. the software has to service the watchdog timer before it overflows. if this is not the case because of a hardware or software failure, the watchdog timer overflows, generating a prewarning interrupt and then a reset request. the watchdog timer is a 16-bit timer clock ed with the system clock divided by 16,384 or 256. the watchdog timer register is set to a prespecified reload value (stored in wdtrel) in order to allow further variation of the monitored time interval. each time it is serviced by the application software, the watchdog timer is reloaded and the prescaler is cleared. time intervals between 3.2 s and 13.4 s can be monitored (@ 80 mhz). the default watchdog timer interval after power-up is 6.5 ms (@ 10 mhz). 3.17 clock generation the clock generation unit can generate the system clock signal f sys for the xc236xa from a number of external or internal clock sources: ? external clock signals with pad voltage or core voltage levels ? external crystal or resonator using the on-chip oscillator ? on-chip clock source for operation without crystal/resonator ? wake-up clock (ultra-low-power) to further reduce power consumption the programmable on-chip pll with multiple prescalers generates a clock signal for maximum system performance from standard cryst als, a clock input signal, or from the on-chip clock source. see also section 4.6.2 . the oscillator watchdog (owd) generates an interrupt if the crystal oscillator frequency falls below a certain limit or stops completely. in this case, the system can be supplied with an emergency clock to enable operation even after an external clock failure. all available clock signals can be output on one of two selectable pins. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 66 v2.0, 2009-03 3.18 parallel ports the xc236xa provides up to 76 i/o lines which are organized into 7 input/output ports and 2 input ports. all port lines are bit-addressable, and all input/output lines can be individually (bit-wise) configured via port contro l registers. this configuration selects the direction (input/output), push/pull or open-dr ain operation, activation of pull devices, and edge characteristics (shape) and driver characteristics (output current) of the port drivers. the i/o ports are true bidirectional ports which are switched to high impedance state when configured as inputs. during the internal reset, all port pins are configured as inputs without pull devices active. all port lines have alternate input or out put functions associated with them. these alternate functions can be programmed to be assigned to various port pins to support the best utilization for a given application. for th is reason, certain functions appear several times in table 10 . all port lines that are not used for alternat e functions may be used as general purpose i/o lines. table 10 summary of the xc236xa?s ports port width i/o connected modules p0 8 i/o ebc (a7...a0), ccu6, usic, can p1 8 i/o ebc (a15...a8), ccu6, usic p2 14 i/o ebc (ready, bhe , a23...a16, ad15...ad13, d15...d13), can, cc2, gpt12e, usic, dap/jtag p4 4 i/o ebc (cs 3 ...cs0 ), cc2, can, gpt12e, usic p5 11 i analog inputs, ccu6, dap/jtag, gpt12e, can p6 3 i/o adc, can, gpt12e p7 5 i/o can, gpt12e, scu, dap/jtag, ccu6, adc, usic p10 16 i/o ebc(ale, rd , wr , ad12...ad0, d12...d0), ccu6, usic, dap/jtag, can p15 5 i analog inputs, gpt12e free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 67 v2.0, 2009-03 3.19 instruction set summary table 11 lists the instructions of the xc236xa. the addressing modes that can be used with a specific instruction, the function of the instructions, parameters for conditional ex ecution of instructions, and the opcodes for each instruction can be found in the ?instruction set manual? . this document also provides a detailed description of each instruction. table 11 instruction set summary mnemonic description bytes add(b) add word (byte) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply direct gpr by direct gpr (16- 16-bit) 2 div(u) (un)signed divide register mdl by direct gpr (16-/16-bit) 2 divl(u) (un)signed long divide reg. md by direct gpr (32-/16-bit) 2 cpl(b) complement direct word (byte) gpr 2 neg(b) negate direct word (byte) gpr 2 and(b) bitwise and, (word/byte operands) 2 / 4 or(b) bitwise or, (word/byte operands) 2 / 4 xor(b) bitwise exclusive or, (word/byte operands) 2 / 4 bclr/bset clear/set direct bit 2 bmov(n) move (negated) direct bit to direct bit 4 band/bor/bxor and/or/xor direct bit with direct bit 4 bcmp compare direct bit to direct bit 4 bfldh/bfldl bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 cmp(b) compare word (byte) operands 2 / 4 cmpd1/2 compare word data to gpr and decrement gpr by 1/2 2 / 4 cmpi1/2 compare word data to gpr and increment gpr by 1/2 2 / 4 prior determine number of shift cycles to normalize direct word gpr and store result in direct word gpr 2 shl/shr shift left/right direct word gpr 2 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 68 v2.0, 2009-03 rol/ror rotate left/right direct word gpr 2 ashr arithmetic (sign bit) shift right direct word gpr 2 mov(b) move word (byte) data 2 / 4 movbs/z move byte operand to word op. with sign/zero extension 2 / 4 jmpa/i/r jump absolute/indirect/r elative if condition is met 4 jmps jump absolute to a code segment 4 jb(c) jump relative if direct bit is set (and clear bit) 4 jnb(s) jump relative if direct bit is not set (and set bit) 4 calla/i/r call absolute/indirect/relat ive subroutine if condition is met 4 calls call absolute subroutine in any code segment 4 pcall push direct word register onto system stack and call absolute subroutine 4 trap call interrupt service routine via immediate trap number 2 push/pop push/pop direct word register onto/from system stack 2 scxt push direct word register onto system stack and update register with word operand 4 ret(p) return from intra-segment subroutine (and pop direct word register from system stack) 2 rets return from inter-segment subroutine 2 reti return from interrupt service subroutine 2 sbrk software break 2 srst software reset 4 idle enter idle mode 4 pwrdn unused instruction 1) 4 srvwdt service watchdog timer 4 diswdt/enwdt disable/enable watchdog timer 4 einit end-of-initialization register lock 4 atomic begin atomic sequence 2 extr begin extended register sequence 2 extp(r) begin extended page (and register) sequence 2 / 4 exts(r) begin extended segment (and register) sequence 2 / 4 table 11 instruction set summary (cont?d) mnemonic description bytes free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line functional description data sheet 69 v2.0, 2009-03 nop null operation 2 comul/comac multiply (and accumulate) 4 coadd/cosub add/subtract 4 co(a)shr (arithmetic) shift right 4 coshl shift left 4 coload/store load accumulator/store mac register 4 cocmp compare 4 comax/min maximum/minimum 4 coabs/cornd absolute value/round accumulator 4 comov data move 4 coneg/nop negate accumulator/null operation 4 1) the enter power down mode instruction is not used in the xc236xa, due to the enhanced power control scheme. pwrdn will be correctly decoded, but will trigger no action. table 11 instruction set summary (cont?d) mnemonic description bytes free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 70 v2.0, 2009-03 4 electrical parameters the operating range for the xc236xa is defined by its electrical parameters. for proper operation the specified limits must be respected during system design 4.1 general parameters these parameters are valid for all subsequent descriptions, unless otherwise noted. note: stresses above the values listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other c onditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for an extended time may affect device reliability. during absolute maximum rating overload conditions ( v in > v ddp or v in < v ss ) the voltage on v ddp pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. table 12 absolute maximum rating parameters parameter symbol values unit note / test condition min. typ. max. storage temperature t st -65 ? 150 c ? junction temperature t j -40 ? 150 c under bias voltage on v ddi pins with respect to ground ( v ss ) v ddim , v ddi1 -0.5 ? 1.65 v ? voltage on v ddp pins with respect to ground ( v ss ) v ddpa , v ddpb -0.5 ? 6.0 v ? voltage on any pin with respect to ground ( v ss ) v in -0.5 ? v ddp + 0.5 v v in < v ddpmax 1) 1) one of these limits must be kept. keeping v in within the given limits avoids damage due to overload conditions. input current on any pin during overload condition ?-10?10ma 1) absolute sum of all input currents during overload condition ? ? ? |100| ma ? output current on any pin i oh , i ol ? ? |30| ma ? free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 71 v2.0, 2009-03 operating conditions the following operating conditions must not be exceeded to ensure correct operation of the xc236xa. all parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. note: typical parameter values refer to room temperature and nominal supply voltage, minimum/maximum parameter values also include conditions of minimum/maximum temperature and minimum/maximum supply voltage. additional details are described where applicable. table 13 operating condition parameters parameter symbol values unit note / test condition min. typ. max. digital core supply voltage v ddi 1.4 ? 1.6 v digital supply voltage for io pads and voltage regulators, upper voltage range v ddpa , v ddpb 4.5 5.0 5.5 v 1) digital supply voltage for io pads and voltage regulators, lower voltage range v ddpa , v ddpb 3.0 3.3 4.5 v 1) digital ground voltage v ss 0?0vreference voltage overload current i ov -5 ? 5 ma per io pin 2)3) -2 ? 5 ma per analog input pin 2)3) overload positive current coupling factor for analog inputs 4) k ova ?1.0 10 -6 1.0 10 -4 ? i ov > 0 3) overload negative current coupling factor for analog inputs 4) k ova ?2.5 10 -4 1.5 10 -3 ? i ov < 0 3) overload positive current coupling factor for digital i/o pins 4) k ovd ?1.0 10 -4 5.0 10 -3 ? i ov > 0 3) overload negative current coupling factor for digital i/o pins 4) k ovd ?1.0 10 -2 3.0 10 -2 ? i ov < 0 3) free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 72 v2.0, 2009-03 parameter interpretation the parameters listed in the following include both the characteristics of the xc236xa and its demands on the system. to aid in corr ectly interpreting the parameters when evaluating them for a design, they are marked accordingly in the column ?symbol?: absolute sum of overload currents |iov| ? ? 50 ma 3) external pin load capacitance c l ?20 5) ? pf pin drivers in default mode 6) voltage regulator buffer capacitance for dmp_m c evrm 1.0 ? 4.7 f 7) voltage regulator buffer capacitance for dmp_1 c evr1 0.47 ? 2.2 f one for each supply pin 7) operating frequency f sys ??80mhz 8) ambient temperature t a ???c 1) performance of pad drivers, a/d converter, and flash module depends on v ddp . 2) overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range: v ov > v ihmax ( i ov >0) or v ov < v ilmin ( i ov < 0). the absolute sum of input overload currents on all pins may not exceed 50 ma . the supply voltages must remain within the specified limits. proper operation under overload conditions depends on the application. overload conditions must not occur on pin xtal1 (powered by v ddim ). 3) not subject to production test - verified by design/characterization. 4) an overload current ( i ov ) through a pin injects an error current ( i inj ) into the adjacent pins. this error current adds to that pin?s leakage current ( i oz ). the value of the error current depends on the overload current and is defined by the overload coupling factor k ov . the polarity of the injected error current is reversed from the polarity of the overload current that produces it. the total current through a pin is | i tot | = | i oz | + (| i ov | k ov ). the additional error current may distort the input voltage on analog inputs. 5) this is the reference load. for bigger capacitive loads, use the derating factors from section 4.6.4 . 6) the timing is valid for pin drivers operating in default current mode (selected after reset). reducing the output current may lead to increased delays or reduced driving capability ( c l ). 7) to ensure the stability of the voltage regulators the evrs must be buffered with ceramic capacitors. separate buffer capacitors with the recomended values shall be connected as close as possible to each v ddi pin to keep the resistance of the board tracks below 2 . connect all v ddi1 pins together. the minimum capacitance value is required for proper operation under all conditions (e.g. temperature). higher values slightly increase the startup time. 8) the operating frequency range may be reduced for specific types of the xc236xa . this is indicated in the device designation ( fxxl). 80-mhz devices are marked f80l. table 13 operating condition parameters (cont?d) parameter symbol values unit note / test condition min. typ. max. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 73 v2.0, 2009-03 cc ( c ontroller c haracteristics): the logic of the xc236xa provides signals with the specified characteristics. sr ( s ystem r equirement): the external system must provide signals with the specified characteristics to the xc236xa. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 74 v2.0, 2009-03 4.2 dc parameters these parameters are static or average values that may be exceeded during switching transitions (e.g. output current). the xc236xa can operate within a wide supply voltage range from 3.0 v to 5.5 v. however, during operation this supply voltage must remain within 10 percent of the selected nominal supply voltage. it cannot vary across the full operating voltage range. because of the supply voltage restriction and because electrical behavior depends on the supply voltage, the parameters are specified separately for the upper and the lower voltage range. during operation, the supply voltages may only change with a maximum speed of dv/dt < 1 v/ms. leakage current is strongly dependent on the operating temperature and the voltage level at the respective pin. the maximum val ues in the following tables apply under worst case conditions, i.e. maximum temperature and an input level equal to the supply voltage. the value for the leakage current in an application can be determined by using the respective leakage derating formula (see t ables) with values from that application. the pads of the xc236xa are designed to o perate in various driver modes. the dc parameter specifications refer to the pad current limits specified in section 4.6.4 . free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 75 v2.0, 2009-03 pullup/pulldown device behavior most pins of the xc236xa feature pullup or pulldown devices. for some special pins these are fixed; for the port pins they can be selected by the application. the specified current values indicate how to load the respective pin depending on the intended signal level. figure 12 shows the current paths. the shaded resistors shown in the figure may be required to compensate system pull currents that do not match the given limit values. figure 12 pullup/pulldown current definition mc_xc2x_pull v ddp v ss pullup pulldown free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 76 v2.0, 2009-03 4.2.1 dc parameters for upper voltage area these parameters apply to the upper io voltage range, 4.5 v v ddp 5.5 v. note: operating conditions apply. keeping signal levels within the limits specified in this table ensures operation without overload conditions. for signal le vels outside these specifications, also refer to the specification of the overload current i ov . table 14 dc characteristics for upper voltage range parameter symbol values unit note / test condition min. typ. max. input low voltage (all except xtal1) v il sr -0.3 ? 0.3 v ddp v? input high voltage (all except xtal1) v ih sr 0.7 v ddp ? v ddp + 0.3 v? input hysteresis 1) hys cc 0.11 v ddp ??v v ddp in [v], series resistance = 0 output low voltage v ol cc ? ? 1.0 v i ol i olmax 2) output low voltage v ol cc ? ? 0.4 v i ol i olnom 2)3) output high voltage 4) v oh cc v ddp - 1.0 ??v i oh i ohmax 2) output high voltage 4) v oh cc v ddp - 0.4 ??v i oh i ohnom 2)3) input leakage current (port 5, port 15) 5) i oz1 cc ? 10 200 na 0 v < v in < v ddp input leakage current (all other) 5)6) i oz2 cc ? 0.2 5 a t j 110c, 0.45 v < v in < v ddp input leakage current (all other) 5)6) i oz2 cc ? 0.2 15 a t j 150c, 0.45 v < v in < v ddp pull level keep current i plk ?? 30 a v pin v ih (up) 7) v pin v il (dn) pull level force current i plf 250 ? ? a v pin v il (up) 7) v pin v ih (dn) pin capacitance 8) (digital inputs/outputs) c io cc ? ? 10 pf free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 77 v2.0, 2009-03 1) not subject to production test - verified by design /characterization. hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cannot suppress switching due to external system noise under all conditions. 2) the maximum deliverable output current of a port driver depends on the selected output driver mode, see section 4.6.4 . the limit for pin groups must be respected. 3) as a rule, with decreasing output current the output levels approach the respective supply level ( v ol v ss , v oh v ddp ). however, only the levels for nominal output currents are verified. 4) this specification is not valid for outputs which are switched to open drain mode. in this case the respective output will float and the voltage is determined by the external circuit. 5) an additional error current ( i inj ) will flow if an overload current flows through an adjacent pin. please refer to the definition of the overload coupling factor k ov . 6) the given values are worst-case values. in production test, this leakage current is only tested at 125c; other values are ensured by correlation. for derating, please refer to the following descriptions: leakage derating depending on temperature ( t j = junction temperature [c]): i oz = 0.05 e (1.5 + 0.028tj) [ a]. for example, at a temperature of 95c the resulting leakage current is 3.2 a. leakage derating depending on voltage level (dv = v ddp - v pin [v]): i oz = i oztempmax - (1.6 dv) [ a] this voltage derating formula is an approximation which applies for maximum temperature. because pin p2.8 is connected to two pads (standard pad and high-speed clock pad), it has twice the normal leakage. 7) keep current: limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: v pin v ih for a pullup; v pin v il for a pulldown. force current: drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: v pin v il for a pullup; v pin v ih for a pulldown. these values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose io pins. 8) not subject to production test - verified by design/characterization. because pin p2.8 is connected to two pads (standard pad and high-speed clock pad), it has twice the normal capacitance. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 78 v2.0, 2009-03 4.2.2 dc parameters for lower voltage area these parameters apply to the lower io voltage range, 3.0 v v ddp 4.5 v. note: operating conditions apply. keeping signal levels within the limits specified in this table ensures operation without overload conditions. for signal le vels outside these specifications, also refer to the specification of the overload current i ov . table 15 dc characteristics for lower voltage range parameter symbol values unit note / test condition min. typ. max. input low voltage (all except xtal1) v il sr -0.3 ? 0.3 v ddp v? input high voltage (all except xtal1) v ih sr 0.7 v ddp ? v ddp + 0.3 v? input hysteresis 1) hys cc 0.07 v ddp ??v v ddp in [v], series resistance = 0 output low voltage v ol cc ? ? 1.0 v i ol i olmax 2) output low voltage v ol cc ? ? 0.4 v i ol i olnom 2)3) output high voltage 4) v oh cc v ddp - 1.0 ??v i oh i ohmax 2) output high voltage 4) v oh cc v ddp - 0.4 ??v i oh i ohnom 2)3) input leakage current (port 5, port 15) 5) i oz1 cc ? 10 200 na 0 v < v in < v ddp input leakage current (all other) 5)6) i oz2 cc ? 0.2 2.5 a t j 110c, 0.45 v < v in < v ddp input leakage current (all other) 5)6) i oz2 cc ? 0.2 8 a t j 150c, 0.45 v < v in < v ddp pull level keep current i plk ?? 10 a v pin v ih (up) 7) v pin v il (dn) pull level force current i plf 150 ? ? a v pin v il (up) 7) v pin v ih (dn) pin capacitance 8) (digital inputs/outputs) c io cc ? ? 10 pf free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 79 v2.0, 2009-03 1) not subject to production test - verified by design /characterization. hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cannot suppress switching due to external system noise under all conditions. 2) the maximum deliverable output current of a port driver depends on the selected output driver mode, see section 4.6.4 . the limit for pin groups must be respected. 3) as a rule, with decreasing output current the output levels approach the respective supply level ( v ol v ss , v oh v ddp ). however, only the levels for nominal output currents are verified. 4) this specification is not valid for outputs which are switched to open drain mode. in this case the respective output will float and the voltage is determined by the external circuit. 5) an additional error current ( i inj ) will flow if an overload current flows through an adjacent pin. please refer to the definition of the overload coupling factor k ov . the leakage current value is not tested in the lower voltage range but only in the upper voltage range. this parameter is ensured by correlation. 6) the given values are worst-case values. in production test, this leakage current is only tested at 125c; other values are ensured by correlation. for derating, please refer to the following descriptions: leakage derating depending on temperature ( t j = junction temperature [c]): i oz = 0.03 e (1.35 + 0.028tj) [ a]. for example, at a temperature of 95c the resulting leakage current is 1.65 a. leakage derating depending on voltage level (dv = v ddp - v pin [v]): i oz = i oztempmax - (1.3 dv) [ a] this voltage derating formula is an approximation which applies for maximum temperature. because pin p2.8 is connected to two pads (standard pad and high-speed clock pad), it has twice the normal leakage. 7) keep current: limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: v pin v ih for a pullup; v pin v il for a pulldown. force current: drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: v pin v il for a pullup; v pin v ih for a pulldown. these values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose io pins. 8) not subject to production test - verified by design/characterization. because pin p2.8 is connected to two pads (standard pad and high-speed clock pad), it has twice the normal capacitance. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 80 v2.0, 2009-03 4.2.3 power consumption the power consumed by the xc236xa depends on several factors such as supply voltage, operating frequency, active circuits, and operating temperature. the power consumption specified here c onsists of two components: ? the switching current i s depends on the device activity ? the leakage current i lk depends on the device temperature to determine the actual power consumption, always both components, switching current i s ( table 16 ) and leakage current i lk ( table 17 ) must be added: i ddp = i s + i lk . note: the power consumption values are not subject to production test. they are verified by design/characterization. to determine the total power consumption for dimensioning the external power supply, also the pad driver currents must be considered. the given power consumption parameters and their values refer to specific operating conditions: ? active mode : regular operation, i.e. peripherals ar e active, code execution out of flash. ? stopover mode : crystal oscillator and pll stopped, flash switched off, clock in domain dmp_1 stopped. note: the maximum values cover the complete specified operating range of all manufactured devices. the typical values refer to average devices under typical conditions, such as nominal supply voltage, room temperature, application-oriented activity. after a power reset, the decoupling capacitors for v ddi are charged with the maximum possible current. for additional information, please refer to section 5.2 , thermal considerations . note: operating conditions apply. table 16 switching power consumption xc236xa parameter sym- bol values unit note / test condition min. typ. max. power supply current (active) with all peripherals active and evvrs on i sact ? 10 + 0.6 f sys 10 + 1.0 f sys ma active mode 1)2)3) f sys in [mhz] power supply current in stopover mode, evvrs on i sso ? 0.7 2.0 ma stopover mode 3) free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 81 v2.0, 2009-03 active mode power supply current the actual power supply current in active mode not only depends on the system frequency but also on the configuration of the xc236xa?s subsystem. besides the power consumed by the device logic ( table 16 ) the power supply pins also provide the current that flows through the pin output drivers. a small current is consumed because the drivers? input stages are switched. the io power domains can be supplied separately. power domain a ( v ddpa ) supplies the a/d converters and port 6. power domain b ( v ddpb ) supplies the on-chip evvrs and all other ports. during operation domain a draws a maximum current of 1.5 ma for each active a/d converter module from v ddpa . in fast startup mode (with the flash modules deactivated), the typical current is reduced to 3 + 0.6 f sys ma. 1)the pad supply voltage pins ( v ddpb ) provide the input current for the on-chip evvrs and the current consumed by the pin output drivers. a small current is consumed because the drivers? input stages are switched. 2) please consider the additional conditions described in section ?active mode power supply current?. 3) the pad supply voltage has only a minor influence on this parameter. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 82 v2.0, 2009-03 figure 13 supply current in active mo de as a function of frequency note: operating conditions apply. mc_xc2xm_is f sys [mhz] i s [ma] 10 20 40 20 40 80 60 50 60 70 90 100 i sacttyp i sactmax 30 80 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 83 v2.0, 2009-03 note: a fraction of the leakage current flows through domain dmp_a (pin v ddpa ). this current can be calculated as 7,000 e - , with = 5000 / (273 + 1.3 t j ). for t j = 150c, this results in a current of 160 a. table 17 leakage power consumption xc236xa parameter sym- bol values unit note / test condition 1) 1) all inputs (including pins configured as inputs) are set at 0 v to 0.1 v or at v ddp - 0.1 v to v ddp and all outputs (including pins configured as outputs) are disconnected. min. typ. max. leakage supply current 2) formula 3) : 600,000 e - ; = 5000 / (273 + b t j ); typ.: b = 1.0, max.: b = 1.3 2) the supply current caused by leakage depends mainly on the junction temperature (see figure 14 ) and the supply voltage. the temperature difference between the junction temperature t j and the ambient temperature t a must be taken into account. as this fraction of the supply current does not depend on device activity, it must be added to other power consumption values. 3) this formula is valid for temperatures above 0c. for temperatures below 0c a value of below 10 a can be assumed. i lk1 ? 0.030.05ma t j = 25c ?0.51.3ma t j = 85c ?2.16.2ma t j = 125c ? 4.4 13.7 ma t j = 150c free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 84 v2.0, 2009-03 figure 14 leakage supply current as a function of temperature mc_xy_ilkn t j [c] i lk [ma] 2 6 10 0 50 150 100 -50 4 8 12 14 i lk1max i lk1typ 125 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 85 v2.0, 2009-03 4.3 analog/digital converter parameters these parameters describe the conditions for optimum adc performance. note: operating conditions apply. table 18 a/d converter characteristics parameter symbol limit values unit test condition min. typ. max. analog reference supply v aref sr v agnd + 1.0 ? v ddpa + 0.05 v 1) analog reference ground v agnd sr v ss - 0.05 ?1.5v? analog input voltage range v ain sr v agnd ? v aref v 2) analog clock frequency f adci 0.5 ? 20 mhz upper voltage area 3) 0.5 ? 16.5 mhz lower voltage area 3) conversion time for 10-bit result 4) t c10 cc (13 + stc) t adci + 2 t sys ?? conversion time for 8-bit result 4) t c8 cc (11 + stc) t adci + 2 t sys ?? wakeup time from analog powerdown, fast mode t waf cc??4 s? wakeup time from analog powerdown, slow mode t was cc??15 s? broken wire detection delay against v agnd t bwg cc??50 5) result below 10% (66 h ) broken wire detection delay against v aref t bwr cc??50 6) result above 80% (332 h ) total unadjusted error 7) tue cc ? 1 2lsb v aref = 5.0 v 1) dnl error ea dnl cc ? 0.8 1lsb inl error ea inl cc ? 0.8 1.2 lsb gain error ea gain cc ? 0.4 0.8 lsb offset error ea off cc ? 0.5 0.8 lsb free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 86 v2.0, 2009-03 total capacitance of an analog input c aint cc??10pf 8)9) switched capacitance of an analog input c ains cc??4pf 8)9) resistance of the analog input path r ain cc??2k 8)9) total capacitance of the reference input c areft cc ??15pf 8)9) switched capacitance of the reference input c arefs cc ??7pf 8)9) resistance of the reference input path r aref cc??2k 8)9) 1) tue is tested at v arefx = v ddpa , v agnd = 0 v. it is verified by design for all other voltages within the defined voltage range. the specified tue is valid only if the absolute sum of input overload currents on port 5 or port 15 pins (see i ov specification) does not exceed 10 ma, and if v aref and v agnd remain stable during the measurement time. 2) v ain may exceed v agnd or v arefx up to the absolute maximum ratings. ho wever, the conversion result in these cases will be x000 h or x3ff h , respectively. 3) the limit values for f adci must not be exceeded when selecting the peripheral frequency and the prescaler setting. 4) this parameter includes the sample time (also the additional sample time specified by stc), the time to determine the digital result and the time to load the result register with the conversion result. values for the basic clock t adci depend on programming and are found in table 19 . 5) the broken wire detection delay against v agnd is measured in numbers of co nsecutive precharge cycles at a conversion rate of not more than 500 s. 6) the broken wire detection delay against v aref is measured in numbers of co nsecutive precharge cycles at a conversion rate of not more than 10 s. this function is influenced by leakage current, in particular at high temperature. 7) the total unadjusted error tue is the maximum deviation from the ideal adc transfer curve, not the sum of individual errors. all error specifications are based on measurement methods standardized by ieee 1241.2000. 8) not subject to production test - verified by design/characterization. 9) these parameter values cover the complete operating range. under relaxed operating conditions (temperature, supply voltage) typical values can be used for calculation. at room temperature and nominal supply voltage the following typical values can be used: c ainttyp = 12 pf, c ainstyp = 5 pf, r aintyp = 1.0 k , c arefttyp = 15 pf, c arefstyp = 10 pf, r areftyp = 1.0 k . table 18 a/d converter characteristics (cont?d) parameter symbol limit values unit test condition min. typ. max. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 87 v2.0, 2009-03 figure 15 equivalent circuitry for analog inputs a/d converter mcs05570 r source v ain c ext c aint c ains - r ain, on c ains free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 88 v2.0, 2009-03 sample time and conversion time of the xc236xa?s a/d converters are programmable. the timing above can be calculated using table 19 . the limit values for f adci must not be exceeded when selecting the prescaler value. converter timing example a: converter timing example b: table 19 a/d converter computation table globctr.5-0 (diva) a/d converter analog clock f adci inpcrx.7-0 (stc) sample time 1) t s 1) the selected sample time is doubled if broken wire detection is active (due to the presampling phase). 000000 b f sys 00 h t adci 2 000001 b f sys / 2 01 h t adci 3 000010 b f sys / 3 02 h t adci 4 : f sys / (diva+1) : t adci (stc+2) 111110 b f sys / 63 fe h t adci 256 111111 b f sys / 64 ff h t adci 257 assumptions: f sys = 80 mhz (i.e. t sys = 12.5 ns), diva = 03 h , stc = 00 h analog clock f adci = f sys / 4 = 20 mhz, i.e. t adci = 50 ns sample time t s = t adci 2 = 100 ns conversion 10-bit: t c10 = 13 t adci + 2 t sys = 13 50 ns + 2 12.5 ns = 0.675 s conversion 8-bit: t c8 = 11 t adci + 2 t sys = 11 50 ns + 2 12.5 ns = 0.575 s assumptions: f sys = 40 mhz (i.e. t sys = 25 ns), diva = 02 h , stc = 03 h analog clock f adci = f sys / 3 = 13.3 mhz, i.e. t adci = 75 ns sample time t s = t adci 5 = 375 ns conversion 10-bit: t c10 = 16 t adci + 2 t sys = 16 75 ns + 2 25 ns = 1.25 s conversion 8-bit: t c8 = 14 t adci + 2 t sys = 14 75 ns + 2 25 ns = 1.10 s free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 89 v2.0, 2009-03 4.4 system parameters the following parameters specify several aspects which are important when integrating the xc236xa into an application system. note: these parameters are not subject to produ ction test but verified by design and/or characterization. table 20 various system parameters parameter symbol values unit note / test condition min. typ. max. supply watchdog (swd) supervision level (see table 21 ) v swd cc v lv - 0.15 v lv v lv + 0.15 v v lv = selected voltage in upper voltage area v lv - 0.10 1) 1) the limit v lv - 0.10 v is valid for the ok1 level. the limit for the ok2 level is v lv -0.15v. v lv v lv + 0.15 v v lv = selected voltage in lower voltage area core voltage (pvc) supervision level (see table 22 ) v pvc cc v lv - 0.03 v lv v lv + 0.07 2) 2) this value includes a hysteresis of approximately 50 mv for rising voltage. v v lv = selected voltage wakeup clock source frequency f wu cc 400 500 600 khz freqsel=00 b 210 270 330 khz freqsel=01 b 140 180 220 khz freqsel=10 b 110 140 170 khz freqsel=11 b internal clock source frequency f int cc 4.8 5.0 5.2 mhz short-term 3) deviation of int. clock source frequency 3) the short-term frequency deviation refers to a timeframe of 20 ms and is measured relative to the current frequency at the beginning of the respective timeframe. the short-term deviation with the duration of a lin-frame allows error-free transmission. df int cc -1 ? 1 % rel. to current start frequency startup time from stopover mode t sso cc 200 260 320 s user instruction from psram free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 90 v2.0, 2009-03 table 21 coding of bitfields levxv in register swdcon0 code default voltage level notes 1) 1) the indicated default levels are selected automatically after a power reset. 0000 b 2.9 v 0001 b 3.0 v lev1v: reset request 0010 b 3.1 v 0011 b 3.2 v 0100 b 3.3 v 0101 b 3.4 v 0110 b 3.6 v 0111 b 4.0 v 1000 b 4.2 v 1001 b 4.5 v lev2v: no request 1010 b 4.6 v 1011 b 4.7 v 1100 b 4.8 v 1101 b 4.9 v 1110 b 5.0 v 1111 b 5.5 v table 22 coding of bitfields levxv in registers pvcyconz code default voltage level notes 1) 1) the indicated default levels are selected automatically after a power reset. 000 b 0.95 v 001 b 1.05 v 010 b 1.15 v 011 b 1.25 v 100 b 1.35 v lev1v: reset request 101 b 1.45 v lev2v: interrupt request 110 b 1.55 v 111 b 1.65 v free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 91 v2.0, 2009-03 4.5 flash memory parameters the xc236xa is delivered with all flash sectors erased and with no protection installed. the data retention time of the xc236xa?s flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the flash memory has been erased and programmed. note: these parameters are not subject to produ ction test but verified by design and/or characterization. note: operating conditions apply. table 23 flash characteristics parameter symbol limit values unit note / test condition min. typ. max. programming time per 128-byte page t pr ?3 1) 1) programming and erase times depend on the internal flash clock source. the control state machine needs a few system clock cycles. this requirement is only relevant for extremely low system frequencies. 3.5 ms ms erase time per sector/page t er ?7 1) 8msms data retention time t ret 20 ? ? years 1,000 erase / program cycles flash erase endurance for user sectors 2) 2) a maximum of 64 flash sectors can be cycled 15,000 ti mes. for all other sectors the limit is 1,000 cycles. n er 15,000 ? ? cycles data retention time 5 years flash erase endurance for security pages n sec 10 ? ? cycles data retention time 20 years drain disturb limit n dd 32 ? ? cycles 3) 3) this parameter limits the number of subsequent programming operations within a physical sector. the drain disturb limit is applicable if wordline erase is used repeatedly. for normal sect or erase/program cycles this limit will not be violated. parallel flash module program/erase limit, depending on the flash read activity n pp ? ? 1 ? unrestricted 4) execution 4) flash module 3 can be erased/programmed while code is executed and/or data is read from any other flash modules. ? ? 4 ? restricted 5) execution 5) all flash modules can be erased/programmed while code is executed and/or data is read from only one flash module or from psram. the flash module that delivers code/data can, of course, not be erased/programmed. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 92 v2.0, 2009-03 access to the xc236xa flash modules is controlled by the imb. built-in prefetch mechanisms optimize the performance for sequential access. flash access waitstates only affect non-sequential access. due to prefetch mechanisms, the performance for sequential access (depending on the software structure) is only partially influenced by waitstates. note: the maximum achievable system frequency is limited by the properties of the respective derivative. table 24 flash access waitstates required waitstates system frequency range 4 ws (wsflash = 100 b ) f sys f sysmax 3 ws (wsflash = 011 b ) f sys 17 mhz 2 ws (wsflash = 010 b ) f sys 13 mhz 1 ws (wsflash = 001 b ) f sys 8 mhz 0 ws (wsflash = 000 b ) forbidden! must not be selected! free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 93 v2.0, 2009-03 4.6 ac parameters these parameters describe the dynamic behavior of the xc236xa. 4.6.1 testing waveforms these values are used for characterization and production testing (except pin xtal1). figure 16 input output waveforms figure 17 floating waveforms mcd05556c 0.3 v ddp input signal (driven by tester) output signal (measured) hold time output delay output delay hold time output timings refer to the rising edge of clkout. input timings are calculated from the time, when the input signal reaches v ih or v il , respectively. 0.2 v ddp 0.8 v ddp 0.7 v ddp mca05565 timing reference points v load + 0.1 v v load - 0.1 v v oh - 0.1 v v ol + 0.1 v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, but begins to float when a 100 mv change from the loaded v oh / v ol level occurs ( i oh / i ol = 20 ma). free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 94 v2.0, 2009-03 4.6.2 definition of internal timing the internal operation of the xc236xa is controlled by the internal system clock f sys . because the system clock signal f sys can be generated from a number of internal and external sources usi ng different mechanisms, the duration of the system clock periods (tcss) and their variation (as well as the derived external timing) depend on the mechanism used to generate f sys . this must be considered when calculating the timing for the xc236xa. figure 18 generation mechanisms for the system clock note: the example of pll operation shown in figure 18 uses a pll factor of 1:4; the example of prescaler operation uses a divider factor of 2:1. the specification of the external timing (a c characteristics) depends on the period of the system clock (tcs). mc_xc2x_clockgen phase locked loop operation (1:n) f in direct clock drive (1:1) prescaler operation (n:1) f sys f in f sys f in f sys tcs tcs tcs free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 95 v2.0, 2009-03 direct drive when direct drive operation is selected (syscon0.clksel = 11 b ), the system clock is derived directly from the input clock signal clkin1: f sys = f in . the frequency of f sys is the same as the frequency of f in . in this case the high and low times of f sys are determined by the duty cycle of the input clock f in . selecting bypass operation from the xtal1 1) input and using a divider factor of 1 results in a similar configuration. prescaler operation when prescaler operation is selected (syscon0.clksel = 10 b , pllcon0.vcoby = 1 b ), the system clock is derived either from the crystal oscillator (input clock signal xtal1) or from the internal clock source through the output prescaler k1 (= k1div+1): f sys = f osc / k1. if a divider factor of 1 is selected, the frequency of f sys equals the frequency of f osc . in this case the high and low times of f sys are determined by the duty cycle of the input clock f osc (external or internal). the lowest system clock frequency results from selecting the maximum value for the divider factor k1: f sys = f osc / 1024. phase locked loop (pll) when pll operation is selected (syscon0.clksel = 10 b , pllcon0.vcoby = 0 b ), the on-chip phase locked loop is enabled and provides the system clock. the pll multiplies the input frequency by the factor f ( f sys = f in f ). f is calculated from the input divider p (= pdiv+1), the multiplication factor n (= ndiv+1), and the output divider k2 (= k2div+1): ( f = n / (p k2)). the input clock can be derived either from an external source at xtal1 or from the on- chip clock source. the pll circuit synchronizes the system clock to the input clock. this synchronization is performed smoothly so that the system cl ock frequency does not change abruptly. adjustment to the input clock continuously changes the frequency of f sys so that it is locked to f in . the slight variation causes a jitter of f sys which in turn affects the duration of individual tcss. 1) voltages on xtal1 must comply to the core supply voltage v ddi1 . free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 96 v2.0, 2009-03 the timing in the ac characteristics refers to tcss. timing must be calculated using the minimum tcs possible under the given circumstances. the actual minimum value for tcs depends on the jitter of the pll. because the pll is constantly adjusting its output frequency to correspond to the input frequency (from crystal or oscillator), the accumulated jitter is limited. this means that the relative deviation for periods of more than one tcs is lower than for a single tcs (see formulas and figure 19 ). this is especially important for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. for all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the pll jitter is negligible. the value of the accumulated pll jitter depends on the number of consecutive vco output cycles within the respective timeframe. the vco output clock is divided by the output prescaler k2 to generate the system clock signal f sys . the number of vco cycles is k2 t , where t is the number of consecutive f sys cycles (tcs). the maximum accumulated jitter (long-term jitter) d tmax is defined by: d tmax [ns] = (220 / (k2 f sys ) + 4.3) this maximum value is applicable, if either the number of clock cycles t > ( f sys / 1.2) or the prescaler value k2 > 17. in all other cases for a timeframe of t tcs the accumulated jitter d t is determined by: d t [ns] = d tmax [(1 - 0.058 k2) (t - 1) / (0.83 f sys - 1) + 0.058 k2] f sys in [mhz] in all formulas. example, for a period of 3 tcss @ 33 mhz and k2 = 4: d max = (220 / (4 33) + 4.3) = 5.97 ns (not applicable directly in this case!) d 3 = 5.97 [(1 - 0.058 4) (3 - 1) / (0.83 33 - 1) + 0.058 4] = 5.97 [0.768 2 / 26.39 + 0.232] = 1.7 ns example, for a period of 3 tcss @ 33 mhz and k2 = 2: d max = (220 / (2 33) + 4.3) = 7.63 ns (not applicable directly in this case!) d 3 = 7.63 [(1 - 0.058 2) (3 - 1) / (0.83 33 - 1) + 0.058 2] = 7.63 [0.884 2 / 26.39 + 0.116] = 1.4 ns free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 97 v2.0, 2009-03 figure 19 approximated accumulated pll jitter note: the specified pll jitter values are vali d if the capacitive load per pin does not exceed c l = 20 pf (see table 13 ). the maximum peak-to-peak noise on th e pad supply voltage (measured between v ddpb pin 100/144 and v ss pin 1) is limited to a peak-to-peak voltage of v pp = 50 mv. this can be achieved by appropriate blocking of the supply voltage as close as possible to the supply pins and using pcb supply and ground planes. different frequency bands can be selected for the vco so that the operation of the pll can be adjusted to a wide range of input and output frequencies: table 25 vco bands for pll operation 1) 1) not subject to production test - verified by design/characterization. pllcon0.vcosel vco frequency range base frequency range 00 50 ? 110 mhz 10 ? 40 mhz 01 100 ? 160 mhz 20 ? 80 mhz 1x reserved mc_xc 2x_jitter cycles t 0 1 2 3 4 5 6 7 8 acc. jitter d t 20 40 60 80 100 ns f sys = 66 mhz 1 f vco = 132 mhz f vco = 66 mhz 9 f sys = 33 mhz free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 98 v2.0, 2009-03 wakeup clock when wakeup operation is selected (syscon0.clksel = 00 b ), the system clock is derived from the low-frequency wakeup clock source: f sys = f wu . in this mode, a basic functionality can be maintained without requiring an external clock source and while minimizing the power consumption. selecting and changing the operating frequency when selecting a clock source and the clock generation method, the required parameters must be carefully written to the respective bitfields, to avoid unintended intermediate states. many applications change the frequency of the system clock ( f sys ) during operation in order to optimize system performance and power consumption. changing the operating frequency also changes the switching currents, which influences the power supply. to ensure proper operation of the on-chip evrs while they generate the core voltage, the operating frequency shall only be changed in certain steps. this prevents overshoots and undershoots of the supply voltage. to avoid the indicated problems, recommended sequences are provided which ensure the intended operation of the clock system interacting with the power system. please refer to the programmer?s guide. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 99 v2.0, 2009-03 4.6.3 external clock input parameters these parameters specify the external clock generation for the xc236xa. the clock can be generated in two ways: ? by connecting a crystal or ceramic resonator to pins xtal1/xtal2. ? by supplying an external clock signal . this clock signal can be supplied either to pin xtal1 (core voltage domain) or to pin clkin1 (io voltage domain). if connected to clkin1, the input signal must reach the defined input levels v il and v ih . if connected to xtal1, a minimum amplitude v ax1 (peak-to-peak voltage) is sufficient for the operation of the on-chip oscillator. note: the given clock timing parameters ( t 1 t 4 ) are only valid for an external clock input signal. note: operating conditions apply. table 26 external clock input characteristics parameter symbol limit values unit note / test condition min. typ. max. input voltage range limits for signal on xtal1 v ix1 sr -1.7 + v ddi ?1.7v 1) 1) overload conditions must not occur on pin xtal1. input voltage (amplitude) on xtal1 v ax1 sr 0.3 v ddi ? ? v peak-to-peak voltage 2) 2) the amplitude voltage v ax1 refers to the offset voltage v off . this offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by v ix1 . xtal1 input current i il cc ? ? 20 a0v < v in < v ddi oscillator frequency f osc cc 4 ? 40 mhz clock signal 4 ? 16 mhz crystal or resonator high time t 1 sr6??ns low time t 2 sr6??ns rise time t 3 sr?88ns fall time t 4 sr?88ns free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 100 v2.0, 2009-03 figure 20 external clock drive xtal1 note: for crystal/resonator operation, it is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimum parameters for oscillator operation. please refer to the limits specifie d by the crystal/resonator supplier. mc_extclock t 1 t 2 t osc = 1/ f osc t 3 t 4 v off v ax1 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 101 v2.0, 2009-03 4.6.4 pad properties the output pad drivers of the xc236xa can operate in several user-selectable modes. strong driver mode allows controlling external components requiring higher currents such as power bridges or leds. reducing the driving power of an output pad reduces electromagnetic emissions (eme). in strong driver mode, selecting a slower edge reduces eme. the dynamic behavior, i.e. the rise time and fall time, depends on the applied external capacitance that must be charged and disc harged. timing values are given for a capacitance of 20 pf, unless otherwise noted. in general, the performance of a pad driver depends on the available supply voltage v ddp . therefore, table 27 and table 28 list the pad parameters for the upper voltage range and the lower voltage range, respectively. note: these parameters are not subject to produ ction test but verified by design and/or characterization. table 27 standard pad parameters (upper voltage range) parameter symbol limit values unit note / test condition min. typ. max. maximum output current i olmax , - i ohmax ??10 ma strong driver ??4.0ma medium driver ??0.5ma weak driver nominal output current i olnom , - i ohnom ??2.5ma strong driver ??1.0ma medium driver ??0.1ma weak driver rise/fall time (10%-90%) valid for external capacitances in the range of 20 pf c l 100 pf ( c l in [pf]) t r / t f ??4.2 + 0.14* c l ns strong driver, fast edge ? ? 11.6 + 0.22* c l ns strong driver, medium edge ? ? 20.6 + 0.22* c l ns strong driver, slow edge ? ? 23 + 0.6* c l ns medium driver ? ? 212 + 1.9* c l ns weak driver free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 102 v2.0, 2009-03 table 28 standard pad parameters (lower voltage range) parameter symbol limit values unit note / test condition min. typ. max. maximum output current 1) 1) an output current above | i oxnom | may be drawn from up to three pins at the same time. for any group of 16 neighboring output pins, the total output current in each direction ( i ol and - i oh ) must remain below 50 ma. i olmax , - i ohmax ??10 ma strong driver ??2.5ma medium driver ??0.5ma weak driver nominal output current i olnom , - i ohnom ??2.5ma strong driver ??1.0ma medium driver ??0.1ma weak driver rise/fall time (10%-90%) valid for external capacitances in the range of 20 pf c l 100 pf ( c l in [pf]) t r / t f ??6.2 + 0.24* c l ns strong driver, fast edge ? ? 24 + 0.3* c l ns strong driver, medium edge ? ? 34 + 0.3* c l ns strong driver, slow edge ? ? 37 + 0.65* c l ns medium driver ? ? 500 + 2.5* c l ns weak driver free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 103 v2.0, 2009-03 4.6.5 external bus timing the following parameters specify the be havior of the xc236xa bus interface. note: these parameters are not subject to produ ction test but verified by design and/or characterization. figure 21 clkout signal timing note: the term clkout refers to the reference clock output signal which is generated by selecting f sys as the source signal for the clock output signal extclk on pin p2.8 and by enabling the high-speed clock driver on this pin. table 29 clkout reference signal parameter symbol limits unit note / test condition min. max. clkout cycle time t 5 cc 40/25/12.5 1) 1) the clkout cycle time is in fluenced by the pll jitter (given values apply to f sys = 25/40/80 mhz). for longer periods the relative deviation decreases (see pll deviation formula). ns clkout high time t 6 cc3?ns clkout low time t 7 cc3?ns clkout rise time t 8 cc?3ns clkout fall time t 9 cc?3ns mc_x_ebcclkout clkout t 5 t 6 t 7 t 8 t 9 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 104 v2.0, 2009-03 variable memory cycles external bus cycles of the xc236xa are exec uted in five consecut ive cycle phases (ab, c, d, e, f). the duration of each cycle phase is programmable (via the tconcsx registers) to adapt the external bus cycles to the respective external module (memory, peripheral, etc.). the duration of the access phase can optionally be controlled by the external module using the ready handshake input. this table provides a summary of the phases and the ranges for their length. note: the bandwidth of a parameter (from minimum to maximum value) covers the whole operating range (temperature, voltage) as well as process variations. within a given device, however, this bandwidth is smaller than the specified range. this is also due to interdependencies between certain parameters. some of these interdependencies are described in additional notes (see standard timing). note: operating conditions apply. table 30 programmable bus cycle phases (see timing diagrams) bus cycle phase parameter valid values unit address setup phase, the standard duration of this phase (1 ? 2 tcs) can be extended by 0 ? 3 tcs if the address window is changed tpab 1 ? 2 (5) tcs command delay phase tpc 0 ? 3 tcs write data setup/mux tristate phase tpd 0 ? 1 tcs access phase tpe 1 ? 32 tcs address/write data hold phase tpf 0 ? 3 tcs free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 105 v2.0, 2009-03 table 31 external bus cycle timing for upper voltage range parameter symbol limits unit note min. typ. max. output valid delay for: rd , wr (l /h ) t 10 cc ? 13 ns output valid delay for: bhe , ale t 11 cc ? 14 ns address output valid delay for: a23 ? a16, a15 ? a0 t 12 cc ? 14 ns address output valid delay for: ad15 ? ad0 t 13 cc ? 15 ns output valid delay for: cs t 14 cc ? 13 ns data output valid delay for: ad15 ? ad0 (write data, mux) t 15 cc ? 15 ns data output valid delay for: d15 ? d0 (write data, demux) t 16 cc ? 15 ns output hold time for: rd , wr (l /h ) t 20 cc -2 8 ns output hold time for: bhe , ale t 21 cc -2 10 ns address output hold time for: ad15 ? ad0 t 23 cc -3 8 ns output hold time for: cs t 24 cc -3 11 ns data output hold time for: d15 ? d0, ad15 ? ad0 t 25 cc -3 8 ns input setup time for: ready, d15 ? d0, ad15 ? ad0 (read data) t 30 sr 25 ? ns input hold time for: ready, d15 ? d0, ad15 ? ad0 (read data) 1) 1) read data are latched with the same internal clock edge that triggers the address change and the rising edge of rd . address changes before the end of rd have no impact on (demultiplexed) read cycles. read data can change after the rising edge of rd . t 31 sr 0 ? ns free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 106 v2.0, 2009-03 table 32 external bus cycle timing for lower voltage range parameter symbol limits unit note min. typ. max. output valid delay for: rd , wr (l /h ) t 10 cc ? 20 ns output valid delay for: bhe , ale t 11 cc ? 21 ns address output valid delay for: a23 ? a16, a15 ? a0 t 12 cc ? 22 ns address output valid delay for: ad15 ? ad0 t 13 cc ? 22 ns output valid delay for: cs t 14 cc ? 13 ns data output valid delay for: ad15 ? ad0 (write data, mux) t 15 cc ? 22 ns data output valid delay for: d15 ? d0 (write data, demux) t 16 cc ? 22 ns output hold time for: rd , wr (l /h ) t 20 cc -2 10 ns output hold time for: bhe , ale t 21 cc -2 10 ns address output hold time for: ad15 ? ad0 t 23 cc -3 10 ns output hold time for: cs t 24 cc -3 11 ns data output hold time for: d15 ? d0, ad15 ? ad0 t 25 cc -3 10 ns input setup time for: ready, d15 ? d0, ad15 ? ad0 (read data) t 30 sr 29 ? ns input hold time for: ready, d15 ? d0, ad15 ? ad0 (read data) 1) 1) read data are latched with the same internal clock edge that triggers the address change and the rising edge of rd . address changes before the end of rd have no impact on (demultiplexed) read cycles. read data can change after the rising edge of rd . t 31 sr 0 ? ns free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 107 v2.0, 2009-03 figure 22 multiplexed bus cycle clkout tp ab tp c tp d tp e tp f ale t 21 t 11 a23-a16, bhe, csx t 11 / t 12 / t 14 rd wr(l/ h) t 20 t 10 data in ad15-ad0 (read) t 30 t 31 mc_x_ebcmux ad15-ad0 (write) t 13 t 15 t 25 t 13 t 23 data out low address high address low address t 24 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 108 v2.0, 2009-03 figure 23 demultiplexed bus cycle address tp ab tp c tp d tp e tp f t 21 t 11 t 11 / t 12 / t 14 t 20 t 10 data in t 30 t 31 mc_x_ebcdemux t 16 t 25 clkout ale a23-a0, bhe, csx rd wr(l/ h) d15-d0 (read) d15-d0 (write) data out t 24 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 109 v2.0, 2009-03 bus cycle control with the ready input the duration of an exte rnal bus cycle can be c ontrolled by the exter nal circuit using the ready input signal. the polarity of this input signal can be selected. synchronous ready permits the shortest possible bus cycle but requires the input signal to be synchronous to the reference signal clkout. an asynchronous ready signal puts no timing constraints on the input signal but incurs a minimum of one waitstate due to the additional synchronization stage. the minimum duration of an asynchronous ready signal for safe synchronization is one clkout period plus the input setup time. an active ready signal can be deactivated in response to the trailing (rising) edge of the corresponding command (rd or wr ). if the next bus cycle is controlled by ready, an active ready signa l must be disabled before the first valid sample point in the next bus cycle. this sample point depends on the programmed phases of the next cycle. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 110 v2.0, 2009-03 figure 24 ready timing note: if the ready input is sampled inactive at the indicated sampling point (?not rdy?) a ready-controlled waitstate is inserted (tprdy), sampling the ready input active at the indicated sampling point (?ready?) terminates the currently running bus cycle. note the different sampling points for synchronous and asynchronous ready. this example uses one mandatory waitstate (see tpe) before the ready input value is used. mc_ x_ebcready ready asynchron. not rdy ready data out t 25 t 30 d15-d0 (wri te) ready synchronous not rdy ready data in d15-d0 (read) t 10 rd, wr tp d tp e tp rdy tp f clkout t 20 t 30 t 31 t 31 t 30 t 31 t 30 t 31 t 30 t 31 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 111 v2.0, 2009-03 4.6.6 synchronous serial interface timing the following parameters are applicable for a usic channel operated in ssc mode. note: these parameters are not subject to produ ction test but verified by design and/or characterization. note: operating conditions apply. table 33 ssc master/slave mode timing for upper voltage range parameter symbol values unit note / test co ndition min. typ. max. master mode timing slave select output selo active to first sclkout transmit edge t 1 cc t sys - 8 ? 1) 1) the maximum value further depends on the settings for the slave select output leading delay. ns 2) 2) t sys =1/ f sys (= 12.5 ns @ 80 mhz) slave select output selo inactive after last sclkout receive edge t 2 cc t sys - 6 ? 3) 3) the maximum value depends on the settings for the slave select output trailing delay and for the shift clock output delay. ns transmit data output valid time t 3 cc -6 ? 9 ns receive data input setup time to sclkout receive edge t 4 sr 31 ? ? ns data input dx0 hold time from sclkout receive edge t 5 sr -4 ? ? ns slave mode timing select input dx2 setup to first clock input dx1 transmit edge t 10 sr7??ns 4) 4) these input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits dxncr.dsen = 0). select input dx2 hold after last clock input dx1 receive edge t 11 sr7??ns 4) data input dx0 setup time to clock input dx1 receive edge t 12 sr7??ns 4) data input dx0 hold time from clock input dx1 receive edge t 13 sr5??ns 4) data output dout valid time t 14 cc 7 ? 33 ns 4) free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 112 v2.0, 2009-03 table 34 ssc master/slave mode timing for lower voltage range parameter symbol values unit note / test co ndition min. typ. max. master mode timing slave select output selo active to first sclkout transmit edge t 1 cc t sys - 10 ? 1) 1) the maximum value further depends on the settings for the slave select output leading delay. ns 2) 2) t sys =1/ f sys (= 12.5 ns @ 80 mhz) slave select output selo inactive after last sclkout receive edge t 2 cc t sys - 9 ? 3) 3) the maximum value depends on the settings for the slave select output trailing delay and for the shift clock output delay. ns 2) transmit data output valid time t 3 cc -7 ? 11 ns receive data input setup time to sclkout receive edge t 4 sr 40 ? ? ns data input dx0 hold time from sclkout receive edge t 5 sr -5 ? ? ns slave mode timing select input dx2 setup to first clock input dx1 transmit edge t 10 sr7??ns 4) 4) these input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits dxncr.dsen = 0). select input dx2 hold after last clock input dx1 receive edge t 11 sr7??ns 4) data input dx0 setup time to clock input dx1 receive edge t 12 sr7??ns 4) data input dx0 hold time from clock input dx1 receive edge t 13 sr5??ns 4) data output dout valid time t 14 cc 8 ? 41 ns 4) free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 113 v2.0, 2009-03 figure 25 usic - ssc master/slave mode timing note: this timing diagram shows a standard configuration where the slave select signal is low-active and the serial clock signal is not shifted and not inverted. t 2 t 1 usic_ssc_tmgx.vsd clock output sclkout data output dout t 3 t 3 t 5 data valid t 4 fi rs t trans mi t edge data input dx0 select output selox active master mode timing slave mode timing t 11 t 10 clock input dx1 data output dout t 14 t 14 data valid data input dx0 select input dx2 active t 13 t 12 transmit edge: with this clock edge , transmit data is shifted to transmit data output . receive edge: with this clock edge , receive data at receive data input is latched . receive edge last receive edge inactive inactive trans mi t edge inactive inactive fi rst transmi t edge receive edge trans mi t edge last receive edge t 5 data valid t 4 data valid t 12 t 13 drawn for brgh .sclkcfg = 00 b . also valid for for sclkcfg = 01 b with inverted sclkout signal. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 114 v2.0, 2009-03 4.6.7 debug interface timing the debugger can communicate with the xc236xa either via the 2-pin dap interface or via the standard jtag interface. debug via jtag the following parameters are applicable for communication through the jtag debug interface. the jtag module is fully compliant with ieee1149.1-2000. note: these parameters are not subject to produ ction test but verified by design and/or characterization. note: operating conditions apply. table 35 jtag interface timing parameters for upper voltage range parameter symbol values unit note / test condition min. typ. max. tck clock period t 1 sr50??ns 1) 1) under typical conditions, the jtag interface can operate at transfer rates up to 20 mhz. tck high time t 2 sr16??ns tck low time t 3 sr16??ns tck clock rise time t 4 sr??8ns tck clock fall time t 5 sr??8ns tdi/tms setup to tck rising edge t 6 sr6??ns tdi/tms hold after tck rising edge t 7 sr6??ns tdo valid after tck falling edge 2) 2) the falling edge on tck is used to generate the tdo timing. t 8 cc? 2529ns tdo high imped. to valid from tck falling edge 2)3) 3) the setup time for tdo is given implicitly by the tck cycle time. t 9 cc? 2529ns tdo valid to high imped. from tck falling edge 2) t 10 cc? 2529ns tdo hold after tck falling edge 2) t 18 cc5??ns free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 115 v2.0, 2009-03 figure 26 test clock timing (tck) table 36 jtag interface timing parameters for lower voltage range parameter symbol values unit note / test condition min. typ. max. tck clock period t 1 sr50??ns tck high time t 2 sr16??ns tck low time t 3 sr16??ns tck clock rise time t 4 sr??8ns tck clock fall time t 5 sr??8ns tdi/tms setup to tck rising edge t 6 sr6??ns tdi/tms hold after tck rising edge t 7 sr6??ns tdo valid after tck falling edge 1) 1) the falling edge on tck is used to generate the tdo timing. t 8 cc? 3236ns tdo high imped. to valid from tck falling edge 2)3) 2) the setup time for tdo is given implicitly by the tck cycle time. 3) the setup time for tdo is given implicitly by the tck cycle time. t 9 cc? 3236ns tdo valid to high imped. from tck falling edge 1) t 10 cc? 3236ns tdo hold after tck falling edge 1) t 18 cc5??ns mc_jtag_tck 0.9 v ddp 0.5 v ddp t 1 t 2 t 3 0.1 v ddp t 5 t 4 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 116 v2.0, 2009-03 figure 27 jtag timing t 6 t 7 t 6 t 7 t 9 t 8 t 10 tck tms tdi tdo mc_jtag t 18 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 117 v2.0, 2009-03 debug via dap the following parameters are applicable for communication through the dap debug interface. note: these parameters are not subject to produ ction test but verified by design and/or characterization. note: operating conditions apply. table 37 dap interface timing parameters for upper voltage range parameter symbol values unit note / test condition min. typ. max. dap0 clock period t 11 sr25??ns? dap0 high time t 12 sr8??ns? dap0 low time t 13 sr8??ns? dap0 clock rise time t 14 sr??4ns? dap0 clock fall time t 15 sr??4ns? dap1 setup to dap0 rising edge t 16 sr6??ns? dap1 hold after dap0 rising edge t 17 sr6??ns? dap1 valid per dap0 clock period 1) 1) the host has to find a suitable sampling point by analyzing the sync telegram response. t 19 cc 17 20 ? ns ? free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 118 v2.0, 2009-03 figure 28 test clock timing (dap0) table 38 dap interface timing parameters for lower voltage range parameter symbol values unit note / test condition min. typ. max. dap0 clock period t 11 sr25??ns? dap0 high time t 12 sr8??ns? dap0 low time t 13 sr8??ns? dap0 clock rise time t 14 sr??4ns? dap0 clock fall time t 15 sr??4ns? dap1 setup to dap0 rising edge t 16 sr6??ns? dap1 hold after dap0 rising edge t 17 sr6??ns? dap1 valid per dap0 clock period 1) 1) the host has to find a suitable sampling point by analyzing the sync telegram response. t 19 cc 12 17 ? ns ? mc_dap0 0.9 v ddp 0.5 v ddp t 11 t 12 t 13 0.1 v ddp t 15 t 14 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line electrical parameters data sheet 119 v2.0, 2009-03 figure 29 data transfer timing host to device (dap1) figure 30 data transfer timing device to host (dap1) note: the transmission timing is determined by the receiving debugger by evaluating the sync-request synchronization pattern telegram. t 16 t 17 dap0 dap1 mc_dap1_rx dap1 mc_ dap1_tx t 11 t 19 free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line package and reliability data sheet 120 v2.0, 2009-03 5 package and reliability in addition to the electrical parameters, the following specifications ensure proper integration of the xc236xa into the target system. 5.1 packaging these parameters specify the packaging rather than the silicon. note: to improve the emc behavior, it is recommended to connect the exposed pad to the board ground, independent of the thermal requirements. board layout examples are given in an application note. package compatibility considerations the xc236xa is a member of the xc2000 family of microcontrollers. it is also compatible to a certain extent with members of similar series and subfamilies. each package is optimized for the chip it houses. therefore, there may be slight differences between packages of the same pin-count but for different device types. in particular, the size of the exposed pad (if present) may vary. if different device types are considered or planned for an application, it must be ensured that the board layout fits all packages under consideration. table 39 package parameters (pg-lqfp-100-8) parameter symbol limit values unit notes min. max. exposed pad dimension ex ey ? 6.2 6.2 mm ? power dissipation p diss ?1.0w? thermal resistance junction-ambient r ja ? 47 k/w no thermal via 1) 1) device mounted on a 2-layer jedec board (according to jesd 51-3) or a 4-layer board without thermal vias; exposed pad not soldered. 29 k/w 4-layer, no pad 2) 2) device mounted on a 4-layer jedec board (according to jesd 51-7) with thermal vias; exposed pad not soldered. 23 k/w 4-layer, pad 3) 3) device mounted on a 4-layer jedec board (according to jesd 51-7) with thermal vias; exposed pad soldered to the board. free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line package and reliability data sheet 121 v2.0, 2009-03 package outlines figure 31 pg-lqfp-100-8 (plastic green thin quad flat package) all dimensions in mm. you can find complete information about infineon packages, packing and marking in our infineon internet page ?packages?: http://www.infineon.com/packages 1) does not include plastic or metal protrusion of 0.25 max. per side pg-lqfp-100-3, -4, -8-po v11 0.5 12 0.22 a-b 0.08 m c c d 100x 100x ?.05 1.6 max. ?.05 ?.05 c 0.1 0.08 1.4 ?.15 0.6 h 7? max. +0.05 -0.06 0.15 a b index marking 1 100 d 14 1) 16 0.2 a-b d 100x 4x d a-b 0.2 h 14 1) 16 bottom view 100 1 exposed diepad ey ex free datasheet http:///
xc2361a, xc2363a, xc2364a, XC2365A xc2000 family derivatives / base line package and reliability data sheet 122 v2.0, 2009-03 5.2 thermal considerations when operating the xc236xa in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage. the maximum heat that can be dissipated depends on the package and its integration into the target board. the ?thermal resistance r ja ? quantifies these parameters. the power dissipation must be limited so that the average junction temperature does not exceed 150 c. the difference between junction temperature and ambient temperature is determined by t = ( p int + p iostat + p iodyn ) r ja the internal power consumption is defined as p int = v ddp i ddp (switching current and leakage current). the static external power consumption caused by the output drivers is defined as p iostat = (( v ddp - v oh ) i oh ) + ( v ol i ol ) the dynamic external power consumpt ion caused by the output drivers ( p iodyn ) depends on the capacitive load connected to the res pective pins and their switching frequencies. if the total power dissipation for a given system configuration exceeds the defined limit, countermeasures must be taken to ensure proper system operation: ? reduce v ddp , if possible in the system ? reduce the system frequency ? reduce the number of output pins ? reduce the load on active output drivers free datasheet http:///
www.infineon.com published by infineon technologies ag b158-h9272-g3-x-7600 free datasheet http:///

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