september 2014 ?2013 fairchild semiconductor corporation FDZ1323NZ rev.c7 www.fairchildsemi.com 1 FDZ1323NZ common drain n-ch annel 2.5 v powertrench ? wl-csp mosfet FDZ1323NZ common drain n-channe l 2.5 v powertrench ? wl-csp mosfet 20 v, 10 a, 13 m features ? max r s1s2(on) = 13 m at v gs = 4.5 v, i s1s2 = 1 a ? max r s1s2(on) = 13 m at v gs = 3.8 v, i s1s2 = 1 a ? max r s1s2(on) = 16 m at v gs = 3.1 v, i s1s2 = 1 a ? max r s1s2(on) = 18 m at v gs = 2.5 v, i s1s2 = 1 a ? occupies only 3 mm 2 of pcb area ? ultra-thin package: less than 0.35 mm height when mounted to pcb ? high power and current handling capability ? hbm esd protection level > 3.6 kv (note 3) ? rohs compliant general description this device is designed specifically as a single package solution for li-ion battery pack protection circuit and other ultra-portable applications. it features tw o common drain n-channel mosfets, which enables bidirectional current flow, on fairchild?s advanced powertrench ? process with state of the art ?low pitch? wlcsp packagi ng process, the FDZ1323NZ minimizes both pcb space and r s1s2(on) . this advanced wlcsp mosfet embodies a breakthrough in packaging technology which enables the dev ice to combine excellent thermal transfer characteristics, ultra-low profile packaging, low gate charge and low r s1s2(on) . applications ? battery management ? load switch ? battery protection mosfet maximum ratings t a = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v s1s2 source1 to source2 voltage 20 v v gs gate to source voltage 12 v i s1s2 source1 to source2 current -continuous t a = 25c (note 1a) 10 a -pulsed 40 p d power dissipation t a = 25c (note 1a) 2 w power dissipation t a = 25c (note 1b) 0.5 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient (note 1a) 62 c/w r ja thermal resistance, junction to ambient (note 1b) 257 device marking device package reel size tape width quantity ec FDZ1323NZ wl-csp 1.3x2.3 7 ?? 8 mm 5000 units s1 g1 g2 s2 bottom top pin1 wl-csp 1.3x2.3 s1 g1 g2 s2 pin1 s1 s2
FDZ1323NZ common drain n-ch annel 2.5 v powertrench ? wl-csp mosfet www.fairchildsemi.com 2 ?2013 fairchild semiconductor corporation FDZ1323NZ rev.c7 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics source1 to source2 diode characteristics symbol parameter test conditions min typ max units i s1s2 zero gate voltage source1 to source2 current v s1s2 = 16 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 12 v, v s1s2 = 0 v 10 a v gs(th) gate to source threshold voltage v gs = v s1s2 , i s1s2 = 250 a 0.4 0.9 1.2 v r s1s2(on) static source1 to source2 on resistance v gs = 4.5 v, i s1s2 = 1 a 4.5 9.7 13 m v gs = 3.8 v, i s1s2 = 1 a 5.5 10 13 v gs = 3.1 v, i s1s2 = 1 a 7 11 16 v gs = 2.5 v, i s1s2 = 1 a 8 13 18 v gs = 4.5 v, i s1s2 = 1 a,t j = 125 o c 13 20 g fs forward transconductance v s1s2 = 5 v, i s1s2 = 1 a 9 s c iss input capacitance v s1s2 = 10 v, v gs = 0 v, f = 1 mhz 1545 2055 pf c oss output capacitance 269 405 pf c rss reverse transfer capacitance 252 380 pf t d(on) turn-on delay time v s1s2 = 10 v, i s1s2 = 1 a, v gs = 4.5 v, r gen = 6 12 22 ns t r rise time 13 23 ns t d(off) turn-off delay time 34 54 ns t f fall time 13 23 ns q g total gate charge v s1s2 = 10 v, i s1s2 = 1 a, v g1s1 = 4.5 v, v g2s2 = 0 v 17 24 nc q gs gate to source1 gate charge 1.9 nc q gd gate to source2 ?miller? charge 5.4 nc i fss maximum continuous source1 to source2 diode forward current 1 a v fss source1 to source2 diode forward voltage v g1s1 = 0 v, v g2s2 = 4.5 v, i fss = 1 a (note 2) 0.6 1.2 v a. 62 c/w when mounted on a 1 in 2 pad of 2 oz copper. b. 257 c/w when mounted on a minimum pad of 2 oz copper. notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 us, duty cycle < 2.0%. 3. the diode connected between the gate and source serves only protection against esd. no gate overvoltage rating is implied.
FDZ1323NZ common drain n-ch annel 2.5 v powertrench ? wl-csp mosfet www.fairchildsemi.com 3 ?2013 fairchild semiconductor corporation FDZ1323NZ rev.c7 typical characteristics t j = 25c unless otherwise noted figure 1. 0.0 0.2 0.4 0.6 0 10 20 30 40 pulse duration = 80 p s duty cycle = 0.5% max v g2s2 = 4.5 v i s1s2 , source1 to source2 current (a) v s1s2 , source1 to source2 voltage (v) v g1s1 = 2 v v g1s1 = 2.5 v v g1s1 = 3.1 v v g1s1 = 3.8 v v g1s1 = 4.5 v on-region characteristics figure 2. 0.00.20.40.60.81.0 0 10 20 30 40 v s1s2 , source1 to source2 voltage (v) i s1s2 , source1 to source2 current (a) pulse duration = 80 p s duty cycle = 0.5% max v gs = 4.5 v v gs = 3.8 v v gs = 3.1 v v gs = 2.5 v v gs = 2 v o n - r e g i o n c h a r a c t e r i s t i c s figure 3. 0 10203040 0.5 1.0 1.5 2.0 v g1s1 = 4.5 v v g1s1 = 3.1 v v g1s1 = 2 v pulse duration = 80 p s duty cycle = 0.5% max v g2s2 = 4.5 v normalized source1 to source2 on-resistance i s1s2 , source1 to source2 current (a) v g1s1 = 2.5 v v g1s1 = 3.8 v normalized on-resistance vs source1 to source2 current and gate voltage figure 4. 0 10203040 0.5 1.0 1.5 2.0 normalized source1 to source2 on-resistance i s1s2 , source1 to source2 current (a) v gs = 4.5 v v gs = 3.1 v v gs = 2 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 2.5 v v gs = 3.8 v normalized on-resistance vs source1 to source2 current and gate voltage f i g u r e 5 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i s1s2 = 1 a v gs = 4.5 v normalized source1 to source2 on-resistance t j , junction temperature ( o c ) vs junction temperature figure 6. 1.01.52.02.53.03.54.04.5 0 10 20 30 40 50 60 t j = 25 o c t j = 125 o c i s1s2 = 1 a r s1s2(on) , source1 to source2 on-resistance ( m : ) v gs , gate to source voltage (v) pulse duration = 80 p s duty cycle = 0.5% max o n r e s i s t a n c e v s g a t e t o source voltage
FDZ1323NZ common drain n-ch annel 2.5 v powertrench ? wl-csp mosfet www.fairchildsemi.com 4 ?2013 fairchild semiconductor corporation FDZ1323NZ rev.c7 figure 7. 0.5 1.0 1.5 2.0 0 10 20 30 40 t j = 150 o c v s1s2 = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i s1s2 , source1 to source2 current (a) v gs , gate to source voltage (v) transfer characteristics figure 8. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.1 1 10 100 t j = -55 o c t j = 25 o c t j = 150 o c v g1s1 = 0 v, v g2s2 = 4.5 v i fss , source1 to source2 forward current (a) v fss , body diode forward voltage (v) s o u r c e 1 t o s o u r c e 2 d i o d e forward voltage vs source current figure 9. 048121620 0.0 1.5 3.0 4.5 v g2s2 = 0 v i s1s2 = 1 a v s1s2 = 12 v v s1s2 = 8 v v g1s1 , gate1 to source1 voltage (v) q g , gate charge (nc) v s1s2 = 10 v gate charge characteristics figure 10. 0.1 1 10 20 100 1000 5000 f = 1 mhz v gs = 0 v capacitance (pf) v s1s2 , source1 to source2 voltage (v) c rss c oss c iss c a p a c i t a n c e v s s o u r c e 1 to source2 voltage figure 11. 03691215 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 v s1s2 = 0 v t j = 25 o c t j = 125 o c v gs , gate to source voltage (v) i g , gate leakage current (a) g a t e l e a k a g e c u r r e n t vs gate to source voltage figure 12. 0.01 0.1 1 10 100 0.01 0.1 1 10 50 curve bent to measured data 1 s 10 ms dc 10 s 100 ms 1 ms i s1s2 , source1 to source2 current (a) v s1s2 , source1 to source2 voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 257 o c/w t a = 25 o c f orw ard bi as safe operating area typical characteristics t j = 25c unless otherwise noted
FDZ1323NZ common drain n-ch annel 2.5 v powertrench ? wl-csp mosfet www.fairchildsemi.com 5 ?2013 fairchild semiconductor corporation FDZ1323NZ rev.c7 figure 13. 10 -3 10 -2 10 -1 10 0 10 1 100 1000 0.4 1 10 100 single pulse r t ja = 257 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) single pulse maximum power dissipation 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 single pulse r t ja = 257 o c/w ( note 1b ) duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a figure 14. junction-to-ambient transient thermal response curve typical characteristics t j = 25c unless otherwise noted
FDZ1323NZ common drain n-ch annel 2.5 v powertrench ? wl-csp mosfet www.fairchildsemi.com 6 ?2013 fairchild semiconductor corporation FDZ1323NZ rev.c7 pin definations: product specific dimensions: gate source1 source2 b1, b2 a1, c1 a2, c2 dexy 2.3 mm 1.3 mm 0.315 mm 0.49 mm dimensional outline and pad layout package drawings are provided as a service to customers cons idering fairchild components. dr awings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package sp ecifications do not expand the terms of fairchild's worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/package/ packagedetails.html?id=pn_ucbea-006
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