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FEDL22594-04 issue date: dec. 9. 2014 ml22594-xxxmb 4-channel mixing speech synthesis lsi wi th built-in mask rom for automotive 1/73 general description the ml22594-xxx is 4-channel mixing speech synthesis lsis with built-in mask rom for voice data. these lsis incorporate into them an hq-adpcm decoder th at enables high sound quality, 16-bit d/a converter, low-pass filter, 1.0 w monaural speaker amplifier for dr iving speakers , and over-current detectible function for speaker pins. and the high quality and a long time sound regeneration is possible by using the voice regeneration which the outside rom was used for. since functions necessary for voice outp ut are all integrated into a single chip, a system can be upgraded with audio features by only using one of these lsis. ? capacity of internal memory and the maximum voice production time (when hq-adpcm 1 method used) maximum voice production time (sec) product name rom capacity f sam = 8.0 khz f sam = 16.0 khz f sam = 32.0 khz 6 mbits(internal) 243 121 60 ml22594- xxx 128 mbits(exteranal) 5240 2620 1310 features ? rom capacity: internal 6mbits, external 128mbits (max) ? speech synthesis method: can be specified for each phrase. hq-adpcm / 8-bit non-linear pcm / 8-bit pcm / 16-bit pcm ? sampling frequency: can be specified for each phrase. 12.0/24.0/48.0 khz, 8.0/16.0/32.0 khz, 6.4/12.8/25.6 khz ? built-in low-pass filter and 16-bit d/a converter ? built-in speaker driver amplifier: 1.0 w, 8 ? (at dv dd = 5 v) (with over-current detectible function for speaker pins) ? external analog voice input (built-in analog mixing function) ? cpu command interface: clock synchronous serial interface ? maximum number of phrases: 1024 phrases, from 000h to 3ffh ? edit rom ? volume control: cvol command: adjustable through 32 levels (including off) avol command: adjustable through 50 levels (including off) ? repeat function: loop command ? channe mixing function: 4 channels ? power supply voltage detection function: can be controlled at six levels from 2.7 to 4.0 v (including the off setting) ? source oscillation frequency: 4.096 mhz ? power supply voltage: 4.5 to 5.5 v ? operating temperature range: ?40 ? c to +105 ? c 2 ? package: heat sink type 30-pin plastic ssop(p-ssop30-56-0.65-z6k) ? product name: ml22594-xxxmb (?xxx? denotes rom code number) 1 hq-adpcm is a high sound quality audio compression technology of "ky's". ? ? ? is a registered trademark of nation al universities corporate kyushu institute of technology 2 the limitation on the operation time changes by the using condition. (refer to page69)
the table below summarizes the differences between the exsisting speech synthesis lsis (ml225xg and ml22q573) and the ml22594. item ml22q573 ml2257x ml22q553 ml22594 cpu interface serial serial ? ? rom type flash mask ? mask rom capacity 4 mbits 2/4 mbits ? 6 mbits external rom interface no ? ? serial playback method hq-adpcm 8-bit straight pcm 8-bit non-linear pcm 16-bit straight pcm ? ? ? maximum number of phrases 1024 ? ? 1024 (internal512 / external512) sampling frequency (khz) 6.4/8.0/12.0/ 12.8/16.0/24.0/ 25.6/32.0/48.0 ? ? ? clock frequency ? ? ? ? d/a converter 16-bit voltage-type ? ? ? low-pass filter fir interpolation filter (high-pass interpolation) ? ? ? speaker driving amplifier built-in 1.0 w (8 ? , dv dd = 5 v) ? ? ? over-current detectible function for speaker pins ? ? yes ? simultaneous sound production function (mixing function) 4-channel ? ? ? edit rom ? ? ? ? volume control 32 levels ? ? ? silence insertion ? ? ? ? repeat function ? ? ? ? external analog input yes ? ? ? external speech data input no ? ? ? interval at which a seam is silent during continuous playback ? ? ? ? power supply voltage 2.7 v to 5.5 v ? 4.5 v to 5.5 v ? ambient temperature -40 bc to 105 b c ?? ? ? package 30-pin ssop ? ? ?
FEDL22594-04 ml22594-xxx 3/73 block diagram the block diagrams of the ml22594-xxx are shown below. block diagram of ml22594-xxx timing controller i/o interface address controller spm resetb csb sck si so cbusyb status err diph osc xtb xt s pv dd s pgnd pll pcm synthesizer lpf(cvol) 16bit dac sp-amp (avol) spp ain dv dd dgnd v ddl sg testi1 cmd analyzer 6mbits maskrom serial rom interface esck eso esi iov dd ecsb flw
FEDL22594-04 ml22594-xxx 4/73 pin configuration (top view) ml22594-xxx 30-pin plastic ssop nc unused pin ain sg nc dv dd dgnd v ddl diph status err csb sck si so cbusyb dgnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 spv dd spgnd spp spm esi eso esck ecsb testi1 flw resetb iovdd dv dd xt xtb 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEDL22594-04 ml22594-xxx 5/73 pin description (1) pin symbol i/o attribute description attribute initial value 1 ain i ? speaker amplifier input pin. analog 0 2 sg o ? built-in speaker amplifier?s re ference voltage output pin. connect a capacitor of 0.1 ? f or more between this pin and dgnd. analog 0 3 nc ? ? nc(unused) pin analog 0 4,18 dv dd ? ? digital power supply pin. connect a bypass capacitor of 10 ? f or more between this pin and dgnd. power ? 5,15 dgnd ? ? digital ground pin gnd ? 6 v ddl o ? 2.5 v regulator output pin. acts as an internal power supply (for logic). connect a capacitor of 10 ? f or more between this pin and dgnd. power 0 7 diph i positive serial interface switching pin. pin for choosing between rising edges and falling edges as to the edges of the sck pulses used for shifting serial data input to the si pin into the inside of the lsi. when this pin is at a ?l? level, si input data is shifted into the lsi on the rising edges of the sck clock pulses and a status signal is output from the so pin on the falling edges of the sck clock pulses. when this pin is at a ?h? level, si input data is shifted into the lsi on the falling edges of the sck clock pulses and a status signal is output from the so pin on the rising edges of the sck clock pulses. digital 0 8 status o positive channel status output pin. outputs the busyb or ncr signal for each channel by inputting the outstat command. digital 1 9 err o positive error output pin. outputs a ?h? level if an error occurs. digital 0 10 csb i negative chip select pin. a ?l? level on this pin accepts the sck or si inputs. when this pin is at a ?h? level, neither the sck nor si signal is input to the lsi. digital 1 11 sck i positive synchronous serial clock input pin. clk 0 12 si i ? synchronous serial data input pin. when the diph pin is at a ?l? le vel, data is shifted in on the rising edges of the sck clock pulses. when the diph pin is at a ?h? le vel, data is shifted in on the falling edges of the sck clock pulses. digital 0 13 so o positive channel status serial output pin. outputs a status signal on the falling edges of the sck clock pulses when the diph pin is at a ?l? level; outputs a status signal on the rising edges of the sck clock pulses when the diph pin is at a ?h? level. when the csb pin is at a ?l? leve l, the status of each channel is output serially in sync with the sck clock. when the csb pin is at a ?h? level, this pin g oes into a high impedance state. digital hi-z
FEDL22594-04 ml22594-xxx 6/73 pin description (2) pin symbol i/o attribute description attribute initial value (*1) 14 cbusyb o negative command processing status signal output pin. this pin outputs a ?l? level during command processing. be sure to enter commands with the cbusyb pin driven at a ?h? level. digital 0 (*2) 16 xtb o negative connects to a crystal or a ceramic resonator. when using an external clock, leave this pin open. if a crystal or a ceramic resonator is used, connect it as close to the lsi as possible. clk 1 17 xt i positive connects to a crystal or a ceramic resonator. a feedback resistor of around 1 m ? is built in between this xt pin and the xtb pin. when using an external clock, input the clock from this pin. if a crystal or a ceramic resonator is used, connect it as close to the lsi as possible. clk 0 19 io vdd i ? external rom interface power supply pin. use the power supply which is the same as the external rom. connect a bypass capacitor of 0.1 ? f or more between this pin and dgnd. analog 0 20 resetb i negative reset input pin. at ?l? level input, the lsi enter s the initial state. after a reset input, the entire circuit is stopped and enters a power down state. upon power-on, input a ?l? level to this pin. after the power supply voltage is stabilized, drive this pin at a ?h? level. this pin has a pull-up resistor built in. digital 0 21 flw i positive external rom interface disenable pin. when a ?h? level is inputted, the external rom interface is disenable. ?l? level is inputted, the external rom interface is enable. has a pull-down resistor built in. digital 0 22 testi1 i negative used as either an input pin for testing or a reset input pin for flash rewriting. has a pull-down resistor built in. digital 0 23 ecsb o negative external rom interface chip select pin. a ?l? level is external rom access. digital 1 24 esck o positive external rom interface serial clock output pin. digital 1 25 eso o positive external rom interface serial data output pin. digital 1 26 esi i positive external rom interface serial data input pin. has a pull-down resistor built in. digital 0 27 spm o ? output pin of the built -in speaker amplifier. analog hi-z 28 spp o ? output pin of the built -in speaker amplifier. can be configured as an aout amplifier output by command setting. analog 0 29 spgnd ? ? speaker amplifier ground pin. gnd ? 30 spv dd ? ? speaker amplifier power supply pin. connect a bypass capacitor of 10 ? f or more between this pin and spgnd. power ? *1: indicates the initial value at reset input or during power down. *2: when ml22594 is reset, this pin is "l" level, when ml22594 is power-down, this pin is "h" level.
FEDL22594-04 ml22594-xxx 7/73 absolute maximum ratings dgnd = spgnd = 0 v, ta = 25 ?c parameter symbol condition rating unit power supply voltage dv dd spv dd ? ? 0.3 to +7.0 v input voltage v in ? ? 0.3 to dv dd +0.3 v power dissipation p d when the lsi is mounted on jedec 4-layer board. when spv dd = 5v 1000 mw applies to all pins except spm, spp, v ddl, and v ddr . 10 ma applies to spm and spp pins. 500 ma output short-circuit current i os applies to v ddl and v ddr pins. 50 ma storage temperature t stg ? ? 55 to +150 c recommended operating conditions dgnd = spgnd = 0 v parameter symbol condition range unit dv dd , spv dd power supply voltage dv dd spv dd ? 4.5 to 5.5 v io vdd power supply voltage io vdd ? 2.7 to 5.5 *1 v operating temperature top ? ? 40 to +105 c min. typ. max. master clock frequency f osc ? 3.5 4.096 4.5 mhz *1 : when external rom in terface does not be used, io vdd can be set in 0v.
FEDL22594-04 ml22594-xxx 8/73 electrical characteristics dc characteristics dv dd = spv dd = 4.5 to 5.5 v, iov dd = 2.7 to 5.5 v, dgnd = spgnd = 0 v, ta = ? 40 to +105c parameter symbol condition min. typ. max. unit ?h? input voltage1(*1) v ih1 ? 0.8 ? dv dd ? dv dd v ?h? input voltage2(*2) v ih2 ? 0.8 ? iov dd ? iov dd v ?l? input voltage1(*1) v il1 ? 0 ? 0.2 ? dv dd v ?l? input voltage2(*2) v il2 ? 0 ? 0.2 ? iov dd v ?h? output voltage 1 (*3) v oh1 i oh = ? 1 ma dv dd ? 0.4 ? ? v ?h? output voltage 2 (*4) v oh2 i oh = ? 50 a dv dd ? 0.4 ? ? v ?h? output voltage 3 (*5) v oh3 i oh = ? 1 ma iov dd ? 0.4 ? ? v ?l? output voltage 1 (*3) v ol1 i ol = 2 ma ? ? 0.4 v ?l? output voltage 2 (*4) v ol2 i ol = 50 a ? ? 0.4 v ?l? output voltage 3 (*5) v ol3 i ol = 2 ma ? ? 0.4 v i ooh voh = dv dd (csb=?h?) ? ? 10 a output leakage current1 (*6) i ool vol = dgnd (csb=?h?) ? 10 ? ? a i ooh voh = iov dd (flw=?h?) ? ? ? 10 a output leakage current2 (*7) i ool vol = dgnd (flw=?h?) ? 10? ? ? a ?h? input current 1 (*8) i ih1 v ih = dv dd ? ? 10 a ?h? input current 2 (*9) i ih2 v ih = dv dd 0.8 5 20 a ?h? input current 3 (*10) i ih3 v ih = dv dd 20 100 400 a ?h? input current 4 (*11) i ih4 v ih = iov dd 2 100 400 a ?l? input current 1 (*12) i il1 v il = dgnd ?10 ? ? a ?l? input current 2 (*9) i il2 v il = dgnd ?20 ? 5.0 ? 0.8 a ?l? input current 3 (*13) i il3 v il = dgnd ?400 ?100 ?20 a ? ? 54(*15) supply current during playback 1 i dd1 f osc = 4.096 mhz fs=48khz, f=1khz, when 16bitpcm playback no output load ? ? 1(*16) ma ? ? 50(*15) supply current during playback 2 (*14) i dd2 f osc = 4.096 mhz fs=48khz, f=1khz, when 16bitpcm playback using external rom no output load ? ? 5(*16) ma ? ? 47(*15) supply current during playback 3 i dd3 f osc = 4.096 mhz during silence playback no output load ? ? 1(*16) ma ta = ? 40 to +55c ? ? 10(*17) a power-down supply current i dds1 ta = ? 40 to +105c ? ? 20(*17) a (*1) applies to the diph, csb, sck, si, resetb, testi1 and xt pins. (*2) applies to the flw, esi pins. (*3) applies to the status, err, so and cbusyb pins. (*4) applies to the xtb pin. (*5) applies to the ecsb, esck and eso pins. (*6) applies to the so pin. (*7) applies to the ecsb, esck and eso pins (*8) applies to the diph, csb, sck, si and resetb pins. (*9) applies to the xt pin. (*10) applies to the testi1 pin. (*11) applies to the flw and esi pins. (typ. is 5.0v condition) (*12) applies to the diph, csb, sck, si, testi1, flw and esi pins. (*13) applies to the resetb pin. (*14) ecsb, esck and eso pins load capacitance = 45pf(max) (*15) supply current which added dv dd and spv dd . (*16) supply current which applies iov dd . (*17) supply current which added dv dd , spv dd and iov dd.
FEDL22594-04 ml22594-xxx 9/73 analog section characteristics dv dd = spv dd = 4.5 to 5.5 v, iov dd = 2.7 to 5.5 v, dgnd = spgnd = 0 v, ta = ? 40 to +105c parameter symbol condition min. typ. max. unit ain input resistance r ain input gain: 0 db 10 20 30 k ? ain input voltage range v ain ? ? spv dd 2/3 vp-p line output resistance r la at 1/2spv dd output ? ? 100 ? line output load resistance r la at spgnd10k ? load 10 ? ? k ? line output voltage range v ao at spgnd10k ? load spv dd /6 ? spv dd 5/6 v sg output voltage v sg ? 0.95x spv dd /2 spv dd /2 1.05x spv dd /2 v sg output resistance r sg ? 57 96 135 k ? spm, spp output load resistance r lsp ? 6 8 ? ? speaker amplifier output power p spo spv dd = 5.0v, f = 1 khz r spo = 8 ? , thd Q 10% 800 1000 ? mw output offset voltage between spm and spp with no signal present v of spin?spm gain = 0 db with a load of 8 ? ? 50 ? +50 mv regulator output voltage v ddl v ddr output load current = ? 35 ma 2.25 2.5 2.75 v
FEDL22594-04 ml22594-xxx 10/73 ac characteristics (1) dv dd = spv dd = 4.5 to 5.5 v, iov dd = 2.7 to 5.5 v, dgnd = spgnd = 0 v, ta = ? 40 to +105c parameter symbol condition min. typ. max. unit master clock duty cycle f duty ? 40 50 60 % resetb input pulse width t rst ? 10 ? ? ? s reset noise rejection pulse width t nrst resetb pin ? ? 0.1 ? s noise rejection pulse width t ninp csb, sck, and si pins ? ? 5 ns command input in terval time1 t int f osc = 4.096 mhz at stop/sloop/cloop/ vol command input after status read 10 ? ? ? s command input in terval time2 t intc f osc = 4.096 mhz after input first command at two-time command input mode 0 ? ? ? s command input enable time t cm f osc = 4.096 mhz during continuous playback at sloop input ? ? 10 ms at pup command input cbusyb ?l? level output time t pup 4.096 mhz at external clock input ? ? 4 ms at amode command input cbusyb ?l? level output time *3 t pupa1 4.096 mhz at external clock input pop = ?0? daen = ?0? ??1? or spen = ?0? ??1? 39 41 43 ms at amode command input cbusyb ?l? level output time t pupa2 4.096 mhz at external clock input pop = ?1? daen = ?0? ??1? (spen = ?0?) 72 74 76 ms at amode command input cbusyb ?l? level output time t pupa3 4.096 mhz at external clock input pop = ?0? daen = ?0? ??1? (spen = ?0?) 32 34 36 ms at pdwn command input cbusyb ?l? level output time t pd f osc = 4.096 mhz ? ? 10 ? s at amode command input cbusyb ?l? level output time *3 t pda1 4.096 mhz at external clock input pop = ?0? daen = ?1? ??0? or spen = ?1? ??0? 106 108 110 ms at amode command input cbusyb ?l? level output time t pda2 4.096 mhz at external clock input pop = ?1? daen = ?1? ??0? (spen = ?0?) 143 145 147 ms
FEDL22594-04 ml22594-xxx 11/73 at amode command input cbusyb ?l? level output time t pda3 4.096 mhz at external clock input pop = ?0? daen = ?1? ??0? (spen = ?0?) 103 105 107 ms cbusyb ?l? level output time 1 (*1) t cb1 f osc = 4.096 mhz ? ? 10 ? s cbusyb ?l? level output time 2 (*2) t cb2 f osc = 4.096 mhz ? ? 3 ms cbusyb ?l? level output time 3 (*4) t cb3 f osc = 4.096 mhz ? ? 200 ? s note: output pin load capacitance = 45 pf (max.) *1: applies to cases where a command is input, ex cept after the pup, pdwn, play, start or amode command input. *2: applies to cases where the play or start command is input. *3: when fad3-0 is initial value (8h) *4: applies to cases where the stop command is input
FEDL22594-04 ml22594-xxx 12/73 ac characteristics (2) cpu serial interface dv dd = spv dd = 4.5 to 5.5 v, iov dd = 2.7 to 5.5 v, dgnd = spgnd = 0 v, ta = ? 40 to +105c parameter symbol condition min. typ. max. unit sck input enable time from csb fall t esck ? 100 ? ? ns sck hold time from csb rise t csh ? 100 ? ? ns data floating time from csb rise t doz r l = 3 k ? ? ? 100 ns data setup time from sck rise t dis1 diph = ?l? 50 ? ? ns data hold time from sck rise t dih1 diph = ?l? 50 ? ? ns data output delay time from sck rise t dod1 r l = 3 k ? ? ? 90 ns data setup time from sck fall t dis2 diph = ?h? 50 ? ? ns data hold time from sck fall t dih2 diph = ?h? 50 ? ? ns data output delay time from sck rise t dod2 r l = 3 k ? ? ? 90 ns sck ?h? level pulse width t sckh ? 100 ? ? ns sck ?l? level pulse width t sckl ? 100 ? ? ns cbusyb output delay time from sck rise t dbsy1 diph = ?l? ? ? 90 ns cbusyb output delay time from sck fall t dbsy2 diph = ?h? ? ? 90 ns note: output pin load capacitance = 45 pf (max.) ac characteristics (3) external rom serial interface dv dd = spv dd = 4.5 to 5.5 v, iov dd = 2.7 to 5.5 v, dgnd = spgnd = 0 v, ta = ? 40 to +105c parameter symbol condition min. typ. max. unit esck input enable time from ecsb fall edge t pcss f osc = 4.096 mhz 50 ? ? ns ? esck input hold time from ecsb rise edge t pcsh f osc = 4.096 mhz 50 ? ? ns data setup time from esck rise edge t pdis f osc = 4.096 mhz 10 ? ? ns data hold time from esck rise edge t pdih f osc = 4.096 mhz 10 ? ? ns ? data output delay time fr om esck rise edge t pdod f osc = 4.096 mhz ? ? 5 ns ? esck clock frequency t esckf f osc = 4.096 mhz 16.0 16.384 16.5 mhz esck ?h? level pulse width t psckh f osc = 4.096 mhz 26 ? ? ns ? esck ?l? level pulse width t psckl f osc = 4.096 mhz 26 ? ? ns ? data output delay time from flw rise edge. t eflh ? ? ? 1 ms data output delay time from flw fall edge. t efhl ? ? ? 1 ms note: output pin load capacitance = 45 pf (max.)
FEDL22594-04 ml22594-xxx 13/73 timing diagrams cpu serial interface data input timing (when diph = ?l?) cpu serial interface data input timing (when diph = ?h?) cpu serial interface data outp ut timing (when diph = ?l?) cpuserial interface data output timing (when diph = ?h?) csb sck si vih vil vil vih vil vih t es c k t di s1 t di h1 t sckh t sckl t csh cbusyb t dbsy1 vo l voh csb sc k si vih vil vil vih vil vih t esck t dis2 t dih 2 t sckl t sc kh t csh c busyb t dbsy 2 vol vo h csb sc k vih vil vil vih t es c k t sckh t sckl t csh cbusyb t dbsy1 vo l voh so vil vih t doz t do d1 csb sc k vih vil vil vih t esck t sckl t sc kh t csh c busyb t dbsy 2 vol vo h so vil vih t doz t dod2
FEDL22594-04 ml22594-xxx 14/73 external rom serial interf a ce data output timing ecsb esck esi vih vil vil vih vil vih t ecss t edis t edih t esckh t esckl t ecsh eso t edod vol voh t esckf
FEDL22594-04 ml22594-xxx 15/73 power-on timing power shut-down timing spv dd vih vil t rst 5 v resetb status power down oscillation is stopped after power-on. be sure to power-on iovdd after dvdd/spvdd. when iovdd isn't used, it is possible that it is fixed in 0v. be sure to set llevel the resetb pin before the first command input. dv dd 5 v iov dd 3.3 v 10% 90 % spv dd iov dd status be sure to power shut-down dvdd/spvdd after iovdd. when iovdd isn't used, it is possible that it is fixed in 0v. dv dd 10% 90% 5v power down 5v 90% 3.3v
FEDL22594-04 ml22594-xxx 16/73 reset input timing no te: the same timing applies in cases where the reset signal is input during waiting for command. t rs t resetb st atu s power down playing xt ? xtb oscillating oscillation stopped v dd l ? sg gnd spm gnd spp hi - z
FEDL22594-04 ml22594-xxx 17/73 power-up timing power-down timing voh vol t pup csb status oscillation stabilized performing reset processing sck si ncrn busybn power down xt ? xtb oscillating oscillation stopped voh vol awaiting command ( internal ) ( internal ) voh vol cbusyb vo h vo l csb statu s command is being processed power down sck si ncrn busybn awaiting command xt ? xtb osc illat in g oscillation stopped vo h vo l ( internal ) ( internal ) vo h vo l t pd cbus y b
FEDL22594-04 ml22594-xxx 18/73 playback start timing by the play command * 1: length of the ?l? interval of busybn is = t cb2 + voice production time length. playback stop timing vo h vol csb status command is being processed playing sck si ncrn bus y bn c omm and s ta ndby spm 1/2vdd spp 1/2vdd vo h vol ad d r es s is be in g cont rolled awaiting command awaiting command ( *1 ) play command 1 st byte play command 2 nd byte ( internal ) ( internal ) vo h vol cbus y b t cb1 t cb2 voh vol csb status awaiting command sck si ncrn busybn spm 1/2vdd spp 1/2vdd voh vol playing stop command ( internal ) ( internal ) voh vol cbus y b t cb3 command is being processed
FEDL22594-04 ml22594-xxx 19/73 continuous playback timing by the play command silence insertion timing by the muon command *1: the ?l? level period of the ncr pin during playback or silence insertion operation varies depending on the timing at which the muon command is input. vo h vo l csb statu s pl ayi ng ph rase 1 sck si ncrn bus y bn spm 1/2vdd spp 1/2vdd address is being controlled aw ai ti ng co mman d playing phrase 2 t cb1 t cm ( internal ) ( internal ) vo h vo l cbusyb t cb2 t cb1 pl ay command 1 st byte play command 2 nd byte pl ay command 2 nd byte voh vol csb status playing sck si ncrn busybn spm 1/2vdd spp 1/2vdd address is being controlled awaiting command silence is being inserted t cb1 playing waiting for silence insertion to be finished t cb1 t cm voh vol cbusyb t cb2 (*1) (*1) ( internal ) ( internal ) t cb1 t cb1 muon command 1 st byte play command 2 nd byte muon command 2 nd byte play command 1 st byte play command 2 nd byte t cm
FEDL22594-04 ml22594-xxx 20/73 repeat playback set/release timing by the sloop and cloop commands timing of volume change by the cvol com mand vo h vol csb status playing sck si ncrn busybn spm 1/2vdd spp 1/2vdd ad dr ess is be ing co ntrolled a waiting command awaiting command play command 2 nd by te sl oop co mman d pla ying a ddr ess is b eing cont rolled cloo p com mand t int comma nd is b eing pr oce sse d vih vil voh vol cbusyb t cb2 t cm ( internal ) ( internal ) voh vol csb status awaiting command sck si ncrn busybn command is being processed t cb1 awaiting command cvol command 1 st b y te voh vol voh vol cbusyb ( internal ) ( internal ) t cb1 command is being processed awaiting command cvol command 2 nd b y te
FEDL22594-04 ml22594-xxx 21/73 external rom interf ace at flw rise external rom int erface at flw fall voh vol flw status hi-z psck psi output voh vol voh vol t eflh pcsb vih vil hi-z hi-z hi-z voh vol flw status output psck psi hi-z voh vol voh vol t efhl pcsb vih vil hi-z hi-z hi-z
FEDL22594-04 ml22594-xxx 22/73 functional description synchronous serial interface the csb, sck, si, and so pins are used to input various commands or read the status of the device. for command input, after inputting a ?l? level to the csb pin, input data through the si pin with msb first in sync with the sck clock signal. the data input through th e si pin is shifted into the lsi in sync with the sck clock signal, then the command is executed at the eighth pulse of the rising or falling edge of the sck clock. for status reading, after a ?l? level is input to the csb pin, stauts is output from the so pin in sync with the sck clock signal. choosing between rising edges and falling edges of the clock pulses input through the sck pin is determined by the signal input through the diph pin: - when the diph pin is at a ?l? level, the data input through the si pin is shifted into the lsi on the rising edges of the sck clock pulses and a status signal is output from the so pin on the falling edges of the sck clock pulses. - when the diph pin is at a ?h? level, the data input through the si pin is shifted into the lsi on the falling edges of the sck clock pulses and a status signal is output from the so pin on the rising edges of the sck clock pulses. it is possible to input commands even with the csb pin tied to a ?l? level. howeve r, if unexpected pulses caused by noise etc. are induced through the sck pin, sck clock pulses are incorrectly counted, causing a failure in normal input of command. in addition, the serial interface can be brought back to its initial state by driving the csb pin at a ?h? level. when the csb pin is at ta ?l? level, the status of each channel is output serially in sync with the sck clock. when the csb pin is at a ?h? level, the so pin goes into a high impedance state. csb sck si ? command input timing: sck rising edge operation (when diph pin = ?l? level) d7 d6 d5 d4 d3 d2 d1 d0 (msb) (lsb ) csb sck si ? command input timing: sck falling edge operation (when diph pin = ?h? level) d7 d6 d5 d4 d3 d2 d1 d0 (msb) (lsb ) csb sck ? c om ma n d o u tpu t t imi ng : sc k fa lling edg e o pe ra tio n (w he n d iph pin = ?l ? le vel) (msb) (lsb ) csb sck command output timing: sck rising edge operation (when diph pin = ?h? level) (msb) (lsb ) so d7 d6 d5 d4 d3 d2 d1 d0 so d7 d6 d5 d4 d3 d2 d1 d0
FEDL22594-04 ml22594-xxx 23/73 to prevent malfunction caused by serial interface pin noise, the ml2 2594 is provided with the two-time command input mode, where the user inputs one comma nd two times. use the pup command to set the two-time command input mode. for the method of setting the two-time command input mode, see the the section on ?1. pup command? described later. in two-time command input mode, input one command two times in succession. then, the command becomes valid only when the data input first matches the data input second. after the first data input, if a data mismatch occurs when the second data is input, a ?h? level is output from the err pin. an error, if occurred, can be cleared by the ercl command. vo h vol csb statu s co mma nd is b ein g pr ocesse d pla yi ng sck si ncrn bus y bn a waiting command spm 1/2vdd spp 1/2vdd vo h vol a ddr ess is bei ng controlled a waiting command a waiting command play command 1 st byte play command 2 nd byte ( internal ) ( internal ) vo h vol cbus y b t cb2 a waiting command play command 1 st byte t cb1 play command 2 nd byte a waiting command command is being processed com man d is be ing pro cesse d
FEDL22594-04 ml22594-xxx 24/73 voice synthesis algorithm the ml22594 contains four algorithm types to match the characteristic of playback voice: hq-adpcm algorithm, 8-bit straight pcm algorithm, 8-bit non-lin ear pcm algorithm, and 16-b it straight pcm algorithm. key feature of each al gorithm is described in the table below. voice synthesis algorithm feature hq-adpcm algorithm that enables high sound quality and high compression, which have been achieved by the improved 4-bit adpcm that uses variable bit-length coding. 8-bit nonlinear pcm algorithm that plays back mid-range of waveform as 10-bit equivalent voice quality. 8-bit pcm normal 8-bit pcm algorithm 16-bit pcm normal 16-b it pcm algorithm
FEDL22594-04 ml22594-xxx 25/73 voice control area (fixed 64kbits) voice control area (fixed 64kbits) memory allocation and creating voice data th e rom is partitioned into four data areas: voice (i.e., phrase) control area, test ar ea, voice area, and edit rom area. the voice control area manages the rom?s voice data. it contains data for controlling the start/stop addresses of voice data for 1024 phrases(512phrases for internal rom, 512phases for external rom), use/non-use of the edit rom function and so on. the test area contains data for testing. the voice area contains actual waveform data. the edit rom area contains data for effective use of voice data. for the details, refer to the section on ?edit rom function.? no edit rom area is available unless the edit rom is used. the rom data is created using a dedicated tool. playback time and memory capacity the playback time depends on the memory capacity, sampling frequency, and playback method. the equation showing the relationship is given below. the equation below gives the playback time when the edit rom function is not used. example: let the sampling frequency be 16 khz and hq-adpcm algorithm. then the playback time is approx. 80 seconds, as shown below. 1.024 ? (4096 ?? 64) (kbits) 16 (khz) ? ? 80 (sec) 1.024 ? (memory capacity ? 64) (kbits) sampling frequency (khz) ? bit length playback time = (sec) test area edit rom area depends on creation of rom data 0x00000 0x01fff 0x02000 0xbffff 0x0206f 0x02070 filter area configuration of internal rom data(6mbit) 0x000000 0x001fff 0xffffff configuration of external rom data(128mbit) edit rom area depends on creation of rom data 0x021af voice area 0x021b0 test area 0x002000 0x00206f 0x002070 filter area 0x0021af 0x0021b0 voice area
FEDL22594-04 ml22594-xxx 26/73 edit rom function w ith the edit rom function, multiple phrases can be pl ayed in succession. the fo llowing functions can be configured using the edit rom function: ? continuous playback: there is no limit to the con tinuous playback count that can be specified. it depends on the memory capacity only. ? silence insertion: 20 to 1024 ms using the edit rom function enables an effec tive use of the memory capacity of voice rom. below is an example of the rom configuration in the case of using the edit rom function. phrase 1 phrase 2 phrase 3 phrase 4 a d a c e b e c phrase 5 d d d b a d b e b d silence a b c d e address control area editing area examples of phrases using the edit rom function example of rom data where the contents above are stored in rom
FEDL22594-04 ml22594-xxx 27/73 mixing function the ml22594 can perform simultaneous mixing of four channels. it is possible to specify fadr, play, stop, and cvol for each channel separately. ? precautions for waveform clamp at the time of channel mixing if channel mixing is done, the possibility of an occurrence of a clamp increases from the mixing calculation point of view. if it is known beforehand that a clamp will occur, then adjust the sound volume of each channel using the vol command. ? mixing of different sampling frequency it is not possible to perform channel mixing by a different sampling frequency group. when performing channel mixing, the sampling frequency group of the first playback channel is selected. therefore, note that if channel mixing is performed by a sampling frequency group other than the selected sampling frequency group, then the playback will not be of constant speed: some times faster and at other times slower. the available sampling groups for channel mixing by a different sampling frequency are listed below. 8.0 khz, 16.0 hz, 32.0 khz ? (group 1) 12.0 khz, 24.0 khz, 48 khz ? (group 2) 6.4 khz, 12.8 khz, 25.6 khz ? (group 3) figures below show cases where a phrase is played at a sampling frequency belonging to a different sampling frequency group. figure 1 case where a phrase is played at a sampling frequency belonging to a different sampling frequency group during playback on channels 1 and 2 played normally if not being played by other channel. channel 1 channel 2 fs = 16.0 khz fs = 25.6 khz (valid) end of channel 1 figure 2 case where a phrase is played at a sampling frequency belonging to a different sampling frequency group after playb ack is finished at the other channel channel 1 channel 2 fs 16.0khz fs 25.6khz fs 16.0khz invalid will be played as fs 12.8khz
FEDL22594-04 ml22594-xxx 28/73 over-current detectible f unction at speaker pins the o ver-current detectible function for the speaker pins detect a short between spp and spm, and a short between spp/spm and gnd. the over-current detectible function is effect ive on speaker power-up by the amode command. when the over-current is detected, the speaker amplifie r output pin(spp/spm) go to po wer-down forcibly, and a short error is informed by the err pin ?h?. in the case of error outbreak, please confirm a status of error by the rdstat command, stop playback, and set the speaker power-down by the amod e command. afterwards, please clear an error by the ercl command. if performing playback again, set the speaker power-up by the amode command, and next set the play command. however, when shorting to gnd is going on, even if the following operation is done, the speaker amplifier output pin(spp/spm) go to power-down forcibly, and the err pin becomes ?h?. (1)after setting power-down by the amode command , do power-up by the amode command (2)after detect a short error, when input ercl command without power-down operation of speaker amplifier by the amode command over - current detecti ble function for speaker pins hiz er r serial i/f pup spp spvdd spgnd spm spvdd spgnd analog powerdown s p eaker p owerdown analog powerup s p eaker p oweru p analog powerdown s p eaker p owerdown analog powerup s p eaker p oweru p over - current detecti ble function active status amode spkr_mode powerup amode spkr_mode powerdown amode spkr_mode p oweru p dvdd play pdwn pup over - current detecti ble function active er r serial i/f over - current detecti ble function operation flow ( exam p le ) detect a short ercl pup hiz analog powerdown speaker powerdown analog powerup speaker powerup analog powerup speaker powerdown analog powerdown speaker powerdown analog powerup speaker powerup amode spkr_mode p oweru p amode spkr_mode powerdown amode spkr_mode powerup spp spm status rdstat err read hiz spvdd spgnd spvdd spgnd over - current detecti ble function active over - current detecti ble function active
FEDL22594-04 ml22594-xxx 29/73 command list each c ommand is configured in 1-byte (8-bit) units. each of the amode, avol fadr, play, muon, and cvol commands forms one command by two bytes.be sure to input the following commands only. input each command with cbusyb set to a ?h? level. command d7 d6 d5 d4 d3 d2 d1 d0 description pup 0 0 0 0 0 0 0 wcm shifts the device currently powered down to a command wait state. also the two-time command input mode is set by this command. 0 0 0 0 0 1 hpf1 hpf0 amode 0 dag1 dag0 aig1 aig0 daen spen pop analog section control command. configures settings for power-up operation and analog input/output. selects the type of hpf. 0 0 0 0 1 0 0 0 avol ? ? av5 av4 av3 av2 av1 av0 analog mixing signal volume setting command. use the data of the 2nd byte to specify volume. 0 0 0 0 1 1 0 0 fad 0 0 0 0 fad3 fad2 fad1 fad0 sets the fade-in time in cases where the speaker amplifier is enabled by the amode command. pdwn 0 0 1 0 0 0 0 0 shifts the device from a command wait state to a power-down state. 0 0 1 1 c1 c0 f9 f8 fadr f7 f6 f5 f4 f3 f2 f1 f0 playback phrase specification command. can be specified for each channel. 0 1 0 0 c1 c0 f9 f8 play f7 f6 f5 f4 f3 f2 f1 f0 playback start command. use the data of the 2nd byte to specify a phrase number. can be specified for each channel. start 0 1 0 1 ch3 ch2 ch1 ch0 playback start command without phrase specification. used to start playback on multiple channels at the same time after phrases are specified with the fadr command. after a phrase is played with the play command, the same phrase can be played with this command. stop 0 1 1 0 ch3 ch2 ch1 ch0 playback stop command. can be specified for each channel.
FEDL22594-04 ml22594-xxx 30/73 command d7 d6 d5 d4 d3 d2 d1 d0 description 0 1 1 1 ch3 ch2 ch1 ch0 muon m7 m6 m5 m4 m3 m2 m1 m0 silence insertion command. use the data of the 2nd byte to specify the length of silence. can be specified for each channel. sloop 1 0 0 0 ch3 ch2 ch1 ch0 repeat playback mode setting command. the setting is enabled during playback. can be specified for each channel. cloop 1 0 0 1 ch3 ch2 ch1 ch0 repeat playback mode release command. when the stop command is input, repeat playback mode is released automatically. can be specified for each channel. 1 0 1 0 ch3 ch2 ch1 ch0 cvol ? ? ? cv4 cv3 cv2 cv1 cv0 volume setting command. use the data of the 2nd byte to specify volume. can be specified for each channel. rdstat 1 0 1 1 0 0 0 err status serial read command. this command reads the command status and the status of the fail safe function for each channel. outstat 1 1 0 0 0 busy/ncr c1 c0 status output command. this command outputs the command status of each channel from the status pin. 1 1 0 1 0 0 0 0 safe tm2 tm1 tm0 tsd1 tsd0 bld2 bld1 bld0 fail safe setti ng command. sets settings for power supply voltage detection, temperature detection, and monitoring time. ercl 1 1 1 1 1 1 1 1 this command clears error while the fail safe function is operating.
FEDL22594-04 ml22594-xxx 31/73 description of command functions 1. pup command ? command 0 0 0 0 0 0 0 wcm the pup command is used to shift the ml22594 from a power down st ate to a command waiting state. the ml22594 can only accept the pup command while it is in a power down state. therefore, in a power down state, the device will ignore any other command if entered. the ml22594 enters a power down state under any of the following conditions: 1) when power is turned on 2) at resetb input 3) when cbusyb go to a ?h? level af ter inputting the power down command the wcm bit is used to set the two-time command input mode. when set to ?1?, the command input thereafter will be processed in two-time command input mode and becomes valid only when the first data input matches the second one. wcm two-time command input mode 0 no (initial value) 1 yes the regulator starts operating after the pup command is entered. any command will be ignored if entered while oscillation is stabilized. however, if a ?l? leve l is input to the resetb pin, the lsi enters a power down state immediately. neither line output nor speaker output is enabled by the pup command. power up the analog section by the amode command. csb s tatus o sc illa tio n sta bilized sck si cbusyb power down xt ? xt b oscillating o s c ill atio n s to pp ed awaiting comm and t pup reset being processed
FEDL22594-04 ml22594-xxx 32/73 2. amode command ? command 0 0 0 0 0 1 hpf1 hpf0 1st byte 0 dag1 dag0 aig1 aig0 daen spen pop 2nd byte the amode command is used to configure vari ous settings for the analog section. if the pdwn command is input while the analog section is in the power-up state, the analog section enters a power down state under the setting conditions that were in effect when the analog section was powered up by the amode command. to perform a power-down operation using different conditions from those used at analog section power-up, set settings by the amode command. to change the setting of daen/spen while the analog sec tion is in the power-up state, first put the analog section into the power-down state and then put the analog section into the power-up state again by the amode command. the detailed command settings are shown below. each setting is initialized upon reset release or by the pup command. don?t input the stop command during the amode command is being proccessed (cbusyb=?l?). input the amode command for analog section into the po wer-down state before the pdwn command is input. the hpf1/hpf0 bits set the cut-off frequency of the hpf. hpf1 hpf0 cut-off frequency 0 0 off (initial value) 0 1 200 hz 1 0 300 hz 1 1 400 hz the pop bit specifies whether to suppress generation of ?pop? noise. - if the bit is ?0? (no pop noise suppression) and the da en bit is ?1?, the line output rises from the dgnd level to the sg level in about 35 ms, at which time the an alog section enters the powe r-up state. if the daen bit is ?0?, the line output falls from the sg level to the dgnd level in about 110 ms, at which time the analog section enters the power down state. - if the bit is ?1? (with pop noise suppression) and the daen bit is ?1?, the line output rises from the dgnd level to the sg level in about 90 ms, at which time the an alog section enters the powe r-up state. if the daen bit is ?0?, the line output falls from the sg level to the dgnd level in about 140 ms, at which time the analog section enters the power down state. pop pop noise suppression 0 no (initial value) 1 yes
FEDL22594-04 ml22594-xxx 33/73 ? when powering up the speaker amplifier setting values: pop bit = ?0?, daen and spen bits = ?0? ? ?1? ? when powering up the line amplifier (with pop noise suppression) setting values: pop bit = ?1?, daen bit = ?0? ? ?1? (spen bit = ?0?) voh vol csb status command is being processed awaiting command sc k si ncr busyb awaiting command voh vol command is being processed awaiting command amode command 1st byte amode command 2nd byte line out p ut gnd spm gnd 1/2spvdd spp hi-z 1/2spvdd voh vol cbusyb t cb1 t pupa1 ( internal ) ( internal ) ( internal ) 1/2dvdd voh vol csb sc k si ncr busyb voh vol amode command 1st byte amode command 2nd byte spp voh vol cbusyb t cb1 t pupa2 gnd 1/2dvdd (internal) (internal) (line output) status command is being processed awaiting command awaiting command awaiting command command is being processed pop noise suppressed
FEDL22594-04 ml22594-xxx 34/73 ? when powering up the line amplifier (without pop noise suppression) setting values: pop bit = ?0?, daen bit = ?0? ? ?1? (spen bit = ?0?) ? when putting the speaker amplifier into the power down state setting values: pop bit = ?0?, daen and spen bits = ?1? ? ?0? voh vol csb sc k si ncr busyb voh vol amode command 1st byte amode command 2nd byte spp voh vol cbusyb t cb1 t pupa3 gnd 1/2dvdd (internal) (internal) (line output) status command is being processed awaiting command awaiting command awaiting command command is being processed voh vol csb sc k si nc r (internal) busyb (internal) voh vol line output spm spp voh vol cbusyb t cb1 t pda1 gnd 1/2dvdd gnd 1/2spvdd hi-z 1/2spvdd status command is being processed awaiting command awaiting command command is being processed awaiting command amode command 1st byte amode command 2nd byte
FEDL22594-04 ml22594-xxx 35/73 ? when putting the line amplifier into the pow er down state (with pop noise suppression) setting values: pop bit = ?1?, daen bit = ?1? ? ?0? (spen bit = ?0?) ? when putting the line amplifier into the power down state (without pop noise suppression) setting values: pop bit = ?0?, daen bit = ?1? ? ?0? (spen bit = ?0?) voh vol csb sc k si ncr busyb voh vol spp voh vol cbusyb t cb1 t pda2 gnd 1/2dvdd (internal) (internal) (line output) amode command 1st byte amode command 2nd byte status command is being processed awaiting command awaiting command awaiting command command is being processed pop noise suppressed voh vol csb sc k si ncr busyb voh vol spp voh vol cbusyb t cb1 t pd a 3 gnd 1/2dvdd (internal) (internal) (line output) amode command 1st byte amode command 2nd byte status command is being processed awaiting command awaiting command awaiting command command is being processed
FEDL22594-04 ml22594-xxx 36/73 the dag1,0 bits are used to set the gain of the internal dac signal. the aig1,0 bits are used to set the gain of an analog signal from the ain pin. dag1,0 and ai g1,0 are only enabled when the speaker amplifier is used. dag1 dag0 volume 0 0 input off 0 1 input on ( ? 6 db) 1 0 input on (0 db) (initial value) 1 1 input on (0 db) (setting prohibited) aig1 aig0 volume 0 0 input off (initial value) 0 1 input on ( ? 6 db) 1 0 input on (0 db) 1 1 input on (0 db) (setting prohibited) input the analog signal from the ain pi n after the amode command (cbusyb=?h?). the daen bit takes power-up and power-down control of the dac section. daen status of the dac section 0 powe r -down state (initial value) 1 po w e r -up state the spen bit takes power-up and power-down control of the speaker section. when the spen bit = ?0?, the spp pin is configured as a line output. spen status of the speaker section 0 powe r -down state (initial value) 1 powe r -up state relationship between daen, spen, and pop signals and the analog section daen spen pop mode status at speaker output power-down (initial value) 0 0 0 at line output power-down (without pop noise suppression) at speaker output power-down 0 0 1 at line output power-down (with pop noise suppression) D 1 D speaker output dac/speaker power-up 1 0 0 line output dac power-up (without pop noise suppression) 1 0 1 line output dac power-up (with pop noise suppression) pin status during power down the status of each output pin during power down by the amode command is shown below. analog output pin state v ddl dgnd v ddr dgnd sg dgnd spm hi-z spp dgnd
FEDL22594-04 ml22594-xxx 37/73 3. avol command ? command 0 0 0 0 1 0 0 0 1st byte 0 0 av5 av4 av3 av2 av1 av0 2nd byte the avol command is used to adjust the volume of the speaker amplifier. it is possible to input the avol command regardless of the status of the ncr signal. the command enables 50-level adjustment of volume, as shown in the table below. when the pup or amode command is input, the value set by the avol command is initialized (0 db). av5 ? 0 volume av5 ? 0 volume 3f +12db 1f ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1.0 06 off 25 ? 2.0 05 off 24 ? 3.0 04 off 23 ? 4.0 03 off 22 ? 5.0 00 off 21 ? 6.0 01 off 20 ? 7.0 00 off
FEDL22594-04 ml22594-xxx 38/73 4. fad command ? command 0 0 0 0 1 1 0 0 1st byte 0 0 0 0 fad3 fad2 fad1 fad0 2nd byte the fad command is used to set the fade-in time for the speaker amplifier. the fade-in time cna be adjusted through 16 levels, as sh own in the table below. the initial value after reset is 298 ? s. when the pup command is input, the va lue set by the fad command is initialized (298 ? s). fad3?0 fade-in time ( ? s) f 442 e 422 d 401 c 381 b 360 a 340 9 319 8 298 (initial value) 7 278 6 257 5 237 4 216 3 195 2 175 1 154 0 134
FEDL22594-04 ml22594-xxx 39/73 5. pdwn command ? command 0 0 1 0 0 0 0 0 the pdwn command is used to shift the ml22594 from a command waiting state to the power down state. however, since every setting will be initialized after enteri ng the power down state, initial settings need to be set after power-up. this command is invalid during playback. to resume playback after the ml22594 has shifted to the power down state, first input the pup and amode commands and then input the play command. oscillation stops after a lapse of command processing time after the pdwn command is input. the regulator stops operation after a lapse of comma nd processing time after the pdwn command is input. at this time, the spm output of the speaker amplifier goes into a hi-z state to prevent generation of pop noise. initial stauts at reset input and status during power down the status of each output pin is as follows: analog output pin state v ddl dgnd v ddr dgnd sg dgnd spm hi-z spp dgnd csb status command is being processed power down sck si ncr bus y b awaiting command xt ? xtb oscillatin g oscillation stopped cbus y b (internal) ( internal )
FEDL22594-04 ml22594-xxx 40/73 6. fadr command ? command 0 0 1 1 c1 c0 f9 f8 1st byte f7 f6 f5 f4 f3 f2 f1 f0 2nd byte the fadr command is used to specify a phrase to be pl ayed. a playback channel and a playback phrase are set by this command. the fadr command can be se t for each channel; however, the command cannot be input for multiple channels simultaneously. input the fadr command wi th each ncr set to a ?h? level. when a playback phrase is specified for each ch annel, use the start command to start playback. since it is possible to specify a playb ack phrase (f9?f0) at the time of creating a rom that stores voice data, specify the phrase that was speci fied when the rom was created. number of phrase ( internal rom and external rom ) number of phrase f9-f0 internal rom 512 000h ? 1ffh external rom 512 200h ? 3ffh channel settings c1 c0 channel 0 0 channel 0 0 1 channel 1 1 0 channel 2 1 1 channel 3 the diagram below shows the timing for specifying (f9?f0) = 02h as the phrase to play on channel 1. csb status command is being processed sck si ncr busyb awaiting command awaiting command awaiting comman d fadr command 1st byte fadr command 2nd byte cbusyb ( internal ) ( internal ) command is being processed
FEDL22594-04 ml22594-xxx 41/73 7. play command ? command 0 1 0 0 c1 c0 f9 f8 1st byte f7 f6 f5 f4 f3 f2 f1 f0 2nd byte the play command is used to start playback with ph rase specified. this command can be input when the ncr signal on the target channel is at a ?h? level. since it is possible to specify a playb ack phrase (f9?f0) at the time of creating a rom that stores voice data, specify the phrase that was speci fied when the rom was created. the figure below shows the timing of phrase (f9?f0 = 01h) playback. when the 1 st byte of the play command is input, the de vice enters a state awaiting input of the 2 nd byte of the play command after a lapse of comm and processing time. when the 2 nd byte of play command is input, after a lapse of command processing time, the device star ts reading from the rom the address information of the phrase to be played. thereafter, playback operation starts, the playback is performed up to the specified rom address, and then the playba ck terminates automatically. the ncr signal is at a ?l? level during address control, and goes ?h? when the addr ess control is finished and playback starts. when the ncr signal on the target channel goes ?h?, it is possible to input the play command for the next playback phrase. during address control, the busyb si gnal is at a ?l? level during playb ack and goes ?h? when playback is finished. whether the playback is going on can be known by the busyb signal. number of phrase ( internal rom and external rom ) number of phrase f9-f0 internal rom 512 000h ? 1ffh external rom 512 200h ? 3ffh csb sck si nc r busyb spm 1/2vdd spp 1/2vdd cbusyb (internal) ( internal ) play command 1st byte pl ay com man d 2nd byte st atu s command is being processed playing awaiting command a dd ress is being co ntrolled a waiting command awaiting command
FEDL22594-04 ml22594-xxx 42/73 channel settings c1 c0 channel 0 0 channel 0 0 1 channel 1 1 0 channel 2 1 1 channel 3 play command input timing for continuous playback the diagram below shows the play command input timing in cases where one phrase is played and then the next phrase is played in succession. as shown in the diagram above, if performing continuous playback, input the play command for the second phrase within 10 ms (t cm ) after the ncr signal on the target channel goes ?h?. input the following play command after checking that playback is completed by the rdstat command, when it is not continuous playback. c s b sck si ncr bus y b spm 1/2vdd spp 1/2vdd t cm cbusy b (internal) (internal) play command 2nd byte play command 1st byt e play command 2nd byte statu s playing phrase 1 addr ess i s b ei ng con tr ol led a waiting command playin g phrase 2 address is being controlled
FEDL22594-04 ml22594-xxx 43/73 8. start command ? command 0 1 0 1 ch3 ch2 ch1 ch0 the start command is a channel synchronization start (i.e., starts phrase playback on multiple channels simultaenously) command. it is necessary to speci fy playback phrases usi ng the fadr command before inputting the start command. setting any bit(s) from ch0 to ch3 to ?1? starts playback on the corresponding channel( s). input the start command with each ncr set to a ?h? level. the figure below shows the timing when starting playback on channel 00 and channel 1 simultaneously. channel settings channel ch0 setting this bit to ?1? st arts playback on channel 0. ch1 setting this bit to ?1? st arts playback on channel 1. ch2 setting this bit to ?1? st arts playback on channel 2. ch3 setting this bit to ?1? st arts playback on channel 3. be sure to set the channel setting bits( ch0-ch3). ncr0 ncr1 busyb0 busyb1 spp output awaiting command status playing awaiting command address is being controlled (internal) csb sck si (internal) (internal) (internal) cbusyb start command t cb2
FEDL22594-04 ml22594-xxx 44/73 start command input timing for continuous playback the diagram below shows the start command input timing in cases where one phrase is played and then the next phrase is played in succession. as shown in the diagram above, if performing continuous playback, input the start command for the second phrase within 10 ms (t cm ) after the ncr signal on the target channel goes ?h?. input the following start command after checking that playback is completed by the rdstat command, when it is not continuous playback. spm 1/2vdd spp 1/2vdd statu s playing phrase 1 ad dr ess is bei ng con tr olle d a waiting command playing phrase 2 csb sck si ncr busyb start command t cm cbus y b ( internal ) ( internal ) start command
FEDL22594-04 ml22594-xxx 45/73 9. stop command ? command 0 1 1 0 ch3 ch2 ch1 ch0 the stop command is used to stop playback. it can be set for each channel. setting any bit(s) from ch0 to ch3 to ?1? stops playback on the corr esponding channel(s). if the speech sy nthesis processing for all channels stops, the aout output goes to the v sg level and the ncr and busyb signals go to a ?h? level. although it is possible to input the stop command re gardless of the status of ncr during playback, a prescribed command interval time needs taking. channel settings channel ch0 setting this bit to ?1? stops playback on channel 0. ch1 setting this bit to ?1? stops playback on channel 1. ch2 setting this bit to ?1? stops playback on channel 2. ch3 setting this bit to ?1? stops playback on channel 3. be sure to set the channel setting bits( ch0-ch3). the stop command allows specifying multiple channels at one time. c s b status awaiting sck si ncr bus y b spm 1/2vdd spp 1/2vdd playing stopcommand command is be ing pro cesse d cbusy b (internal) ( internal ) fs 29cycle
FEDL22594-04 ml22594-xxx 46/73 10. muon command ? command 0 1 1 1 ch3 ch2 ch1 ch0 1st byte m7 m6 m5 m4 m3 m2 m1 m0 2nd byte the muon command allows inserting a silence between two playback phrases. the command can be input when the ncr signal on the target channel is at a ?h? level. set the silence time length after inputting this comman d. it can be set for each channel. the muon command allows specifying multiple channels at one tim e. setting any bit(s) from ch0 to ch3 to ?1? plays silence on the corres ponding channel(s). channel settings channel ch0 setting this bit to ?1? inserts a silence on channel 0. ch1 setting this bit to ?1? inserts a silence on channel 1. ch2 setting this bit to ?1? inserts a silence on channel 2. ch3 setting this bit to ?1? inserts a silence on channel 3. be sure to set the channel setting bits( ch0-ch3). as the silence length (m7?m0), a value between 20 ms and 1024 ms can be set at 4 ms intervals (252 steps in total). the equation to set the silence time length is shown below. the silence length (m7?m0) must be set to 04h or higher. t mu =(2 7 ? (m7)+2 6 ? (m6)+2 5 ? (m5)+2 4 ? (m4)+2 3 ? (m3)+2 2 ? (m2)+2 1 ? (m1)+2 0 ? (m0)+1) ? 4ms the figure below shows the timing of inserting a silence of 20 ms between the repetitio ns of a phrase of (f7?f0) = 01h. csb sck si ncr (internal ) busyb (internal) spm 1/2vdd spp 1/2vdd t cm t cm cbusyb play command 2nd byte mu on com mand 1st byte m uon comm and 2nd byte play command 1st b yte play command 2nd byte st atu s playin g a ddress is being controlled awaiting command silence is being inserted playing waiting for sil ence inserti on to be finished waiting for playback to be finished
FEDL22594-04 ml22594-xxx 47/73 when the play command is input, the address control ove r phrase 1 ends, the phrase playback starts, and the cbusyb and ncr signals go to a ?h? level. input the muon command after th is cbusyb signal changes to a ?h? level. after th e muon command input, the ncr signal remains ?l? until the end of phrase 1 playback, and the device enters a state waiting for the phrase 1 playback to terminate. when the phrase 1 playback is terminated, the silence play back starts and the ncr signal goes to a ?h? level. after the ncr signal has gone to a ?h? level, re-inp ut the play command in order to play phrase 1. after the play command input, the ncr signal once again goes to a ?l? level and the device enters a state waiting for the termination of silence playback. when the silence playback is terminat ed and then the phrase 1 playback st arts, the ncr signal goes ?h?, and the device enters a state where it is possible to input the next play or muon command. the busyb signal remains ?l? until the end of a series of playback. as shown in the diagram above, if performing continuous playback, input the muon/play/start command for the second phrase within 10 ms (t cm ) after the ncr signal on the target channel goes ?h?. input the following muon/play/start command after checking that playb ack is completed by the rdstat command, when it is not continuous playback.
FEDL22594-04 ml22594-xxx 48/73 11. sloop command ? command 1 0 0 0 ch3 ch2 ch1 ch0 the sloop command is used to set repeat playback m ode. the command can be input for each channel. the sloop command allows specifying multiple channels at one time. setting any bit(s) from ch0 to ch3 to ?1? repeats playback on the corresp onding channel(s). input the sloop command with each ncr set to a ?h? level. channel settings channel ch0 setting this bit to ?1? repeats playback on channel 0. ch1 setting this bit to ?1? repeats playback on channel 1. ch2 setting this bit to ?1? repeats playback on channel 2. ch3 setting this bit to ?1? repeats playback on channel 3. be sure to set the channel setting bits( ch0-ch3). once repeat playback mode is set, the current phrase is repeatedly played until the repeat playback setting is released by the sloop command or until playback is sto pped by the stop command. in the case of a phrase that was edited using the edit function, the edited phrase is repeatedly played. following shows the sloop command input timing. effective range of sloop command input the sloop command is only enabled during playback. after the play command is input, input the sloop command within 10 ms (t cm ) after the ncr signal on the target channel goes ?h?. this will enable the sloop command, so that repeat playback will be carried out. the ncr signal remains ?l? during repeat playback mode. csb sck si ncr busyb spm 1/2 vdd spp 1/2 vdd t cm cbusyb (internal) (internal) play command 2n d b yte sloop command cloop command sta tus pl a yi ng address is being controlled a waiting command a wai ting command playing address is being controlled command is being processed
FEDL22594-04 ml22594-xxx 49/73 12. cloop command ? command 1 0 0 1 ch3 ch2 ch1 ch0 the cloop command releases repeat playback mode. the command can be input for each channel. the cloop command allows specifying multiple channels at one time. setting any bit(s) from ch0 to ch3 to ?1? releases repeat playback on the corr esponding channel(s). when repeat playback mode is released, the ncr signal goes ?h?. it is possible to input the cloop command regardless of the status of the ncr signal during playback, but a prescribed command interval needs taking. channel settings channel ch0 setting this bit to ?1? releases repeat playback on channel 0. ch1 setting this bit to ?1? releases repeat playback on channel 1. ch2 setting this bit to ?1? releases repeat playback on channel 2. ch3 setting this bit to ?1? releases repeat playback on channel 3. be sure to set the channel setting bits( ch0-ch3). csb status playing sck si ncr busyb spm 1/2vdd spp 1/2vdd add ress b e i ng controlled awaiting command a waiting command play command 2nd byte sloop command playing c omman d b e i ng processed cloop command c omman d b e i ng processed t cm cbus y b (internal) (internal)
FEDL22594-04 ml22594-xxx 50/73 13. cvol command ? command 1 0 1 0 ch3 ch2 ch1 ch0 1st byte 0 0 0 cv4 cv 3 cv 2 cv 1 cv 0 2nd byte the cvol command is used to adjust the playback volume on each channel. it is possible to input the vol command regardless of the status of the ncr signal. the cvol command can be set for each channel. the c vol command allows specifying multiple channels at one time. setting any bit(s) from ch0 to ch3 to ?1? sets the playback volume on the corresponding channel(s). the volume setting is initialized by the amode command. channel settings channel ch0 setting this bit to ?1? se ts the volume on channel 0. ch1 setting this bit to ?1? se ts the volume on channel 1. ch2 setting this bit to ?1? se ts the volume on channel 2. ch3 setting this bit to ?1? se ts the volume on channel 3. be sure to set the channel setting bits( ch0-ch3). the command enables 32-level adjustment of volume, as shown in the table below. the initial value after reset release is set to 0 db. upon reset release or when the pup command is input, the values set by the cvol command are initialized. cv4 ? 0 volume cv4 ? 0 volume 1f 0 db (initial value) 0f ? ? 0.28 0e ? ? 0.58 0d ? ? 0.88 0c ? ? 1.20 0b ? ? 1.53 0a ? ? 1.87 09 ? ? 2.22 08 ? ? 2.59 07 ? ? 2.98 06 ? ? 3.38 05 ? ? 3.81 04 ? ? 4.25 03 ? ? 4.72 02 ? ? 5.22 01 ? ? 5.74 00 off
FEDL22594-04 ml22594-xxx 51/73 14. rdstat command ? command 1 0 1 1 0 0 0 err the rdstat command enables reading the status of internal operation. it is possible to input the cloop command regardless of the status of the ncr signal during playback, but a prescribed command interval needs taking. the err bit selects reading the playback status for each ch annel or reading the status of the fail-safe function. keep the si pin to ?l? when read the status. err content of data to read 0 ncr and busyb signals for each channel (initial value) 1 status of the fail-safe function if the err bit is set to ?0?, the following status will be read: output bit d7 d6 d5 d4 d3 d2 d1 d0 output data busyb3 busyb2 busyb1 busyb0 ncr3 ncr2 ncr1 ncr0 when the err bit = ?0?, the ncr an d busyb signals of each channel are read. the ncr signal outputs a ?l? level while this lsi is perfor ming command processing and goes to a ?h? level when the lsi enters a command waiting state. the busy signal ou tputs a ?l? level during voice playback. the table below shows the contents of each data output at a status read. output status signal busy3 channel 3 busyb output busy2 channel 2 busyb output busy1 channel 1 busyb output busy0 channel 0 busyb output ncr3 channel 3 ncr output ncr2 channel 2 ncr output ncr1 channel 1 ncr output ncr0 channel 0 ncr output
FEDL22594-04 ml22594-xxx 52/73 if the err bit is set to ?1?, the following status will be read output bit d7 d6 d5 d4 d3 d2 d1 d0 output data 0 0 exr err spm err spp err tsd err bld err wcm err when the err bit=?1?, the state of six fail-safe function is read. if any of fail-safe function is activated,the err pin is set to a ?h? level and the corresponding error bit is set to ?1?. if the err pins set to a ?h? level, check the error contents using the rdstat command and take appropriate measures. err bit is cleared by ercl command error signal error contents exrerr external rom read err bit. this bit is set to ?1? if the voice c ontrol area data of external rom is ?00h?. it becomes an error when it accesses the extern al rom under the conditi on that the external rom isn't connected. spmerr spm pin short error bit. this bit is set to ?1? if the spm pin is short to spp pin or gnd spperr spp pin short error bit this bit is set to ?1? if the spp pin is short to spm pin or gnd tsderr high temperature error bit. this bit is set to ?1? if the temperature of the lsi reaches or exceeds the temperature set by the safe command. for details see the section on the safe command. blderr power supply voltage error bit. this bit is set to ?1? if the power supply voltage level reaches or falls below the voltage set by the safe command. for details see the section on the safe command. wcmerr command tansfer errro bit. this bit is set to ?1? if a transfer erro r occurs in two-time command input mode.
FEDL22594-04 ml22594-xxx 53/73 15. outstat command ? command 1 1 0 0 0 busy/ncr c1 c0 the outstat command is used to output the busyb or ncr signal on the specified channel from the status pin. it is possible to input the cloop command regardless of the status of the ncr signal during playback, but a prescribed co mmand interval needs taking. busy/ncr status pin status 0 outputs the ncr signal on the specified channel. 1 outputs the busyb signal on the specified channel. channel settings c1 c0 channel 0 0 channel 0 (initial value) 0 1 channel 1 1 0 channel 2 1 1 channel 3 csb sck si ncr busyb outstat command cbusyb (internal) (internal) status c s b sck si ncr bus y b outstat c ommand cbusy b (internal) ( internal ) status
FEDL22594-04 ml22594-xxx 54/73 16. safe command ? command 1 1 0 1 0 0 0 0 tm2 tm1 tm0 tsd1 tsd0 bld2 bld1 bld0 the safe command is sets the settings for the low-voltage detection and temperature detection functions. the bld2?0 bits are used to set th e power supply voltage detection level. the judgment voltage can be selected from among six levels from 2.7 to 4.0 v. the power supply voltage is monitored each time it reaches the value set by tm2?0, and if the power supply voltage reaches or falls below the set detection voltage two times or more, the err pin outputs a ?h? level and the rdstat command?s blderr bit is set to ?1?. if the err pin is set to a ?h? level, check the error contents using the rdstat command. if the blderr bit is at ?1?, it is possibly a power supply related failure. bld2 bld1 bld0 judgment power supply voltage 0 0 0 off 0 0 1 2.7v ? ? ? ? ? ? ? the tsd1?0 bits are used to set the temperature detection level. tj=140 ? c or off can be selected as the judgment temperature. the temperat ure is monitored each time it reaches the value set by tm2?0, and if the temperature reaches or exceeds the set value two tim es or more, the err pin outputs a ?h? level and the rdstat command?s tsderr bit is set to ?1?. if the err pin is set to a ?h? level, check the error contents using the rdstat command. if the tsderr bit is at ?1?, reduce the volume using the avol command or put the analog section in to the power down state using the amode command. tsd1 tsd0 judgment temperature (tj) 0 0 off 0 1 setting prohibited 1 0 setting prohibited 1 1 140 ? 10? c ( initial valle, ) the judgment temperature(tj) is 140 ? 10 ? c. this lsi is beyond tj=130 ? c in the operating temperature(-40 ? c - +150 ? c) depending on a operating condition and occurs by a high temperature error. the ambient temperature at that case is as follows. power supply(d vdd =sp vdd ) power dissipation(p d ) amient temperature(ta) 4.5v 0.686w not detect in the operating temperature 5.0v 0.861w detect more than 104 ?c 5.5v 1.055w detect more than 98 ? c * ja 31.2[ ? c/w](jedec 2layers(refer to 67pages)), 1w/8ohm-speaker
FEDL22594-04 ml22594-xxx 55/73 ja changes by an implementation condition. the maximum ambient temperatur e(tamax) that this lsi does not detect the high temperature error is calculated in the following expressions in using the power dissipation. tamax = 130[ ? c] - ja[? c/w] p d [w] the maximum ambient temperature(tamax) in power supply voltage 5.0v and ja=36[ ? c/w] is as follows. tamax = 130[ ? c] - 36 0.861 P 99[ ? c] the tm2?0 bits are used to set the monitor interval to detect a low voltage or temperature. tm2 tm1 tm0 monitor interval 0 0 0 constantly monitors 0 0 1 2 ms (initial value) 0 1 0 4 ms 0 1 1 8 ms 1 0 0 16 ms 1 0 1 32 ms 1 1 0 64 ms 1 1 1 128 ms
FEDL22594-04 ml22594-xxx 56/73 17. ercl command ? command 1 1 1 1 1 1 1 1 the ercl command is used to clear an error if it occurs. if an error occurs, a ?h? level is outputted from the e rr pin. when the ercl command is inputted, the err pin outputs a ?l? level. however, when the high temperature error and the power-supply voltage error continue, tsderr of the rdstat command , blderr of the rdstat command an d the err pin keep outputting "h" even if the ercl command is inputted. timing diagram for when an error occurs at the time of setting the two-time command input mode timing diagram for when an error occurs at the external rom err t cb1 ( internal ) 00h 01h rdstat err re g ister 00h start command 2nd times er cl comm and 1st time ercl command 2nd times vo h vol csb sc k si ncrn busybn t intc vih vil v oh vol cbusyb ( internal ) ( internal ) erclcommand csb sck si voh vol cbusyb t cb1 err ( internal ) 00h 20h 00h rdstat errre g ister
FEDL22594-04 ml22594-xxx 57/73 if a power supply voltage error occurs and then the power supply voltage is returned (when the safe command?s bld2?0 bits = 001h) if a power supply voltage error occurs but the power supply voltage is not returned ercl command csb sck si voh vol cbusyb t cb1 err (internal) 00h 02h 00h 2.6v 3.0v 3.0v dv dd rdstat err register ercl command csb sck si voh vol cbusyb t cb1 err (internal) 00h 02h 2.6v 3.0v dv dd rdstat err register
FEDL22594-04 ml22594-xxx 58/73 when speaker-short situation is released before error clear flow(*1) when speaker-short situation is co ntinued after error clear flow(*1). when ercl is inputed before error clear flow(*1). *1:error clear flow:rdstat=>amode(speaker power-down) => ercl *2: spm pin short error serial i/f err speaker short state amode spkr_powerup ercl amode spkr_powerdown rdstat 00h 10h (*2) 00h rdstat err reg (internal) amode spkr_powerup serial i/f err speaker short state amode spkr_powerup ercl amode spkr_powerdown rdstat 00h 10h (*2) 00h rdstat err reg (internal) amode spkr_powerup 10h serial i/f err speaker short state amode spkr_powerup ercl 00h 10h (*2) rdstat errreg (internal) 00h 10h (*2) ercl amode spkr_powerdown rdstat 00h
FEDL22594-04 ml22594-xxx 59/73 command flow charts 1-b yte command input flow (applied to the pup, pdwn, start, stop, sloop, cloop, outstat, and ercl commands) 2-byte command input flow (applied to the amode, avol, fad, fadr, play, muon, cvol, and safe commands) status read flow input command end cbusyb ?h?? y n start cbusyb ?h?? n y input the 1st byte of command cbusyb ?h?? input the 2nd byte of command end cbusyb ?h?? y n y n start cbusyb ?h?? y n rdstat command cbusyb ?h?? read status (si=?l?) y n
FEDL22594-04 ml22594-xxx 60/73 power-on flow example of power-up flow example of playback start flow example of playback stop flow apply power, drive resetb ?l? waited for 10 ?
FEDL22594-04 ml22594-xxx 61/73 continuous playback start flow loop start flow loop stop flow power-down flow looping cloop command stop command stop after playback is finished all the way through the phrase stop playback forcibly power-up state pdwn command play/start/muon command playback(playing) play/start/muon command within 10ms play/start command playback(playing) sloop command within 10ms
FEDL22594-04 ml22594-xxx 62/73 detailed flow of ?power-up ? playback ? power-down? power-down state 1st byte of play command cbusyb ?h?? pup command 1st byte of amode command cbusyb ?h?? 2nd byte of amode command cbusyb ?h?? cbusyb ?h?? y n y n y n y n cbusyb ?h?? 2nd byte of play command y n a a busyb ?h?? rdstat command pdwn command power-down state cbusyb ?h?? cbusyb ?h?? y n y n y n cbusyb ?h?? read status y n 1st byte of amode command cbusyb ?h?? 2nd byte of amode command cbusyb ?h?? y n y n
FEDL22594-04 ml22594-xxx 63/73 detailed flow of ?spp/spm short detecting? spperr/spmerr cbusyb ?h? rdstat command read status pla y back end y n y n 1st byte of amode command 2nd byte of amode command cbusyb ?h? y n waiting for command cbusyb ?h? y n err ?h? *it is confirmed that spmerr or spperr is "h". * speaker-mode is set power-down. ercl command cbusyb ?h? y n * err-bit and err-port are cleared. stop command
FEDL22594-04 ml22594-xxx 64/73 1-byte command input flow of two-time command input mode applied to the pdwn,stop,sloop,cloop,rdstat,outstat,and ercl commands n one-time command input end two-time command input cbusyb ?h? err ?l? one-time command input(re-input) end cbusyb ?h? err ?l? one-time ercl command in p ut y y y y n n n n two-time ercl command input y n err ?l? cbusyb ?h? two-time command input(re-input)
FEDL22594-04 ml22594-xxx 65/73 2-byte command input flow of two-time command input mode applied to the amode,avol,fad,fadr,play,muon,cvol, and safe commands one-time command input (1byte) end two-time command input (1byte) one-time command input(1byte)(re-input) two-time command input(1byte) (re-input) one-time ercl command input y y y y n n n n two-time ercl command input y n one-time command input (2byte) two-time command input (2byte) y n y n one-time erclcommand input y n two-time erclcommand input y n cbusyb ?h? err ?l? cbusyb ?h? err ?l? err ?l? cbusyb ?h? err ?l? cbusyb ?h? err ?l? cbusyb ?h?
FEDL22594-04 ml22594-xxx 66/73 handling of the sg pin th e sg pin is the signal ground pin for the built-in speake r amplifier. connect a capacitor between this pin and the analog ground so that this pin will not carry noise. the recommended capacitance value is shown below; howe ver, it is recommended that the user determine the capacitance value after evaluation. always start playback after each output voltage is stabilized. pin recommended capacitance value remarks sg 0.1 ? f ? 20% the larger the connection capacitance, the longer the speaker amplifier output pin (spm and spp) voltage stabilization time. handling of the v ddl pins the v ddl pin is the power supply pins for the internal circ uits. connect a capacitor between each of these pins and the ground in order to prevent noise generation and power fluctuation. the recommended capacitance value is shown below; howe ver, it is recommended that the user determine the capacitance value after evaluation. always start the next operation after each output voltage is stabilized. pin recommended capacitance value remarks v ddl 10 ? f ? 20% the larger the connection ca pacitance, the longer the stabilization time.
FEDL22594-04 ml22594-xxx 67/73 power supply wiring th e power supplies of this lsi are divided into the following three: ? digital power supply (dv dd ) and digital ground(dgnd) ? speaker amplifier power supply (spv dd ) and speaker amplifier ground(spgnd) ? external rom interface power supply(io v dd ) as shown in the figure below, be sure to diverge the wiring of dv dd and spv dd from the root of the same power supply. dgnd/spgnd is similar, too. iov dd is sure to wire external rom power supply. dv dd spv d d dgnd spgnd 5v iov dd 3.3v * 1 *1 : iov dd is sure to wire external rom power supply.
FEDL22594-04 ml22594-xxx 68/73 application circuit at using internal speaker amplifier (speaker output) at using external speaker amplifier (line output) spm spp sg ain resetb csb sck si so cbusyb err status diph testi1 flw ecsb esck eso esi xt xtb mcu 4.096mhz 15pf 15pf speaker iov dd v ddl dv dd spv dd dgnd spgnd 0.1 ? ? external rom 5v 0.1uf 0.1uf 10uf 10uf 10uf 3.3v *1 0.1uf speaker 0.1 ? dd v ddl dv dd spv dd dgnd spgnd 5v 0.1 ? ? external rom 0.1uf
FEDL22594-04 ml22594-xxx 69/73 recommended ceramic oscillation recommended ceramic resonators for oscillation and conditions are shown below for reference. kyocera corporation optimal load capacity freq [hz] type c1 [pf] c2 [pf] rf [ohm] rd [ohm] supply voltage range [v] operating temperature range [ ?c] 4.096m pbrv4.096mr50y000 15(internal) --- -- 4.5 to 5.5 -40 to +125 murata corporation optimal load capacity freq [hz] type c1 [pf] c2 [pf] rf [ohm] rd [ohm] supply voltage range [v] operating temperature range [ ?c] 4m cstcr4m00g55b-r0 4.096m cstcr4m09g55b-r0 39(internal) --- -- 4.5 to 5.5 -40 to +125 circuit diagram c1 c2 gnd xt xtb dgnd/ spgnd dv dd /spv dd v dd
FEDL22594-04 ml22594-xxx 70/73 limitation on the operation time (play-back time) ml22594?s operating temperature is 105 ? c. but the average ambient temper ature at 1w play-back (8ohm drive) during 10 years in the reliability design is ta=70 ? c. (max ( the package heat resistance ja=24.6[ ? c/w]) ) when ml22594 operates 1w play-back(8ohm drive) consecutively, the product life changes by the package temperature rise by the consumption. this limitation does not matter in the state that a speaker amplifier does not play. the factor to decide the op eration time ( play-back time ) is the aver age ambient temperature( ta ), play-back watts( at the speaker drive mode), the soldering area ratio*1, and so on. in addition, the limitation on the operation time changes by the heat designs of the board. package heat resistance value (reference value) the following table is the pa ckage heat resistance value ja (reference value). this value changes the condition of the board (size, layer number, and so on) the board ja the condition jedec 4layers *1 w/l/t 76.2/114.5/1.6 mm 24.6[ ?c /w] jedec 2layers *2 w/l/t 76.2/114.5/1.6 mm 31.2[ ?c /w] no wind (0m/sec) the soldering area ratio* 3 100% *1 : the wiring density : 1st layer(top) 60% / 2nd layer 100% / 3rd layer 100% / 4th layer(bottom) 60%. *2 : the wiring density : 1st layer(top) 60% / 2nd layer(bottom) 100%. *3 : the soldering area ratio is the ratio that the heat sink area of ml22594 and a land pattern on the board are soldered. 100% mean that the heat sink area of ml22594 is completely soldered to the land pattern on the board. about the land pattern on the board, be sure to refer to the next clause (package dimensions).
FEDL22594-04 ml22594-xxx 71/73 package dimensions notes for mounting the su rface mount type package the surface mount type packages are ve ry susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package c ode and desired mounting co nditions (reflow method, temperature and times). notes for heat sink type package this lsi adopts a heat sink type package to raise a radiation of heat characteristic. be sure to design the land pattern corresponding to the heat sink area of the lsi on a board, and solder each other. the heat sink area of the lsi solder open or gnd on the board.
FEDL22594-04 ml22594-xxx 72/73 revision history page document no. date previous edition current edition description fedl22594full-01 sep. 19, 2012 ? ? final edition 1. 51 51 add exrerr. fedl22594full-02 nov. 20, 2012 55 55 add external rom error timing diagram. 11 11 add tcb3. fedl22594-03 apr. 24, 2013 18 18 change playback stop timing. - 34 add tpupa3 timing diagram. FEDL22594-04 dec. 9, 2014 - 35 add tpda3 timing diagram.
FEDL22594-04 ml22594-xxx 73/73 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants an d any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the info rmation specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or othe r rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatso ever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to en hance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe desi gns. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the pr escribed scope or not in acc ordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a me dical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety devi ce). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, pleas e contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or t echnology specified herein th at may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2012-2014 lapis semiconductor co., ltd. 2-4-8 shinyokohama, kouhoku-ku, yokohama 222-8575, japan http://www.lapis-semi.com/en/

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