fdn5630 fdn5630 rev. c march 2000 ? 2000 fairchild semiconductor corporation absolute maximum ratings t a = 25 c unless otherwise noted symbol parameter ratings units v dss drain-source voltage 60 v v gss gate-source voltage 20 v i d drain current - continuous (note 1a) 1.7 a - pulsed 10 p d power dissipation for single operation (note 1a) 0.5 w (note 1b) 0.46 t j , t stg operating and storage junction temperature range -55 to +150 c thermal characteristics r ja thermal resistance, junction-to-ambient (note 1a) 250 c/w r jc thermal resistance, junction-to-case (note 1) 75 c/w package marking and ordering information device marking device reel size tape width quantity 5630 fdn5630 7 8mm 3000 units gs d g d s supersot -3 tm general description this n-channel mosfet has been designed specifically to improve the overall efficiency of dc/dc converters using either synchronous or conventional switching pwm controllers. this mosfet features very low r ds(on) in a small sot23 footprint. fairchild?s powertrench technology provides faster switching than other mosfets with comparable r ds(on) specifications. the result is higher overall efficiency with less board space. applications dc/dc converter motor drives features 1.7 a, 60 v. r ds(on) = 0.100 ? @ v gs = 10 v r ds(on) = 0.120 ? @ v gs = 6 v. optimized for use in high frequency dc/dc converters. low gate charge. very fast switching. supersot tm - 3 provides low r ds(on) in sot23 footprint. fdn5630 60v n-channel powertrench ? ? ? ? ? mosfet
fdn5630 fdn5630 rev. c notes: 1: r ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r jc is guaranteed by design while r ja is determined by the user's board design. scale 1 : 1 on letter size paper 2: pulse test: pulse width 300 s, duty cycle 2.0% a) 250 c/w when mounted on a 0.02 in 2 pad of 2 oz. cu. b) 270 c/w when mounted on a minimum pad. electrical characteristics t a = 25 c unless otherwise noted symbol parameter test conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 60 v ? bv dss ? t j breakdown voltage temperature coefficient i d = 250 a,referenced to 25 c 63 mv/ c i dss zero gate voltage drain current v ds = 48 v, v gs = 0 v 1 a i gssf gate-body leakage current, forward v gs = 20 v, v ds = 0 v 100 na i gssr gate-body leakage current, reverse v gs = -20 v, v ds = 0 v -100 na on characteristics (note 2) v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 12.4 3 v ? v gs(th) ? t j gate threshold voltage temperature coefficient i d = 250 a,referenced to 25 c 6.9 mv/ c r ds(on) static drain-source on-resistance v gs = 10 v, i d = 1.7 a v gs = 10 v, i d = 1.7 a, t j = 125 c v gs = 6 v, i d = 1.6 a 0.073 0.127 0.083 0.100 0.180 0.120 ? i d(on) on-state drain current v gs = 10 v, v ds = 1.7 v 5 a g fs forward transconductance v ds = 10 v, i d = 1.7 a 6 s dynamic characteristics c iss input capacitance 400 pf c oss output capacitance 102 pf c rss reverse transfer capacitance v ds = 15 v, v gs = 0 v, f = 1.0 mhz 21 pf switching characteristics (note 2) t d(on) turn-on delay time 10 20 ns t r turn-on rise time 6 15 ns t d(off) turn-off delay time 15 28 ns t f turn-off fall time v dd = 30 v, i d = 1 a, v gs = 10 v, r gen = 6 ? 515ns q g total gate charge 7 10 nc q gs gate-source charge 1.6 nc q gd gate-drain charge v ds = 20 v, i d = 1.7 a, v gs = 10 v, 1.2 nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current 0.42 a v sd drain-source diode forward voltage v gs = 0 v, i s = 0.42 a (note 2) 0.72 1.2 v
fdn5630 fdn5630 rev. c typical characteristics figure 1. on-region characteristics. figure 2. on-resistance variation with drain current and gate voltage. figure 5. transfer characteristics. figure 6. body diode forward voltage variation with source current and temperature. figure 3. on-resistance variation with temperature. figure 4. on-resistance variation with gate-to-source voltage. 0 2 4 6 8 10 12345 v gs , gate to source voltage (v) i d , drain current (a) t a = -55 o c 25 o c 125 o c v ds =5v 0.001 0.01 0.1 1 10 0 0.2 0.4 0.6 0.8 1 1.2 v sd , body diode voltage (v) i s , reverse drain current (a) t j =125 o c 25 o c -55 o c v gs =0 0.9 1 1.1 1.2 1.3 1.4 1.5 02468 i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs = 4.5v 10v 6.0v 7.0v 5.0v 0 0.05 0.1 0.15 0.2 0.25 246810 v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) i d = 1.7a t a = 125 o c t a = 25 o c 0 2 4 6 8 10 012345 v ds , drain-source voltage (v) i d , drain current (a) 6.0v 5.0v 4.5v 4.0v 3.5v v gs = 10v 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistance i d =1.7a v gs = 10v
fdn5630 fdn5630 rev. c typical characteristics (continued) figure 7. gate charge characteristics. figure 8. capacitance characteristics. figure 9. maximum safe operating area. figure 10. single pulse maximum power dissipation. figure 11. transient thermal response curve. thermal characterization performed using the conditions described in note 1b. transient themal response will change depending on the circuit board design. 0.0001 0.001 0.01 0.1 1 10 100 300 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r (t) = r(t) * r r = 270 c/w duty cycle, d = t /t 1 2 ja ja ja t - t = p * r (t) ja a j p(pk) t 1 t 2 r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 0 4 8 12 16 20 0.0001 0.001 0.01 0.1 1 10 100 1000 single pulse time (sec) power (w) single pulse r ja =270 o c/w t a =25 o c 0 2 4 6 8 10 02468 q g , gate charge (nc) v gs , gate-source voltage (v) i d = 1.7a v ds = 10v 20v 30v 0 100 200 300 400 500 600 0 102030405060 v ds , drain to source voltage (v) capacitance (pf) c iss c rss c oss f = 1mhz v gs = 0 v 0.01 0.1 1 10 0.1 1 10 100 v ds , drain-source voltage (v) i d , drain current (a) dc 10s 1s 100ms 10ms 1ms 100 s r ds(on) limit v gs = 10v single pulse r ja = 270 o c/w t a = 25 o c
trademarks acex? bottomless? coolfet? crossvolt? e 2 cmos tm fact? fact quiet series? fast fastr? gto? the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. supersot?-8 syncfet? tinylogic? uhc? vcx? hisec? isoplanar? microwire? pop? powertrench qfet? qs? quiet series? supersot?-3 supersot?-6 ? rev. e ?
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