TQC9311 0 .4 - 3.6 ghz dual channel dvga datasheet : rev. d 08 - 19 - 14 - 1 of 9 - disclaimer: subject to change without notice ? 2014 triquint www.triquint.com applications ? wireless infrastructure ? lte / wcdma / cdma / gsm ? general purpose wireless ? diversity or mimo receivers 32- pin 7? x ? 7 ?mm l eadless smt p ackage product features ? dual channel, integrating dsa + amp functionality ? 0.4 C 3.6 ? ghz broadband performance ? 1 3.2 ? db gain at 1.9 5 ? ghz ? 3.8 ? db noise figure at max gain setting ? +2 1 . 1 ? dbm p1db ? +3 6.5 ? dbm oip3 ? +5 ? v supply voltage ? int egrated on - chip matching and bias chokes ? 3 - wire spi control programming ? + 1.8 ? v and + 3.3 ? v logic compatible serial input functional block diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dsa dsa 12- bit spi amp1 amp2 ordering information part no. description TQC9311 0.4 - 3.6 ghz dual - channel dvga TQC9311 - pcb ev aluation board standard t/r size = 2500 pcs on a 13 reel. general description the TQC9311 is a dual - channel, digitally - controlled variable gain amplifier (dvga) operating over a broadband frequency range of 4 00 to 36 00 mhz. the dvga features + 3 6.5 dbm oip3 while providi ng digital variable gain with 31 .5 db of gain range in 0.5 db steps through a 12 - bit serial mode control interface. this combination of performance parameters makes the dvga ideal for diversity or mimo receiver applications requiring gain con trol with high linearity and low noise figure. the TQC9311 integrates a high performance digital step attenuator followed by a high linearity, broadband gain block in a dual - channel configuration . the dual channel dvga is internally matched to 5 0 ohms and do es not require any external matching components. bias choke inductors and bypass/ blocking capacitors are also integrated into the module thereby reducing the number of external components needed. the TQC9311 is packaged in a rohs - compliant , compact 7 ? x ? 7 mm surface - mount leadless package. pin configuration pin no. label pin no. label 1 rfin_1 8 rfin_2 3 v cc_spi 15 v dd_amp2 4 le 17 rfout_2 5 data 24 rf_out1 6 clk 26 v dd_amp1 7, 10, 13, 28, 31 no connect 26 v dd_amp1 all other p ins are internally grounded.
TQC9311 0 .4 - 3.6 ghz dual channel dvga datasheet : rev. d 08 - 19 - 14 - 2 of 9 - disclaimer: subject to change without notice ? 2014 triquint www.triquint.com recommended operating conditions parameter min typ max units supply voltage (v dd ) +4.75 +5 +5.25 v t ch (for >10 6 hours mttf) + 190 c case temperature - 40 + 105 c electrical specifications are measured at specified test conditions. specifications are not guaranteed over all recommended operating conditions. absolute maximum ratings parameter rating storage temperature ? 65 to 150 ? c rf input power , cw, 50, 24 hr, 25c +24 dbm v dd , power supply voltage + 6 v reverse device voltage ?0.3 v digital input voltage v dd + 0.5 v operation of this devi ce outside the parameter ranges given above may cause permanent damage. el ectrical specifications test conditions : v amp = v dd =+5 ? v , t lead =+25c parameter conditions min typ max units operational frequency range 4 00 36 00 mhz test frequency 1950 mhz gain max gain setting 13.2 db gain control range 31 .5 db gai n control step size 0.5 db control interface 12 bits gain accuracy 700 C 2700 mhz , major states (0.3 + 5 % of atten. setting) db input return loss 13 db output return loss 1 1.5 db output p1db +2 1 . 1 dbm output ip3 pout = +3 dbm/tone, f = 1mhz + 3 6.5 dbm input ip3 pin = - 8 dbm /tone , f = 1mhz + 2 3.3 dbm isolation channel - to - channel 55 db noise figure max gain setting 3.8 db supply current per channel 87 ma thermal resistance (r th ) channel to case c /w
TQC9311 0 .4 - 3.6 ghz dual channel dvga datasheet : rev. d 08 - 19 - 14 - 3 of 9 - disclaimer: subject to change without notice ? 2014 triquint www.triquint.com serial contro l interface the TQC9311 has a cmos spi tm input compatible serial interface. this serial control interface converts the serial data input stream to parallel output word. the input is 3 - wire (clk, le and sid) spi tm input compatible. at power up, the s erial control interface resets the dvga to the minimum gain state ( maximum attenuation setting) . the 12 - bit serial input data (sid) word is loaded into the register on rising edge of the clk, msb first. when le is high, clk is internally disabled in the dvga. serial control timing characteristics test conditions: v dd - dsa = +5 v (1) , t lead =25c parameter condition min max units clock frequency, f clk 50% duty cycle , 25 mhz le setup time, t lesup clk to le setup time 5 ns clk setup time, t clksup le to clk setup time 5 ns le pulse width, t lepw 10 ns serin set - up time, t sdsup before clk rising edge 5 ns serin hold - time, t sdhld after clk rising edge 5 ns propagation delay, t plo 20 ns notes: 1. internal spi chip compatible to +1.8 ?v and +3.3?v logic levels . serial control dc logic characteristics test conditions: v dd = +5 v, temp.=25c parameter condition min max units low state input voltage, v il 0 0.5 v high state input voltage, v ih 1.2 v dd v input current, i ih / i il o n sid, le and clk ? 10 +10 a serin le t sdsup t sdhld t lesup t lepw parallel data valid clk d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t clksup
TQC9311 0 .4 - 3.6 ghz dual channel dvga datasheet : rev. d 08 - 19 - 14 - 4 of 9 - disclaimer: subject to change without notice ? 2014 triquint www.triquint.com serial control interface serial in control logic truth table , msb in first 12 - bit control word attenuation channel 1 control channel 2 control d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 1 1 1 1 1 maxi mum gain 1 1 1 1 1 0 1 1 1 1 1 0 ?0.5 db 1 1 1 1 0 1 1 1 1 1 0 1 ?1 db 1 1 1 0 1 1 1 1 1 0 1 1 ?2 db 1 1 0 1 1 1 1 1 0 1 1 1 ?4 db 1 0 1 1 1 1 1 0 1 1 1 1 ?8 db 0 1 1 1 1 1 0 1 1 1 1 1 ?16 db 0 0 0 0 0 0 0 0 0 0 0 0 ?31.5 db any combination of the possible 64 states will provide a reduction in gain of approximately the sum of the bits selected. application board schematic
TQC9311 0 .4 - 3.6 ghz dual channel dvga datasheet : rev. d 08 - 19 - 14 - 5 of 9 - disclaimer: subject to change without notice ? 2014 triquint www.triquint.com applicatio n board layout top rf layer is 0.014, dielectric isola fr408hr, 4 - laye r, 0.062 overall thickness. bill of material C tqc931 1 - pcb reference des. value description manuf. part number u1 n/a dual channel dvga triquint TQC9311 c1, c6, c8 1000 pf cap, 0402, 10%, 50v various c5, c7, c9 0.1 uf cap, 0402, 10% various r2 0 ? res, 0402, 5%, 1/16w various
TQC9311 0 .4 - 3.6 ghz dual channel dvga datasheet : rev. d 08 - 19 - 14 - 6 of 9 - disclaimer: subject to change without notice ? 2014 triquint www.triquint.com performance summary test conditions : t lead =+25c, v dd =+5v frequency 900 1950 2700 mhz gain 13.8 13 12.6 db input return loss 19 13 25 db output return loss 15 11.7 10.5 db output p1db +21.1 db m output ip3 ( pout/tone= +3 dbm, f=1mhz) +37.1 +36.5 +36 dbm isolation (ch1 to ch2) 63 55 51 db noise figure 3.1 3.8 4.4 db amplifier curren t (per channel) 8 7 ma performance plots : channel 1/ channel 2 test conditions unless otherwise noted: v cc ? = ? +5 ? v, i c q ? = ? 87 ?ma (typ.) 0 5 10 15 20 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 gain (db) frequency (ghz) gain vs. frequency dsa at minimum attenuation state +85 c +25 c ?40 c +105 c -35 -30 -25 -20 -15 -10 -5 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 |s11| (db) frequency (ghz) input return loss vs. frequency dsa at minimum attenuation state +85 c +25 c ?40 c +105 c -25 -20 -15 -10 -5 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 |s22| (db) frequency (ghz) output return loss vs. frequency dsa at minimum attenuation state +105 c +85 c +25 c ?40 c -2 -1 0 1 2 0 15 30 45 60 attenuation error (db) attenuation states attenuation error vs. attenuation states +85 c +25 c ?40 c +105 c frequency = 1950 mhz 20 25 30 35 40 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 oip3 (dbm) frequency (ghz) oip3 vs. frequency +85 c +25 c ?40 c +105 c 14 16 18 20 22 24 -40 -15 10 35 60 85 p1db (dbm) temperature ( c) op1db vs. temperature frequency = 1950 mhz 0 1 2 3 4 5 6 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 noise figure (db) frequency (ghz) noise figure vs. frequency +85 c +25 c ?40 c +105 c -80 -70 -60 -50 -40 -30 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 isolation (db) frequency (ghz) isolation (ch1 to ch2) vs. frequency +85 c +25 c ?40 c +105 c 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 k - factor frequency (ghz) k - factor vs. frequency +85 c +25 c ?40 c minimum attenuation state
TQC9311 0 .4 - 3.6 ghz dual channel dvga datasheet : rev. d 08 - 19 - 14 - 7 of 9 - disclaimer: subject to change without notice ? 2014 triquint www.triquint.com pin configuration and description pin no. label description 1 rfin_1 channel 1 rf input. this pin is dc blocked internally. 2, 9, 11, 12, 14, 16, 18 19, 20, 21, 22, 23, 25 27, 29, 3 0 gnd these pins a re grounded internally and should be connected to the pcb ground for good performance. 3 vcc_spi dc supply into spi and dsa. 4 le latch enable 5 data serial input data 6 clk serial clock 7, 10, 13, 28, 31 nc no electrical connection. provide land pads for pcb mounting integrity. these pins can be grounded on the pcb. 8 rfin_2 channel 2 rf input. this pin is dc blocked internally. 15 vdd_amp2 dc supply into channel 2 amplifier. there is a rf choke and 100 pf bypass capacitor internal to the module. 1 7 rf_out_2 channel 2 rf output. this pin is dc blocked internally. 24 rf_out_1 channel 1 rf output. this pin is dc blocked internally. 26 vdd_amp1 dc supply into channel 1 amplifier. there is a rf choke and 100 pf bypass capacitor internal to the module. backside paddle rf/dc gnd rf/dc ground. follow recommended via pattern and ensure good solder attach for best thermal and electrical performance.
TQC9311 0 .4 - 3.6 ghz dual channel dvga datasheet : rev. d 08 - 19 - 14 - 8 of 9 - disclaimer: subject to change without notice ? 2014 triquint www.triquint.com package dimensions and marking notes: 1. all dimensions are in millimeters. angles are in degrees. 2. except where noted, this part outline conforms to jedec standard mo - 270, issue b (variation dae) for extra thin profile, fine pitch, internal stack ing module (ism). 3. dimension and tolerance formats conform to asme y14.4m - 1994. 4. the terminal #1 identifier and terminal numbering conform to jesd 95 - 1 spp -012. 5. co - planarity applies to the exposed ground/thermal pad as well as the contact pins . pcb mounting pattern all dimensions are in millimeters (inches). angles are in degrees.
TQC9311 0 .4 - 3.6 ghz dual channel dvga datasheet : rev. d 08 - 19 - 14 - 9 of 9 - disclaimer: subject to change without notice ? 2014 triquint www.triquint.com product compliance information esd sensitivity ratings caution! esd - sensitive device esd rating: class 1b value: ? 500 ?v to < ?1 000?v test: human body model (hbm) standard: esda/ jedec standard js - 001 - 2012 esd rating: class c3 value: ? 1000v test: charged device model (cdm) standard: jedec standard jesd22 - c101 f solderability compatible with both lead - free (260 c max. refl ow temp.) and tin/lead (245 c max. reflow temp.) soldering processes. package lead plating: electrolytic plated au over ni. rohs compliance this part is compliant with eu 2002/95/ec rohs directive (restrictions on the use of certain hazardous substances in electrical and electronic equipment). this product also has the following attributes: ? halogen free (chlorine, bromine) ? antimony free ? tbbp - a (c 15 h 12 br 4 0 2 ) free ? pfos free ? svhc free ? lead free msl rating msl rating: level 3 test: +260 c convection re flow standard: jedec standard ipc/jedec j - std - 020 contact information for the latest specifications, additional product information, worldwide sales and distribution locations, and information about triquint: web: www.triquint.com tel: +1.503.615.9000 email: info - sales@triquint.com fax: +1.503.615.8902 for technical questions and application information: email: sjcapplications.engineering@triquint.com important notice the information contained herein is believed to be reliable. triquint makes no warranties regarding the information contained herein. triquint assumes no responsi bility or liability whatsoever for any of the information contained herein. triquint assumes no responsibility or liability whatsoever for the use of the information contained herein. the information contained herein is provided "as is, where is" and wit h all faults, and the entire risk associated with such information is entirely with the user. all information contained herein is subject to change without notice. customers should obtain and verify the latest relevant information before placing orders f or triquint products. the information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information it self or anything described by such information. triquint products are not warranted or authorized for use as critical components in medical, life - saving, or life - sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death.
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