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document no. doc-12914-3 www.psemi.com page 1 of 13 ?2012-2015 peregrine semiconductor corp. all rights reserved. product description the pe42920 is a dual differential single pole double throw (ddspdt) rf switch developed on peregrine?s ultracmos ? process technology. it is a broadband and low loss device enabling the switching of two independent differential signals. this device consumes less power than active differential switches and offers 2 kv hbm esd protection. it has high isolation between same channel inputs as well as opposite active channels. it has been designed for low phase mismatch between matched paths. the pe42920 is manufactured on peregrine?s ultracmos process, a patented variation of silicon-on- insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. product specification ultracmos ? passive ddspdt high-isolation rf switch 10 khz?6 ghz pe42920 features ?? dual differential single pole double throw switch ?? broadband: 10 khz to 6 ghz ?? low frequency insertion loss: 0.7 db typical ?? high isolation between same channels at 6 ghz: 26 db typical ?? high isolation between opposite active channels at 6 ghz: 30 db typical ?? low phase mismatch between matched paths at 6 ghz: 15 degrees typical ?? high esd performance: 2 kv hbm figure 1. functional diagram note: differential pairs b1/b2 and y1/y2 must be switched simultaneously to pairs c1/c2 and z1/z2. see table 5 , truth table. figure 2. package type 16-lead 3 3 mm qfn doc-52427 50 k 100 k 50 k 100 k v dda a1 b1 c1 b2 c2 a2 50 k 100 k 50 k 100 k v ddx x1 y1 z1 y2 z2 x2 cmos control / driver and esd v ddx v sel v dda
product specification pe42920 page 2 of 13 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-12914-3 ultracmos ? rfic solutions table 1. typical specifications v dd = 3.3v, temp = +25 c (z s = z l = 100 ? differential) min/max specifications v dd = 3.3v 10%, ?40 c temp +85 c, (z s = z l = 100 ? differential) ac coupled ? exter nal dc blocking caps electrical parameter condition/notes min typ max unit frequency range 10 khz 6 ghz as shown differential 3 db bandwidth 5.6 6 ghz insertion loss at 10 khz v cm = 1.1v 0.7 1.25 db insertion loss at 1 ghz v cm = 1.1v 1.0 1.4 db isolation between same channel inputs at 6 ghz a to c when b is on. a to b when c is on x to z when y on. x to y when z is on 24 26 db isolation between opposite (active) channels at 6 ghz channels a ? x. v cm = 1.1v 25 30 db input 1db compression* (p 1db ) vcm = 1.1v, differential 10 13 dbm return loss common ports a and x differential 50?1250 mhz 1250?2500 mhz 2500?4000 mhz 12.5 8 5.5 14 9 8 db db db single ended 50?1250 mhz 1250?2500 mhz 2500?4000 mhz 14.5 12 10.5 17.5 14 13 db db return loss active ports b, c, y, z differential 50?1250 mhz 1250?2500 mhz 2500?4000 mhz 12.5 8.5 8 15.5 9.5 9.5 db db db single ended 50?1250 mhz 1250?2500 mhz 2500?4000 mhz 16 13 10.5 18.5 16 14.5 db db db switching time 50% control to 10/90% rf 270 450 ns phase mismatch on matched paths at 6 ghz v sel = 1 matched paths (a1 ? b1 & a2 ? b2) (x1 ? y1 & x2 ? y2) v sel = 0 matched paths (a1 ? c1 & a2 ? c2) (x1 ? z1 & x2 ? z2) v cm = 1.1v 15 30 degrees phase mismatch on un-matched paths at 6 ghz unmatched: average of a1,a2 delay to average of x1,x2 v cm = 1.1v 22 50 degrees phase delta stability across voltage and temperature 2 degrees common mode voltage common port self biased v cm (v cm v dd /3) 1.1 v common mode impedance common port bias resistances z cm to v dd z cm to gnd 100 50 k ? k ? input ip3 single ended (see figure 19 ) dbm operating frequency note: * p1db is an indication of device linearity, max operating power is restricted to limits in table 3.
product specification pe42920 page 3 of 13 document no. doc-12914-3 www.psemi.com ?2012-2015 peregrine semiconductor corp. all rights reserved. figure 3. pin configuration (top view) table 2. pin descriptions pin no. pin name description 1 c2 c-channel [logic low] rf port ? 2 c1 c-channel [logic low] rf port + 3 b2 b-channel [logic high] rf port ? 4 b1 b-channel [logic high] rf port + 5 vdda a-channel supply 6 a1 a-channel rf common port + 7 a2 a-channel rf common port ? 16 z1 z-channel [logic low] rf port + 8 gnd ground 13 y2 y-channel [logic high] rf port ? 9 vsel simultaneous logic select 12 vddx x-channel supply 10 x1 x-channel rf common port + 11 x2 x-channel rf common port ? 14 y1 y-channel [logic high] rf port + 15 z2 z-channel [logic low] rf port ? paddle gnd exposed solder pad: ground for proper operation table 3. operating ranges 2 parameter min typ max unit v dd 1 power supply voltage 2.97 3.3 3.63 v i dd supply current 100 500 a t op operating temperature ?40 85 c p dc dc power consumption 2 mw v ih v sel control voltage high 0.7xv dd v dd v v il v sel control voltage low 0 0.3xv dd v i ih/ i il i sel control current ? input high/low 1 a p max max. input power (100 ? differential, active port) 10 dbm p max max. input power (50 ? single ended, active port) 7 dbm v peak-to-peak max input differential (100 ? ) single ended (50 ? ) 2.8 1.4 v pp v pp notes: 1. operating below min. v dd results in degraded performance. 2. operation should be restricted to the limits in the operating ranges table. table 4. absolute maximum ratings exceeding absolute maximum ratings may cause permanent damage. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. parameter/condition min max unit p max max. input power (100 ? differential, active port) 10 dbm p max max. input power (50 ? single ended, active port) 7 dbm v sel control voltage 4 v i sw dc current on rf path 5 ma t st storage temperature ?65 +150 c v esd hbm esd voltage 1 2000 v esd mm esd voltage 2 100 v peak-to-peak max input differential (100 ? ) single ended (50 ? ) 2.8 1.4 v pp v pp v v notes: 1. hbm esd voltage (h bm, mil_std 883, method 3015.7). 2. mm esd voltage (jesd22-a115-a). exposed ground pad c2 c1 b2 b1 vdda a1 a2 gnd vddx x2 x1 vsel z1 z2 y1 y2 1 3 2 4 12 10 11 9 5 7 6 8 16 14 15 13 pin 1 dot marking
product specification pe42920 page 4 of 13 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-12914-3 ultracmos ? rfic solutions table 5. truth table: signal-path control logic path channel a channel x v sel a ? b a ? c x ? y x ? z low off on off on high on off on off a = differential pair a1/a2 b = differential pair b1/b2 c = differential pair c1/c2 x = differential pair x1/x2 y = differential pair y1/y2 z = differential pair z1/z2 latch-up avoidance unlike conventional cmos devices, ultracmos devices are immune to latch-up. electrostatic discharge (esd) precautions when handling this ultracmos device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. moisture sensitivity level the moisture sensitivity level rating for the pe42920 in the 16-lead 3 3 mm qfn package is msl1.
product specification pe42920 page 5 of 13 document no. doc-12914-3 www.psemi.com ?2012-2015 peregrine semiconductor corp. all rights reserved. typical performance data @ 3.3v and +25 c, unless otherwise specified figure 4. differential insertion loss over v dd figure 5. differential insertion loss over temp figure 6. differential active port (b, c, y, or z) return loss over v dd figure 7. differential active port (b, c, y, or z) return loss over temp
product specification pe42920 page 6 of 13 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-12914-3 ultracmos ? rfic solutions figure 8. differential common port (a or x) return loss over v dd figure 9. differential common port (a or x) return loss over temp typical performance data @ 3.3v and +25 c, unless otherwise specified figure 10. single-ended active port (b1, b2, c1, c2, y1, y2) return loss over v dd figure 11. single-ended active port (b1, b2, c1, c2, y1, y2) return loss over temp
product specification pe42920 page 7 of 13 document no. doc-12914-3 www.psemi.com ?2012-2015 peregrine semiconductor corp. all rights reserved. typical performance data @ 3.3v and +25 c, unless otherwise specified (cont.) figure 14. opposite channel (a to x) isolation over v dd figure 15. opposite channel (a to x) isolation over temp figure 12. single-ended common port (a1, a2, x1, x2) return loss over v dd figure 13. single-ended common port (a1, a2, x1, x2) return loss over temp
product specification pe42920 page 8 of 13 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-12914-3 ultracmos ? rfic solutions figure 16. same channel (a to b/c and x to y/z) isolation over v dd figure 17. same channel (a to b/c and x to y/z) isolation over temp typical performance data @ 3.3v and +25 c, unless otherwise specified (cont.) 20 25 30 35 40 45 50 55 60 0.1 1 10 100 1000 10000 iip3(dbm) frequency ? (mhz) vdd ? = ? 3.3v, ? temp ? = ? 25c figure 18. switching time (10/90% rf) figure 19. iip3 (single ended)
product specification pe42920 page 9 of 13 document no. doc-12914-3 www.psemi.com ?2012-2015 peregrine semiconductor corp. all rights reserved. \ 20 \ 15 \ 10 \ 5 0 5 10 15 20 \ 40 25 85 phase ? delta ? [deg] temperature ? [ c] b2 \ b1 c2 \ c1 y2 \ y1 z2 \ z1 0 5 10 15 20 25 2.97 3.3 3.63 phase ? delta ? [deg] vdd ? [v] b \ y c \ z b \ z c \ y \ 20 \ 15 \ 10 \ 5 0 5 10 15 20 2.97 3.3 3.63 phase ? delta ? [deg] vdd ? [v] b2 \ b1 c2 \ c1 y2 \ y1 z2 \ z1 figure 20. phase delta matched paths (6 ghz and +25 c) stability across v dd figure 21. phase delta matched paths (6 ghz and 3.3v) stability across temp figure 22. phase delta un-matched paths (6 ghz and +25 c) stability across v dd figure 23. phase delta un-matched paths (6 ghz and 3.3v) stability across temp
product specification pe42920 page 10 of 13 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-12914-3 ultracmos ? rfic solutions evaluation board the ddspdt switch evaluation kit board was designed to ease customer evaluation of the pe42920 ddspdt switch. calibration structures are available on the bottom side of the pcb. as an alternate connector option, a through transmission line connects connectors j14 and j13. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. j20 provides a means for applying v dd and controlling the logic of the device. a jumper can be used to set aux = v dd or aux = gnd,* to toggle the logic state. proper pcb design is essential for full isolation performance. this evaluation board demonstrates good trace and ground management for minimum coupling and radiation. dc blocking capacitors (external or on board) are required to prevent interaction with external test equipment. they can be used as external broadband dc blocks or replace 0 ? resistors on board with the desired capacitance value on operation frequency. note: * silkscreen error ? aux and v sel labels are swapped. aux jumper pin on j20 header is equivalent to the v sel control in the block diagram. v sel jumper pin on j20 header is a no connect. figure 24. evaluation board layouts top bottom prt-09905 logic = high logic = low
product specification pe42920 page 11 of 13 document no. doc-12914-3 www.psemi.com ?2012-2015 peregrine semiconductor corp. all rights reserved. figure 25. evaluation board schematic 1,2,3 doc-12926 notes: 1. caution: contains parts and assemblies su sceptible to damage by elec trostatic discharge (esd). 2. silkscreen error: aux and vsel labels are swapped on pcb at j20 location. 3. pin 8 is grounded in pe42920. short 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm j13 dni 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 10 10 12 12 14 14 13 13 9 9 11 11 j20 header 14 1 c2 2 c1 3 b2 4 b1 5 vdda 6 a1 7 a2 8 gnd 9 vsel 11 x2 10 x1 12 vddx 13 y2 14 y1 16 z1 15 z2 u1 pe42920 j1 sma j2 sma j3 sma j4 sma j5 sma j6 sma j7 sma j8 sma j9 sma j10 sma j11 sma j12 sma c14 10pf c13 0.01uf c16 10pf c15 0.01uf testpoint2 c18 dni r6 dni c1 0 ohm c2 0 ohm c3 0 ohm c4 0 ohm c5 0 ohm c6 0 ohm c7 0 ohm c8 0 ohm c9 0 ohm c10 0 ohm c11 0 ohm c12 0 ohm j14 dni j16 dni r1 0 ohm r2 0ohm r3 0ohm r4 0 ohm r5 0ohm r7 0 ohm c17 dni c19 dni c20 dni vdd y2 y1 z2 z1 c2 c1 b2 b1 x2 x1 a2 a1 thru aux vsel
product specification pe42920 page 12 of 13 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-12914-3 ultracmos ? rfic solutions figure 27. top marking specification doc-66062 figure 26. package drawing 16-lead 3 3 mm qfn doc-01881 top view side view bottom view 3.00 3.00 pin #1 corner 1.700.05 0.750.05 0.05 0.203 recommended land pattern 13 16 1 4 5 9 8 12 1.700.05 0.50 0.230.05 (x16) 1.50 0.3750.05 (x16) 1.75 3.40 3.40 0.10 c a b 0.05 c a 0.10 c (2x) c 0.10 c 0.05 c seating plane b all features 0.10 c (2x) 0.575 (x16) 0.28 (x16) 0.50 1.75 (x12) = yy = ww = zzzzz = pin 1 indicator last two digits of assembly year assembly work week assembly lot code (maximum five characters) 42920 yyww zzzzz
product specification pe42920 page 13 of 13 document no. doc-12914-3 www.psemi.com ?2012-2015 peregrine semiconductor corp. all rights reserved. table 6. ordering information figure 28. tape and reel specifications 16-lead 3x3 mm qfn order code description package shipping method pe42920mlaa-z pe42920 ddspdt rf switch green 16-lead 3 3 mm qfn 3000 units t/r EK42920-01 pe42920 evaluation b oard evaluation kit 1/box advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com . t k0 a0 b0 p0 p1 d1 a section a-a a direction of feed d0 e w0 p2 see note 3 see note 1 f see note 3 a0 b0 k0 d0 d1 e f p0 p1 p2 t w0 3.30 3.30 1.10 1.50 + 0.1/ -0.0 1.5 min 1.75 0.10 5.50 0.05 4.00 8.00 2.00 0.05 0.30 0.05 12.00 0.3 device orientation in tape pin 1 notes: 1. 10 sprocket hole pitch cumulative tolerance 0.2 2. camber in compliance with eia 481 3. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole

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