general description features ics9169c-41 block diagram frequency generator for pentiumpro? based systems 9169-41rev d 5/02/00 pin configuration 34-pin ssop pentium is a trademark on intel corporation. ? 12 selectable cpu/sdram/agp clocks up to 75 mhz six pci clocks, synchronous or asynchronous mode, pin selectable by bus select input (pin 19) one usb clock at 48mhz, meets intel jitter, accuracy, as well as rise and fall time requirements one i/o clock at 24mhz two ref. clocks at 14.318mhz cpu clocks to pci clock skew of 1-4ns (cpu early) low cpu and pci clock jitter <200ps low skew outputs, skew window 250ps for cpu clocks and for pci clocks improved output drivers are designed for low emi test mode 3.3v 10% operation space saving and low cost 34-pin ssop package the ics9169c-41 is a clock synthesize/driver chip for pentium, pentiumpro or cyrix 68x86 based motherboards using sdram. features include four dual purpose i/o pins which provide extra cpu clocks and enable the part to be packaged in a low-cost 34-pin ssop package. these four pins latch the select inputs at the internal power-on reset. additionally, the device meets the pentium and pentiumpro power-up stabilization, which requires that cpu and pci clocks be stable within 2ms after power-up. the ics9169c-41 clock outputs are designed for low emi emissions. controlled rise and fall times, unique output driver circuits and innovative circuit layout techniques enable the ics9169c-41 to have lower emi than other clock devices. the ics9169c-41 accepts a 14.318mhz reference crystal or clock as its input and runs from a 3.3v supply. ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ics9169c-41 pin descriptions r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 6 2 , 4 1 , 8 , 1v d d r w py l p p u s e g a t l o v 21 xn iz h m 8 1 3 . 4 1 y l l a n i m o n . t u p n i l a t s y r c 32 xt u oz h m 8 1 3 . 4 1 y l l a n i m o n . t u p t u o l a t s y r c 9 2 , 3 2 , 0 2 1 1 , 4d n gr w pd n u o r g 5 1 k l c u p ct u o e c n e r e f e r t u p n i e h t f o e l p i t l u m a e r a h c i h w t u p t u o k c o l c r o s s e c o r p . e l b a t g n i d e c e r p e h t n i n w o h s s a k c o l c 2 s fn i g n i m m a r g o r p n i p d e r a h s e e s . s n i p t c e l e s r e i l p i t l u m y c n e u q e r f . n o i t a n a l p x e r e h t r u f r o f t e e h s a t a d s i h t n i r e t a l n o i t p i r c s e d , 2 1 , 3 1 , 7 1 , 8 1 , 6 , 7 , 9 , 0 1 ) 2 : 7 , 0 1 , 1 1 ( k l c u p ct u ot u p t u o k c o l c u p c 5 1 8 k l c u p ct u o e c n e r e f e r t u p n i e h t f o e l p i t l u m a e r a h c i h w t u p t u o k c o l c r o s s e c o r p . e l b a t g n i d e c e r p e h t n i n w o h s s a k c o l c 1 s fn i g n i m m a r g o r p n i p d e r a h s e e s . n i p t c e l e s r e i l p i t l u m y c n e u q e r f . n o i t a n a l p x e r e h t r u f r o f t e e h s a t a d s i h t n i r e t a l n o i t p i r c s e d 6 1 9 k l c u p ct u o e c n e r e f e r t u p n i e h t f o e l p i t l u m a e r a h c i h w t u p t u o k c o l c r o s s e c o r p . e l b a t g n i d e c e r p e h t n i n w o h s s a k c o l c 0 s fn i g n i m m a r g o r p n i p d e r a h s e e s . s n i p t c e l e s r e i l p i t l u m y c n e u q e r f . n o i t a n a l p x e r e h t r u f r o f t e e h s a t a d s i h t n i r e t a l n o i t p i r c s e d 9 1 2 1 k l c u p ct u o e c n e r e f e r t u p n i e h t f o e l p i t l u m a e r a h c i h w t u p t u o k c o l c r o s s e c o r p . e l b a t g n i d e c e r p e h t n i n w o h s s a k c o l c l e s bn i k c o l c s u b ) w o l ( s u o n o r h c n y s a r o ) h g i h ( s u o n o r h c n y s r o f n o i t c e l e s a t a d s i h t n i r e t a l n o i t p i r c s e d g n i m m a r g o r p n i p d e r a h s e e s . n o i t a r e p o . n o i t a n a l p x e r e h t r u f r o f t e e h s 1 2 , 2 2 , 4 2 , 5 2 , 7 2 , 8 2) 1 : 6 ( k l c i c pt u o. y a l e d s n 4 - 1 h t i w u p c o t s u o n o r c n y s . s t u p t u o k c o l c i c p 0 3k l c b s ut u oz h m 8 4 t u p t u o k c o l c b s u 1 3k l c o it u oz h m 4 2 t u p t u o k c o l c o / i 2 3d d v ar w py l p p u s e g a t l o v g o l a n a 3 31 f e rt u o) z h m 8 1 3 . 4 1 ( t u p t u o k c o l c e c n e r e f e r 4 30 f e rt u o s t o l s a s i r o f ) z h m 8 1 3 . 4 1 ( t u p t u o k c o l c e c n e r e f e r c s e v i r d ( d a o l ) f p 5 4 =
ics9169c-41 functionality 3.3v10%, 0-70 c crystal (x1, x2) = 14.31818 mhz notes 1. tclk is supplied on xtalin pin 2. bidirectional cpuclk i/o pins are high in test mode. 2 s f1 s f0 s fn i l a t xk l c u p c ) 5 - 1 ( k l c i c p 1 = l e s b ) 5 - 1 ( k l c i c p 0 = l e s b ) 1 - 0 ( f e rk l c b s uk l c o i 000 z h m 8 1 3 . 4 1z h m 3 3 . 3 3z h m 7 6 . 6 1z h m 2 3z h m 8 1 3 . 4 1z h m 8 4z h m 4 2 00 1 z h m 8 1 3 . 4 1z h m 0 . 5 7z h m 5 . 7 3z h m 2 3z h m 8 1 3 . 4 1z h m 8 4z h m 4 2 010 z h m 8 1 3 . 4 1z h m 0 . 5 5z h m 5 . 7 2z h m 2 3z h m 8 1 3 . 4 1z h m 8 4z h m 4 2 011 z h m 8 1 3 . 4 1z - i hz - i hz - i hz - i hz - i hz - i h 10 0 z h m 8 1 3 . 4 1z h m 0 . 0 5z h m 0 . 5 2z h m 2 3z h m 8 1 3 . 4 1z h m 8 4z h m 4 2 10 1 z h m 8 1 3 . 4 1z h m 7 6 . 6 6z h m 3 3 . 3 3z h m 2 3z h m 8 1 3 . 4 1z h m 8 4z h m 4 2 110 z h m 8 1 3 . 4 1z h m 0 . 0 6z h m 0 . 0 3z h m 2 3z h m 8 1 3 . 4 1z h m 8 4z h m 4 2 111 k l c t ) 1 ( 2 / k l c t ) 2 ( 4 / k l c t3 / k l c tk l c t2 / k l c t4 / k l c t
ics9169c-41 absolute maximum ratings electrical characteristics at 3.3v supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ? 0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0 c to +70 c storage temperature . . . . . . . . . . . . . . . . . . . . . . ? 65 c to +150 c v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. s c i t s i r e t c a r a h c c d r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u e g a t l o v w o l t u p n i v l i --v 2 . 0 d d v e g a t l o v h g i h t u p n i v h i v 7 . 0 d d --v t n e r r u c w o l t u p n i i l i v 0 = n i v0 . 8 2 -5 . 0 1 --a t n e r r u c h g i h t u p n i i h i v = n i v d d 0 . 5 --0 . 5a t n e r r u c w o l t u p t u o 1 i l o s k l c f e r , i c p , u p c r o f ; v 8 . 0 = l o v0 . 6 10 . 5 2-a m t n e r r u c h g i h t u p t u o 1 i h o s k l c f e r , i c p , u p c r o f ; v 0 . 2 = l o v-0 . 0 3 -0 . 4 1 -a m t n e r r u c w o l t u p t u o 1 i l o k l c d e x i f r o f ; v 8 . 0 = l o v0 . 9 10 . 0 3-a m t n e r r u c h g i h t u p t u o 1 i h o k l c d e x i f r o f ; v 0 . 2 = l o v-0 . 8 3 -0 . 6 1 -a m e g a t l o v w o l t u p t u o 1 v l o f e r , i c p , u p c r o f ; a m 8 = l o i-3 . 04 . 0v e g a t l o v h g i h t u p t u o 1 v h o f e r , i c p , u p c r o f ; a m 8 - = h o i4 . 28 . 2-v e g a t l o v w o l t u p t u o 1 v l o s ' k l c d e x i f ; a m 8 1 = l o i-3 . 04 . 0v e g a t l o v h g i h t u p t u o 1 v h o s ' k l c d e x i f ; a m 8 1 - = h o i4 . 28 . 2-v t n e r r u c y l p p u s i d d d e d a o l n u s t u p t u o l l a ; z h m 6 . 6 6 @-5 75 9a m
ics9169c-41 electrical characteristics at 3.3v v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. s c i t s i r e t c a r a h c c a r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u e m i t e s i r 1 t1 rf e r t p e c x e l l a ; v 0 . 2 o t 8 . 0 , d a o l f p 0 2-9 . 02 . 1s n e m i t l l a f 1 t1 ff e r t p e c x e l l a ; v 8 . 0 o t 0 . 2 , d a o l f p 0 2-8 . 02 . 1s n e m i t e s i r 1 t2 rf e r t p e c x e l l a v 0 . 2 - 8 . 0 , d a o l f p 0 3-3 . 16 . 1s n e m i t l l a f 1 t2 ff e r t p e c x e l l a v 8 . 0 - 0 . 2 , d a o l f p 0 3-3 . 16 . 1s n e m i t e s i r3 r ty l n o f e r ; v 0 . 2 - 8 . 0 ; f p 5 4-7 . 10 . 2s n e m i t l l a f3 f ty l n o f e r ; v 8 . 0 - 0 . 2 ; f p 5 4-0 . 10 . 2s n e l c y c y t u d 1 dt v 5 . 1 = t u o v @ d a o l f p 5 4 , 0 3 , 0 25 40 55 5% a m g i s e n o , r e t t i j 1 t1 s 1 js k c o l c i c p & u p c-0 50 5 1s p e t u l o s b a , r e t t i j 1 t1 b a j) z h m 6 6 & 0 6 @ ( s k c o l c i c p & u p c0 5 2 --0 5 2s p a m g i s e n o , r e t t i j 1 t2 s 1 js k l c d e x i f & f e r-13% e t u l o s b a , r e t t i j 1 t2 b a js k l c d e x i f & f e r-0 . 15 . 2% e l c y c o t e l c y c - r e t t i jtc c s t u p t u o u p c-0 9 20 5 3s p 0 f e r & s k c o l c d e x i f-5 . 46% y c n e u q e r f t u p n i 1 fi 0 . 2 18 1 3 . 4 10 . 6 1z h m e c n a t i c a p a c t u p n i c i g o l 1 cn is n i p t u p n i c i g o l-5-f p r o t a l l i c s o l a t s y r c e c n a t i c a p a c 1 cx n is n i p 2 x , 1 x-8 1-f p e m i t n o - r e w o p 1 tn o v m o r fd dz h m 6 . 6 6 f o g n i s s o r c t s 1 o t v 6 . 1 = vd ds m 0 4 < p m a r y l p p u s -9 . 10 . 2s m e m i t g n i l t t e s y c n e u q e r f 1 ts o t n o i t i s i u q c a f o g n i s s o r c t s 1 m o r f g n i l t t e s % 1 < -0 . 20 . 4s m w e k s k c o l c 1 ) w o d n i w (t1 k sv 5 . 1 @ ; d a o l e m a s ; i c p - i c p & u p c o t u p c-8 8 10 0 3s p w e k s k c o l c 1 ) w o d n i w (2 k s t s i u p c ( v 5 . 1 @ ; ) f p 0 3 ( i c p - ) f p 0 2 ( u p c ) y l r a e 0 . 12 . 10 . 4s n
ics9169c-41 technical pin function descriptions vdd this is the power supply to the internal logic of the device as well as the following clock output buffers: this pin may be operated at any voltage between 3.0 and 3.7 volts. clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels of these clocks, please consult the ac parameter table in this data sheet. gnd this is the power supply ground return pin. x1 this pin serves one of two functions. when the device is used with a crystal, x1 acts as the input pin for the reference signal that comes from the discrete crystal. when the device is driven by an external clock signal, x1 is the device input pin for that reference clock. this pin also implements an internal crystal loading capacitor that is connected to ground. see the data tables for the value of the capacitor. x2 this pin is used only when the device uses a crystal as the reference frequency source. in this mode of operation, x2 is an output signal that drives (or excites) the discrete crystal. this pin also implements an internal crystal loading capacitor that is connected to ground. see the data tables for the value of the capacitor. cpu (1:12) these pins are the clock output that drive the processor and other cpu related circuitry that require clocks which are in tight skew tolerance with the cpu clock. see the functionality table at the beginning of this data sheet for a list of the specific frequencies that these clocks operate at and the selection codes that are necessary to produce these frequencies. some of these pin serve dual functions. pciclk clock output driver for the pci bus. fs0, fs1, fs2 these pins control the frequency of the clocks at the cpu, bus and sdram pins. see the funtionality table at the beginning of this data sheet for a list of the specific frequencies that these clock operate at and the selection codes that are necessary to produce these frequencies. the device reads these pins at power-up and stores the programmed selection code in an internal data latch. if a "1" value is desired for a specific frequency selection bit,a 10k ohm resistor must be connected from the appropriate fs pin to the vdd supply. if a "o" value is desired, then the 10k resistor must be connected to ground. after the internal power on reset latches the input data, these pins become output clocks and no further frequency selection is possible. 48mhz this is a fixed frequency clock that is typically used to drive usb peripheral device needs. 24mhz this is a fixed frequency clock that is typically used to drive super i/o peripheral device needs. ref (0:1) this is a fixed frequency clock that runs at the same frequency as the input freerence clock (typically 14.31818 mhz) is and typically used to drive video and isa bus requirements.
ics9169c-41 ordering information ics9169cf-41 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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