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AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 1 features ? very low output resistance ? extended supply voltage range: 12 .5 v to 24 v ? ttl/cmos compatible inputs ? cmos schmitt-triggered inputs ? matched propagation delay for both channels ? outputs in phase with inputs ? enable function ? under voltage lock out function ? automotive qualified ? leadfree, rohs compliant typical applications ? automotive general purpose dual low side driver ? gate transformer driver ? bridge tied gate transformer driver ? dc -dc converters secondary side driver ? hybrid power train driver product summary topology dual low side driver v out 12 .5 v C 24 v i o+ & i o- (vcc=15 v) > 6 a output resistance (max) 0. 65 ohm t on & t off (max) 55ns package psoic- 8n typical connection diagram vcc ina com inb outa outb to load en rg rg nc - vbatt + logic level input orderable part number package type standard pack note form quantity AUIRB24427Str psoic8-n tape & reel 2500 downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 2 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the de vice may occur. all voltage parameters are absolute voltages referenced to com lead. stresses beyond those lis ted under " absolute maximum ratings" may cause permanent damage to the device. these are s tress ratings only; and functional operation of the device at these or any other condition beyond t hose indicated in the Drecommended operating conditions is not implied. exposure to absolute -maximum-rated conditions for extended periods may affect device reliability. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. ambient temperature (t a ) is 25c, unless otherwise specified. recommended operating conditions for proper operation the device should be used within the recommended conditions. all voltage parameters are absolute voltage referenced to com. symbol definition min. max. units v cc fixed supply voltage -0.3 24 v v o output voltage -0.3 24 v in logic input voltage -0.3 5.5 v en logic enable voltage -0.3 5.5 rth jc thermal resistance, junction to case 4 c/w t j junction temperature 150 c t s storage temperature - 55 150 t l lead temperature (soldering, 10 seconds) 300 symbol definition min. max. units v cc fixed supply voltage 5 20 v v o output voltage 0 v cc v in logic input voltage 0 5 v en logic enable voltage 0 5 t a ambient temperature - 40 125 c r g external gate resistance 2.5 ?? c bp vcc to com bypass capacitance C x7r dielectric type. 1 ? f ? downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 3 static electrical characteristics unless otherwise specified, these specifications apply for an operating junction temperature range of - 40 c ta 125 c and power supply v cc =15 v. the v in and i in parameters are referenced to com and are applicable to input leads: ina and inb. the v o and i o parameters are referenced to com and are applicable to the output leads: outa and outb. ( ?) guaranteed by design symbol definition min typ max units test conditions v il logic D0 input voltage 0.8 v v ih logic D1 input voltage 2.5 v hys - in input voltage hysteresis 0.8 v enl logic D0 enable voltage 0.8 v enh logic D1 enable voltage 2.5 v hys - en enable voltage hysteresis 0.8 roh +25 source output resistance 450 m ? ta=+25c rol +25 sink output resistance 450 roh +125 source output resistance 650 ta=+125c rol +125 sink output resistance 650 voh +25 output high level voltage vcc- vo 450 mv ta=+25c, iout=100ma vol +25 output low level voltage vo 450 voh +125 output high level voltage vcc- vo 650 ta=+125c, iout=100ma vol +125 output low level voltage vo 650 i in+ logic D1 input bias current 25 50 a vin=5v, vcc=15v i in - logic D0 input bias current 1 vin=0v, vcc=15v i qb quiescent supply current 0.5 1.2 2.5 ma vcc=15v, ina & inb not switching v ccuvhys vcc supply undervoltage hysteresis 1.5 v v ccuv+ vcc supply undervoltage turn on threshold 10.5 11.5 12.6 v ccuv - vcc supply undervoltage turn off threshold 9.0 10.0 11 i o+ output high short circuit pulsed current ( ?) 6 a vcc=15v, pw<10us i o- output high short circuit pulsed current ( ?) 6 vcc=15v, pw<10us downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 4 dynamic electrical characteristics unless otherwise noted, these specifications apply for an operating junction temperature range of - 40 c ta 125 c with bias conditions of v cc = 15 v, cl = 4700pf. refer to figure t2 for switching time definition and to figure t3 for switching time test circuit (page 15 ). input/output table en ina inb outa outb l x l l l x l l h l l l l h h h h h this table is held true in the voltages ranges defined in the recommended conditions sectio n. see also fig. t1 on page 14. symbol definition min typ max units test conditions propagation delay characteristics ns c bp =10uf t on turn-on propagation delay 40 t off turn-off propagation delay 55 t on - en enable turn-on propagation delay 40 t off - en enable turn-off propagation delay 55 t r turn-on rise time 33 t f turn-off fall time 33 downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 5 functional block diagram : downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 6 input/output/enable pin equivalent circuit diagrams v cc com outa outb esd diode esd diode 24v lead definitions pin symbol description 1 en enable pin 2 ina logic input for gate driver output (outa), in phase 3 com ground 4 inb logic input for gate driver output (outb), in phase 5 outb gate drive output b 6 vcc supply voltage 7 outa gate drive output a 8 nc no connection downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 7 package information downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 8 symbols dimensions millimiter inches min max min max a --- 1.70 --- .067 a1 0 0.10 0 .004 a2 1.25 --- .049 --- b 0.31 0.51 .012 .020 c 0.17 0.25 .007 .010 d 4.90 .193 d1 3.20 3.40 .126 .134 e 6.00 bsc .236 bsc e1 3.90 bsc .153 bsc e2 1.00 --- .039 --- e 1.27 bsc .050 bsc h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 l1 1.04 ref .041 ref l2 0.25 bsc .010 bsc 0 8 0 8 recommended pcb footprint downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 9 part marking information downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 10 application information 1. gate driver the AUIRB24427S has been designer as a high current gate driver for single ended applications. thanks to its very high output current and low thermal resistance vs. pcb, it is capable to drive mosfets with very large input capacitance at frequencies up to fsw=200khz or higher without the need of negative supply. the following figure 1 shows the typical device application schematic: vcc ina com inb outa outb load en rg rg nc logic level input load vcc cbp figure 1: typical gate driver application rg values have to be selected based on the requested tr and tf of the application and may vary between 2.5 ? and 20 ??? while the input capacitance of the fets can go up to 20nf or more depending on fsw. since the very high peak output current, the bypass capacitor cpb has to be mounted in the close proximity of the vcc and com pins and a ceramic type with low esr has to be chosen. 2. bt -gtd (bridge tied gate transformer driver) this is a popular configuration that allows driving high side fets using a low side gate driver, the fig. 2 shows the typical schematic for a single fet drive: vcc ina com inb outa outb en rg,ps rg,ps nc logic level input rg,ss cdec pulsetransf. vcc cbp figure 2 : bridge tied gate driver configuration in this configuration the gate transformer parameters have a very important role, most manufacturers indicate the following in their datasheets: ? v* ? s ratings: this factor must be respected, in bipolar drive application (like the one shown in fig.2) a maximum of up to twice that parameter is still acceptable for most manufacturers, this factor then must be chosen accordingly to the following formula: downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 11 (1) where vprim is the voltage applied to the primary, ? is the duty cycle and fsw the switching frequency of the application; ? n, turns ratio: usually 1:1, in some cases 1:2 or 1:1:1 (dual driver) this determines the voltage ratio between primary and secondary; ? lp, primary inductance: this value determines the magnetizing inductance as follows: (2) where k is the coupling factor between primary and secondary windings. ? l lk , leakage inductance: this parameter, usually indicated at primary, is equal to: (3) the higher is lm, the lower is the magnetizing current flowing into the transformer and consequent power lo sses into the driver. on the other hand the lower is l lk , the lower and shorter will be the ringing of the secondary lc network created by l lk , and ciss of the fet , damped by rg,ss and much lower overshot will appear on the vgs across the fet during transition. then a too high lm requires a very good mec hanical construction of the gate transformer to achieve high k and consequent low l lk . in a gate driver application running in the range of 50khz-200khz and using the AUIRB24427S, a good choice is usually a lm between 300uh and 2mh and a l lk < 1 uh . this translate for the formula (2) and (3) above in a coupling factor k between 0.9940 and 0.9995 for good operation and to reduce unneeded power losses into the AUIRB24427S driver, the mag netizing current has to be kept i lm < 0.5a, from this then derives a minimum lm to be calculated as follows: (4) where vg is the gate driving voltage of the fet fig. 2.a show a good design waveform obtained with the following parameters: vg = +/ -15v, lm=400uh, l lk =0.4uh, n=1, fsw=100khz, ciss fet =10 nf , rg ,ps=3 ? , rg,ss=4 ? ?? cdec=1uf cdec is the ac coupling capacitor needed to reset the driver transformer flux, its value has to be calculated in a way that the voltage across it can be considered constant during normal operation. the higher the fsw the smaller will be cdec. a ceramic capacitor is normally used. downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 12 figure 3a: bridge tied gate driver waveforms the waveforms in fig. 2a show that: ? the lower is l lk , the lower and shorter is the ringing on the fets gate voltage, particular care must be paid to guarantee that the max vgs voltage of the fet is not exceeded during operation; ? the lower is l lk , the shorter is the propagation delay from the driver to the gate of the fet and the higher is the peak current into its gate; ? the higher is lm, the lower is i lm; at the primary side the gate peak current, summed to i lm , constitute the total current flowing out of the gate driver. downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 13 3. driving circuitry design: thermal considerations the following design example shows how to get a proper design of the gate driving circuitry considering the following target application data: ? switching frequency 150k hz . ? load capacitance range [10- 100 ] nf . ? supply voltage vcc=12v. the switching losses due to the charge/discharge of the capacitive load cl rep resent the main component of the ic power dissipation. these losses are proportionally shared between the ic out put resistance and the external gate resistance rg. as a consequence the thermal behavior of the ic, with the constraint o f a maximum junction temperature equal to 150c, is one of the key points in dimensioning the system parameters. fi gure 3 shows the power that is dissipated inside the ic as a function of load capacitance cl. the external resistance rg has been chosen in order to keep the product rl*cg as constant and equal to 300ns (refer to figure 4 for switching cir cuit schematic). for a given parameter sizing the value of pow allows to calculate the junction temperature tj as : ja th a j r pow t t ? ? ? ? (1) where t a is the ambient temperature and rth ja is the junction to ambient thermal resistance. figure 3: simulated ic power dissipation as a function of load capacitance. ic dissipated power 0.000 0.100 0.200 0.300 0.400 0.500 0.600 0.700 0 10 20 30 40 50 60 70 80 90 100 c [nf] pow [w] downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 14 4. bias and transient conditions the input pins of the ic are protected by esd events with the circuitry shown into Dfunctional block diagram section at par.: input/output/enable pin equivalent circuit diagrams. this shows that an esd diode is placed in between each of these pins and vcc. in case vcc voltage will be lower than one of the voltage applied to the se pins the diode will conduct. because of its power dissipation the junction temperature will increase. in order to av oid dangerous working conditions it is recommended to keep the vcc voltage always higher or equal to the ina/inb/ena ble pin voltages; it is remind that input voltage must respect the defined absolute maximum rating limits. 5. system functionality with improved thermal behavior. the psoic8n package is characterized by a metal thermal pad whose functionali ty is to reduce the junction to case thermal resistance. in order to better exploit this feature it is necessary to reduce as much as possible the thermal pad to pcb thermal resistance (rthtp-pcb in. fig. 4). two possible ways are suggested: a- foresee a footprint on layout that allows to solder the thermal pad to the pcb. b- use thermal material filling the air gap in between the thermal pad and the pcb. pcb plastic case thermal pad solder paste j tp rth j-tp rth tp-pcb pcb ambient rth pcb-a figure 4: steady state equivalent thermal circuit. 6. square input pulse distortion the following chapter provides a characterization of pulse width distortion. thi s is defined as the ratio between the output pulse width with respect to input pulse width. characterization is done w ith no load on outa and outb and it is applicable to both ina, inb and en input pulses. fig. 5a and 5b show the output pulse length with respect to input pulse len gth. in particular, fig. 5 a describes the pulse distortion in case of a short turn-on input pulse (e.g. low duty cycl e condition); while fig. 5b shows the pulse distortion in case of a turn-off input pulse (e.g. high duty cycle c ondition). downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 15 a b fig. 5 output pulse distortion in case of a short turn-on input pulse (a) and turn-off input pulse (b). 0 50 100 150 200 250 0 50 100 150 200 250 output pulse width [ns] input pulse width [ns] real ideal 0 50 100 150 200 250 0 50 100 150 200 250 output pulse width [ns] input pulse width [ns] real ideal downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 16 7. bypass capacitor the bypass capacitor stores an electrical charge that is released to t he power line whenever a transient voltage spike occurs. it provides a low-impedance supply source and it minimizes the noise generated by the switching of the outputs. it is recommended to place the bypass capacitor as close as possible to the ga te driver in order to improve its effectiveness by reducing the effect of parasitic inductance of pcb lines. the value of bypass capacitor is related to: a- the current that the gate driver has to provide to the outa/b loads during turn-on switching condition; b- the speed at which the output pin is driven; c- the maximum allowed drop on power supply pins. for instance, if it considered that outputs outa and outb provide 6a source current with 20ns rise time and the maximum wished drop on vcc pin is 0.1v, then the bypass capacitance can be calculat ed as: f v ns a v t i n c ? 4.2 1.0 20 6*2 * ? ? ? ? ? (1) where n is the number of outputs that are switching at the same time. in this case it has been considered that outa and outb are driven in phase. equation 1 does not contain the information about capacitance esr that introduces a further drop in the power supply voltage. as a consequence it is recommended to use low esr capac itances (e.g. x7r dielectric material). additional details figure t1: input/output timing diagram downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 17 figure t2 : switching time waveform definitions vcc ina com inb outa outb en nc cgb cga - vbatt + c bp vcc gnd gnd vcc en in in parameter definitio en in t on turn-on propagation delay 5v pulse 0v to 5v t off turn-off propagation delay 5v pulse 5v to 0v t on - en enable turn-on propagation delay pulse 0v to 5v 5v t off - en enable turn-off propagation delay pulse 5v to 0v 5v figure t3 : switching time test circuit and test conditions downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 18 qualification information qualification level automotive (per aec-q100) comments: this family of ics has passed an automotive qualification. irs industrial and consumer qualification level is granted by extension of the higher automotive level. moisture sensitivity level psoic8-n msl3 , 260c (per ipc/jedec j-std- 020) esd machine model class m2 ( +/ -150 v) (per aec-q100-003) human body model class h2 ( +/ -2500 v) (per aec-q100-002) charged device model class c4 ( +/ -1000 v) (per aec-q100-011) ic latch-up test class ii, level a (per aec-q100-004) rohs compliant yes ? qualification standards can be found at international rectifiers web site http://www.irf.com/ downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 19 important notice unless specifically designated for the automotive market, in ternational rectifier corporation and its subsidiaries (ir) reserv e the right to make corrections, modifications, enhancements, imp rovements, and other changes to its products and service s at any time and to discontinue any product or services without notic e. part numbers designated with the Dau prefix follow automotiv e industry and / or customer specific requirements with rega rds to product discontinuance and process change notific ation. all products are sold subject to irs terms and conditions of sale s upplied at the time of order acknowledgment. ir warrants performance of its hardware products to the specificati ons applicable at the time of sale in accordance with irs standard warranty. testing and other quality control technique s are used to the extent ir deems necessary to support this warranty. except where mandated by government requirements, tes ting of all parameters of each product is not necessarily performed. ir assumes no liability for applications assistance or cust omer product design. customers are responsible for their products and applications using ir components. to minimize the risks w ith customer products and applications, customers should provide adequate design and operating safeguards. reproduction of ir information in ir data books or data sheet s is permissible only if reproduction is without alterat ion and is accompanied by all associated warranties, conditions, li mitations, and notices. reproduction of this information with alterations is an unfair and deceptive business practice. ir is not resp onsible or liable for such altered documentation. informat ion of third parties may be subject to additional restrictions. resale of ir products or serviced with statements different fro m or beyond the parameters stated by ir for that product or servic e voids all express and any implied warranties for the asso ciated ir product or service and is an unfair and deceptive b usiness practice. ir is not responsible or liable for any such statements. ir products are not designed, intended, or authorized for u se as components in systems intended for surgical impl ant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of the ir product could create a situation where personal injury or death may occur. should buyer purchase or use ir products for any suc h unintended or unauthorized application, buyer shall inde mnify and hold international rectifier and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against a ll claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauth orized use, even if such claim alleges that ir was negligent regarding the de sign or manufacture of the product. only products certified as military grade by the defense log istics agency (dla) of the us department of defense, are designed and manufactured to meet dla military specifications required b y certain military, aerospace or other applications. buyers acknowledge and agree that any use of ir products not certifie d by dla as military-grade, in applications requiring mili tary grade products, is solely at the buyers own risk and that they are s olely responsible for compliance with all legal and re gulatory requirements in connection with such use. ir products are neither designed nor intended for use in a utomotive applications or environments unless the speci fic ir products are designated by ir as compliant with iso/ts 16949 requireme nts and bear a part number including the designation Dau. buyers acknowledge and agree that, if they use any non-des ignated products in automotive applications, ir will not be responsible for any failure to meet such requirements. for technical support, please contact irs technical assistance center http://www.irf.com/technical-info/ world headquarters: 101 n. sepulveda blvd., el segundo, california 90245 tel: (310) 252-7105 downloaded from: http:///
AUIRB24427S www.irf.com ? 2014 international rectifier sept 29 nd , 2014 20 rev description 1v7 june, 26 th 2013 updated datasheet parameters according to standard lots test results. outx_x splitted overt uvlo+ increased the max to 12.6v toff increased to 45ns from 40ns toff-en increased to 48ns from 40ns introduced voh/l parameters changed fig. t2. added application sections: 1- pulse width distortion 2- bypass capacitance 1v8 september, 23 rd 2013 updated pulse width distortion section based on new r0e silicon. added min vcc in recommended table. updated toff delay page 4 added cbp min in recommended table. 1v9 nov. 15 th updated comments on page 13 and 3 updated rdson max on page 1 2v0 dec 2013 updated vhys on page 3, removed tube packaging and updated typical applications on page 1, updated qualification information updated date, added important notice page, dr3 version 2v1 mar 18 th 2014 updated ton & toff value on page 1, updated toff limits on page 4 2v2 mar 24 th 2014 updated tr & tf value on page 4. last dr3 version 2v3 may 23 rd 2014 updated application sections adding typical and bt-gtd circuits. updated typi cal application list on page 1 sept.29,2104 part marking drawing updated downloaded from: http:///

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