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32013nkpc 20130225-s00009 no.a2177-1/20 semiconductor components industries, llc, 2013 march, 2013 http://onsemi.com LV5069JA overview LV5069JA is step-down switching regulator controller. the recommended operating range is 4.5v-23v. the operating current is about 68 a, and low power consumption is achieved. features and functions ? typical value of light load mode current is 68 a ? 4.5v to 23v operating input voltage range ? the oscillatory frequency can be set by the extern al pin. the oscillatory frequency is 300khz - 1mhz. ? output voltage adjustable to 1.26v ? built-in ocp circuit with p-by-p method ? when p-by-p is generated continuous ly, it shifts to the hiccup operation ? if connect c-hiccup to gnd pin, then latch-off when over current ? external capacitor soft-start ? under voltage lock-out, thermal shutdown and power good indication applications ? dvd/blu-raytm drivers and hdd ? lcd monitors and tvs ? point of load dc/dc converters ? office supplies typical application orderin g numbe r : ena2177 bi-cmos ic low power consumptio n and high efficiency step-down switching regulator controller 40 30 20 10 50 60 70 80 90 1 23 57 10 23 57 100 23 57 1000 23 57 23 57 load current -- ma efficienc y efficiency -- % 0 100 0.1 10000 v out = 5v v i n = 8 v v i n = 1 2 v v i n = 1 5 v gnd v in LV5069JA en c1: grm31cb31e106k [murata] c2: c2012jb0j106m [tdk] q1: cph6350 d1: sb3003ch l1: fdve1040-100m [toko] fb pg ref comp ss c-hiccup rt v in pdr i lim rsns hdrv 10 f 2 l1 10 h d1 q1 r4 r5 v out v fb c3 1 f c1 10 f 3 c2 r1 30m r2 v fb c8 2.2nf c7 2.2nf c7 4.7nf c7 1 f r7 470k r6 47k
LV5069JA no.a2177-2/20 specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit input voltage v in max 25 v pdr v in v v in -pdr 6 v hdrv v in v rsns v in v i lim v in v en v in v pg v in v ref 6 v rt ref v ss ref v fb ref v comp ref v allowable pin voltage c-hiccup ref v allowable power dissipation pd max specified substrate *1 0.74 w operating temperature topr -40 to +85 c storage temperature tstg -55 to +150 c *1 specified substrate : 114.3mm 76.1mm 1.6mm, fiberglass epoxy printed circuit board caution 1) absolute maximum ratings represent the va lues which cannot be exceeded for any length of time. caution 2) even when the device is used within the range of abso lute maximum ratings, as a result of continuous usage under hig h temperature, high current, high voltage, or drastic temperature change, the reliability of th e ic may be degraded. please contact us for the further detai ls. recommendation operating conditions at ta = 25 c parameter symbol conditions ratings unit input voltage range v in 4.5 to 23 v electrical characteristics at ta = 25 c, v in = 15v ratings parameter symbol conditions min typ max unit [reference voltage] internal reference voltage v ref 1.247 1.260 1.273 v pch drive voltage v pdr i out = 0 to -5ma v in -5.5 v in -5.0 v in -4.5 v [saw wave oscillator] oscillatory frequency f osc rt = 470k 280 330 380 khz [on/off circuit] ic startup voltage (en pin) v cnt _on 2.0 v in v disable voltage (en pin) v cnt _off 0.3 v [soft start circuit] soft start source current i ss _sc en > 2v 1.3 2.0 2.7 a soft start sink current i ss _sk en < 0.3v, ss = 0.4v 2 3 4 ma [uvlo circuit] uvlo release voltage v uvlon fb = comp 3.3 3.7 4.1 v uvlo lock voltage v uvlof fb = comp 3.02 3.42 3.82 v [error amplifier] input bias current i ea _in -100 -50 100 na error amplifier gain g ea 100 250 400 a/v output sink current i ea _osk fb = 1.75v -40 -20 -10 a output source current i ea _osc fb = 0.75v 10 20 40 a continued on next page. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LV5069JA no.a2177-3/20 continued from preceding page. ratings parameter symbol conditions min typ max unit [over current limit circuit] reference current i lim 48.4 55 61.6 a over current detection comparator offset voltage v lim _ofs -5 5 mv rsns pin input range v rsns v in -0.23 v in v hiccup timer start-up cycle n cyc 15 cycle hiccup comparator threshold voltage v thic 1.23 1.29 1.35 v hiccup timer charge current i hic 12 3 a [pwm comparator] maximum on-duty d max rt = 470k 94 % [logic output] power good ?l? sink current i pwrgd _l pg = 5v 4 5 6 ma power good ?h? leakage current i pwrgd _h pg = 5v 1 a power good threshold voltage v tpg 1.0 1.1 1.2 v power good hysteresis v pg _h 40 50 60 mv [output] high side output on resistance r onh 5 low side output on resistance r onl 9 high side output on current i onh 300 ma low side output on current i onl 150 ma [the entire device] standby current i ccs en < 0.3v 1 a light load mode consumption current i sleep en > 2v no switching 48 68 88 a thermal shutdown tsd *design guarantee 170 c *design guarantee: signifies target value in design. these parameters are not tested in an independent ic.
LV5069JA no.a2177-4/20 package dimensions unit : mm (typ) 3178b mounting pad sketch (unit: mm) caution: the mounting pad sketch is a reference value, which is not a guaranteed value. reference symbol ssop16(225mil) ee 5.80 e 0.65 b3 0.32 l1 1.00 ssop16(225mil) 5.2 4.4 6.4 0.22 0.65 (0.33) 18 9 16 0.5 0.15 1.5max 0.1 (1.3) 0 0.4 1.2 0.8 0.74 80 0.38 60 20 40 0100 -- 40 -- 20 pd max -- ta ambient temperature, ta -- c allowable power dissipation, pd max -- w specified substrate: 114.376.11.6mm 3 glass epoxy board e b3 l1 ee
LV5069JA no.a2177-5/20 evaluation board pattern diagram top bottom 2 nd layer 3 rd layer
LV5069JA no.a2177-6/20 pin assignment pin function description pin no pin name description 1 pg power good pin. connect to open drain of mos-fet in ics inside. setting output voltage to "l", w hen fb voltage is 1.05v or less. 2 en on/off pin. 3 i lim for current detection. sink current is about 55 a. the current limiter comparator works when an external resistor is connected between this pin and v in , and if the voltage of this resistor is less than the voltage of rsns then pch mos is turned off. this operation is reset each pwm pulse. 4 v in supply voltage pin. it is observed by the uvlo function. when its voltage becomes 3.7v or more, ics startup in soft start. 5 rsns current detection resistor connection pin. resistor is connected between v in and this pin, and the current flow to mosfet is measured. 6 hdrv the external high-side mosfet gate drive pin. 7 pdr pch mosfet gate drive voltage. the bypass capacitor is necessarily connected between this pin and v in . 8 gnd ground pin. ground pin voltage is reference voltage 9 nc nc pin. the nc pin becomes open in an ic. 10 rt oscillation frequency setting pin. resistor is connected between this pin and gnd. 11 c-hiccup it is capacitor connection pin for sett ing re-startup cycl e in hiccup mode. if connect it to gnd pin, t hen latch-off when over current. 12 ss capacitor connection pin for soft start. about 2.0 a current charges the soft start capacitor. 13 nc nc pin. the nc pin becomes open in an ic. 14 comp error amplifier output pin. the phase compensation network is connected between gnd pin and comp pin. thanks to current-mode control, comp pin voltage would tell y ou the output current amplitude. comp pin is connected internally to an init.comparator which com pares with 0.9v reference. if comp pin vo ltage is larger than 0.9v, ic operates in ?continuous mode?. if comp pin voltage is smaller than 0.9v, ic operates in ?discontinuous mode (low consumption mode)?. 15 fb error amplifier reverse input pin. ics make its voltage keep 1.26v. output voltage is divided by external resistances and it across fb. 16 ref reference voltage. 1 pg 16 ref 2 en 15 fb 3 i lim 14 comp 4 LV5069JA ssop16 top view v in 13 n.c. 5 rsns 12 ss 6 hdrv 11 c-hiccup 7 pdr 10 rt 8 gnd 9 n.c.
LV5069JA no.a2177-7/20 block diagram wake-up level-shift tsd uvlo.comp pwm comp pbypcomp band-gap bias 15pulse counter osc s r ck q ref pch drive lnit.comp slope clk pdr v in err.amp 1.1v enable hiccup.comp 1.26v pg.comp 6.hdrv enable q 9.13.nc 8.gnd 1.pg 15.fb 12.ss 14.comp 2.en 11.c-hiccup 10.rt 3.i lim 5.rsns 4.v in 7.pdr 16.ref
LV5069JA no.a2177-8/20 pin equivalent circuit pin no. pin name equivalent circuit 1 pg 1k pg gnd 2 en v in en gnd 4.8m 3 i lim v in i lim gnd 1k 5k 4 v in v in gnd 5 rsns v in rsns gnd 5k 5k 6 hdrv v in hdrv pdr 310k continued on next page.
LV5069JA no.a2177-9/20 continued from preceding page. pin no. pin name equivalent circuit 7 pdr v in gnd pdr 1.6m 1.3m 15 10k 10 8 gnd v in gnd 9 nc 10 rt 20k v in rt gnd 11 c-hiccup v in c-hiccup gnd 1k 12 ss 1k 10k v in ss gnd 13 nc continued on next page.
LV5069JA no.a2177-10/20 continued from preceding page. pin no. pin name equivalent circuit 14 comp v in comp gnd 1k 1k 70k 15 fb v in fb gnd 10k 5k 10k 16 ref v in ref gnd 10 10 1k 50k 600k 1.28m
LV5069JA no.a2177-11/20 detailed description power-save feature this ic has power-saving feature to enhance efficiency when the load is light. by shutting down unnecessary circuits, op erating current of the ic is minimized and high efficiency is realized. gnd v in LV5069JA en fb pg ref comp ss c-hiccup rt v in pdr i lim rsns hdrv l1 c5 r6 d1 q1 r4 r5 v out v fb c6 c7 c3 c1 c2 r1 r2 v fb v in r3 c8 r7 output voltage setting output voltage (v out ) is configurable by the resistance r4 between v out and fb and the r5 between fb and gnd. v out is given by the following equation (1). v out = (1 + r4 r5 ) v ref = (1 + r4 r5 ) 1.26 [v] (1) switching frequency setting the switching frequency (f osc ) is set by resistance r7 between rt and gnd. the relation of resistance r7 to switching frequency is shown in a right graph. soft start soft start time (t ss ) is configurable by the capacitor c7 between ss and gnd. the setting value of t ss is given by the equation (2). t ss = c7 v ref i ss = c7 1.26 2.0 10 -6 [ms] (2) power good fb constantly monitors v out . when fb voltage is lower than 1.05v, pg is pulled down to low. pg comparator has hysteresis of 50mv. because pg is open-d rain output, you can connect other ics w ith pg to realize wi red-or with other ics. 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 resistance r7 -- k ? oscillatory frequency -- khz
LV5069JA no.a2177-12/20 hiccup over-current protection over current limit (i cl ) is set by current sensing resister r1 and resistance (r2) between v in and i lim . the setting value of i cl is given by the equations (3) and (4). v lim = r2 i lim = r2 55 10 -6 [v] (3) i cl = v lim r1 = r2 55 10 -6 r1 [a] (4) when the voltage between v in and rsns (v rsns ) is higher than the voltage between v in and i lim for 15 consecutive times, the protection deems it as over current and stops the ic. stop period (t hic ) is defined by the external capacitor (c8) of the c-hiccup. the setting value of t hic is given by the equations (5). t hic = c8 v thic i hic = c8 1.29 2.0 10 -6 [s] (5) when c-hiccup is about 1.29v, the ic starts up. regardle ss of a status; whether it starts up or ss charge, once over current is detected, the ic stops again an d when the protection does not detect over current status, the ic starts up again. when the rsns pin exceeds the overcurrent limit value for 15 continuous times, the ic stops. * stop time is determined by the external capacitor connected to the c-hiccup pin when the c-hiccup pin exceeds 1.29v, the ic re-starts by soft-start. ? if the overcurrent is detected, then ic stops again. ? if the overcurrent is detected, then ic re-starts normally. * fb = 1.1v ? high v in v lim ss fb fb=1.05v pg rsns c-hiccup 1.29v
LV5069JA no.a2177-13/20 design procedure inductor selection when conditions for input voltage, output voltage and ripple current are defined, the following equations (6) give inductance value. l = v in - v out i r t on (6) t on = 1 {((v in - v out ) (v out + vf)) + 1} f osc f osc : oscillatory frequency vf : forward voltage of schottky barrier diode v in : input voltage v out : output voltage ? inductor current: peak value (i rp ) current peak value (i rp ) of the inductor is given by the equation (7). i rp = i out + v in - v out 2l t on (7) make sure that rating current value of the indu ctor is higher than a peak value of ripple current. ? inductor current: ripple current ( ? i r ) ripple current ( ? i r ) is given by the equation (8). i r = v in - v out l t on (8) when load current (i out ) is less than 1/2 of the ripple curren t, inductor current flows discontinuously. output capacitor selection make sure to use a capacitor with lo w impedance for switching power supply b ecause of large ripple current flows through output capacitor. this ic is a switching regulator which adopts current mode control method. therefore, you can use capacitor such as ceramic capacitor and os capacitor in which equivalent series resistance (esr) is exceedingly small. effective value is given by the equation (9) because the rippl e current (ac) that flows th rough output capacitor is saw tooth wave. i c_out = 1 2 3 v out (v in - v out ) l f osc v in [arms] (9) input capacitor selection ripple current flows through input capacitor which is higher than that of the output capacitors. therefore, caution is also required for allowable ripple current value. the effective value of the ripple current flows through input capacitor is given by the equation (10). i c_in = d (1 - d) i out [arms] (10) d = t on t = v out v in in (10), d signifies the ratio between on/off period. when th e value is 0.5, the ripple current is at a maximum. make sure that the input capacitor does not exceed the allowable ripple current value given by equation (10). in the board wiring from input capacitor, v in to gnd, make sure that wiring is wide enough to keep impedance low because of the current fluctuation. make sure to connect input capacitor near outp ut capacitor to lower voltage bound due to regeneration current. when change of load current is excessive (i out : high ? low), the power of output electric capacitor is regenerated to input capacitor. if input capacitor is small, input voltage increas es. therefore, you need to implement a large input capacitor. regeneration power changes according to the change of ou tput voltage, inductance of a coil and load current.
LV5069JA no.a2177-14/20 selection of external phase compensation component this ic adopts current mode control which allows use of ceramic capacitor with low es r and solid polymer capacitor such as os capacitor for output capacitor with simple phase compensation. therefore, you can design long-life and high quality step-down power supply circuit easily. frequency characteristics the frequency characteristic of this ic is c onstituted with the following transfer functions. (1) output resistance breeder : h r (2) voltage gain of error amplifier : g vea current gain : g mea (3) impedance of phase compensation external element : z c (4) current sense loop gain : g cs (5) output smoothing impedance : z o fb v ref g ver g mer r c c c z c r l c o z o comp clk current sence loop h r v o v in r sns r 2 r 1 osc 1/g cs q d c r closed loop gain is obtained with the following formula (11). g = h r ? g mer ? z c ? g cs ? z o = v ref v out ? g mer ? r c + 1 sc c ? g cs ? r l 1 + sc o ? r l (11) frequency characteristics of the closed loop gain is given by pole fp1 consists of output capacitor c o and output load resistance r l , zero point fz consists of external capacitor c c of the phase compensa tion and resistance r c , and pole fp2 consists of output impedance z er of error amplifier and external capacitor of phase compensation c c as shown in equation (9). fp1, fz, fp2 are obtained with the following equations (12) to (14). fp1 = 1 2 ? c o ? r l (12) fz = 1 2 ? c c ? r c (13) fp2 = 1 2 ? z er ? c c (14)
LV5069JA no.a2177-15/20 calculation of external phase compensation constant generally, to stabilize switching regula tor, the frequency where closed loop gain is 1 (zero-cross frequency f zc ) should be 1 10 of the switching frequency (or 1 5 ). since the switching frequency of this ic is 330khz, the zero-cross frequency should be 33khz. based on the above condition, we obtain the following formula (15). v ref v out ? g mer ? r c + 1 sc c ? g cs ? r l 1 + sc o ? r l = 1 (15) as for zero-cross frequency, since the impe dance element of phase compensation is rc >> 1 sc c , the following equation (16) is obtained. v ref v out ? g mer ? r c ? g cs ? r l 1 + 2 ? f zc ? c o ? r l = 1 (16) phase compensation external resistance can be obtained with the following equation (16), the variation of the equation (17). since 2 ? f zc ? c o ? r l >> 1 in the equation (17), we know that the external resistance is independent of load resistance. r c = v out v ref ? 1 g mer ? 1 g cs ? 1 + 2 ? f zc ? c o ? r l r l (17) when output is 5v and load resistance is 5 (1a load), r sns is 30m , the resistances of phase compensation are as follows. g cs = 0.125 r sns = 4.167a/v, g mer = 250 a/v, f zc = 33khz r c = 5 1.26 1 250 10 -6 1 4.167 1 + 2 3.14 (33 10 3 ) (30 10 -6 ) 5 5 = 24.45 10 3 = 24.45 [k ] if frequency of zero point fz and pole fp1 are in the same po sition, they cancel out each ot her. therefore, only the pole frequency remains for frequency characteristics of the closed loop gain. in other words, gain decreases at -20db/dec and phase only ro tates by 90o and this allows characteristics where oscillation never occurs. fp1 = fz 1 2 ? c o ? r l ? 1 2 ? c o ? r c c c = r l ? c o r c ? 5 (30 10 -6 ) 24.45 10 3 = 6.13 10 -9 = 6.13 [nf] the above shows external compensation constant obtained through ideal equations. in reality, we need to define phase constant through testing to verify constant ic operation at a ll temperature range, load range and input voltage range. in the evaluation board for delivery, phase compensation constants are defined based on the above constants. the zero-cross frequency required in the actual system board, in other word, transient response is adjust ed by external compensation resistance. also, if the influence of noise is significant, use of external phase co mpensation capacitor with higher value is recommended.
LV5069JA no.a2177-16/20 caution in pattern design pattern design of the board affects the char acteristics of dc-dc converter. this ic switches high current at a high speed. therefore, if inductance element in a pattern wiring is high, it c ould be the cause of noise. make sure that the pattern of the main circuit is wide and short. (1) pattern design of the input capacitor connect a capacitor near the ic for noise reduction between v in and the gnd. the change of current is at the largest in the pattern between an input capacitor and v in as well as between gnd and an in put capacitor among all the main circuits. hence make sure that the pattern is as thick and short as possible. (2) pattern design of an inductor and the output capacitor high electric current flows into the choke coil and the output capacitor. ther efore this pattern should also be as thick and short as possible. (3) pattern design with current channel into consideration make sure that when high side mosfet is on (red arro w) and off (orange arrow), the two current channels runs through the same channel and an area is minimized. (4) pattern design of the capacitor between v in -pdr make sure that the pattern of the capacitor between v in and pdr is as short as possible. (5) pattern design of the rsns rsns pattern should also be as think and short as possible for noise reduction. (6) pattern design of the small signal gnd the gnd of the small signal should be separated from the power gnd. (7) pattern design of the fb-out line wire the line shown in red between fb and out to the output capacitor as near as possible. when the influence of noise is significant, use of feedback resistors r2 and r3 with lower value is recommended. fig: fb-out line fb out
LV5069JA no.a2177-17/20 typical performance characteristics application curves at ta = 25 c operation waveforms (circuit from typical application, ta = 25 c, v in = 15v, v out = 5v) efficiency 10 20 30 40 50 60 70 80 90 20 30 40 50 60 70 80 90 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 0.1 1 23 57 10 23 57 100 23 57 1000 23 57 23 57 1 23 57 10 23 57 100 23 57 1000 23 57 23 57 10000 1 23 57 10 23 57 100 23 57 1000 23 57 23 57 1 23 57 10 23 57 100 23 57 1000 23 57 23 57 10000 load current -- ma efficiency efficiency -- % 0.1 load current -- ma efficiency efficienc y -- % 10 100 0.1 10000 load current -- ma efficiency efficiency -- % 10 100 0.1 10000 light load mode output voltage load current -- ma efficienc y -- % v out = 1.26v v out = 1.8v v out = 3.3v v out = 5v v i n = 5 v 1 5 v 1 2 v 8 v 8v v i n = 5 v v i n = 8 v 1 5 v 1 5 v 1 2 v v i n = 5 v 1 5 v 1 2 v i out = 10ma 10 s/div i out = 10ma 10 s/div v sw 5v/div i l 1a/div v out 20mv/div i l 1a/div 8v 1 2 v
LV5069JA no.a2177-18/20 i out = 2a 5 s/div i out = 2a 5 s/div v sw 5v/div i l 1a/div v out 20mv/div i l 1a/div discontinious current mode output voltage continious current mode output voltage load transient response over current protection soft start and shutdown i out = 200ma 5 s/div i out = 200ma 5 s/div v sw 5v/div i l 1a/div v out 20mv/div i l 1a/div i out = 0.5 ? 2.5a, slew rate = 100 s 500 s/div i out = 2a 2ms/div v out 0.2v/div i out 2a/div v out 5v/div v pg 10v/div v ss 5v/div v en 2v/div out - gnd short 10ms/div v ss 5v/div v hiccup 1v/div i out 5a/div v out 5v/div
LV5069JA no.a2177-19/20 characterization curves at ta = 25 c, v in = 15v light load mode consumption current 48 58 68 78 2 4 6 8 10 12 48 50 52 54 56 58 88 1.24 1.25 1.26 1.27 --50 --25 0 25 50 75 100 125 --25 0 25 50 75 100 125 --25 0 25 50 75 100 125 --25 0 25 50 75 100 125 --25 0 25 50 75 100 125 --25 0 25 50 75 100 125 --25 0 25 50 75 100 125 --25 0 25 50 75 100 125 150 150 temperature -- c internal reference voltag e internal reference voltage -- v -- 50 temperature -- c output on resistance output on resistance -- m 0 14 --50 150 temperature -- c reference current reference current -- a 46 60 --50 150 temperature -- c input current -- a 310 320 330 340 3.2 3.4 3.6 3.8 temperature -- c oscillatory frequency oscillatory frequency -- khz 300 350 --50 150 temperature -- c uvlo uvlo voltage -- v 3.0 4.0 --50 150 1.6 2.0 1.8 2.4 2.2 1.5 2.0 2.5 temperature -- c soft start source current soft start source current -- a 1.4 2.6 --50 150 temperature -- c hiccup timer charge current hiccup timer charge current -- a 1.0 3.0 --50 150 u v l o r e l e a s e v o l t a g e l o w s i d e h i g h s i d e u v l o l o c k v o l t a g e
LV5069JA ps no.a2177-20/20 ic startup voltage 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.00 1.10 1.05 1.15 1.20 --50 --25 0 25 50 75 100 125 --25 0 25 50 75 100 125 150 150 temperature -- c power good threshold voltage power good threshold voltage -- v --50 temperature -- c en voltage -- v on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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