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integrated circuits d a t a sh eet product speci?cation file under integrated circuits, ic20 1997 aug 01 P8XCE560 8-bit microcontroller
1997 aug 01 2 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 contents 1 features 2 general description 2.1 electromagnetic compatibility (emc) 2.2 recommendation on ale 3 ordering information 4 block diagram 5 functional diagram 6 pinning information 6.1 pinning diagram 6.2 pin description 7 functional description 8 memory organization 8.1 program memory 8.2 internal data memory 8.3 addressing 9 i/o facilities 10 pulse width modulated outputs (pwm) 10.1 prescaler frequency control register (pwmp) 10.2 pulse width register 0 (pwm0) 10.3 pulse width register 1 (pwm1) 11 analog-to-digital converter (adc) 11.1 adc features 11.2 adc functional description 11.3 adc timing 11.4 adc configuration and operation 11.5 adc during idle and power-down mode 11.6 adc resolution and characteristics 11.7 adc after reset 11.8 adc special function registers 12 timers/counters 12.1 timer 0 and timer 1 12.2 timer t2 12.3 watchdog timer t3 13 serial i/o ports 13.1 serial i/o port: sio0 (uart) 13.2 serial i/o port: sio1 (i 2 c-bus interface) 14 interrupt system 14.1 interrupt enable registers 14.2 interrupt handling 14.3 interrupt priority structure 14.4 interrupt vectors 14.5 interrupt enable and priority registers 15 power reduction modes 15.1 idle mode 15.2 power-down mode 15.3 wake-up from power-down mode 15.4 status of external pins 15.5 power control register (pcon) 16 oscillator circuits 16.1 xtal1; xtal2 oscillator: standard 80c51 16.2 xtal3; xtal4 oscillator: 32 khz pll oscillator (with seconds timer) 17 reset circuitry 17.1 power-on reset 18 instruction set 18.1 addressing modes 18.2 80c51 family instruction set 18.3 instruction set description 19 limiting values 20 dc characteristics 21 ac characteristics 22 eprom characteristics 22.1 programming and verification 22.2 security 23 special function registers overview 24 package outlines 25 soldering 25.1 introduction 25.2 reflow soldering 25.3 wave soldering 25.4 repairing soldered joints 26 definitions 27 life support applications 28 purchase of philips i 2 c components
1997 aug 01 3 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 1 features 80c51 central processing unit (cpu) 64 kbytes rom (only p83ce560) 64 kbytes eprom (only p87ce560) rom/eprom code protection 2048 bytes ram, expandable externally to 64 kbytes two standard 16-bit timers/counters an additional 16-bit timer/counter coupled to four capture registers and three compare registers a 10-bit analog-to-digital converter (adc) with eight multiplexed analog inputs and programmable autoscan two 8-bit resolution, pulse width modulation outputs five 8-bit i/o ports plus one 8-bit input port shared with analog inputs i 2 c-bus serial i/o port with byte oriented master and slave functions full-duplex uart compatible with the standard 80c51 on-chip watchdog timer 15 interrupt sources with 2 priority levels (2 to 6 external sources possible) phase-locked loop (pll) oscillator with 32 khz reference and software-selectable system clock frequency seconds timer software enable/disable of ale output pulse electromagnetic compatibility improvements wake-up from power-down by external or seconds interrupt frequency range for 80c51-family standard oscillator: 3.5 to 16 mhz extended temperature range: - 40 to +85 c supply voltage: 4.5 to 5.5 v. 2 general description the 8-bit microcontrollers p80ce560, p83ce560 and p87ce560 - hereafter referred to as P8XCE560 - are manufactured in an advanced cmos process and are derivatives of the 80c51 microcontroller family. the P8XCE560 contains a volatile 2048 bytes read/write data memory, five 8-bit i/o ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80c51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input adc, a dual digital-to-analog convertor (dac), pulse width modulated interface, two serial interfaces (uart and i 2 c-bus), a watchdog timer, an on-chip oscillator and timing circuits. the P8XCE560 is available in 3 versions: p80ce560: romless version p83ce560: containing a non-volatile 64 kbytes mask programmable rom p87ce560: containing 64 kbytes programmable eprom/otp. the P8XCE560 is a control-oriented cpu with on-chip program and data memory; it cannot be extended with external program memory. it can access up to 64 kbytes of external data memory. for systems requiring extra capability, the P8XCE560 can be expanded using standard ttl compatible memories and peripherals. in addition, the P8XCE560 has two software selectable reduced power modes: idle mode and power-down mode. the idle mode freezes the cpu while allowing the ram, timers, serial ports, and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator, causing all other chip functions to be inoperative.the power-down mode can be terminated by an external reset, by the seconds interrupt and by any one of the two external interrupts; see section 15.3. the device also functions as an arithmetic processor having facilities for both binary and bcd arithmetic as well as bit-handling capabilities. the instruction set of the P8XCE560 is the same as the 80c51 and consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three-byte. with a 16 mhz system clock, 58% of the instructions are executed in 0.75 m s and 40% in 1.5 m s. multiply and divide instructions require 3 m s.
1997 aug 01 4 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 2.1 electromagnetic compatibility (emc) primary attention is paid to the reduction of electromagnetic emission of the microcontroller P8XCE560. the following features reduce the electromagnetic emission and additionally improve the electromagnetic susceptibility: four digital part supply voltage pins (v dd1 to v dd4 ) and four digital ground pins (v ss1 to v ss4 ) are placed as pairs of v ddn and v ssn at two adjacent pins, at each side of the package. separated v dd pins for the internal logic and the port buffers. internal decoupling capacitance improves the emc radiation behaviour and the emc immunity. external capacitors should be connected across associated v ddn and v ssn pins (i.e. v dd1 and v ss1 ). lead length should be as short as possible. ceramic chip capacitors are recommended (100 nf). 2.2 recommendation on ale for applications that require no external memory or temporarily no external memory: the ale output signal (pulses at a frequency of 1 6 f osc ) can be disabled under software control (bit rfi; sfr: pcon.5); if disabled, no ale pulse will occur. ale pin will be pulled down internally, switching an external address latch to a quiet state. the movx instruction will still toggle ale (external data memory is accessed). ale will retain its normal high value during idle mode and a low value during power-down mode while in the rfi reduction mode. additionally during internal access ( ea = 1) ale will toggle normally when the address exceeds the internal program memory size. during external access ( ea = 0) ale will always toggle normally, whether the flag rfi is set or not. 3 ordering information notes 1. romless type. 2. rom coded type; nnn denotes the rom code number. 3. eprom/otp type. type number package frequency range (mhz) temperature range ( c) name description version p80ce560efb (1) qfp80 plastic quad ?at package; 80 leads (lead length 1.95 mm); body 14 20 2.8 mm sot318-2 3.5 to 16 - 40 to +85 p83ce560efb/nnn (2) p87ce560efb (3)
1997 aug 01 5 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 4 block diagram handbook, full pagewidth mbh074 rd wr psen xtal2 ale selxtal rstin xtal1 ad0 to ad7 a8 to a15 ea xtal3 xtal4 adexs adc0 to adc7 v ref(p)(a) v ref(n)(a) rstout ew cmsr0 to cmsr5 cmt0, cmt1 rt2 t2 ct0i to ct3i p4 p5 rxd txd p3 p2 p1 p0 t0 t1 int0 int1 v dd v ss v dda v ssa three 16-bit comparators with registers parallel i/o ports & ext. bus serial uart port 8-bit i/o ports four 16-bit capture latches 16-bit timer/ event counter (t2) 16 16 comparator output selection watchdog timer (t3) two 16 - bit timer/ event counters (t0,t1) 80c51 core excluding rom/ram cpu program memory data memory 256 bytes ram + 1792 bytes aux-ram dual pwm pll oscillator + 'seconds' timer i 2 c-bus serial i/o adc 8-bit internal bus P8XCE560 sda scl 64 kbytes rom/ eprom pwm0 pwm1 (4) (4) (4) (4) (7) (6) (5) (2) (2) (4) (4) (3) (1) (4) (4) fig.1 block diagram P8XCE560. (1) alternative function of port 0. (2) alternative function of port 1. (3) alternative function of port 2. (4) alternative function of port 3. (5) alternative function of port 5. (6) alternative function of port 6. (7) not present in p80ce560.
1997 aug 01 6 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 5 functional diagram fig.2 functional diagram. (1) only the p87ce560 with an alternative function. (2) v dda /v ssa - 2 analog supply pairs; v dd /v ss - 4 digital supply pairs. handbook, full pagewidth mbh075 P8XCE560 0 1 2 3 4 5 6 7 port 0 xtal3 v dda v dd v ssa v ss 0 1 2 3 4 5 6 7 port 1 0 1 2 3 4 5 6 7 (2) port 3 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 low order address and data bus alternative function 0 1 2 3 4 5 6 7 port 2 a8 a9 a10 a11 a12 a13 a14 a15 high order address bus ct0i/int2 ct1i/int3 ct2i/int4 ct3i/int5 t2 rt2 0 1 2 3 4 5 6 7 port 5 0 1 2 3 4 5 6 7 port 4 rstin rstout ew alternative function adc0 cmsr0 adc1 adc2 adc3 adc4 adc5 adc6 adc7 cmsr1 cmsr2 cmsr3 cmsr4 cmsr5 cmt0 cmt1 v ref(p)(a) v ref(n)(a) stadc psen pwm0 pwm1 xtal1 xtal2 rxd/data txd/clock t0 t1 rd wr int1 int0 ale/prog (1) ea/v pp (1) adexs scl sda xtal4 selxtal1
1997 aug 01 7 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 6 pinning information 6.1 pinning diagram fig.3 pin configuration qfp80/sot318 version. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 25 26 27 29 30 31 32 33 34 35 36 37 38 39 40 28 80 79 78 76 75 74 73 72 71 70 69 68 67 66 65 77 P8XCE560 v ssa1 v dda1 p5.7/adc7 p5.6/adc6 p5.5/adc5 p5.4/adc4 p5.3/adc3 p5.2/adc2 p5.1/adc1 p5.0/adc0 v ss1 v dd1 adexs p4.0/cmsr0 p4.1/cmsr1 p4.2/cmsr2 p4.3/cmsr3 rstout p4.4/cmsr4 ew pwm1 pwm0 v ref(p)(a) v ref(n)(a) p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 v ss3 v dd3 v ss4 v dd4 v ssa2 v dda2 xtal1 xtal2 n.c. n.c. p3.5/t1 p3.4/t0 p3.1/txd p3.0/rxd p3.2/int0 p3.3/int1 p3.6/wr p3.7/rd psen p4.5/cmsr5 p4.6/cmt0 p4.7/cmt1 v dd2 v ss2 rstin p1.7 p1.6 scl sda p1.0/ct0i/int2 p1.1/ct1i/int3 p1.2/ct2i/int4 p1.3/ct3i/int5 p1.4/t2 p1.5/rt2 mbh076 p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 xtal3 xtal4 selxtal1 ea/v pp (1) ale/prog (1) (1) only the p87ce560 with this alternative function.
1997 aug 01 8 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 6.2 pin description table 1 pin description for qfp80 (sot318-2) to avoid a latch-up effect at power-on: v ss - 0.5 v < voltage at any pin at any time < v dd + 0.5 v. symbol pin description v ref(n)(a) 1 low-end of adc reference resistor. v ref(p)(a) 2 high-end of adc reference resistor. v ssa1 3 ground , analog part. for adc receiver and reference voltage. v dda1 4 power supply , analog part (+5 v). for adc receiver and reference voltage. p5.7/adc7 to p5.0/adc0 5to12 port 5 (p5.7 to p5.0) : 8-bit input port lines; adc7 to adc0 : 8 input channels to the adc. v ss1 to v ss4 13, 29, 54, 67 ground; digital part; circuit ground potential. v ss1 , v ss2 , v ss4 must be connected, v ss3 is internally connected to digital ground, but should be connected externally. v dd1 to v dd4 14, 28, 53, 66 power supply, digital part (+5 v). power supply pins during normal operation and power reduction modes. all pins must be connected. adexs 15 start adc operation. input starting adc, triggered by a programmable edge; adc operation can also be started by software. this pin must not ?oat. pwm0 16 pulse width modulation output 0. pwm1 17 pulse width modulation output 1. ew 18 enable watchdog timer (wdt): enable for t3 watchdog timer and disable power-down mode. this pin must not ?oat. p4.0/cmsr0 to p4.5/cmsr5 19 to 22, 24, 25 port 4 ( p4.0 to p4.7) : 8-bit quasi-bidirectional i/o port lines; cmsr0 to cmsr5 : compare and set/reset outputs for timer t2; cmt0 to cmt1 : compare and toggle outputs for timer t2. p4.6/cmt0 to p4.7/cmt1 26, 27 rstout 23 reset output of the P8XCE560 for resetting peripheral devices during initialization and watchdog timer over?ow. rstin 30 reset input to reset the P8XCE560. p1.0/ct0i/int2 to p1.3/ct3i/int5 31 to 34 port 1 (p1.0 to p1.7) : 8-bit quasi-bidirectional i/o port lines; ct0i to ct3i : capture timer inputs for timer t2; int2 to int5 : external interrupts 2 to 5; t2 : t2 event input (rising edge triggered); rt2 : t2 timer reset input (rising edge triggered). p1.4/t2 to p1.5/rt2 35, 36 p1.6 to p1.7 37 to 38 scl 39 i 2 c-bus serial clock i/o port. if scl is not used, it must be connected to v ss . sda 40 i 2 c-bus serial data i/o port. if sda is not used, it must be connected to v ss . p3.0/rxd 41 port 3 (p3.0 to p3.7) : 8-bit quasi-bidirectional i/o port lines; rxd : serial input port; txd : serial output port; int0 : external interrupt input 0; int1 : external interrupt input 1; t0 : timer 0 external interrupt input; t1 : timer 1external interrupt input; wr : external data memory write strobe; rd : external data memory read strobe. p3.1/txd 42 p3.2/ int0 43 p3.3/ int1 44 p3.4/t0 45 p3.5/t1 46 p3.6/ wr 47 p3.7/ rd 48 n.c. 49, 50 not connected pins.
1997 aug 01 9 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 xtal2 51 crystal pin 2: output of the inverting ampli?er that forms the oscillator. left open-circuit when an external oscillator clock is used. xtal1 52 crystal pin 1: input to the inverting ampli?er that forms the oscillator, and input to the internal clock generator. receives the external oscillator clock signal when an external oscillator is used. must be connected to logic high if the pll oscillator is selected (selxtal1 = low). p2.0/a08 to p2.7/a15 55 to 62 port 2 (p2.0 to p2.7) : 8-bit quasi-bidirectional i/o port lines; a08 to a15 : high-order address byte for external memory. psen 63 program store enable output: read strobe to the external program memory via ports 0 and 2. is activated twice each machine cycle during fetches from external program memory. when executing out of external program memory two activations of psen are skipped during each access to external data memory. psen is not activated (remains high) during no fetches from external program memory. psen can sink/source 8 lsttl inputs. it can drive cmos inputs without external pull-ups. ale/ prog 64 address latch enable output. latches the low byte of the address during access of external memory in normal operation. it is activated every six oscillator periods except during an external data memory access. ale can sink/source 8 lsttl inputs. it can drive cmos inputs without an external pull-up. to prohibit the toggling of ale pin (rfi noise reduction) the bit rfi (sfr: pcon.5) must be set by software; see section 2.2. prog : the programming pulse input; alternative function for the p87ce560. ea/v pp 65 external access input. if, during reset, ea is held at a ttl level high the cpu executes out of the internal program memory. if, during reset, ea is held at a ttl level low the cpu executes out of external program memory via port 0 and port 2. ea is not allowed to ?oat. ea is latched during reset and dont care after reset. v pp : the programming supply voltage; alternative function for the p87ce560. p0.7/ad7 to p0.0/ad0 68 to 75 port 0 (p0.7 to p0.0) : 8-bit open-drain bidirectional i/o port lines; ad7 to ad0 : multiplexed low-order address and data bus for external memory. v dda2 76 power supply, analog part (+5 v). for pll oscillator. v ssa2 77 ground , analog part. for pll oscillator. xtal3 78 crystal pin 3: output of the inverting ampli?er that forms the 32 khz oscillator. xtal4 79 crystal pin 2: input to the inverting ampli?er that forms the 32 khz oscillator. xtal3 is pulled low if the pll oscillator is not selected (selxtal1 = 1) or if reset is active. selxtal1 80 selxtal1 = high, selects the hf oscillator, using the xtal1/xtal2 crystal. if selxtal1 = low the pll is selected for clocking of the controller, using the xtal3/xtal4 crystal. symbol pin description
1997 aug 01 10 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 7 functional description the P8XCE560 is a stand-alone high-performance microcontroller designed for use in real time applications such as instrumentation, industrial control, medium to high-end consumer applications and specific automotive control applications. in addition to the 80c51 standard functions, the device provides a number of dedicated hardware functions for these applications. the P8XCE560 is a control-oriented cpu with on-chip program and data memory, but it cannot be extended with external program memory. it can access up to 64 kbytes of external data memory. for systems requiring extra capability, the P8XCE560 can be expanded using standard memories and peripherals. the functional description of the device is described in: chapter 8 memory organization chapter 9 i/o facilities chapter 10 pulse width modulated outputs chapter 11 analog-to-digital converter (adc) chapter 12 timers/counters chapter 13 serial i/o ports chapter 14 interrupt system chapter 15 reduced power modes chapter 16 oscillator circuits chapter 17 reset circuitry.
1997 aug 01 11 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 8 memory organization the central processing unit (cpu) manipulates operands in three memory spaces; these are the 64 kbytes external data memory, 2048 bytes internal data memory (consisting of 256 bytes standard ram and 1792 bytes aux-ram) and the 64 kbytes internal or 64 kbytes external program memory (see fig.4). 8.1 program memory the program memory of the P8XCE560 consists of 64 kbytes rom or 64 kbytes eprom. if, during reset, the ea pin was held high, the P8XCE560 always executes out of the internal program memory. if the ea pin was held low during reset the P8XCE560 fetches all instructions from the external program memory. the ea input is latched during reset and is dont care after reset. the internal program memory content is protected by setting a mask programmable security bit (rom) or by the software programmable security bits (eprom) respectively, i.e. it cannot be read out at any time by any test mode or by any instruction in the external program memory space. the movc instructions are the only ones which have access to program code in the internal or external program memory. the ea input is latched during reset and is dont care after reset. this implementation prevents from reading internal program code by switching from external program memory to internal program memory during movc instruction or an instruction that handles immediate data. table 2 lists the access to the internal and external program memory with movc instructions whether the security feature has been activated or not. due to the maximum size of the internal program memory, the movc instructions can always operate either in the internal or in the external program memory. table 2 memory access by the movc instruction for code protection of the p87ce560 see section 23.2. note 1. not applicable due to 64 kbytes internal program memory. movc instruction program memory access internal external movc in internal program memory yes no (1) movc in external program memory no (1) yes 8.2 internal data memory the internal data memory is divided into three physically separated parts: 256 bytes of ram, 1792 bytes of aux-ram, and a 128 bytes special function registers (sfrs) area. these parts can be addressed each in a different way as described in sections 8.2.1 to 8.2.2 and table 3. table 3 internal data memory map 8.2.1 ram ram 0 to 127 can be addressed directly and indirectly as in the 80c51. address pointers are r0 and r1 of the selected register bank. ram 128 to 255 can only be addressed indirectly. address pointers are r0 and r1 of the selected register bank. four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower ram area. only one of these banks may be enabled at a time. the next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. the stack can be located anywhere in the internal 256 bytes ram. the stack depth is only limited by the available internal ram space of 256 bytes (see fig.6). all registers except the program counter and the four register banks reside in the special function register address space. 8.2.2 s pecial f unction r egisters the special function registers can only be addressed directly in the address range from 128 to 255 (see fig.7). 8.2.3 aux-ram aux-ram 0 to 1791 is indirectly addressable via page register (xramp) and movx-ri instructions, unless it is disabled by setting ard = 1 (see fig.5). when executing from internal program memory, an access to aux-ram 0 to 1791 will not affect the ports p0, p2, p3.6 and p3.7. aux-ram 0 to 1791 is also indirectly addressable as external data memory locations 0 to 1791 via movx-ri instructions, unless it is disabled by setting ard = 1. memory location address mode ram 0 to 127 direct and indirect 128 to 255 indirect only sfr 128 to 255 direct only aux-ram 0 to 1791 indirect only with movx
1997 aug 01 12 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 an access to external data memory locations higher than 1791 will be performed with the movx @dptr instructions in the same way as in the 80c51 structure, so with p0 and p2 as data/address bus and p3.6 and p3.7 as write and read timing signals. note that the external data memory cannot be accessed with r0 and r1 as address pointer if the aux-ram is enabled (ard = 0, default). 8.2.4 aux-ram p age r egister (xramp) the aux-ram page register is used to select one of seven 256-bytes pages of the internal 1792 bytes aux-ram for movx-accesses via r0 or r1. its reset value is xxxx x000b. table 4 aux-ram page register (address fah) table 5 description of xramp bits table 6 memory locations for all possible movx-accesses x = dont care. note 1. ard: aux-ram disable, is a bit in sfr pcon (bit pcon.6); see section 15.5. 76543210 xrampx xrampx xrampx xrampx xrampx xramp2 xramp1 xramp0 bit symbol function 7 to 3 xrampx reserved for future use. during read xrampx = unde?ned; a write operation must write logic 0s to these locations. 2 to 0 xramp2 to xramp0 aux-ram page select bits 2 to 0; see table 6. ard (1) xramp2 xramp1 xramp0 memory locations movx @ri,a and movx a,@ri instructions access 0 0 0 0 aux-ram locations 0 to 255 (reset condition) 0 0 0 1 aux-ram locations 256 to 511 0 0 1 0 aux-ram locations 512 to 767 0 0 1 1 aux-ram locations 768 to 1023 0 1 0 0 aux-ram locations 1024 to 1279 0 1 0 1 aux-ram locations 1280 to 1535 0 1 1 0 aux-ram locations 1536 to 1791 0 1 1 1 no valid memory access; reserved for future use 1 x x x external ram locations 0 to 255 movx @dptr,a and movx a,@dptr instructions access 0 x x x aux-ram locations 0 to 1791 (reset condition); external ram locations 1792 to 65535 1 x x x external ram locations 0 to 65535
1997 aug 01 13 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 fig.4 memory map and address space. h andbook, full pagewidth mbh077 internal (ea = 1) 64 kbytes external (ea = 0) 64 kbytes 64 kbytes 0 00 127 255 indirect only overlapped space special function registers auxiliary ram (ard = 0) 1792 bytes external data memory internal data memory program memory main ram direct and indirect 1791 (ard = 1) fig.5 indirect addressing aux-ram (1792 bytes); ard = 0 (bit pcon.6). handbook, full pagewidth mbh078 (xramp) = 06 h 0 255 255 1791 1536 1535 (xramp) = 05 h 0 255 1280 1279 (xramp) = 04 h 0 255 1024 1023 (xramp) = 03 h 0 255 768 767 (xramp) = 02 h 0 255 512 511 (xramp) = 01 h 0 255 0 256 255 0 (xramp) = 00 h movx @dptr, a movx a, @dptr movx @ri, a movx a, @ri
1997 aug 01 14 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 8.3 addressing the P8XCE560 has five methods for addressing: register direct register-indirect immediate base-register plus index-register-indirect. the first three methods can be used for addressing destination operands. most instructions have a destination/source field that specifies the data type, addressing methods and operands involved. for operations other than movs, the destination operand is also a source operand. access to memory addresses is as follows: register in one of the four register banks through register, direct or register-indirect addressing. internal ram (2048 bytes) through direct or register-indirect addressing. C internal ram: bytes 0 to 127; may be addressed directly/indirectly. C internal ram: bytes 128 to 255; share their address location with the sfrs and so may only be addressed indirectly as data ram. C aux-ram: bytes 0 to 1791; can only be addressed indirectly via movx. special function registers through direct addressing at address locations 128 to 255 (see fig.7). external data memory through register-indirect addressing. program memory look-up tables through base-register plus index-register-indirect addressing. fig.6 internal main ram bit addresses. mbh079 7f 7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70 6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60 5f 5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50 4f 4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 18h 17h 10h 0fh 08h 07h 00h 24 23 31 16 15 8 7 0 bank 0 bank 1 bank 2 bank 3 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 (msb) (lsb) 255 ffh 2fh 2eh 2dh 2ch 2bh 2ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 1fh byte address (decimal) byte address (hex) bit address (hex)
1997 aug 01 15 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 fig.7 special function registers bit addresses. handbook, full pagewidth mbh456 ff (msb) (lsb) ip1 ffh f8h register (mnemonic) byte address (hex) bit address (hex) pt2 pcm2 pcm1 pcm0 pct3 pct2 pct1 pct0 fe fd fc fb fa f9 f8 f7 b f0h f6 f5 f4 f3 f2 f1 f0 et2 ecm2 ecm1 ecm0 ect3 ect2 ect1 ect0 ef ien1 f8h ee ed ec eb ea e9 e8 c7 p4 c0h c6 c5 c4 c3 c2 c1 c0 - pad ps1 ps0 pt1 px1 pt0 px0 bf ip0 b8h be bd bc bb ba b9 b8 b7 p3 b0h b6 b5 b4 b3 b2 b1 b0 ea ead es1 es0 et1 ex1 et0 ex0 af ien0 a8h ae ad ac ab aa a9 a8 a7 p2 a0h a6 a5 a4 a3 a2 a1 a0 sm0 sm1 sm2 ren tb8 rb8 ti ri 9f s0con 98h 9e 9d 9c 9b 9a 99 98 97 p1 90h 96 95 94 93 92 91 90 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 8f tcon 88h 8e 8d 8c 8b 8a 89 88 87 p0 80h 86 85 84 83 82 81 80 e7 acc e0h e6 e5 e4 e3 e2 e1 e0 cr2 ens1 sta sto si aa cr1 cr0 cy ac f0 rs1 rs0 ov f1 p df s1con d8h psw d0h tm2ir c8h de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t2ov cmi2 cmi1 cmi0 cti3 cti2 cti1 cti0 cf ce cd cc cb ca c9 c8
1997 aug 01 16 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 9 i/o facilities the P8XCE560 has six 8-bit ports. ports 0 to 3 are the same as in the 80c51, with the exception of the additional functions of port 1. the parallel i/o function of port 4 is equal to that of ports 1, 2 and 3. all ports are bidirectional with the exception of port 5 which is only a parallel input port. ports 0, 1, 2, 3, 4 and 5 perform the following alternative functions: port 0 provides the multiplexed low-order address and data bus used for expanding the P8XCE560 with standard memories and peripherals. port 1 is used for a number of special functions: 4 capture inputs (or external interrupt request inputs if capture information is not utilized) external counter input external counter reset input. port 2 provides the high-order address bus when the P8XCE560 is expanded with external data memory and / or the P8XCE560 executes from external program memory. port 3 pins can be configured individually to provide: external interrupt request inputs counter inputs receiver input and transmitter output of serial port sio 0 (uart) control signals to read and write external data memory. port 4 can be configured to provide signals indicating a match between timer/counter t2 and its compare registers. port 5 may be used in conjunction with the adc interface. unused analog inputs can be used as digital inputs. as port 5 lines may be used as inputs to the adc, these digital inputs have an inherent hysteresis to prevent the input logic from drawing too much current from the power lines when driven by analog signals. channel-to-channel crosstalk should be taken into consideration when both digital and analog signals are simultaneously input to port 5 (see chapter 21). a pin of which the alternative function is not used may be used as normal bidirectional i/o. the generation or use of a port 1, port 3 or port 4 pin as an alternative function is carried out automatically by the P8XCE560 provided the associated special function register bit is set high. the sda and scl lines serve the serial port si01 (i 2 c-bus). because the i 2 c-bus may be active while the device is disconnected from v dd , these pins are provided with open-drain drivers. figure 8 shows the pull-up arrangements of ports 1 to 4; transistor p1 is turned on for 2 oscillator periods after q makes a high-to-low transition. during this time, p1 also turns on p3 through the inverter to form an additional pull-up. fig.8 i/o buffers in the P8XCE560 (port 1 to port 4). handbook, full pagewidth mlc926 - 1 p1 p2 p3 input data read port pin 2 oscillator periods n strong pull-up i/o pin v i1 q from port latch input buffer dd
1997 aug 01 17 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 10 pulse width modulated outputs the P8XCE560 contains two pulse width modulated (pwm) output channels (see fig.9). these channels generate pulses of programmable length and interval. the repetition frequency is defined by an 8-bit prescaler pwmp, which supplies the clock for the counter. the prescaler and counter are common to both pwm channels. the 8-bit counter counts modulo 255, i.e., from 0 to 254 inclusive. the value of the 8-bit counter is compared to the contents of two registers: pwm0 and pwm1. provided the contents of either of these registers is greater than the counter value, the corresponding pwm0 or pwm1 output is set low. if the contents of these registers are equal to, or less than the counter value, the output will be high. the pulse-width-ratio is therefore defined by the contents of the registers pwm0 and pwm1. the pulse-width-ratio is in the range of 0 255 to 255 255 and may be programmed in increments of 1 255 . buffered pwm outputs may be used to drive dc motors. the rotation speed of the motor would be proportional to the contents of pwmn. the pwm outputs may also be configured as a dual dac. in this application, the pwm outputs must be integrated using conventional operational amplifier circuitry. if the resulting output voltages have to be accurate, external buffers with their own analog supply should be used to buffer the pwm outputs before they are integrated. the repetition frequency f pwm , at the pwmn outputs is given by: this gives a repetition frequency range of 123 hz to 31.4 khz (at f clk = 16 mhz). by loading the pwm registers with either 00h or ffh, the pwm channels will output a constant high or low level, respectively. since the 8-bit counter counts modulo 255, it can never actually reach the value of the pwm registers when they are loaded with ffh. when a compare register (pwm0 or pwm1) is loaded with a new value, the associated output is updated immediately. it does not have to wait until the end of the current counter period. both pwmn output pins are driven by push-pull drivers. these pins are not used for any other purpose. f pwm f clk 2 pwmp 1 + () 255 --------------------------------------------------------------- = fig.9 functional diagram of pulse width modulated outputs. handbook, full pagewidth mga154 i n t e r n a l b u s f clk pwmp pwm1 prescaler 8-bit counter 1/2 pwm0 8-bit comparator 8-bit comparator output buffer pwm1 output buffer pwm0
1997 aug 01 18 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 10.1 prescaler frequency control register (pwmp) reading pwmp gives the current reload value. the actual count of the prescaler cannot be read. table 7 prescaler frequency control register (address feh) table 8 description of pwmp bits 10.2 pulse width register 0 (pwm0) table 9 pulse width register (address fch) table 10 description of pwm0 bits 10.3 pulse width register 1 (pwm1) table 11 pulse width register (address fdh) table 12 description of pwm1 bits 76543210 pwmp.7 pwmp.6 pwmp.5 pwmp.4 pwmp.3 pwmp.2 pwmp.1 pwmp.0 bit symbol description 7 to 0 pwmp.7 to pwmp.0 prescaler division factor . the prescaler division factor = (pwmp) + 1. 76543210 pwm0.7 pwm0.6 pwm0.5 pwm0.4 pwm0.3 pwm0.2 pwm0.1 pwm0.0 bit symbol description 7 to 0 pwm0.7 to pwm0.0 pulse width ratio. 76543210 pwm1.7 pwm1.6 pwm1.5 pwm1.4 pwm1.3 pwm1.2 pwm1.1 pwm1.0 bit symbol description 7 to 0 pwm1.7 to pwm1.0 pulse width ratio. low/high ratio of pwm0 signals pwm0 () 255 pwm0 () C ----------------------------------------- - = low/high ratio of pwm1 signals pwm1 () 255 pwm1 () C ----------------------------------------- - =
1997 aug 01 19 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 11 analog-to-digital converter (adc) 11.1 adc features 10-bit resolution 8 multiplexed analog inputs programmable autoscan of the analog inputs bit oriented 8-bit scan-select register to select analog inputs continuous scan or one time scan configurable from 1 to 8 analog inputs start of a conversion by software or with an external signal eight 10-bit buffer registers, one register for each analog input channel interrupt request after one channel scan loop programmable prescaler (dividing by 2, 4, 6, 8) to adapt to different system clock frequencies conversion time for one analog-to-digital conversion: 15 to 50 m s differential non-linearity (dl e ): 1 lsb integral non-linearity (il e ): 2 lsb offset error (os e ): 2 lsb gain error (g e ): 4% absolute voltage error (a e ): 3 lsb channel-to-channel matching (m ctc ): 1 lsb crosstalk between analog inputs (c t ): < 60 db at 100 khz monotonic and no missing codes separated analog (v dda ,v ssa ) and digital (v dd ,v ss ) supply voltages reference voltage at two special pins: v ref(n)(a) and v ref(p)(a) . for information on the adc characteristics, refer to chapter 21. 11.2 adc functional description the P8XCE560 has a 10-bit successive approximation adc with 8 multiplexed analog input channels, comprising a high input impedance comparator, dac (built with 1024 series resistors and analog switches), registers and control logic. input voltage range is from v ref(n)(a) (typical 0 v) to v ref(p)(a) (typical +5 v). each of the set of 8 buffer registers (10-bit wide) store the conversion results of the proper analog input channel. eleven special function registers (sfrs) perform the user software interface to the adc; see table 14 for an overview of the adc sfrs. in order to have a minimum of adc service overhead in the microcontroller program, the adc is able to operate autonomously within its user configurable autoscan function. figure 10 shows the functional diagram of the adc. 11.3 adc timing a programmable prescaler is controlled by the user selectable bits adpr1 and adpr0 in sfr adcon to adapt the conversion time for different microcontroller clock frequencies. table 13 shows conversion times (t adc ) for one analog-to-digital conversion at some convenient system clock frequencies (f clk ) and adc programmable prescaler divisors: m . conversion time t adc =(6 m + 1) machine cycles. a conversion time t adc consists of one sample time period (which equals two bit conversion times), 10 bit conversion time periods and one machine cycle to store the result. after result storage an extra initializing time period follows to select the next analog input channel (according to the contents of sfr adpss), before the input signal is sampled.thus the time period between two adjacent conversions within an autoscan loop is larger than the pure time t adc . this autoscan cycle time is (7 m) machine cycles. at the start of an autoscan conversion the time between writing to sfr adcon and the first analog input signal sampling depends on the current prescaler value ( m ) and the relative time offset between this write operation and the internal (divided) adc clock. this gives a variation range for the analog-to-digital conversion start time of ( 1 2 m) machine cycles. table 13 conversion time con?guration examples note 1. prohibited t adc values; for t adc outside the limits of 15 m s t adc 50 m s, the specified adc characteristics are not guaranteed. m t adc ( m s) at f clk : 6 mhz 8 mhz 12 mhz 16 mhz 2 26.00 19.50 13.00 (1) 9.75 (1) 4 50.00 37.50 25.00 18.75 6 74.00 (1) 55.50 (1) 37.00 27.75 8 98.00 (1) 73.50 (1) 49.00 36.75
1997 aug 01 20 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 fig.10 functional diagram of adc. handbook, full pagewidth mbh080 8 8 2 2 10 10 10 8 2 latches adcon scan logic analog multiplexer internal bus 8 adpss read adrsln read adrsh 8 x 10-bit result registers adexs v ssa1 v dda1 v ref(n)(a) v ref(p)(a) adc0 to adc7 sar dac comparator 11.4 adc con?guration and operation every analog-to-digital conversion is an autoscan conversion. the two user selectable general operation modes are continuous scan and one-time scan mode. the desired analog input port channel(s) for conversion is(are) selected by programming analog-to-digital input port scan-select bits in sfr adpss. an analog input channel is included in the autoscan loop if the corresponding bit in sfr adpss is logic 1, a channel is skipped if the corresponding bit in sfr adpss is logic 0. an autoscan is always started according to the lowest bit position of sfr adpss that contains a logic 1. an autoscan conversion is started by setting the flag adsst in register adcon either by software or by an external start signal at input pin adexs, if enabled. either no edge (external start totally disabled), a rising edge or/and a falling edge of adexs is selectable for external conversion start by the bits adsre and adsfe in register adcon. after completion of an analog-to-digital conversion the 10-bit result is stored in the corresponding 10-bit buffer register. then the next analog input is selected according to the next higher set bit position in adpss, converted and stored, and so on. when the result of the last conversion of this autoscan loop is stored, the adc interrupt flag adint (sfr adcon), is set. it is not cleared by interrupt hardware - it must be cleared by software.
1997 aug 01 21 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 in continuous scan mode (adcsa = 1; adcon.2) the adc start and status flag adsst (adcon.3) retains the set state and the autoscan loop restarts from the beginning. in one-time scan mode (adcsa = 0) conversions stop after the last selected analog input was converted, adint (adcon.4) is set and adsst is cleared automatically. adsst cannot be set (neither externally nor by software) as long as adint = 1, i.e. as long as adint is set, a new conversion start - by setting flag adsst - is inhibited; actually it is only delayed until adint is cleared. if a logic 1 is written to adsst while adint = 1, this new value is internally latched and preserved, not setting adsst until adint = 0. in this state, a read of sfr adcon will display adsst = 0, because always the effective adc status is read. note that under software control the analog inputs can also be converted in arbitrary order, when one-time scan mode is selected and in sfr adpss only one bit is set at a time. in this case adint is set and adsst is cleared after every conversion. 11.5 adc during idle and power-down mode the analog-to-digital converter is active only when the microcontroller is in normal operating mode. if the idle or power-down mode is activated, then the adc is switched off and put into a power saving idle state - a conversion in progress is aborted, a previously set adsst flag is cleared and the internal clock is halted. the conversion result registers are not affected. the interrupt flag adint will not be set by activation of idle or power-down mode. a previously set flag adint will not be cleared by the hardware. (note: adint cannot be cleared by hardware at all, except for a reset - it must be cleared by the user software.) after a wake-up from idle or power-down mode a set flag adint indicates that at least one autoscan loop was finished completely before the microcontroller was put into the respective power reduction mode and it indicates that the stored result data may be fetched now - if desired. for further information on idle and power-down modes, refer to chapter 15. 11.6 adc resolution and characteristics the adc system has its own analog supply pins v dda1 and v ssa1 . it is referenced by two special reference voltage input pins sourcing the resistance ladder of the dac: v ref(p)(a) and v ref(n)(a) . the voltage between v ref(p)(a) and v ref(n)(a) defines the full-scale range. due to the 10-bit resolution the full scale range is divided into 1024 unit steps. the unit step voltage is 1 lsb, which is typically 5 mv (v ref(p)(a) = 5.12 v, v ref(n)(a) =0 v=v ssa1 ). the dac's resistance ladder has 1023 equally spaced taps, separated by a unit resistance r. the first tap is located 0.5 r above v ref(n)(a) , the last tap is located 1.5 r below v ref(p)(a) . this results in a total ladder resistance of 1024 r. this structure ensures that the dac is monotonic and results in a symmetrical quantization error. for input voltages between: v ref(n)(a) and [v ref(n)(a) + 1 2 lsb] the 10-bit conversion result code will be 0000000000b (= 000h or 0d) [v ref(p)(a) - 3 2 lsb] and v ref(p)(a) the 10-bit conversion result code will be 1111111111b (= 3ffh or 1023d). the result code corresponding to an analog input voltage (v in(a) ) can be calculated from the formula: the analog input voltage should be stable when it is sampled for conversion. at any times the input voltage slew rate must be less than 10 v/ms (5 v conversion range) in order to prevent an undefined result. this maximum input voltage slew rate can be ensured by an rc low pass filter with r = 2.2 k w and c = 100 nf. the capacitor between analog input pin and analog ground pin shall be placed close to the pins in order to have maximum effect in minimizing input noise coupling. 11.7 adc after reset after a reset of the microcontroller the adcon and adpss registers are initialized to zero. registers adrsln and adrsh are not initialized by a reset. result code 1024 v in(a) v ref(n)(a) C v ref(p)(a) v ref(n)(a) C ----------------------------------------------- - =
1997 aug 01 22 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 11.8 adc special function registers table 14 adc special function registers overview the sfrs are not bit addressable. for more information on special function registers refer to section 8.2. 11.8.1 adc r esult r egisters the binary result code of the analog-to-digital conversions is accessed by the adc result registers: adrsln (adrsl0 to adrsl7); eight input channel related conversion result sfrs for the 8 result lower bytes. each of adrsln is associated with the indexed analog input channel adcn (adc0/p5.0 to adc7/p5.7). adrsh for the adc; one general sfr for the 2 result upper bits (bit 9 and 8). during read (by software) of the adrsln register, simultaneously the two highest bits of the 10-bit conversion result are copied into the two latches, adrsh.0 and adrsh.1 (sfr adrsh) preserving them until the next read of any adrsln register. thus to ensure that the 10-bit result of the same single analog-to-digital conversion is captured, first read the adrsln register and then the adrsh register. table 15 adc result register low byte; adrsln; n = 0 to 7 (address see 86h to f6h) table 16 description of adrsln bits address name r/w reset value description 86h adrsl0 r - adc result registers low byte: adrsl0 to adrsl7 ; the read value after reset is indeterminate. their data are not affected by chip reset. 96h adrsl1 a6h adrsl2 b6h adrsl3 c6h adrsl4 d6h adrsl5 e6h adrsl6 f6h adrsl7 f7h adrsh r 00h adc result register high bits : one common result sfr for the upper 2 result bits. e7h adpss r/w 00h adc input port scan-select register . contains control bits to select the analog input channel(s) to be scanned for analog-to-digital conversion. d7h adcon r/w 00h adc control register . contains control and status bits for the analog-to-digital converter peripheral block. c7h p5 r - digital input port register ; shared with analog inputs. p5 is not affected by chip reset. 76543210 adrsn.7 adrsn.6 adrsn.5 adrsn.4 adrsn.3 adrsn.2 adrsn.1 adrsn.0 bit symbol description 7 to 0 adrsn.7 to adrsn.0 adc result lower byte.
1997 aug 01 23 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 17 adc result register high bits; adrsh (address f7h) table 18 description of adrsh bits 11.8.2 adc i nput p ort s can -s elect r egister (adpss) table 19 adc input port scan-select register (address e7h) table 20 description of adpss bits 11.8.3 adc c ontrol r egister (adcon) table 21 adc control register (address d7h) table 22 description of adcon bits 76543210 000000 adrsn.9 adrsn.8 bit symbol description 7to2 - the upper 6 bits adrsh.2 to adrsh.7 are always read as a logic 0. 1 to 0 adrsn.9 to adrsn.8 adc result upper 2 bits. 76543210 adpss7 adpss6 adpss5 adpss4 adpss3 adpss2 adpss1 adpss0 bit symbol description 7 to 0 adpss7 to adpss0 control bits to select the analog input channel(s) to be scanned for analog-to-digital conversion. if all bits adpss0 to adpss7 = 0, then no conversion can be started. if adpss is written while an analog-to-digital conversion is in progress (adsst = 1; adcon.3) then the autoscan loop with the previous selected analog inputs is completed ?rst. the next autoscan loop is performed with the new selected analog inputs. for each individual bit position adpssn (n = 0 to 7): if adpssn = 0, then the corresponding analog input is skipped in the autoscan loop if adpssn = 1, then the corresponding analog input is included in the autoscan loop. 76543210 adpr1 adpr0 adpos adint adsst adcsa adsre adsfe bit symbol description 7 adpr1 these two bits determine the value of the prescaler divisor (m); see table 23. 6 adpr0 5 adpos adpos is reserved for future use. must be a logic 0 if adcon is written. 4 adint adc interrupt. this ?ag is set when all selected analog inputs are converted (both in continuous scan and in one-time scan mode). an interrupt is invoked if this interrupt ?ag is enabled. adint must be cleared by software. it cannot be set by software.
1997 aug 01 24 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 23 prescaler selection 11.8.4 d igital i nput p ort r egister (p5) digital input port register (p5) is shared with analog inputs. p5 is not affected by chip reset. sfr p5 always represents the binary value of the logic level at input pins p5.0/adc0 to p5.7/adc7. reading p5 does not affect analog-to-digital conversions. but it is recommended to use the digital input port function of the hardware port 5 only as an alternative to analog input voltage conversions. simultaneous mixed operation is discouraged to guarantee a reliable and accurate adc result. for more information on p5 refer to chapter 9. table 24 digital input port register (address c7h) table 25 description of p5 bits 3 adsst adc start and status. setting this bit by software or by hardware (via adexs input) starts the analog-to-digital conversion of the selected analog inputs. adsst stays a logic 1 in continuous scan mode. in one-time scan mode, adsst is cleared by hardware when the last selected analog input channel has been converted. as long as adsst = 1, new start commands to the adc-block are ignored. an analog-to-digital conversion in progress is aborted if adsst is cleared by software. 2 adcsa adcsa =1 results in a continuous scan of the selected analog inputs after a start of an analog-to-digital conversion. adcsa = 0 results in an one-time scan of the selected analog inputs after a start of an analog-to-digital conversion. 1 adsre if adsre = 1, then a rising edge at input adexs will start the analog-to-digital conversion and generate a capture signal. if adsre = 0, then a rising edge at input adexs has no effect. 0 adsfe if adsfe = 1, then a falling edge at input adexs will start the analog-to-digital conversion and generate a capture signal. if adsfe = 0, then a falling edge at input adexs has no effect. adpr1 adpr0 prescaler divisor (m) 0 0 2 (default by reset) 01 4 10 6 11 8 76543210 p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 bit symbol description 7 to 0 p5.7 to p5.0 binary value of the logic level at input pins p5.0/adc0 to p5.7/adc.7. bit symbol description
1997 aug 01 25 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 12 timers/counters the P8XCE560 contains, three 16-bit timer/event counters: timer 0, timer 1 and timer t2 one 8-bit timer, t3. 12.1 timer 0 and timer 1 timer 0 and timer 1 may be programmed to carry out the following functions: measure time intervals and pulse durations count events generate interrupt requests. timers 0 and 1 each have a control bit in sfr tmod that selects the timer or counter function of the corresponding timer. in the timer function, the register is incremented every machine cycle. thus, one can think of it as counting machine cycles. since a machine cycle consists of 12 oscillator periods, the count rate is 1 12 the oscillator frequency. in the counter function, the register is incremented in response to a high-to-low transition at the corresponding external input pin, t0 or t1. in this function, the external input is sampled during s5p2 of every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the counter is incremented. thus, it takes two machine cycles (24 oscillator periods) to recognize a high-to-low transition. there are no restrictions on the duty cycle of the external input signal. to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. timer 0 and timer 1 can be programmed independently to operate in one of four modes: mode 0 8-bit timer or 8-bit counter each with divide-by-32 prescaler. mode 1 16-bit time-interval or event counter. mode 2 8-bit time-interval or event counter with automatic reload upon overflow. mode 3 timer 0: one 8-bit time-interval or event counter and one 8-bit time-interval counter. timer 1: stopped. when timer 0 is in mode 3, timer 1 can be programmed to operate in modes 0, 1 or 2 but cannot set an interrupt request flag or generate an interrupt. however, the overflow from timer 1 can be used to pulse the serial port baud rate generator. with a 16 mhz crystal, the counting frequency of these timers/counters is as follows: in the timer function, the timer is incremented at a frequency of 1.33 mhz ( 1 12 the system clock frequency) when programmed for external inputs: 0 to 660 khz ( 1 24 the system clock frequency). both internal and external inputs can be gated to the counter by a second external source for directly measuring pulse durations. when configured as a counter, the register is incremented on every falling edge on the corresponding input pin t0 or t1. the earliest moment, the incremented register value can be read is during the second machine cycle following the machine cycle within which the incrementing pulse occurred. the counters are started and stopped under software control. each one sets its interrupt request flag when it overflows from all highs to all lows (or automatic reload value), with the exception of mode 3 as previously described.
1997 aug 01 26 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 12.1.1 t imer /c ounter m ode c ontrol r egister (tmod) table 26 timer/counter mode control register (address 89h) table 27 description of tmod bits for timer 1 and timer 0 timer 0: bit tmod.0 to tmod.3; timer 1: bit tmod.4 to tmod.7; n = 0, 1. table 28 timer 0, timer 1 mode select 12.1.2 t imer /c ounter c ontrol r egister (tcon) table 29 timer/counter control register (address 88h) table 30 description of tcon bits 76543210 gate c/t m1 m0 gate c/t m1 m0 bit symbol description 7 and 3 gate gating control . when set timer/counter n is enabled only while intn pin is high and control bit trn (tr1 or tr0) is set. when cleared timer n is enabled whenever trn control bit is set. 6 and 2 c/t timer or counter selector . cleared for timer operation; input from internal system clock. set for counter operation; input from pin tn (t1 or t0). 5 and 1 m1 timer 0, timer 1 mode select ; see table 28. 4 and 0 m0 m1 m0 operating 0 0 timer tl0/tl1 serves as 5-bit prescaler. 0 1 16-bit timer/counter th0/th1 and tl0/tl1 are cascaded; there is no prescaler. 1 0 8-bit auto-reload timer/counter th0/th1 holds a value which is to be reloaded into tl0/tl1 each time it over?ows. 1 1 timer 0: tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits. 1 1 timer 1: timer/counter 1 stopped. 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit symbol description 7 and 5 tf1 and tf0 timer 1 and timer 0 over?ow ?ag . set by hardware on timer/counter over?ow. cleared by hardware when processor vectors to interrupt routine. 6 and 4 tr1 and tr0 timer 1 and timer 0 run control bit . set/cleared by software to turn timer/counter on/off. 3 and 1 ie1 and ie0 interrupt 1 and interrupt 0 edge ?ag . set by hardware when external interrupt edge detected. cleared when interrupt processed. 2 and 0 it1 and it0 interrupt 1 and interrupt 0 type control bit . set/cleared by software to specify falling edge/low level triggered external interrupts.
1997 aug 01 27 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 12.2 timer t2 timer t2 is a 16-bit timer/counter which has capture and compare facilities. the operational diagram is shown in figure 11. the 16 bit timer/counter is clocked via a prescaler with a programmable division factor of 1, 2, 4 or 8. the input of the prescaler is clocked with 1 12 of the clock frequency, or by an external source connected to the t2 input, or it is switched off. the maximum repetition rate of the external clock source is 1 12 f clk , twice that of timer 0 and timer 1. the prescaler is incremented on a rising edge. it is cleared if its division factor or its input source is changed, or if the timer/counter is reset (see in table 31). t2 is readable on the fly, without any extra read latches; this means that software precautions have to be taken against misinterpretation at overflow from least to most significant byte while t2 is being read. t2 is not loadable and is reset by the rst signal or at the positive edge of the input signal rt2, if enabled. in the idle or power-down mode the timer/ counter and prescaler are reset and halted. t2 is connected to four 16-bit capture registers: ct0, ct1, ct2 and ct3. a rising or falling edge on the inputs ct0i, ct1i, ct2i or ct3i (alternative function of port 1) results in loading the contents of t2 into the respective capture registers and an interrupt request. using the capture register ctcon (see table 35), these inputs may invoke capture and interrupt request on a positive edge, a negative edge or on both edges. if neither a positive nor a negative edge is selected for capture input, no capture or interrupt request can be generated by this input. the contents of the compare registers cm0, cm1 and cm2 are continuously compared with the counter value of timer t2. when a match occurs, an interrupt may be invoked. a match of cm0 sets the bits 0 to 5 of port 4, a cm1 match resets these bits and a cm2 match toggles bits 6 and 7 of port 4, provided these functions are enabled by the ste respectively rte registers. a match of cm0 and cm1 at the same time results in resetting bits 0-5 of port 4. cm0, cm1 and cm2 are reset by the rstin signal. for more information concerning the tm2con, ctcon, tm2ir and the ste/rte registers see data handbook ic20; section 80c51 family hardware description . port 4 can be read and written by software without affecting the toggle, set and reset signals. at a byte overflow of the least significant byte, or at a 16-bit overflow of the timer/counter, an interrupt sharing the same interrupt vector is requested. either one or both of these overflows can be programmed to request an interrupt. all interrupt flags must be reset by software. 12.2.1 t2 c ontrol r egister (tm2con) table 31 t2 control register (address eah) table 32 description of tm2con bits 76543210 t2is1 t2is0 t2er t2bo t2p1 t2p0 t2ms1 t2ms0 bit symbol description 7 t2is1 timer t2 16-bit over?ow interrupt select. 6 t2is0 timer t2 byte over?ow interrupt select. 5 t2er timer t2 external reset enable. when this bit is set, timer t2 may be reset by a rising edge on rt2 (p1.5). 4 t2bo timer t2 byte over?ow interrupt ?ag. 3 t2p1 timer t2 prescaler select (see table 33). 2 t2p0 1 t2ms1 timer t2 mode select (see table 34). 0 t2ms0
1997 aug 01 28 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 33 timer 2 prescaler select t2p1 t2p0 timer t2 clock 0 0 clock source 01 1 2 clock source 10 1 4 clock source 11 1 8 clock source table 34 timer 2 mode select t2ms1 t2ms0 mode selected 0 0 timer t2 halted (off) 01 1 12 f clk t2 clock source 1 0 test mode; do not use 1 1 t2 clock source = pin t2 12.2.2 c apture c ontrol r egister (ctcon) table 35 capture control register (address ebh) table 36 description of ctcon bits 12.2.3 i nterrupt f lag r egister (tm2ir) table 37 interrupt ?ag register (address c8h) table 38 description of tm2ir bits 76543210 ctn3 ctp3 ctn2 ctp2 ctn1 ctp1 ctn0 ctp0 bit symbol description 7 ctn3 interrupt triggered on negative edge of ct3i 6 ctp3 interrupt triggered on positive edge of ct3i 5 ctn2 interrupt triggered on negative edge of ct2i 4 ctp2 interrupt triggered on positive edge of ct2i 3 ctn1 interrupt triggered on negative edge of ct1i 2 ctp1 interrupt triggered on positive edge of ct1i 1 ctn0 interrupt triggered on negative edge of ct0i 0 ctp0 interrupt triggered on positive edge of ct0i 76543210 t2ov cmi2 cmi1 cmi0 cti3 cti2 cti1 cti0 bit symbol description 7 t2ov t2: 16-bit over?ow interrupt ?ag 6 cmi2 cm2: interrupt ?ag 5 cmi1 cm1: interrupt ?ag 4 cmi0 cm0: interrupt ?ag 3 cti3 ct3: interrupt ?ag 2 cti2 ct2: interrupt ?ag 1 cti1 ct1: interrupt ?ag 0 cti0 ct0: interrupt ?ag
1997 aug 01 29 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 12.2.4 s et e nable r egister (ste) table 39 set enable register (address eeh) table 40 description of ste bits 12.2.5 r eset /t oggle e nable r egister (rte) table 41 reset/toggle enable register (address efh) table 42 description of rte bits 76543210 tg47 tg46 sp45 sp44 sp43 sp42 sp41 sp40 bit symbol description 7 tg47 if high then p4.7 is reset on the next toggle, if low p4.7 is set on the next toggle. 6 tg46 if high then p4.6 is reset on the next toggle, if low p4.6 is set on the next toggle. 5 sp45 if high then p4.5 is set on a match between cm0 and t2. 4 sp44 if high then p4.4 is set on a match between cm0 and t2. 3 sp43 if high then p4.3 is set on a match between cm0 and t2. 2 sp42 if high then p4.2 is set on a match between cm0 and t2. 1 sp41 if high then p4.1 is set on a match between cm0 and t2. 0 sp40 if high then p4.0 is set on a match between cm0 and t2. 76543210 tp47 tp46 rp45 rp44 rp43 rp42 rp41 rp40 bit symbol description 7 tp47 if high then p4.7 toggles on a match between cm2 and t2. 6 tp46 if high then p4.6 toggles on a match between cm2 and t2. 5 rp45 if high then p4.5 toggles on a match between cm1 and t2. 4 rp44 if high then p4.4 toggles on a match between cm1 and t2. 3 rp43 if high then p4.3 toggles on a match between cm1 and t2. 2 rp42 if high then p4.2 toggles on a match between cm1 and t2. 1 rp41 if high then p4.1 toggles on a match between cm1 and t2. 0 rp40 if high then p4.0 toggles on a match between cm1 and t2.
1997 aug 01 30 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 fig.11 block diagram of timer 2. handbook, full pagewidth mgd632 ste r rte i/o port 4 = set = reset = toggle = toggle status s r t tg t2 sfr address: tml2 = lower 8 bits tmh2 = higher 8 bits int comp cm0 (s) int comp cm1 (r) int comp cm2 (t) ct3i int cti3 ct3 off f clk t2 rt2 t2er external reset enable prescaler 1/12 t2 counter 8-bit overflow interrupt 16-bit overflow interrupt ct2i int cti2 ct2 ct1i int cti1 ct1 ct0i int cti0 ct0 r r r r r t t p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 s s s s s s tg tg
1997 aug 01 31 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 12.3 watchdog timer (t3) in addition to timer t2 and the standard timers, a watchdog timer (t3) consisting of an 11-bit prescaler and an 8-bit timer is also incorporated (see fig.12). t3 is incremented every 1.5 ms, derived from the oscillator frequency of 16 mhz by the following formula: when a timer overflow occurs, the microcontroller is reset and a reset output pulse is generated at pin rstout. also the pll control register is reset. to prevent a system reset the timer must be reloaded in time by the application software. if the processor suffers a hardware/software malfunction, the software will fail to reload the timer. this failure will produce a reset upon overflow thus preventing the processor running out of control. f timer f clk 12 2048 ------------------------- - = the watchdog timer can only be reloaded if the condition flag wle = pcon.4 has been previously set by software. at the moment the counter is loaded the condition flag is automatically cleared. the time interval between the timers reloading and the occurrence of a reset depends on the reloaded value. for example, this may range from 1.5 ms to 0.375 s when using an oscillator frequency of 16 mhz. in the idle state the watchdog timer and reset circuitry remain active. the watchdog timer is controlled by the watchdog enable pin ( ew). a low level enables the watchdog timer and disables the power-down mode. a high level disables the watchdog timer and enables the power-down mode. fig.12 functional diagram of t3 watchdog timer. handbook, full pagewidth mbh081 internal bus 1/12 f clk write t3 prescaler 11-bit timer t3 (8-bit) load clear to reset circuitry loaden ew loaden pcon.4 pcon.1 clear wle pd internal bus (1) (1) see fig.20.
1997 aug 01 32 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 13 serial i/o ports the P8XCE560 is equipped with 2 independent serial ports: sio0, which is the full duplex uart port, identical to the pcb80c51 serial port sio1,which is an i 2 c-bus serial i/o interface with byte oriented master and slave functions. 13.1 serial i/o port: sio0 (uart) sio0 is a full duplex serial i/o port - it can transmit and receive simultaneously. this serial port is also receive-buffered. it can commence reception of a second byte before the previously received byte has been read from the receive register. if, however, the first byte has still not been read by the time reception of the second byte is complete, one of the bytes will be lost. the sio0 receive and transmit registers are both accessed via the s0buf special function register. writing to s0buf loads the transmit register, and reading s0buf accesses a physically separate receive register. sio0 can operate in four modes: mode 0 serial data is transmitted and received through rxd. txd outputs the shift clock. 8 data bits are transmitted/received (lsb first). the baud rate is fixed at 1 12 the oscillator frequency. a write into s0con should be avoided during a transmission to avoid spikes on rxd/txd. mode 1 10 bits are transmitted via txd or received through rxd: a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit is put into rb8 of the s0con sfr. the baud rate is variable. mode 2 11 bits are transmitted through txd or received through rxd: a start bit (0), 8 data bits (lsb first), a programmable 9 th data bit, and a stop bit (1). on transmit, the 9 th data bit (tb8 in s0con) can be assigned the value of 0 or 1. with nominal software, tb8 can be the parity bit (p in psw). during a receive, the 9 th data bit is stored in rb8 (s0con), and the stop bit is ignored. the baud rate is programmable to either 1 32 or 1 64 of the oscillator frequency. mode 3 11 bits are transmitted through txd or received through rxd: a start bit (0), 8 data bits (lsb first), a programmable 9 th data bit, and a stop bit (1). mode 3 is the same as mode 2 except for the baud rate which is variable in mode 3. in all four modes, transmission is initiated by any instruction that writes to the sfr s0buf. reception is initiated in mode 0 when ri = 0 and ren = 1. in the other three modes, reception is initiated by the incoming start bit provided that ren = 1. modes 2 and 3 are provided for multiprocessor communications. in these modes, 9 data bits are received with the 9 th bit written to rb8 (s0con). the 9 th bit is followed by the stop bit. the port can be programmed so that with receiving the stop bit, the serial port interrupt will be activated if, and only if rb8 = 1. this feature is enabled by setting bit sm2 in s0con. it may be used in multiprocessor systems. for more information about how to use the uart in combination with the registers s0con, pcon, ie, sbuf and the timer register, refer to data handbook ic20 .
1997 aug 01 33 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 13.1.1 s erial p ort c ontrol r egister (s0con) table 43 serial port control register (address 98h) table 44 description of s0con bits table 45 serial port mode select 76543210 sm0 sm1 sm2 ren tb8 rb8 ti ri bit symbol description 7 sm0 these bits are used to select the serial port mode; see table 45. 6 sm1 5 sm2 enables the multiprocessor communication feature in modes 2 and 3. in these modes, if sm2 = 1, then ri will not be activated if the received 9 th data bit (rb8) is a logic 0. in mode 1, if sm2 = 1, then ri will not be activated if a valid stop bit was not received. in mode 0, sm2 should be a logic 0. 4 ren enables serial reception. set by software to enable reception. clear by software to disable reception. 3 tb8 the 9 th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. 2 rb8 in modes 2 and 3, rb8 is the 9 th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. 1ti transmit interrupt ?ag . set by hardware at the end of the 8 th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. 0ri receive interrupt ?ag . set by hardware at the end of the 8 th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. sm0 sm1 mode description baud rate 0 0 mode 0 shift register 1 12 f clk 0 1 mode 1 8-bit uart variable 1 0 mode 2 9-bit uart 1 64 or 1 32 f clk 1 1 mode 3 9-bit uart variable
1997 aug 01 34 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 13.2 serial i/o port: sio1 (i 2 c-bus interface) the sio1 of the P8XCE560 provides the fast mode, which allows a fourth-fold increase of the bit rate up to 400 khz. nevertheless it is downward compatible, i.e. it can be used in a 0 to 100 kbit/s i 2 c-bus system. except from the bit rate selection (see table 48) and the timing of the scl and sda signals (see chapter 11) the sio circuit is the same as described in detail in the 80c51-based data handbook ic20 for the 8xc552 microcontroller. the i 2 c-bus is a simple bidirectional 2-wire bus for efficient inter-ic data exchange. features of the i 2 c-bus are: only two bus lines are required: a serial clock line (scl) and a serial data line (sda) each device connected to the bus is software addressable by a unique address masters can operate as master transmitter or as master receiver it is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer serial clock synchronization allows devices with different bit rates to communicate via the same serial bus ics can be added to or removed from an i 2 c-bus system without affecting any other circuit on the bus fault diagnostics and debugging are simple; malfunctions can be immediately traced. for more information on the i 2 c-bus specification (including fast-mode) please refer to the philips publication the i 2 c-bus and how to use it ordering number 9398 393 40011 and/or the 80c51-based data handbook ic20 . the on-chip i 2 c logic provides a serial interface that meets the i 2 c-bus specification, supporting 4 modes of operation: master transmitter master receiver slave transmitter slave receiver. the sio1 logic performs a byte oriented data transport; clock generation, address recognition and bus control arbitration are all controlled by hardware. via two pins the external i 2 c-bus is interfaced to the sio1 logic: scl serial clock i/o and sda serial data i/o (sfr s1con bit ens1 for enabling the sio1 logic). the sio1 logic handles byte transfer autonomously. it keeps track of the serial transfers, and a status register (s1sta) reflects the status of sio1 and the i 2 c-bus. via 4 sfrs the cpu interfaces to the i 2 c-bus logic: s1con; serial control register. bit-addressable by the cpu s1sta; status register whose contents may be used as a vector to service routines s1dat; data shift register. the data byte is stable as long as si = 1 (sfr s1con) s1adr; slave address register. its lsb enables/disables general call address recognition. 13.2.1 s erial c ontrol r egister (s1con) the cpu can read from and write to this 8-bit, directly addressable sfr. two bits are affected by the sio1 hardware: the si bit is set when a serial interrupt is requested, and the sto bit is cleared when a stop condition is present on the i 2 c-bus. the sto bit is also cleared when ens1 = 0. when sio1 is in a master mode, serial clock frequency is determined by the clock rate bits cr2, cr1 and cr0. the various bit rates are shown in table 48. the data shown in table 48 do not apply to sio1 in a slave mode. in the slave modes, sio1 will automatically synchronize with any clock frequency up to 400 khz. however, serial clock frequencies above 100 khz require an oscillator frequency f clk of at least 12 mhz.
1997 aug 01 35 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 46 serial control register (address d8h) table 47 description of s1con bits 76543210 cr2 ens1 sta sto si aa cr1 cr0 bit symbol description 7 cr2 clock rate bit 2, see table 48. 6 ens1 enable serial i/o . ens1 = 0: serial i/o disabled and reset. sda and scl outputs are high-z. ens1 = 1: serial i/o enabled. 5sta start ?ag. when this bit is set in slave mode, the hardware checks the i 2 c-bus and generates a start condition if the bus is free or after the bus becomes free. if the device operates in master mode it will generate a repeated start condition. 4sto stop ?ag . if this bit is set in a master mode a stop condition is generated. a stop condition detected on the i 2 c-bus clears this bit. this bit may also be set in slave mode in order to recover from an error condition. in this case no stop condition is generated to the i 2 c-bus, but the hard ware releases the sda and scl lines and switches to the not selected receiver mode. the stop ?ag is cleared by the hardware. 3si serial interrupt ?ag. this ?ag is set and an interrupt request is generated, after any of the following events occur: a start condition is generated in master mode. the own slave address has been received during aa = 1. the general call address has been received while gc (bit s1adr.0) and aa = 1. a data byte has been received or transmitted in master mode (even if arbitration is lost). a data byte has been received or transmitted as selected slave. a stop or start condition is received as selected slave receiver or transmitter. while the si ?ag is set, scl remains low and the serial transfer is suspended. si must be reset by software. 2aa assert acknowledge ?ag. when this bit is set, an acknowledge is returned after any one of the following conditions: own slave address is received. general call address is received; gc (bit s1adr.0) = 1. a data byte is received, while the device is programmed to be a master receiver. a data byte is received. while the device is a selected slave receiver. when the bit is reset, no acknowledge is returned. consequently, no interrupt is requested when the own address or general call address is received. 1 cr1 clock rate bits 1 and 0; see table 48. 0 cr0
1997 aug 01 36 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 48 selection of i 2 c-bus bit rate note 1. these bit rates are for fast-mode i 2 c-bus applications and cannot be used for standard i 2 c bit rates up to 100 kbits/s. cr2 cr1 cr0 bit rate (kbits/s) at f clk 12 mhz 16 mhz 1 0 0 50 66.7 1 0 1 3.75 5 1 1 0 75 100 1 1 1 100 - 0 0 0 200 (1) 266.7 (1) 0 0 1 7.5 10 0 1 0 300 (1) 400 (1) 0 1 1 400 (1) - mlb199 slave address s1adr gc shift register s1dat sda arbitration sync logic scl bus clock generator s1sta internal bus 70 s1con 70 70 70 control register status register fig.13 block diagram of i 2 c serial i/o interface.
1997 aug 01 37 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 13.2.2 s erial s tatus r egister (s1sta) the contents of this register may be used as a vector to a service routine. this optimizes the response time of the software and consequently that of the i 2 c-bus. s1sta is a read-only register. the status codes for all possible modes of the i 2 c-bus interface are given in tables 51 to 55. table 49 serial status register (address d9h) table 50 description of s1sta bits table 51 mst/trx mode table 52 mst/rec mode 76543210 sc4 sc3 sc2 sc1 sc0 0 0 0 bit symbol description 7 to 3 sc4 to sc0 5-bit status code. 2to0 - these 3 bits are held low (for service routine vector increment 8). s1sta value description 08h a start condition has been transmitted. 10h a repeated start condition has been transmitted. 18h sla and w have been transmitted, ack has been received. 20h sla and w have been transmitted, ack received. 28h data and s1dat has been transmitted, ack received. 30h data and s1dat has been transmitted, ack received. 38h arbitration lost in sla, r/w or data. s1sta value description 38h arbitration lost while returning ack. 40h sla and r have been transmitted, ack received. 48h sla and r have been transmitted, ack received. 50h data has been received, ack returned. 58h data has been received, ack returned.
1997 aug 01 38 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 53 slv/rec mode table 54 slv/trx mode table 55 miscellaneous table 56 symbols used in tables 51 to 55 s1sta value description 60h own sla and w have been received, ack returned. 68h arbitration lost in sla, r/w as mst. own sla and w have been received, ack returned. 70h general call has been received, ack returned. 78h arbitration lost in sla, r/w as mst. general call has been received. 80h previously addressed with own sla. data byte received, ack returned. 88h previously addressed with own sla. data byte received, ack returned. 90h previously addressed with general call. data byte has been received, ack has been returned. 98h previously addressed with general call. data byte has been received, ack has been returned. a0h a stop condition or repeated start condition has been received while still addressed as slv/rec or slv/trx. s1sta value description a8h own sla and r have been received, ack returned. b0h arbitration lost in sla, r/w as mst. own sla and r have been received, ack returned. b8h data byte has been transmitted, ack returned. c0h data byte has been transmitted, ack returned. c8h last data byte has been transmitted (aa = logic 0), ack received. s1sta value description 00h bus error during mst mode or selected slv mode, due to an erroneous start or stop condition. f8h no relevant information available, si not set. symbol description sla 7-bit slave address r read bit w write bit ack acknowledgement (acknowledge bit = logic 0) ack no acknowledgement (acknowledge bit = logic 1) data 8-bit data byte to or from i 2 c-bus mst master slv slave trx transmitter rec receiver
1997 aug 01 39 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 13.2.3 d ata s hift r egister (s1dat) this register contains the serial data to be transmitted or data which has been received. bit 7 is transmitted or received first; i.e. data is shifted from right to left. table 57 data shift register (address dah) 13.2.4 a ddress r egister (s1adr) this 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receiver/transmitter. table 58 address register (address dbh) table 59 description of s1adr bits 76543210 s1dat.7 s1dat.6 s1dat.5 s1dat.4 s1dat.3 s1dat.2 s1dat.1 s1dat.0 76543210 sla6 sla5 sla4 sla3 sla2 sla1 sla0 gc bit symbol description 7 to 1 sla6 to sla0 own slave address. 0 gc this bit is used to determine whether the general call address is recognized. when gc = 0, the general call address is not recognized; when gc = 1, the general call address is recognized.
1997 aug 01 40 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 14 interrupt system external events and the real-time-driven on-chip peripherals require service by the cpu asynchronously to the execution of any particular section of code. to tie the asynchronous activities of these functions to normal program execution a multiple-source, two-priority-level, nested interrupt system is provided. interrupt response time in a single-interrupt system is in the range 2.25 m s to 6.75 m s when using a 16 mhz crystal. the latency time depends on the sequence of instructions executed directly after an interrupt request. the P8XCE560 acknowledges interrupt requests from 15 sources as follows (see fig.14): int0 and int1 external interrupts timer 0 and timer 1 internal timer/counter interrupts timer 2 internal timer/counter byte and/or 16-bit overflow, 3 compare and 4 capture interrupts (or 4 additional external interrupts). note that if a capture register is unused and its contents are of no interest, then the corresponding input pin ctni/p1.n (n = 0 to 3) may be used as a (configurable) positive and/or negative edge triggered additional external interrupt input ( int2, int3, int4 and int5). uart serial i/o port receive/transmit interrupt i 2 c-bus interface serial i/o interrupt adc autoscan completion interrupt seconds timer interrupt sec (ored with int1); for details please refer to chapter 16.2.4. the external interrupts int0 and int1 can each be either level-activated or transition-activated, depending on bits it0 and it1 in register tcon. the flags that actually generate these interrupts are bits ie0 and ie1 in tcon. when an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to, only if the interrupt was transition-activated. if the interrupt was level-activated then the interrupt request flag remains set until the external interrupt pin intn goes high. consequently, the external source has to hold the request active until the requested interrupt is actually generated. then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. as these external interrupts are active low a wire-oring of several interrupt sources to one input pin allows expansion. the timer 0 and timer 1 interrupts are generated by tf0 and tf1, which are set by a roll-over in their respective timer/counter register (except for timer 0 in mode 3 of the serial interface). when a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. the eight timer/counter t2 interrupt sources are: 4 capture interrupts (1), 3 compare interrupts and an overflow interrupt. the appropriate interrupt request flags must be cleared by software. the uart serial port interrupt is generated by the logical or of ri and ti (register s0con). neither of these flags is cleared by hardware. the service routine will normally have to determine whether it was ri or ti that generated the interrupt, and the bit will have to be cleared by software. the i 2 c interrupt is generated by bit si in register s1con. this flag has to be cleared by software. the adc interrupt is generated by bit adint, which is set when the conversion of all selected analog inputs to be scanned is finished. adint must be cleared by software. it cannot be set by software. the seconds timer interrupt is generated by bit secint in register pllcon. this flag has to be cleared by software. note that the seconds timer can only be used with the 32 khz pll oscillator. all of the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware (except the adc interrupt request flag adint, which cannot be set by software). that is, interrupts can be generated or pending interrupts can be cancelled in software. the interrupts x0, t0, x1, t1, sec, s0 and s1 are able to terminate the idle mode. 14.1 interrupt enable registers each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable special function registers ien0 and ien1. all interrupt sources can also be globally disabled by clearing bit ea in ien0. the interrupt enable registers are described in tables 62 and 64.
1997 aug 01 41 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 14.2 interrupt handling the interrupt sources are sampled at s5p2 of every machine cycle. the samples are polled during the following machine cycle. if one of the flags was in a set condition at s5p2 of the previous machine cycle, the polling cycle will detect it and the interrupt system will generate an lcall to the appropriate service routine, provided this hardware generated lcall is not blocked by any of the following conditions: 1. an interrupt of higher or equal priority level is already in progress. 2. the current machine cycle is not the final cycle in the execution of the instruction in progress. (no interrupt request will be serviced until the instruction in progress is completed.). 3. the instruction in progress is reti or any access to the interrupt priority or interrupt enable registers. (no interrupt will be serviced after reti or after a read or write to ip0, ip1, ie0, or ie1 until at least one other instruction has been subsequently executed.). the polling cycle is repeated every machine cycle, and the values polled are the values present at s5p2 of the previous machine cycle. note that if an interrupt flag is active but is not being responded to because of one of the above conditions, and if the flag is inactive when the blocking condition is removed, then the blocked interrupt will not be serviced. thus, the fact that the interrupt flag was once active but not serviced is not remembered. every polling cycle is new. the processor acknowledges an interrupt request by executing a hardware-generated lcall to the appropriate service routine. in some cases it also clears the flag which generated the interrupt, and in others it does not. it clears the timer 0, timer 1, and external interrupt flags. an external interrupt flag (ie0 or ie1) is cleared only if it was transition-activated. all other interrupt flags are not cleared by hardware and must be cleared by the software. the lcall pushes the contents of the program counter on to the stack (but it does not save the psw) and reloads the pc with an address that depends on the source of the interrupt being vectored to as shown in table 60. execution proceeds from the vector address until the reti instruction is encountered. the reti instruction clears the priority level active flip-flop that was set when this interrupt was acknowledged. it then pops the top two bytes from the stack and reloads the program counter. execution of the interrupted program continues from where it was interrupted. 14.3 interrupt priority structure each interrupt source can be assigned one of two priority levels: high and low. interrupt priority levels are defined by the interrupt priority sfrs ip0 and ip1, which are described in tables 66 and 68. interrupt priority levels are as follows: logi c 0 = low priority logi c 1 = high priority. a low priority interrupt may be interrupted by a high priority interrupt. a high priority interrupt cannot be interrupted by any other interrupt source. if two requests of different priority occur simultaneously, the high priority level request is serviced. if requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. thus, within each priority level, there is a second priority structure determined by the polling sequence. this second priority structure is shown in table 60. 14.4 interrupt vectors the vector indicates the program memory location where the appropriate interrupt service routine starts; table 60. table 60 interrupt vectors and priority structure note 1. x0 has the highest priority; t2 the lowest. source symbol (1) vector address (hex) external 0 x0 (highest) 0003 serial i/o: sio1 (i 2 c-bus) s1 002b adc completion adc 0053 timer 0 over?ow t0 000b t2 capture 0 ct0 0033 t2 compare 0 cm0 005b external 1/ seconds interrupt x1/sec 0013 t2 capture 1 ct1 0033 t2 compare 1 cm1 0063 timer 1 over?ow t1 001b t2 capture 2 ct2 0043 t2 compare 2 cm2 006b serial i/o sio0 (uart) s0 0023 t2 capture 3 ct3 004b t2 over?ow t2 (lowest) 0073
1997 aug 01 42 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 fig.14 interrupt system. handbook, full pagewidth interrupt sources source enable global enable interrupt enable registers a1 a2 b1 b2 c1 c2 d1 d2 e1 e2 f1 f2 g1 g2 h1 h2 i1 i2 j1 j2 k1 k2 l1 l2 m1 m2 n1 n2 o1 o2 interrupt priority registers a1 source identification vector b1 c1 d1 e1 f1 g1 h1 i1 j1 k1 l1 m1 n1 o1 high priority interrupt request mbc754 a2 source identification vector b2 c2 d2 e2 f2 g2 h2 i2 j2 k2 l2 m2 n2 o2 low priority interrupt request polling hardware ct3i ct2i ct1i ct0i int0 int1 external interrupt request 0 adc timer 0 overflow timer 2 capture 0 timer 2 compare 0 external interrupt request 1 timer 2 capture 1 timer 2 compare 1 timer 1 overflow timer 2 capture 2 timer 2 compare 2 uart serial port timer 2 capture 3 timer t2 overflow t r i 2 c-bus serial port
1997 aug 01 43 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 14.5 interrupt enable and priority registers 14.5.1 i nterrupt e nable r egister 0 (ien0) logic 0 = interrupt disabled; logic 1 = interrupt enabled. table 61 interrupt enable register 0 (address a8h) table 62 description of ien0 bits 14.5.2 i nterrupt e nable r egister 1 (ien1) logic 0 = interrupt disabled; logic 1 = interrupt enabled. table 63 interrupt enable register 1 (address e8h) table 64 description of ien1 bits 76543210 ea ead es1 es0 et1 ex1 et0 ex0 bit symbol description 7ea general enable/disable control . if bit ea is: low, then no interrupt is enabled. high, then any individually enabled interrupt will be accepted. 6 ead enable adc interrupt. 5 es1 enable sio1 (i 2 c-bus) interrupt. 4 es0 enable sio0 (uart) interrupt. 3 et1 enable timer 1 interrupt. 2 ex1 enable external 1 interrupt / seconds interrupt. 1 et0 enable timer 0 interrupt. 0 ex0 enable external 0 interrupt. 76543210 et2 ecm2 ecm1 ecm0 ect3 ect2 ect1 ect0 bit symbol description 7 et2 enable t2 over?ow interrupt(s). 6 ecm2 enable t2 comparator 2 interrupt. 5 ecm1 enable t2 comparator 1 interrupt. 4 ecm0 enable t2 comparator 0 interrupt. 3 ect3 enable t2 capture register 3 interrupt. 2 ect1 enable t2 capture register 2 interrupt. 1 ect1 enable t2 capture register 1 interrupt. 0 ect0 enable t2 capture register 0 interrupt.
1997 aug 01 44 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 14.5.3 i nterrupt p riority r egister 0 (ip0) logic 0 = low priority; logic 1 = high priority. table 65 interrupt priority register 0 (address b8h) table 66 description of ip0 bits 14.5.4 i nterrupt p riority r egister 1 (ip1) logic 0 = low priority; logic 1 = high priority. table 67 interrupt priority register 1 (address f8h) table 68 description of ip1 bits 76543210 - pad ps1 ps0 pt1 px1 pt0 px0 bit symbol description 7 - reserved for future use. 6 pad adc interrupt priority level. 5 ps1 sio1 (i 2 c-bus) interrupt priority level. 4 ps0 sio0 (uart) interrupt priority level. 3 pt1 timer 1 interrupt priority level. 2 px1 external interrupt 1/seconds priority level. 1 pt0 timer 0 interrupt priority level. 0 px0 external interrupt 0 priority level. 76543210 pt2 pcm2 pcm1 pcm0 pct3 pct2 pct1 pct0 bit symbol description 7 pt2 t2 over?ow interrupt(s) priority level. 6 pcm2 t2 comparator 2 priority interrupt level. 5 pcm1 t2 comparator 1 priority interrupt level. 4 pcm0 t2 comparator 0 priority interrupt level. 3 pct3 t2 capture register 3 priority interrupt level. 2 pct2 t2 capture register 2 priority interrupt level. 1 pct1 t2 capture register 1 priority interrupt level. 0 pct0 t2 capture register 0 priority interrupt level.
1997 aug 01 45 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 15 reduced power modes two software-selectable modes of reduced power consumption are implemented: idle and power-down mode. these modes are activated by software via sfr pcon. 15.1 idle mode idle mode operation permits the interrupt, serial ports and timer blocks t0, t1 and t3 to function while the cpu is halted. the functions that are switched off when the microcontroller enters the idle mode are: cpu (halted) timer 2 (stopped and reset) pwm0, pwm1 (reset, output = high) adc (aborted if conversion in progress). the functions that remain active during idle mode may generate an interrupt or reset and thus terminate the idle mode. these functions are: timer 0, timer 1, timer 3 (watchdog timer) uart i 2 c external interrupt seconds timer. the instruction that sets pcon.0 is the last instruction executed in the normal operating mode before idle mode is activated. once in the idle mode, the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, ram and all other registers maintain their data during idle mode. the status of external pins during idle mode is shown in table 69. there are three ways to terminate the idle mode: activation of any enabled interrupt x0, t0, x1, sec, t1, s0 or s1 will cause pcon.0 to be cleared by hardware terminating idle mode but only, if there is no interrupt in service with the same or higher priority. the interrupt is serviced, and following return from interrupt instruction reti, the next instruction to be executed will be the one which follows the instruction that wrote a logic 1 to pcon.0. the flag bits gf0 and gf1 may be used to determine whether the interrupt was received during normal execution or during idle mode. for example, the instruction that writes to pcon.0 can also set or clear one or both flag bits. when idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. the second way of terminating the idle mode is with an external hardware reset. since the oscillator is still running, the hardware reset is required to be active for two machine cycles (24 hf oscillator periods) to complete the reset operation if the hf oscillator is selected. when the pll oscillator is selected a hardware reset of 3 1 m s (but no longer than 10 ms) is required and the microcontroller will typically restart within 63 ms after the reset has finished. the third way of terminating the idle mode is by internal watchdog reset. the microcontroller restarts after three machine cycles in all cases. 15.2 power-down mode in power-down mode the system clock is halted. if the pll oscillator is selected (selxtal1 = 0) and the run32 bit is set, the 32 khz oscillator keeps running, otherwise it is stopped. if the hf oscillator (selxtal1 = 1) is selected, it is stopped after setting the bit pd in the pcon register. the instruction that sets pcon.1 is the last executed prior to going into the power-down mode. once in power-down mode, the hf oscillator is stopped. the 32 khz oscillator may remain active. the contents of the on-chip ram and the special function registers are preserved. note that the power-down mode can not be entered when the watchdog timer has been enabled. the power-down mode can be terminated by an external reset in the same way as in the 80c51 (ram is saved, but sfrs are cleared due to reset) or in addition by any one of the external interrupts ( int0, int1) or seconds interrupt. the status of the external pins during power-down mode is shown in table 69. if the power-down mode is activated while in external program memory, the port data that is held in the special function register p2 is restored to port 2. if the data is a logic 1, the port pin is held high during the power-down mode by the strong pull-up transistor p1 (see fig.8). the power-down mode should not be entered within an interrupt routine because wake-up with an external or seconds interrupt is not possible in that case.
1997 aug 01 46 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 15.3 wake-up from power-down mode the power-down mode of the P8XCE560 can also be terminated by any one of the three enabled interrupts, int0, int1 or seconds interrupt. if there is an interrupt already in service, which has same or higher priority than the wake-up interrupt, power-down mode will switch over to idle mode and stay there until an interrupt of higher priority terminates idle mode. a termination with these interrupts does not affect the internal data memory and does not affect the special function registers. this gives the possibility to exit power-down without changing the port output levels. to terminate the power-down mode with an external interrupt, int0 or int1 must be switched to be level-sensitive and must be enabled. the external interrupt input signal int0 or int1 must be kept low till the oscillator has restarted and stabilized (see fig.15). a seconds interrupt will terminate the power-down mode if it is enabled and int1 is level sensitive. in order to prevent any interrupt priority problems during wake-up, the priority of the desired wake-up interrupt should be higher than the priorities of all other enabled interrupt sources. the instruction following the one that put the device into the power-down mode will be the first one which will be executed after the interrupt routine has been serviced. 15.4 status of external pins table 69 status of external pins during idle and power-down modes note 1. in idle mode scl and sda can be active as outputs only if sio1 is enabled; if sio1 is disabled (s1con.6/ens1 = 0) these pins are in a high-impedance state. mode memory ale psen pwm0/ pwm1 port0 port1 port2 port3 port4 scl/ sda idle internal 1 1 1 port data port data port data port data port data operative (1) external 1 1 1 high-z port data address port data port data operative (1) power-down internal 0 0 1 port data port data port data port data port data high-z external 0 0 1 high-z port data port data port data port data high-z fig.15 wake-up by interrupt. handbook, full pagewidth mbh083 oscillator start-up time interrupts are polled idle mode lcall interrupt routine > 560 ms power-down mode internal timing stopped 32 khz oscillator stopped > 10 ms 32 khz oscillator running xtal1, 2 oscillator stopped c1 int0 int1 c1 c1 c2 set external interrupt latch
1997 aug 01 47 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 15.5 power control register (pcon) pcon is not bit addressable and the value after reset is 00h. table 70 power control register (address 87h) table 71 description of pcon bits 76543210 smod ard rfi wle gf1 gf0 pd idl bit symbol description 7 smod double baud rate . when set to logic 1 the baud rate is doubled when the serial port sio0 is being used in modes 1, 2 and 3. 6 ard aux-ram disable. when set to logic 1 the internal 1792 bytes aux-ram is disabled, so that all movx-instructions access the external data memory - as it is with the standard 80c51. 5 rfi rfi-reduction mode. when set to high the toggling of ale pin is prohibited. this bit is cleared on reset and can be set and cleared by software. when set, ale pin will be pulled down internally, switching an external address latch to a quiet state. see also sections 2.1 and 6.2. 4 wle watchdog load enable . this ?ag must be set by software prior to loading t3 (watchdog timer). it is cleared when t3 is loaded. 3 gf1 general purpose ?ag bits . 2 gf0 1pd power-down mode select . setting this bit activates power-down mode. it can only be set if input ew is high. 0 idl idle mode select . setting this bit activates the idle mode. fig.16 idle and power-down hardware for clock generation. handbook, full pagewidth mbh082 pll ocsillator clock generator ocsillator 'second' timer 32 khz pd xtal3 xtal3 selxtal1 3.5 to 16 khz xtal2 xtal1 f clk idl interrupts, serial ports t0, t1, t3 cpu t2 adc pwm
1997 aug 01 48 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 16 oscillator circuits 16.1 xtal1; xtal2 oscillator: standard 80c51 the xtal1; xtal2 oscillator: standard 80c51 is selected when input selxtal1 = 1. the oscillator circuit is a single-stage inverting amplifier in a pierce oscillator configuration. the circuitry between pins xtal1 and xtal2 is basically an inverter biased to the transfer point. either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuitry. both are operated in parallel resonance. xtal1 is the high gain amplifier input, and xtal2 is the output; see fig.17. to drive the P8XCE560 externally, xtal1 is driven from an external source and xtal2 is left open-circuit; see fig.18. when the xtal1; xtal2 oscillator is selected the xtal3; xtal4 oscillator is halted; pins xtal3 and xtal4 must not be connected. 16.2 xtal3; xtal4 oscillator: 32 khz pll oscillator (with seconds timer) the xtal3; xtal4 oscillator: 32 khz oscillator and the phase locked loop (pll) are selected when selxtal1 = 0 (xtal1; xtal2 oscillator is halted). in this case pin xtal2 is kept floating. 16.2.1 32 k h z oscillator the 32 khz oscillator consists of an inverter, which forms a pierce oscillator with the on-chip components c1, c2, r f and an external crystal of 32768 hz. the inverter is switched to 3-state and pin xtal3 is pulled to v ss : during power-down mode, when run32 (pllcon.7) = 0 during reset, rstin = 1 when the xtal1; xtal2 oscillator is selected (selxtal1 = 1). 16.2.2 pll c urrent c ontrolled o scillator a current controlled oscillator (cco) generates a clock frequency f cco of approximately 32, 38, 44 or 50 mhz. this cco is controlled by the pll, with the 32 khz oscillator as the reference clock. the system clock frequency f clk is derived from f cco and can be varied under software control by changing the contents of the pll control register (pllcon) bits fsel.4 to fsel.0. the cco frequency f cco can be changed via the pllcon bits fsel.1 and fsel.0 and the maximum locking time is 10 ms (this parameter is characterized). during the stabilization phase, no time critical routines should be executed. changing f clk has to be done in two steps: from high to low frequencies; first change fsel.4 to fsel.2, then fsel.1 to fsel.0 from low to high frequencies; first change fsel.1 to fsel.0 only, and after a stabilization phase of 10 ms, change fsel.4 to fsel.2. if only fsel.4 to fsel.2 is changed, and fsel.1 to fsel.0 not, then it takes approximately 1 m s until the new frequency is available. the frequency selection is shown in table 73. 16.2.3 pll c ontrol r egister (pllcon) pllcon is a special function register, which can be read and written by software. it contains the control bits: to select the system clock frequencies (f clk ) the seconds interrupt flag (secint) to enable the seconds interrupt flag (enseci) the run32 bit, which defines if during power-down mode the 32 khz oscillator is halted or not. pllcon is initialized to 0dh upon reset (rstin = 1) or watchdog timer overflow. pllcon = 0dh corresponds to a system clock frequency f clk = 11.01 mhz.
1997 aug 01 49 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 72 pll control register (address f9h) table 73 description of pllcon bits table 74 system clock frequency (f clk ) selection other combinations than mentioned in this table, are reserved and may not be selected. this allows to generate the standard baudrates 19200, 9600, 4800, 2400 and 1200 baud, when using the uart and timer 1. 76543210 run32 enseci secint fsel.4 fsel.3 fsel.2 fsel.1 fsel.0 bit symbol description 7 run32 if run32 = 0, then the 32 khz oscillator is halted during power-down mode. if run32 = 1, then the 32 khz oscillator remains active during power-down mode. 6 enseci enable the seconds interrupt; enabling int1 is also required. 5 secint seconds interrupt requested by an over?ow of the seconds timer (which occurs every second) or via writing a logic 1 to this bit. secint can only be cleared by writing a logic 0 to this bit. 4 to 0 fsel.4 to fsel.0 system clock frequency selection bits; see table 74. fsel.4 fsel.3 fsel.2 fsel.1 fsel.0 f clk (mhz) 1 0 0 1 1 3.93 0 1 1 1 1 7.86 0 1 0 1 1 15.73 1 0 0 1 0 4.72 0 1 1 1 0 9.44 1 0 0 0 1 5.51 0 1 1 0 1 11.01 1 0 0 0 0 6.29 0 1 1 0 0 12.58 handbook, halfpage mbh084 c1 high c2 c1 = c2 = 20 pf quartz crystal or ceramic resonator v ss xtal2 xtal1 selxtal1 fig.17 using the on-chip oscillator. handbook, halfpage mbh085 high n.c. external clock signal v ss xtal2 xtal1 selxtal1 fig.18 using an external clock.
1997 aug 01 50 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 16.2.4 s econds t imer this counter provides an overflow signal every second, when the 32 khz oscillator is running. the overflow output sets the interrupt flag secint. this interrupt can be disabled/enabled by enseci. if secint is enabled, it is logically ored with int1 (external interrupt 1). the seconds interrupt and int1 therefore share the same priority and vector. the software has to check both flags secint (pllcon.5) and ie1 (tcon.3) to distinguish between the two interrupt sources. secint can only be cleared via writing a logic 0 to this bit. the external interrupts int0, int1 or the seconds interrupt can wake-up the pll oscillator and the microcontroller as described in chapter 15.3. for a wake-up via int1 or seconds interrupt, ie1 must be enabled and level-sensitive. a further function of the seconds timer is to control the start-up timing of the microcontroller after reset or after wake-up from power-down. it controls the stretching of the reset pulse to the microcontroller and controls releasing the system clock to the microcontroller. a rstin signal of 1 m s at minimum will reset the microcontroller. in the even of reset or wake-up with halted 32 khz oscillator: from rstin falling edge or wake-up interrupt it takes 560 ms at maximum for the start-up of the 32 khz oscillator itself and the stabilization of the plls. in the event of wake-up with running 32 khz oscillator: from wake-up interrupt it takes about 10 ms for the stabilization of the plls. after this start-up time, the microcontroller is supplied with the system clock and - in case of a reset - the internally stretched reset signal overlaps about 45 m s, to guarantee a proper initialization of the microcontroller. for further information refer to chapter 15. fig.19 block diagram pll. handbook, full pagewidth mbh086 32 khz ocsillator phase comparator r f c1 c2 loop filter cco 32.768 khz xtal3 xtal4 programmable divider pllcon seconds timer pd pd run32 rstin internal bus 'seconds' interrupt request reset to controller system clock
1997 aug 01 51 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 17 reset circuitry the reset input pin rstin is connected to a schmitt trigger for noise reduction (see fig.20). if the hf oscillator is selected, a reset is accomplished by holding the rstin pin high for at least 2 machine cycles (24 system clock periods). if the pll oscillator is selected the rstin pulse must have a width of at least 1 m s, independent of the 32 khz-oscillator running or not (see pll description). the cpu responds by executing an internal reset. the rstout pin represents the signal resetting the cpu and can be used to reset peripheral devices. the rstout level also could be high due to a watchdog timer overflow.the length of the output pulse from t3 is three machine cycles. a pulse of such short duration is necessary in order to recover from a processor or system fault as fast as possible. during reset, ale and psen output a high level. in order to perform a correct reset, this level must not be affected by external elements. a reset leaves the internal registers as shown in chapter 18. the internal ram is not affected by reset. at power-on, the ram content is indeterminate. 17.1 power-on-reset an automatic reset can be obtained by switching on v dd , if the rstin pin is connected to v dd via a capacitor, as shown in figure 21. is the hf oscillator selected the v dd rise time must not exceed 10 ms and the capacitor should be at least 2.2 m f. the decrease of the rstin pin voltage depends on the capacitor and the internal resistor r rst . that voltage must remain above the lower threshold for at minimum the hf oscillator start-up time plus 2 machine cycles. if the pll oscillator is selected, a 0.1 m f capacitor is sufficient to obtain an automatic reset. fig.20 on-chip reset configuration. handbook, full pagewidth mbh087 schmitt trigger pll oscillator mux rstout internal reset overflow timer t3 r rst rstin selxtal1 on-chip resistor fig.21 power-on-reset. handbook, halfpage v dd v dd rstin c r rst mbh088 P8XCE560 (1)
1997 aug 01 52 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 18 special function registers overview the P8XCE560 has 67 sfrs available to the user. address (hex) name reset value (b) function ff t3 (1) xxxx0000 watchdog timer fe pwmp (1) 00000000 prescaler frequency control register fd pwm1 (1) 0000 0000 pulse width register 1 fc pwm0 (1) 0000 0000 pulse width register 0 fa xramp (1) xxxxx000 aux-ram page register f9 pllcon (1) 00001101 pll control register f8 ip1 (1) 00000000 interrupt priority register 1 f7 adrsh (1) 000000xx adc result register high byte f6 adrsl7 xxxxxxxx adc result register low byte f0 b (2) 00000000 b register ef rte (2) 00000000 reset/toggle enable register ee ste (2) 11000000 set enable register ed tmh2 (2) 00000000 t2 register high byte ec tml2 (2) 00000000 t2 register low byte eb ctcon (2) 00000000 capture control register ea tm2con (2) 00000000 t2 control register e8 ien1 (2) 00000000 interrupt enable register 1 e7 adpss 00000000 adc input port scan-select register e6 adrsl6 xxxxxxxx adc result register low byte e0 acc (2) 00000000 accumulator db s1adr xxxxxxxx address register da s1dat xxxxxxxx data shift register d9 s1sta 00001100 serial status register d8 s1con 00000000 the serial control register d7 adcon xx000000 adc control register d6 adrsl5 xxxxxxxx adc result register low byte d0 psw (2) 00000000 program status word cf cth3 xxxxxxxx t2 capture register 3 high byte ce cth2 xxxxxxxx t2 capture register 2 high byte cd cth1 xxxxxxxx t2 capture register 1 high byte cc cth0 xxxxxxxx t2 capture register 0 high byte cb cmh2 00000000 t2 compare register 2 high byte ca cmh1 00000000 t2 compare register 1 high byte c9 cmh0 00000000 t2 compare register 0 high byte c8 tm2ir (2) 00000000 interrupt flag register c7 p5 (1) 11111111 digital input port register c6 adrsl4 xxxxxxxx adc result register low byte c0 p4 (1)(2) 11111111 digital input port register
1997 aug 01 53 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 notes 1. P8XCE560 specific sfrs. 2. bit addressable register. b8 ip0 (2) xxx00000 interrupt priority register 0 b6 adrsl3 xxxxxxxx adc result register low byte b0 p3 (1)(2) 11111111 digital input port register af ctl3 (2) xxxxxxxx t2 capture register 3 low byte ae ctl2 (2) xxxxxxxx t2 capture register 2 low byte ad ctl1 (2) xxxxxxxx t2 capture register 1 low byte ac ctl0 (2) xxxxxxxx t2 capture register 0 low byte ab cml2 (2) 00000000 t2 compare register 2 low byte aa cml1 (2) 00000000 t2 compare register 1 low byte a9 cml0 (2) 00000000 t2 compare register 0 low byte a8 ien0 (2) 00000000 interrupt enable register 0 a6 adrsl2 xxxxxxxx adc result register low byte a0 p2 11111111 digital input port register 99 s0buf (1) xxxxxxxx serial data buffer register 0 98 s0con (1) 00000000 serial port control register 0 96 adrsl1 xxxxxxxx adc result register low byte 90 p1 11111111 digital input port register 8d th1 00000000 timer 1 high byte 8c th0 00000000 timer 0 high byte 8b tl1 0000000 timer 1 low byte 8a tl0 00000000 timer 0 low byte 89 tmod xx00xx00 timer 0 and 1 mode control register 88 tcon (2) 0000x000 timer 0 and 1 control/external interrupt control register 87 pcon xxxx0000 power control register 86 adrsl0 xxxxxxxx adc result register low byte 83 dph 00000000 data pointer high byte 82 dpl 00000000 data pointer low byte 81 sp 00000111 stack pointer 80 p0 11111111 digital input port register address (hex) name reset value (b) function
1997 aug 01 54 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 19 instruction set the P8XCE560 uses the powerful instruction set of the pcb80c51. it consists of 49 single byte, 45 two byte and 17 three byte instructions. using a 16 mhz crystal, 64 of the instructions are executed in 0.75 m s, 45 in 1,5 m s and the multiply, divide instructions in 3 m s. a summary of the instruction set is given in tables 76, 77, 78, 79 and 80. the P8XCE560 has additional special function registers to control the on-chip peripherals. 19.1 addressing modes most instructions have a destination, source field that specifies the data type, addressing modes and operands involved. for all these instructions, except for movs, the destination operand is also the source operand (e.g. add a,r7). there are five kinds of addressing modes: register addressing C r0 to r7 (4 banks) C a,b,c (bit), ab (2 bytes), dptr (double byte) direct addressing C lower 128 bytes of internal main ram (including the four r0 to r7 register banks) C special function registers C 128 bits in a subset of the internal main ram C 128 bits in a subset of the special function registers register-indirect addressing C internal main ram (@r0, @r1, @sp [push/pop]) C internal auxiliary ram (@r0, @r1, @dptr) C external data memory (@r0, @r1, @dptr) immediate addressing C program memory (in-code 8 bit or 16 bit constant) base-register-plus-index-register-indirect addressing C program memory look-up table (@dptr+a, @pc+a). the first three addressing modes are usable for destination operands. 19.2 80c51 family instruction set table 75 instructions that affect ?ag settings; note 1 note 1. note that operations on sfr byte address 208 or bit addresses 209 to 215 (i.e. the psw or bits in the psw) will also affect flag settings. 2. x = dont care. instruction flag (2) covac add x x x addc x x x subb x x x mul 0 x div 0 x da x x rrc x rlc x setb c 1 clr c 0 cpl c x anl c, bit x anl c,/bit x orl c, bit x orl c,/bit x mov c, bit x cjne x
1997 aug 01 55 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 19.3 instruction set description for the description of the data addressing modes and hexadecimal opcode cross-reference see table 80. table 76 instruction set description: arithmetic operations mnemonic description bytes cycles opcode (hex) arithmetic operations add a,rr add register to a 1 1 2* add a,direct add direct byte to a 2 1 25 add a,@ri add indirect ram to a 1 1 26, 27 add a,#data add immediate data to a 2 1 24 addc a,rr add register to a with carry ?ag 1 1 3* addc a,direct add direct byte to a with carry ?ag 2 1 35 addc a,@ri add indirect ram to a with carry ?ag 1 1 36, 37 addc a,#data add immediate data to a with carry ?ag 2 1 34 subb a,rr subtract register from a with borrow 1 1 9* subb a,direct subtract direct byte from a with borrow 2 1 95 subb a,@ri subtract indirect ram from a with borrow 1 1 96, 97 subb a,#data subtract immediate data from a with borrow 2 1 94 inc a increment a 1 1 04 inc rr increment register 1 1 0* inc direct increment direct byte 2 1 05 inc @ri increment indirect ram 1 1 06, 07 dec a decrement a 1 1 14 dec rr decrement register 1 1 1* dec direct decrement direct byte 2 1 15 dec @ri decrement indirect ram 1 1 16, 17 inc dptr increment data pointer 1 2 a3 mul ab multiply a and b 1 4 a4 div ab divide a by b 1 4 84 da a decimal adjust a 1 1 d4
1997 aug 01 56 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 77 instruction set description: logic operations mnemonic description bytes cycles opcode (hex) logic operations anl a,rr and register to a 1 1 5* anl a,direct and direct byte to a 2 1 55 anl a,@ri and indirect ram to a 1 1 56, 57 anl a,#data and immediate data to a 2 1 54 anl direct,a and a to direct byte 2 1 52 anl direct,#data and immediate data to direct byte 3 2 53 orl a,rr or register to a 1 1 4* orl a,direct or direct byte to a 2 1 45 orl a,@ri or indirect ram to a 1 1 46, 47 orl a,#data or immediate data to a 2 1 44 orl direct,a or a to direct byte 2 1 42 orl direct,#data or immediate data to direct byte 3 2 43 xrl a,rr exclusive-or register to a 1 1 6* xrl a,direct exclusive-or direct byte to a 2 1 65 xrl a,@ri exclusive-or indirect ram to a 1 1 66, 67 xrl a,#data exclusive-or immediate data to a 2 1 64 xrl direct,a exclusive-or a to direct byte 2 1 62 xrl direct,#data exclusive-or immediate data to direct byte 3 2 63 clr a clear a 1 1 e4 cpl a complement a 1 1 f4 rl a rotate a left 1 1 23 rlc a rotate a left through the carry ?ag 1 1 33 rr a rotate a right 1 1 03 rrc a rotate a right through the carry ?ag 1 1 13 swap a swap nibbles within a 1 1 c4
1997 aug 01 57 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 78 instruction set description: data transfer note 1. mov a,acc is not permitted. mnemonic description bytes cycles opcode (hex) data transfer mov a,rr move register to a 1 1 e* mov a,direct (note 1) move direct byte to a 2 1 e5 mov a,@ri move indirect ram to a 1 1 e6, e7 mov a,#data move immediate data to a 2 1 74 mov rr,a move a to register 1 1 f* mov rr,direct move direct byte to register 2 2 a* mov rr,#data move immediate data to register 2 1 7* mov direct,a move a to direct byte 2 1 f5 mov direct,rr move register to direct byte 2 2 8* mov direct,direct move direct byte to direct 3 2 85 mov direct,@ri move indirect ram to direct byte 2 2 86, 87 mov direct,#data move immediate data to direct byte 3 2 75 mov @ri,a move a to indirect ram 1 1 f6, f7 mov @ri,direct move direct byte to indirect ram 2 2 a6, a7 mov @ri,#data move immediate data to indirect ram 2 1 76, 77 mov dptr,#data 16 load data pointer with a 16-bit constant 3 2 90 movc a,@a+dptr move code byte relative to dptr to a 1 2 93 movc a,@a+pc move code byte relative to pc to a 1 2 83 movx a,@ri move external ram (8-bit address) to a 1 2 eb, e3 movx a,@dptr move external ram (16-bit address) to a 1 2 e0 movx @ri,a move a to external ram (8-bit address) 1 2 f2, f3 movx @dptr,a move a to external ram (16-bit address) 1 2 f0 push direct push direct byte onto stack 2 2 c0 pop direct pop direct byte from stack 2 2 d0 xch a,rr exchange register with a 1 1 c* xch a,direct exchange direct byte with a 2 1 c5 xch a,@ri exchange indirect ram with a 1 1 c6, c7 xchd a,@ri exchange low-order digit indirect ram with a 1 1 d6, d7
1997 aug 01 58 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 79 instruction set description: boolean variable manipulation, program and machine control mnemonic description bytes cycles opcode (hex) boolean variable manipulation clr c clear carry ?ag 1 1 c3 clr bit clear direct bit 2 1 c2 setb c set carry ?ag 1 1 d3 setb bit set direct bit 2 1 d2 cpl c complement carry ?ag 1 1 b3 cpl bit complement direct bit 2 1 b2 anl c,bit and direct bit to carry ?ag 2 2 82 anl c,/bit and complement of direct bit to carry ?ag 2 2 b0 orl c,bit or direct bit to carry ?ag 2 2 72 orl c,/bit or complement of direct bit to carry ?ag 2 2 a0 mov c,bit move direct bit to carry ?ag 2 1 a2 mov bit,c move carry ?ag to direct bit 2 2 92 program and machine control acall addr11 absolute subroutine call 2 2 1 lcall addr16 long subroutine call 3 2 12 ret return from subroutine 1 2 22 reti return from interrupt 1 2 32 ajmp addr11 absolute jump 2 2 1 ljmp addr16 long jump 3 2 02 sjmp rel short jump (relative address) 2 2 80 jmp @a+dptr jump indirect relative to the dptr 1 2 73 jz rel jump if a is zero 2 2 60 jnz rel jump if a is not zero 2 2 70 jc rel jump if carry ?ag is set 2 2 40 jnc rel jump if carry ?ag is not set 2 2 50 jb bit,rel jump if direct bit is set 3 2 20 jnb bit,rel jump if direct bit is not set 3 2 30 jbc bit,rel jump if direct bit is set and clear bit 3 2 10 cjne a,direct,rel compare direct to a and jump if not equal 3 2 b5 cjne a,#data,rel compare immediate to a and jump if not equal 3 2 b4 cjne rr,#data,rel compare immediate to register and jump if not equal 3 2 b* cjne @ri,#data,rel compare immediate to indirect and jump if not equal 3 2 b6, b7 djnz rr,rel decrement register and jump if not zero 2 2 d* djnz direct,rel decrement direct and jump if not zero 3 2 d5 nop no operation 1 1 00
1997 aug 01 59 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 80 description of the mnemonics in the instruction set mnemonic description data addressing modes rr working register r0-r7. direct 128 internal ram locations and any special function register (sfr). @ri indirect internal ram location addressed by register r0 or r1 of the actual register bank. #data 8-bit constant included in instruction. #data 16 16-bit constant included as bytes 2 and 3 of instruction. bit direct addressed bit in internal ram or sfr. addr16 16-bit destination address. used by lcall and ljmp. the branch will be anywhere within the 64 kbytes program memory address space. addr11 11-bit destination address. used by acall and ajmp. the branch will be within the same 2 kbytes page of program memory as the ?rst byte of the following instruction. rel signed (two's complement) 8-bit offset byte. used by sjmp and all conditional jumps. range is - 128 to +127 bytes relative to ?rst byte of the following instruction. hexadecimal opcode cross-reference * 8, 9, a, b, c, d, e, f. 1, 3, 5, 7, 9, b, d, f. 0, 2, 4, 6, 8, a, c, e.
1997 aug 01 60 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 81 instruction map note 1. mov a, acc is not a valid instruction. first hexadecimal character of opcode ? second hexadecimal character of opcode ? 0123 456789abcdef 0 nop ajmp addr11 ljmp addr16 rr a inc a inc direct inc @ri inc rr 0 1 01234567 1 jbc bit,rel acall addr11 lcall addr16 rrc a dec a dec direct dec @ri dec rr 0 1 01234567 2 jb bit,rel ajmp addr11 ret rl a add a,#data add a,direct add a,@ri add a,rr 0 1 01234567 3 jnb bit,rel acall addr11 reti rlc a addc a,#data addc a,direct addc a,@ri addc a,rr 0 1 01234567 4 jc rel ajmp addr11 orl direct,a orl direct,#data orl a,#data orl a,direct orl a,@ri orl a,rr 0 1 01234567 5 jnc rel acall addr11 anl direct,a anl direct,#data anl a,#data anl a,direct anl a,@ri anl a,rr 0 1 01234567 6 jz rel ajmp addr11 xrl direct,a xrl direct,#data xrl a,#data xrl a,direct xrl a,@ri xrl a,rr 0 1 01234567 7 jnz rel acall addr11 orl c,bit jmp @a+dptr mov a,#data mov direct,#data mov @ri,#data mov rr,#data 0 1 01234567 8 sjmp rel ajmp addr11 anl c,bit movc a,@a+pc div ab mov direct,direct mov direct,@ri mov direct,rr 0 1 01234567 9 mov dtpr,#data16 acall addr11 mov bit,c movc a,@a+dptr subb a,#data subb a,direct subb a,@ri sub a,rr 0 1 01234567 a orl c,/bit ajmp addr11 mov bit,c inc dptr mul ab mov @ri,direct mov rr,direct 0 1 01234567 b anl c,/bit acall addr11 cpl bit cpl c cjne a,#data,rel cjne a,direct,rel cjne @ri,#data,rel cjne rr,#data,rel 0 1 01234567 c push direct ajmp addr11 clr bit clr c swap a xch a,direct xch a,@ri xch a,rr 0 1 01234567 d pop direct acall addr11 setb bit setb c da a djnz direct,rel xchd a,@ri djnz rr,rel 0 1 01234567 e movx a,@dtpr ajmp addr11 movx a,@ri clr a mov a,direct (1) mov a,@ri mov a,rr 0 1 0 1 01234567 f movx @dtpr,a acall addr11 movx @ri,a cpl a mov direct,a mov @ri,a mov rr,a 0 1 0 1 01234567
1997 aug 01 61 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 20 limiting values in accordance with the absolute maximum rating system (iec 134); note 1 notes 1. the following applies to the absolute maximum ratings: a) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the chapters 21 and 22 of this specification is not implied. b) this product includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static charge. however, its suggested that conventional precautions be taken to avoid applying greater than the rated maxima. c) parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. 2. this value is based on the maximum allowable die temperature and the thermal resistance of the package, not on device power consumption. symbol parameter min. max. unit v dd voltage on v dd to v ss and scl, sda to v ss - 0.5 +6.5 v v i input voltage on: any other pin to v ss - 0.5 v dd + 0.5 v ea/v pp to v ss - 0.5 +13 v i i , i o input/output current on any i/o pin - 10 ma p tot total power dissipation (note 2) - 1.0 w t stg storage temperature range - 65 +150 c t amb operating ambient temperature range: P8XCE560efb - 40 +85 c
1997 aug 01 62 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 21 dc characteristics v dd =5v 10%; v ss = 0 v; all voltages with respect to v ss unless otherwise speci?ed; t amb = - 40 to +85 c for the P8XCE560efb ; v dda =5v 10%; v ssa =0v. symbol parameter conditions min. max. unit supply (digital part) v dd supply voltage 4.5 5.5 v i dd operating supply current v dd = 5.5 v; notes 1 and 2 - 40 ma i dd(id) supply current idle mode v dd = 5.5 v; notes 1 and 3 - 12 ma i dd(pd) supply current power-down mode 2 v < v dd 1997 aug 01 63 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 v hys hysteresis of schmitt trigger inputs scl and sda (fast mode) 0.05v dd (20) - v r rst rst pull-down resistor 50 150 k w c i/o i/o pin capacitance test frequency = 1 mhz; t amb =25 c - 10 pf supply (analog part) v dda supply voltage v dda =v dd 0.2 v 4.5 5.5 v i dda supply current operating port 5 = 0 v to v dda ; notes 1 and 2 - 1.2 ma supply current operating 32 khz / pll operation port 5 = 0 v to v dda ; notes 17 and 18 - 7.2 ma i dda(id) supply current idle mode notes 1 and 3 - 70 m a supply current idle mode 32 khz / pll operation notes 17 and 18 - 6.0 ma i dda(pd) supply current power-down mode 2 v < v dd 1997 aug 01 64 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 notes to the dc characteristics 1. see figs 22, 25 and 24 for i dd test conditions. 2. the operating supply current is measured with all output pins disconnected; xtal1 driven with t r =t f = 5ns; v il =v ss + 0.5 v; v ih =v dd - 0.5 v; xtal2, xtal3 not connected; port 0 = ew = scl = sda = selxtal1 = v dd ; ea = rstin = adexs = xtal4 = v ss . 3. the idle mode supply current is measured with all output pins disconnected; xtal1 driven with t r =t f = 5ns; v il =v ss + 0.5 v; v ih =v dd - 0.5 v; xtal2, xtal3 not connected; ea = rstin = port 0 = ew = scl = sda = selxtal1 = v dd ; adexs = xtal4 = v ss . 4. the power-down current is measured with all output pins disconnected; xtal2 not connected; port 0 = ew = scl = sda = selxtal1 = v dd ; ea = rstin = adexs = xtal1 = xtal4 = v ss . 5. the input threshold voltage of scl and sda (sio1) meets the i 2 c specification, so an input voltage below 0.3 v dd will be recognized as a logic 0 while an input voltage above 0.7 v dd will be recognized as a logic 1. 6. pins of ports 1, 2, 3 and 4 source a transition current when they are being externally driven from high to low. the transition current reaches its maximum value when v in is approximately 2 v. 7. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol of ale and ports 1, 3 and 4. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make high-to-low transitions during bus operations. in the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8 v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. 8. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9 v dd specification when the address bits are stabilizing. 9. v ref(n)(a) = 0 v; v dda = 5.0 v, v ref(p)(a) = 5.12 v. v dd = 5.0 v, v ss = 0 v, adc is monotonic with no missing codes. measurement by continuous conversion of v in(a) = - 20 mv to 5.12 v in steps of 0.5 mv, deriving parameters from collected conversion results of adc. adc prescaler programmed according to the actual oscillator frequency, resulting in a conversion time within the specified range for t adc (15 to 50 m s). 10. the differential non-linearity (d le ) is the difference between the actual step width and the ideal step width. 11. the adc is monotonic; there are no missing codes. 12. the integral non-linearity (i le ) is the peak difference between the centre of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error. 13. the offset error (os e ) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and a straight line which fits the ideal transfer curve. the offset error is constant at every point of the actual transfer curve. 14. the gain error (g e ) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. gain error is constant at every point on the transfer curve. 15. the absolute voltage error (a e ) is the maximum difference between the centre of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. 16. this should be considered when both analog and digital signals are simultaneously input to port 5. 17. the supply current with 32 khz oscillator running and pll operation (selxtal1 = 0) is measured with all output pins disconnected; xtal4 driven with t r =t f = 5 ns; v il =v ss + 0.5 v; v ih =v dd - 0.5 v; xtal2 not connected; port 0 = ew = scl = sda = v dd ; ea = rstin = adexs = selxtal 1 = xtal1 = v ss . 18. not 100% tested; sum of i dda(id) (pll) and i dda (hf-oscillator). 19. the parameter meets the i 2 c-bus specification for standard-mode and fast-mode devices. 20. not 100% tested.
1997 aug 01 65 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 fig.22 supply current (i dd ) as a function of frequency at xtal1 (f clk ). handbook, halfpage 048 16 50 0 40 mbh089 12 30 20 10 f (mhz) i dd (ma) (1) (2) for P8XCE560 at v dd = 5.5 v: (1) maximum operating supply current (i dd ). (2) maximum supply current idle mode (i dd(id) ).
1997 aug 01 66 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 fig.23 adc conversion characteristic. (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential non-linearity (dl e ). (4) integral non-linearity (il e ). (5) centre of a step of the actual transfer curve. d book, full pagewidth mgd634 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 v in(a) (lsb ideal ) code out offset error os e offset error os e gain error g e (2) (3) (4) (5) (1) 1 lsb (ideal) 1lsb ideal v ref(p)(a) v ref(n)(a) + 1024 ----------------------------------------------- - =
1997 aug 01 67 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 22 ac characteristics v dd =5v 10%; v ss =0v; t amb = - 40 c to +85 c; c l = 100 pf for port 0, ale and psen; c l = 80 pf for all other outputs unless otherwise speci?ed; t clk(min) = 1/f clk(max) (f clk(max) = maximum operating frequency); t clk(min) =63ns. symbol parameter f clk = 12 mhz f clk =16mhz variable clock f clk = 3.5 to 16 mhz unit min. max. min. max. min. max. external program memory; see fig.27 t lhll ale pulse width 127 - 85 - 2t clk - 40 - ns t avll address valid to ale low 43 - 23 - t clk - 40 - ns t llax address hold after ale low 53 - 33 - t clk - 30 - ns t lliv ale low to valid instruction in - 234 - 150 - 4t clk - 100 ns t llpl ale low to psen low 53 - 33 - t clk - 30 - ns t plph psen pulse width 205 - 143 - 3t clk - 45 - ns t pliv psen low to valid instruction in - 145 - 83 - 3t clk - 105 ns t pxix input instruction hold after psen 0 - 0 - 0 - ns t pxiz input instruction ?oat after psen - 59 - 38 - t clk - 25 ns t aviv address to valid instruction in - 312 - 208 - 5t clk - 105 ns t plaz psen low to address ?oat - 10 - 10 - 10 ns external data memory; see fig.28 t rlrh rd pulse width 400 - 275 - 6t clk - 100 - ns t wlwh wr pulse width 400 - 275 - 6t clk - 100 - ns t avll address valid to ale low 43 - 23 - t clk - 40 - ns t llax address hold after ale low 48 - 28 - t clk - 35 - ns t rldv rd low to valid data in - 252 - 148 - 5t clk - 165 ns t rhdx data hold after rd 0 - 0 - 0 - ns t rhdz data ?oat after rd - 97 - 55 - 2t clk - 70 ns t lldv ale low to valid data in - 517 - 350 - 8t clk - 150 ns t avdv address to valid data in - 585 - 398 - 9t clk - 165 ns t llwl ale low to rd or wr low 200 300 138 238 3t clk - 50 3t clk +50 ns t avwl address valid to rd or wr low 203 - 120 - 4t clk - 130 - ns t whlh rd or wr high to ale high 43 123 23 103 t clk - 40 t clk +40 ns t qvwx data valid to wr transition 33 - 13 - t clk - 50 - ns t qvwh data valid time wr high 433 - 288 - 7t clk - 150 - ns t whqx data hold after wr 33 - 13 - t clk - 50 - ns t rlaz rd low to address ?oat - 0 - 0 - 0ns uart timing - shift register mode; see fig.30 t xlxl serial port clock cycle time 1.0 - 0.75 - 12t clk -m s t qvxh output data setup to clock rising edge 700 - 492 - 10t clk - 133 - ns t xhqx scl clock frequency 50 - 8 - 2t clk - 117 - ns t xhdx input data hold after clock rising edge 0 - 0 - 0 - ns t xhdv clock rising edge to input data valid - 700 - 492 - 10t clk - 133 ns
1997 aug 01 68 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 82 i 2 c-bus interface timing all values referred to v ih(min) and v il(max) levels; see fig.31. notes 1. a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) in order to bridge the undefined region of the falling edge of scl. 2. the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 3. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su, dat > 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r(max) +t su,dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. 4. c b = total capacitance of one bus line in pf. symbol parameter i 2 c-bus unit standard mode fast mode min. max. min. max. f scl scl clock frequency 0 100 0 400 khz t buf bus free time between stop and start condition 4.7 - 1.3 -m s t hd;sta hold time (repeated) start condition; after this period, the ?rst clock pulse is generated 4.0 - 0.6 -m s t low low period of the scl clock 4.7 - 1.3 -m s t high high period of the scl clock 4.0 - 0.6 -m s t su;sta set-up time for a repeated start condition 4.7 - 0.6 -m s t hd;dat data hold time: for cbus compatible masters (see chapter 21; notes 1 and 3) 5.0 -- -m s for i 2 c-bus devices (notes 1 and 2) 0 0 0.9 m s t su;dat data set-up time 250 - 100 (3) - ns t rd ; t rc rise time of sda and scl signals - 1000 20 + 0.1c b (4) 300 ns t fd ; t fc fall time of sda and scl signals - 300 t su;sto set-up time for stop condition 4.0 - 0.6 -m s c b capacitive load for each bus line - 400 - 400 pf t sp pulse width of spikes which must be suppressed by the input ?lter -- 050ns
1997 aug 01 69 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 83 external clock drive xtal1 symbol parameter variable clock (f clk = 3.5 to 16 mhz) unit min. max. t clk oscillator clock period 63 286 ns t high high time 20 t clk - t low ns t low low time 20 t clk - t high ns t r rise time - 20 ns t f fall time - 20 ns t cyc cycle time (12 t clk ) 0.75 3.4 m s fig.24 external clock drive xtal1. handbook, full pagewidth mga175 t high t low t clk t f v ih1 v ih1 0.8 v 0.8 v v ih1 v ih1 0.8 v 0.8 v t r fig.25 ac testing input, output waveform (a) and float waveform (b). ac testing inputs are driven at 2.4 v for a high and 0.45 v for a low. timing measurements are taken at 2.0 v for a high and 0.8 v for a low, see fig.25 (a). the float state is defined as the point at which a port 0 pin sinks 3.2 ma or sources 400 m a at the voltage test levels, see fig.25 (b). handbook, full pagewidth mga174 2.0 v 0.8 v 2.4 v 0.45 v 2.0 v 0.8 v 2.4 v 0.45 v float (b) (a) 2.4 v 0.45 v 2.0 v 0.8 v test points
1997 aug 01 70 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 handbook, full pagewidth mga180 p1 p2 s1 p1 p2 s2 p1 p2 s3 p1 p2 s4 p1 p2 s5 p1 p2 s6 p1 p2 s1 p1 p2 s2 p1 p2 s3 p1 p2 s4 p1 p2 s5 p1 p2 s6 one machine cycle one machine cycle xtal1 input address a0 - a7 inst. in address a0 - a7 inst. in address a0 - a7 inst. in address a0 - a7 inst. in address a8 - a15 address a8 - a15 address a8 - a15 address a8 - a15 address a0 - a7 inst. in address a0 - a7 inst. in address a0 - a7 data output or data input address a8 - a15 address a8 - a15 or port 2 out address a8 - a15 old data new data sampling time of i/o port pins during input (including int0 and int1) serial port clock port input port output port 2 bus (port 0) read or write of external data memory port 2 bus (port 0) external program memory fetch wr rd only active during a write to external data memory only active during a read from external data memory psen ale dotted lines are valid when rd or wr are active fig.26 instruction cycle timing. the port 5 input buffers have a maximum propagation delay of 300 ns. as a result port 5 sample time begins 300 ns before state s5 and ends when s5 has finished.
1997 aug 01 71 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 handbook, full pagewidth mga176 t lhll ale port 0 port 2 t cy lliv t t llpl t plph t llax t avll aviv t plaz t pliv t t pxix t pxiz address a8 to a15 address a8 to a15 inst. input inst. input a0 to a7 a0 to a7 psen fig.27 read from external program memory. fig.28 read from external data memory. handbook, full pagewidth mga177 t lhll ale port 0 port 2 t cy t lldv t llax t avll avdv t rlaz t address a8 to a15 (dph) or port 2 data input a0 to a7 psen t whlh avwl t t llwl t rlrh t rhdx t rhdz t rldv rd
1997 aug 01 72 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 handbook, full pagewidth mga178 t lhll ale port 0 port 2 t cy t llax t avll address a8 to a15 (dph) or port 2 data output a0 to a7 psen t whlh avwl t t llwl t wlwh t whqx t qvwh t qvwx wr fig.29 write to external data memory. fig.30 uart waveforms in shift register mode. h andbook, full pagewidth valid valid valid valid valid valid valid valid instruction ale 8 7 6 5 4 3 2 1 0 clock write to sbuf output data clear ri input data t xlxl t xhqx t qvxh t xhdv t xhdx set ri set ti mga179
1997 aug 01 73 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 t rd t fd t rc t fc t hd;sta t low t high t su;dat1 t hd;dat t su;dat2 t su;dat3 0.7v dd 0.3v dd t su;sto t buf t su;sta sda (input / output) scl (input / output) start condition repeated start condition stop condition start or repeated start condition 0.7v dd 0.3v dd mla773 fig.31 timing sio1 (i 2 c-bus) interface.
1997 aug 01 74 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 23 eprom characteristics the p87ce560 has an on-chip 64 kbytes eprom for fast and flexible controller software development. it is available as an otp-version in a plastic qfp package, p87ce560efb, which is not erasable. 23.1 programming and veri?cation the p87ce560 is programmed by using a modified quick-pulse programming algorithm (trademark algorithm of intel corporation). in table 85, the logic levels for reading the signature bytes and for programming the program memory, the encryption table and the lock bits are listed. the circuit configuration and waveforms for programming are shown in the figs 32 and 33. figure 34 shows the circuit configuration for code data verification. note that programming and verification is done with an oscillator frequency of 4 to 6 mhz. the two signature bytes identifying the device as an p87ce560 manufactured by philips are located as shown in table 84. table 84 programming and veri?cation 23.2 security for code protection the p87ce560 has an encryption table and three lock bits (lb1, lb2 and lb3). after programming the encryption table from addresses 00h to 3fh, a verification sequence will present the data at port 0 as a logical exnor of the program byte with one of the encryption bytes. the encryption table is not readable. the p87ce560 has 3 programmable lock bits which must be programmed according to table 85 to provide different levels of protection of the on-chip code and data. erasing the eprom also erases the encryption array and the program lock bits, returning the part to full functionality. the lock bits cannot be directly verified. verification of the lock bits is done by observing that their features are enabled. address content meaning 30h 15h philips 31h c3h p87ce560 table 85 protection level 69programming p = programmed; u = unprogrammed. protection level lb1 lb2 lb3 protection description 1 u u u no program lock features enabled. (code verify will still be encrypted by the encryption array if programmed.). 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the eprom is disabled. 3 p p u same as protection level 2 and also verify is disabled. 4 p p p same as protection level 3 and external memory execution by forcing ea = low is disabled.
1997 aug 01 75 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 86 eprom programming modes notes 1. each programming pulse is: a) low for 50 5 m s. b) high for at least 5 m s. 2. ale/ prog receives 5 programming pulses while v pp is held at 12.75 0.25 v. mode rstin psen ale/ prog ea/v pp p2.7 p2.6 p3.7 p3.6 p3.3 read signature high low high high low low low low low program code data high low low (1) v pp (2) high low high high high verify code data high low high high low low high high low program encryption table high low low (1) v pp (2) high low high low high program lock bit 1 high low low (1) v pp (2) high high high high high program lock bit 2 high low low (1) v pp (2) high high low low high program lock bit 3 high low low (1) v pp (2) low high low high high fig.32 programming configuration. handbook, full pagewidth P8XCE560 p1 xtal2 4 to 6 mhz a0 to a7 v ss xtal1 v dd p0 p2.7 p2.6 p2.0 to p2.5 pgm data a8 to a13 + 5 v ale/prog psen mbh090 ea/v pp high low low +12.75 v 5 50 m s - pulses to ground p3.4 a14 p3.5 a15 rst p3.6 p3.7 high high high p3.3 high
1997 aug 01 76 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 fig.33 prog waveform. handbook, full pagewidth ale/prog 5 pulses 50 5 m s 3 5 m s mgl170 fig.34 program verification p87ce560. handbook, full pagewidth P8XCE560 p1 rst p3.6 p3.7 xtal2 4 to 6 mhz a0 to a7 v ss xtal1 v dd p0 p2.7 p2.6 p2.0 to p2.5 pgm data a8 to a13 + 5 v ale/prog psen mbh091 high high high p3.3 low ea/v pp high high low low low p3.4 a14 p3.5 a15
1997 aug 01 77 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 table 87 eprom programming and veri?cation characteristics v dd =5v 10%; v ss =0v;t amb =21 cto27 c. symbol parameter min. max. unit v pp programming supply voltage 12.5 13.0 v i pp programming supply current - 50 ma f clk oscillator frequency 4 6 mhz t avgl address set-up to prog low 48 t clk - t ghax address hold after prog high 48 t clk - t dvgl data set-up to prog low 48 t clk - t ghdx data hold after prog high 48 t clk - t ehsh p2.7 ( enable) high to v pp 48 t clk - t shgl v pp set-up to prog low 10 -m s t ghsl v pp hold after prog high 10 -m s t glgh prog pulse width 45 55 m s t avqv address to data valid - 48t clk t elqv p2.7 ( enable) low to data valid - 48t clk t ehqz data ?oat after p2.7 ( enable) high 0 48t clk t ghgl prog high to prog low 5 -m s fig.35 eprom programming and verification. (1) for programming see fig.32. (2) for verification conditions see fig.34. handbook, full pagewidth t ghsl t ghgl t glgh t shgl t avgl t dvgl t ghdx t ghax data in data out address address t avqv t ehsh t elqv t ehqz high low p1.0 - p1.7 p2.0 - p2.5 p3.4 - p3.5 port 0 ale/prog ea/v pp mgd633 (enable) p2.7 programming (1) verification (2)
1997 aug 01 78 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 24 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.36 0.10 2.87 2.57 0.25 0.45 0.30 0.25 0.13 14.1 13.9 0.8 18.2 17.6 1.43 1.23 1.2 0.8 7 0 o o 0.2 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot318-1 92-11-17 95-02-04 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.0 0.6 d b p e q e a 1 a l p q detail x l (a ) 3 b 24 c b p e h a 2 d h v m b d z d a z e e v m a 1 80 65 64 41 40 25 pin 1 index x y w m w m 0 5 10 mm scale 80 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height qfp80: plastic quad flat package; sot318-1 a max. 3.3
1997 aug 01 79 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 25 soldering 25.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 25.2 re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 25.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 25.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 aug 01 80 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 26 definitions 27 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 28 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 aug 01 81 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 notes
1997 aug 01 82 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 notes
1997 aug 01 83 philips semiconductors product speci?cation 8-bit microcontroller P8XCE560 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca55 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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