integrated circuit systems, inc. general description features ics9147-22 block diagram pentium/pro tm system and cyrix? clock chip 9147-22 rev a 072597p pin configuration 48-pin ssop pentium is a trademark on intel corporation. ? generates system clocks for cpu, ioapic, sdram, pci, plus 14.318 mhz (ref0:1), usb, super i/o ? supports single or dual processor systems ? supports intel 60, 66.8mhz, cyrix 55, 75mhz plus 83.3 and 68mhz (turbo of 66.6) speeds. ? synchronous clocks skew matched to 250ps window on cpu, sdram and 500ps window on pci clocks ? cpu clocks to pci clocks skew 1-4ns (cpu early) ? two fixed outputs, 48mhz and 24 mhz ? separate 2.5v and 3.3v supply pins - 2.5v or 3.3v output: cpu, ioapic - 3.3v outputs: sdram, pci, ref, 48/24 mhz ? no power supply sequence requirements ? 48 pin 300 mil ssop the ics9147-22 is a clock synthesizer chip for pentium and pentiumpro plus cyrix cpu based desktop/notebook systems that will provide all necessary clock timing. features include four cpu, seven pci and eight sdram clocks. two reference outputs are available equal to the crystal frequency, plus the ioapic output powered by vddl. additionally, the device meets the pentium power- up stabilization, which requires that cpu and pci clocks be stable within 2ms after power-up. high drive pciclk and sdram outputs typically provide greater than 1 v/ns slew rate into 30 pf loads. cpuclk outputs typically provide better than 1v/ns slew rate into 20 pf loads while maintaining 50 5% duty cycle. the ref clock outputs typically provide better than 0.5v/ns slew rates. the ics9147-22 accepts a 14.318mhz reference crystal or clock as its input and runs on a 3.3v supply. power groups vdd1 = ref (0:1), x1, x2 vdd2 = pciclk_f, pciclk (0:5) vdd3 = sdram (0:7), vdd4 = 48mhz, 24mhz vddl = ioapic, cpuclk (0:3) ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9147-22 pin descriptions pin number pin name type description 1 ref1 out reference clock output 2 ref0 out reference clock output 3, 10, 17, 24, 31, 31, 37, 43 gnd pwr ground (common) 4x1 in crystal or reference input, nominally 14.318 mhz. includes internal load cap to gnd and feedback resistor from x2. 5 x2 out crystal output, includes internal load cap to gnd. 6, 47 n/c - pins are not internally connected 7, 15 vdd2 pwr supply for pciclkf, and pciclk (0:5) 8 pciclk_f out free running pci clock 9, 11, 12, 13, 14, 16 pciclk (0:5) out pci clocks 18 fs0 in frequency select 0 input 1 19 fs1 in frequency select 1 input 1 20 fs2 in frequency select 2 input 1 21 vdd4 pwr supply for 48mhz and 24mhz clocks 22 48mhz out 48mhz driver output for usb clock 23 24mhz out 24mhz driver output for super i/o clock 25, 28,34 vdd3 pwr supply for sdram (0:7) 26, 27, 29, 30, 32, 33, 35, 36 sdram (0:7) out sdrams clock at cpu speed 38, 39, 41, 42 cpuclk (0:3) out cpuclk clock output, powered by vddl 40, 46 vddl pwr supply for cpuclk (0:3) + ioapic 44 pd# in power down stops all clocks low and disables oscillator and internal vco's. 2 45 ioapic out ioapic clock output, powered by vddl at crystal frequency 48 vdd1 pwr supply for ref (0:1), x1, x2 note 1: internal pull-up resistor of nomimally 100k to 120k at 3.3v on indicated inputs. note 2: the pd# input pin has a protection diode clamp to the vddl power supply. if vddl is not connected to vdd, (ie vddl=2.5v, vdd=3.3v) then this input must have a series resistor if the logic high is connected to vdd. this input series resistor provides current limit for the clamp diode. for a pullup to vdd it should be 1kohm or more from the pd# pin to vdd. if the pd# pin is being driven by logic powered by 3.3v, then a 100 w series resistor will be suffcient.
3 ics9147-22 functionality v dd = 3.3v 5% v ddl = 2.5v 5% or 3.3v 5%, t a = 0 to 70 crystal (x1, x2) = 14.31818 mhz power management functionality fs2 fs1 fs0 cpuclk, sdram (mhz) pciclk (mhz) 0 0 0 8.33 1/2 cpu 0 0 1 75 30 0 1 0 83.3 33.3 0 1 1 68.5 1/2 cpu 1 0 0 55 1/2 cpu 1 0 1 75 1/2 cpu 1 1 0 60 1/2 cpu 1 1 1 66.8 1/2 cpu pd# cpuclk outputs pciclk(0:5) outputs pciclk_f, ref, 24/48mhz and sdram crystal osc vco 0 stopped low stopped low stopped low off off 1 running running running running running
4 ics9147-22 technical pin function descriptions vdd(1,2,3,4) this is the power supply to the internal core logic of the device as well as the clock output buffers for ref(0:1), pciclk, 48/24mhz and sdram(0:7). this supply operates at 3.3 volts. clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels for the clocks, please consult the dc parameter table in this data sheet. vddl this is the power supply for the cpuclk and ioapic output buffers. the voltage level for these outputs may be 2.5 or 3.3 volts. clocks from the buffers that each supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels of these clocks, please consult the dc parameter table in this data sheet. gnd this is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. x1 this input pin serves one of two functions. when the device is used with a crystal, x1 acts as the input pin for the reference signal that comes from the discrete crystal. when the device is driven by an external clock signal, x1 is the device input pin for that reference clock. this pin also implements an internal crystal loading capacitor that is connected to ground. see the data tables for the value of this capacitor. also includes feedback resistor from x2. x2 this output pin is used only when the device uses a crystal as the reference frequency source. in this mode of operation, x2 is an output signal that drives (or excites) the discrete crystal. the x2 pin will also implement an internal crystal loading capacitor that is connected to ground. see the data sheet for the value of this capacitor. cpuclk (0:3) these output pins are the clock outputs that drive processor and other cpu related circuitry that requires clocks which are in tight skew tolerance with the cpu clock. the voltage swing of these clocks is controlled by the voltage level applied to the vddl2 pin of the device. see the functionality table for a list of the specific frequencies that are available for these clocks and the selection codes to produce them. sdram(0:7) these output clocks are use to drive dynamic ram?s and are low skew copies of the cpu clocks. the voltage swing of the sdram?s output is controlled by the supply voltage that is applied to vdd3 of the device, operating at 3.3 volts. 48mhz this is a fixed frequency clock output at 48mhz that is typically used to drive usb devices. 24mhz this pin is a fixed frequency clock output typically used to drive super i/o devices. ioapic this output is a fixed frequency output clock that runs at the reference input (typically 14.31818mhz) . its voltage level swing is controlled by vddl and may operate at 2.5 or 3.3volts. ref(0:1) the ref outputs are fixed frequency clocks that run at the same frequency as the input reference clock x1 or the crystal (typically 14.31818mhz) attached across x1 and x2. pciclk_f this output is equivalent to pciclk(0:5) and is free running. pciclk (0:5) these output clocks generate all the pci timing requirements for a pentium/pro based system. they conform to the current pci specification. they run at 1/2 cpu frequency, or cpu/2.5; see frequency table. fs0,1,2 these input pins control the frequency of the clocks at the cpu, pciclk and sdram output pins. see frequency table. pd# this input pin stops all clocks in the low state and powers down the oscillator and vcos.
5 ics9147-22 absolute maximum ratings electrical characteristics at 3.3v supply v oltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage vil latched inputs and fulltime inputs - - 0.2vdd v input high voltage vih latched inputs and fulltime inputs 0.7vdd - - v input low current iil vin = 0v (fulltime inputs) -28.0 -10.5 - a input high current iih vin=vdd (fulltime inputs) -5.0 - 5.0 a output low current iol1a vol = 0.8v; cpu, sdram, 48mhz; vddl = 3.3v 19.0 30.0 - ma iol1b vol = 0.8v; cpu; vddl = 2.5v 19.0 30.0 ma output high current ioh1a voh = 2.0v; cpu, sdram, 48mhz; vddl = 3.3v --26.0-16.0 ma ioh1b voh = 2.0v; cpu; vddl = 2.5v -12.5 -9.5 ma output low current iol2a vol = 0.8v; 24, pci, ref, ioapic; vddl = 3.3v 16.0 25.0 - ma iol2b vol = 0.8v; ioapic; vddl = 2.5v 16.0 25.0 ma output high current ioh2a voh = 2.0v for ref, pci, 24mhz & ioapic at vddl = 3.3v --40.0-14.0ma ioh2b voh = 2.0v; ioapic; vddl = 2.5v -13.0 -4.0 ma output low voltage vol1a iol = 10ma; cpu, sdram, 48mhz; vddl = 3.3v -0.30.4v vol1b iol = 10ma; cpu; vddl=2.5v 0.3 0.4 v output high voltage voh1a ioh = -10ma; cpu, sdram, 48mhz; vddl = 3.3v 2.4 2.8 - v voh1b ioh = -10ma; cpu; vddl=2.5v 1.95 2.1 v output low voltage vol2a iol = 10ma; for ref, pci, 24mhz & ioapic at vddl = 3.3v -0.30.4v vol2b iol = 10ma; ioapic; vddl = 2.5v 0.3 0.4 v output high voltage voh2a ioh = -10ma; for ref, pci, 24mhz & ioapic at vddl = 3.3v 2.4 2.8 - v voh2b ioh = -10ma; ioapic; vddl = 2.5v 1.6 2.1 - v supply current idd @66.6 mhz; all outputs unloaded - 120 180 ma supply current i ddpd power down 300 500 a
6 ics9147-22 electrical characteristics at 3.3v v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. note 2: includes vddl = 2.5v note 3: vdd3 = 3.3v ac characteristics parameter symbol test conditions min typ max units rise time 1 tr1a 20pf load, 0.8 to 2.0v cpu, 48mhz; vdd = 3.3v -0.91.5ns rise time 1 tr1b 20pf load, 0.8 to 2.0v cpu; vddl @ 2.5v -1.52.0ns fall time 1,3 tf1 20pf load, 2.0 to 0.8v cpu, 48mhz; - 0.8 1.4 ns rise time 1 tr2 30pf load sdram 0.8 to 2.0v - 1.0 1.6 ns fall time 1 tf2 30pf load sdram 2.0 to 0.8v - 0.9 1.5 ns rise time 1 tr3 30pf load pci 0.8 to 2.0v - 1.2 2.0 ns fall time 1 tf3 30pf load pci 2.0 to 0.8v - 1.1 1.9 ns rise time 1,3 tr4 20pf load, 0.8 to 2.0v 24mhz, ref1 & ioapic - 0.83 1.4 ns rise time 1 tr4a 20pf load, 0.8 to 2.0v , ioapic with vddl = 2.5v -2.22.6 ns fall time 1,3 tf4 20pf load, 2.0 to 0.8v 24mhz, ref1 & ioapic - 0.81 1.3 ns rise time 1 tr5 load = 45pf 0.8 to 2.0v ref0 vdd = 3.3v 1.6 2.0 ns fall time 1 tf5 load = 45pf 2.0 to 0.8v, ref0 vdd = 3.3v 1.6 2.0 ns duty cycle 1 dt 20pf load @ vout=1.4v 45 50 55 % jitter, cycle to cycle 1 tjc-c cpu, vddl = 3.0 to 3.7v 200 300 ps jitter, one sigma 1 tj1s1 cpu; load=20pf, sdram load = 30pf - 50 150 ps jitter, absolute 1, tjab1 cpu; load=20pf, sdram load = 30pf -250 - 250 ps jitter, one sigma 1 tj1s1a cpu; load=20pf vddl=2.5v - 100 200 ps jitter, absolute 1 tjab1a cpu; load=20pf vddl=2.5v -500 - 500 ps jitter, one sigma 1 tj1s2 pci; load=30pf - 80 150 ps jitter, absolute 1 tjab2 pci; load=30pf -500 - 500 ps jitter, one sigma 1 tj1s3 ref1, 48/24mhz load=20pf, ref0 cl = 45pf - 1 3 % jitter, absolute 1 tjab3 ref1, 48/24mhz load=20pf, ref0 cl = 45pf -5 2 5 % input frequency 1 fi 12.0 14.318 16.0 mhz logic input capacitance 1 cin logic input pins - 5 - pf crystal oscillator capacitance 1 cinx x1, x2 pins - 18 - pf power-on time 1 ton from vdd=1.6v to 1st crossing of 66.6 mhz vdd supply ramp < 40ms -2.54.5 ms clock skew 1 tsk1 cpu to cpu; load=20pf; @1.4v (same vdd) - 150 250 ps clock skew 1 tsk2 sdram to sdram; load=30pf @ 1.4v - 150 250 ps clock skew 1 tsk3 pci to pci; load=30pf; @1.4v - 300 500 ps clock skew 1,2 tsk4 cpu(20pf) to pci (30pf); @1.4v (cpu is early) 1 2.6 4 ns clock skew 1 tsk4 sdram (30pf @3.3v) to cpu (20pf @2.5v) (2.5v cpu is late) 250 400 ps
7 ics9147-22 ordering information ics9147f-22 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp ssop package symbol common dimensions variations d n min. nom. max. min. nom. max. a .095 .101 .110 ac .620 .625 .630 48 a1 .008 .012 .016 ad .720 .725 .730 56 a2 .088 .090 .092 b .008 .010 .0135 c .005 .006 .0085 d see variations e .292 .296 .299 e0.025 bsc h .400 .406 .410 h .010 .013 .016 l .024 .032 .040 n see variations 0 5 8 x .085 .093 .100 this table in inches ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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