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data sheet rev.1.0 22.05.2008 swissbit germany ag wolfener stra?e 36 fon: +49 (0) 30 93 69 54 - 0 www.swissbit.com page 1 d-12681 berlin fax: +49 (0) 30 93 69 54 - 55 email: info@swissbit.com of 13 1gb ddr C sdram registered dimm 184pin ecc registered dimm SDR12872D1B62MT-50R 1gb pc 3200 in fbga technique rohs compliant features: 184-pin 72-bit dual-in-line module. double date rate synchronous dram module for server applications ddr-sdram component base: micron mt46v64m8p-5b-f v dd 2.5v 0.2v, v ddq 2.5v 0.2v registered inputs with one-clock delay phase-lock loop (pll) clock driver to reduce loading supports ecc error detection and correction programmable cas latency, burst length and wrap sequence auto refresh (cbr) and self refresh posted cas by programmable additive latency for better command and data bus efficiency 2.5v i/o ( sstl_2 compatible) serial presence detect with eeprom gold-contact pad this module family is fully pin and functional compatible to the jedec ddr1 spec. the pcb and all components are manufactured according to the rohs compliance specification [eu directive 2002/95/ec restriction of hazardous substances (rohs)] options: frequency / latency marking ddr400 mhz cl3 -50 ddr 333 mhz cl2,5 -60 module densities 1024mb with 18 dies and 2 ranks standard grade t ambient 0c to 70c environmental requirements: operating temperature (ambient) standard grade 0c to 70c operating humidity 10% to 90% relative humidity, noncondensing operating pressure 105 to 69 kpa (up to 10000 ft.) storage temperature -55c to 100c storage humidity 5% to 95% relative humidity, noncondensing storage pressure 1682 psi (up to 5000 ft.) at 50c figure: mechanical dimensions
data sheet rev.1.0 22.05.2008 swissbit germany ag wolfener stra?e 36 fon: +49 (0) 30 93 69 54 - 0 www.swissbit.com page 2 d-12681 berlin fax: +49 (0) 30 93 69 54 - 55 email: info@swissbit.com of 13 this swissbit module family is industry standard 184 -pin 8-byte double date rate synchronous sdram dual -in-line memory modules (dimms), which are organized as x72 high speed memory arrays designed for use in server applications. these dimms are assembled in fbga techno logy. the passive devices and the eeprom are smd components. the dimms use serial presence detects (spd) implemen ted via serial eeprom using the two-pin-i 2 c protocol. the first 128 bytes are utilized by the dimm manufac turer and the second 128 bytes are available to the end user. all swissbit dimms provide a high performance, flex ible 8-byte interface in a 133,35mm long footprint. all modules of the extended temperature grade have seen special tests during the manufacturing process to ensure proper operation according to the field of o peration as stated in the environmental conditions. module configuration organization ddr sdrams used row addr. bank select col. addr. refresh module dimensions in mm 128m x 72 18 x 128m x 8 14 ba0, ba1 12 8k 133,35 ma x product spectrum part number module density transfer rate memory clock/data bit rate latency SDR12872D1B62MT-50R 1gb 3.2 gb/s 5.0ns/400mt/s 3200-333 sdr12872d1b62mt-60r 1gb 2.7 gb/s 6.0ns/333mt/s 2700-2533 pin name a0-a12 address inputs ba0, ba1 bank selects dq0 C dq63 data input/output cb0 - cb7 check bits /ras row address strobe /cas column address strobe /we read / write enable cke0 C cke1 clock enable ck0 C ck2 clock inputs, positive line /ck0 C /ck2 clock inputs, negative line dqs0- dqs17 data strobes
data sheet rev.1.0 22.05.2008 swissbit germany ag wolfener stra?e 36 fon: +49 (0) 30 93 69 54 - 0 www.swissbit.com page 3 d-12681 berlin fax: +49 (0) 30 93 69 54 - 55 email: info@swissbit.com of 13 /s0, /s1 chip select v dd power (2.5v 0.2v) v ddq dq power (2.5v0.2v) v ddspd spd power v ref input/output reference vss ground scl clock for presence detect sda serial data out for presence detect sa0 C sa2 slave address select bus for presence det ect nc no connection pin configuration front side back side pin # pin name pin # pin name pin # pin name pin # pin name 1 v ref 47 dqs8 93 v ss 139 v ss 2 dq0 48 a0 94 dq4 140 dqs17 3 v ss 49 cb2 95 dq5 141 a10 4 dq1 50 v ss 96 v ddq 142 cb6 5 dqs0 51 cb3 97 dqs9 143 v ddq 6 dq2 52 ba1 98 dq6 144 cb7 7 v dd 53 dq32 99 dq7 145 v ss 8 dq3 54 v ddq 100 v ss 146 dq36 9 nc 55 dq33 101 nc 147 dq37 10 /reset 56 dqs4 102 nc 148 v dd 11 v ss 57 dq34 103 nc 149 dqs13 12 dq8 58 v ss 104 v ddq 150 dq38 13 dq9 59 ba0 105 dq12 151 dq39 14 dqs1 60 dq35 106 dq13 152 v ss 15 v ddq 61 dq40 107 dqs10 153 dq44 16 nc 62 v ddq 108 v dd 154 /ras 17 nc 63 /we 109 dq14 155 dq45 18 v ss 64 dq41 110 dq15 156 v ddq 19 dq10 65 /cas 111 cke1 157 /s0 20 dq11 66 v ss 112 v ddq 158 /s1 21 cke0 67 dqs5 113 nc 159 dqs14 22 v ddq 68 dq42 114 dq20 160 v ss 23 dq16 69 dq43 115 a12 161 dq46 24 dq17 70 v dd 116 v ss 162 dq47 25 dqs2 71 nc 117 dq21 163 nc
data sheet rev.1.0 22.05.2008 swissbit germany ag wolfener stra?e 36 fon: +49 (0) 30 93 69 54 - 0 www.swissbit.com page 4 d-12681 berlin fax: +49 (0) 30 93 69 54 - 55 email: info@swissbit.com of 13 front side back side pin # pin name pin # pin name pin # pin name pin # pin name 26 v ss 72 dq48 118 a11 164 v ddq 27 a9 73 dq49 119 dqs11 165 dq52 28 dq18 74 v ss 120 v dd 166 dq53 29 a7 75 nc 121 dq22 167 nc 30 v ddq 76 nc 122 a8 168 v dd 31 dq19 77 v ddq 123 dq23 169 dqs15 32 a5 78 dqs6 124 v ss 170 dq54 33 dq24 79 dq50 125 a6 171 dq55 34 v ss 80 dq51 126 dq28 172 v ddq 35 dq25 81 v ss 127 dq29 173 nc 36 dqs3 82 v ddid 128 v ddq 174 dq60 37 a4 83 dq56 129 dqs12 175 dq61 38 v dd 84 dq57 130 a3 176 v ss 39 dq26 85 v dd 131 dq30 177 dqs16 40 dq27 86 dqs7 132 v ss 178 dq62 41 a2 87 dq58 133 dq31 179 dq63 42 v ss 88 dq59 134 cb4 180 v ddq 43 a1 89 v ss 135 cb5 181 sa0 44 cb0 90 nc 136 v ddq 182 sa1 45 cb1 91 sda 137 ck0 183 sa2 46 v dd 92 scl 138 /ck0 184 v ddspd
data sheet rev.1.0 22.05.2008 swissbit germany ag wolfener stra?e 36 fon: +49 (0) 30 93 69 54 - 0 www.swissbit.com page 5 d-12681 berlin fax: +49 (0) 30 93 69 54 - 55 email: info@swissbit.com of 13 functional block diagramm 1gb 2 ranks ddr-sdram dimm
data sheet rev.1.0 22.05.2008 swissbit germany ag wolfener stra?e 36 fon: +49 (0) 30 93 69 54 - 0 www.swissbit.com page 6 d-12681 berlin fax: +49 (0) 30 93 69 54 - 55 email: info@swissbit.com of 13 dc electrical characteristics and operating conditions (0c t a + 70c ; v dd = +2.5v 0.2v, v ddq = +2.5v 0.2v) see note 1 on page 9 parameter/ condition symbol min max units supply voltage v dd 2.3 2.7 v i/o supply voltage v dd q 2.3 2.7 v i/o reference voltage v ref 0.49 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt v ref C 0.04 v ref + 0.04 v input high (logic 1) voltage v ih (dc) v ref + 0.15 v dd + 0.3 v input low (logic 0) voltage v il (dc) -0.3 v ref C 0.15 v input leakage current any input 0v v in v dd, v ref pin 0v v in 1.35v (all other pins not under test = 0v) i i -10 10 a output leakage current (dq s are disabled; 0v v out v ddq ) i oz -10 10 a output levels: high current ( v out = v ddq -0.373v,minimum v ref, minimum v tt ) low current ( v out =0.373v, maximum v ref, maximum v tt ) i oh i ol -16.8 16.8 - - ma ma ac input operating conditions (0c t a + 70c ; v dd = +2.5v 0.2v, v ddq = +2.5v 0.2v) see note 1 on page 9 parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.310 - v input low (logic 0) voltage v il (ac) - v ref - 0.310 v i/o reference voltage v ref(ac) 0.49 x v dd q 0.51x v dd q v capacitance parameter symbol min max units input/output capacitance: dq , dqs c 10 4.0 5.0 pf input capacitance: command and address c 11 18.0 27.0 pf input capacitance: /s 0,1 c 11 18.0 27.0 pf input capacitance: ck, /ck c 12 10.0 14.0 pf input capacitance: cke c 13 18.0 27.0 pf
data sheet rev.1.0 22.05.2008 swissbit germany ag wolfener stra?e 36 fon: +49 (0) 30 93 69 54 - 0 www.swissbit.com page 7 d-12681 berlin fax: +49 (0) 30 93 69 54 - 55 email: info@swissbit.com of 13 i dd specifications and conditions (0c t a + 70c ; v ddq = +2.5v 0.2v, v dd = +2.5v 0.2v) see note 1 on page 9 max. parameter & test condition symb. 3200-3033 2700-2533 unit operating current *) : one device bank; active- precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i ddo 1440 1215 ma operating current : *) one device bank; active-read-precharge; burst = 2; t rc = t rc (min); t ck = t ck (min);i out = 0ma; address and control inputs changing once per clock cycle i dd1 2160 1485 ma precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p 90 90 ma idle standby current: cs# = high; all device banks idle; t ck = t ck (min); cke= high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd2f 990 810 ma active power-down standby current: one device bank active; power-down mode; t ck = t ck (min);cke = low i dd3p 810 630 ma active standby current: cs# = high; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n 1080 900 ma operating current: burst = 2; reads; continous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r 4815 1530 ma operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w 1854 1620 ma t rc = t rc (min) i dd5 6210 5220 ma auto refresh current t rc = 7.8125s i dd6 198 180 ma self refresh current: cke 0.2v i dd7 90 90 ma operating current *) : four device bank interleaving reads (bl =4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only durin g active read, or write commands i dd8 4050 3690 ma *) value calculated as one module rank in this oper ating condition, and all other module ranks in idd2 p (cke low) mode.
data sheet rev.1.0 22.05.2008 swissbit germany ag wolfener stra?e 36 fon: +49 (0) 30 93 69 54 - 0 www.swissbit.com page 8 d-12681 berlin fax: +49 (0) 30 93 69 54 - 55 email: info@swissbit.com of 13 ddr sdram component electrical characteristics and recom mended ac operating conditions (0c t a + 70c ; v ddq = +2.5v 0.2v, v dd = +2.5v 0.2v) see note 1 on page 9 ac characteristics 3200-3033 2700-2533 parameter symbol min max min max unit access window of dq s ck/ck# t ac -0.70 +0.70 -0.70 +0.70 ns ck high-level width t ch 0.45 0.55 0.45 0.55 t ck ck low-level width t cl 0.45 0.55 0.45 0.55 t ck cl=2.0 t ck (2.0) 7.5 13.0 7.5 13.0 cl=2.5 t ck (2.5) 6.0 13.0 6.0 13.0 ns clock cycle time cl= 3.0 t ck (3.0) 5.0 13.0 ns dq and dm input hold time relative to dqs t dh 0.40 0.45 ns dq and dm input setup time relative to dqs t ds 0.40 0.45 ns dq and dm input pulse width ( for each input ) t dipw 1.75 1.75 ns access window of dqs from ck/ck# t dqsck -0.6 +0.6 -0.6 +0.6 ns dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs Cdq skew, dqs to last dq valid, per group, per access t dqsq 0.40 0.45 ns write command to first dqs latching transition t dqss 0.72 1.28 0.75 1.25 t ck dqs falling edge to ck rising- setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising- hold time t dsh 0.2 0.2 t ck half clock period t hp t ch, t cl t ch, t cl ns data-out high-impedance window from ck/ck# t hz +0.7 +0.7 ns data-out low-impedance window from ck/ck# t lz -0.7 -0.7 ns address and control input hold time ( fast slew rate ) t ihf 0.6 0.75 ns address and control input setup time ( fast slew rate ) t isf 0.6 0.75 ns address and control input hold time ( slow slew rate ) t ihs 0.6 0.8 ns address and control input setup time ( slow slew rate ) t iss 0.6 0.8 ns load mode register command cycle time t mrd 10 12 ns adress and control input pulse width (for each input) t ipw 2.2 2.2 ns dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs ns data hold skew factor t qhs 0.5 0.6 ns
data sheet rev.1.0 22.05.2008 swissbit germany ag wolfener stra?e 36 fon: +49 (0) 30 93 69 54 - 0 www.swissbit.com page 9 d-12681 berlin fax: +49 (0) 30 93 69 54 - 55 email: info@swissbit.com of 13 ac characteristics 3200-3033 2700-2533 parameter symbol min max min max unit active to precharge command t ras 40 70.000 42 70.000 ns active to read with auto precharge command t rap 15 15 ns active to active/auto refresh command period t rc 55 60 ns auto refresh command period t rfc 70 72 ns active to read or write delay t rcd 15 15 ns precharge command period t rp 15 15 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 10 12 ns dqs write preamble t wpre 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 ns dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck write recovery time t wr 15 15 ns internal write to read command delay t wtr 2 1 t ck data valid output window na t qh - t dqsq t qh - t dqsq ns refresh to refresh command interval t refc 70.3 70.3 s average periodic refresh interval t refi 7.8 7.8 s terminating voltage delay to v dd t vtd 0 0 ns exit self refresh to non-read command t xsnr 70 75 ns exit self refresh to read command t xsrd 200 200 t ck note 1: values for ac timing, idd, and electrical a c and dc characteristics might have been collected within the standard temperature range and at nominal reference /supply voltage levels, but the related specificati ons and device operation are guaranteed for the full voltag e range specified and for the corresponding field o f operation according to the actual temperature grade of the mo dule (extended e, i or w; refer to the environmenta l conditions for more details).
data sheet rev.1.0 22.05.2008 swissbit germany ag wolfener stra?e 36 fon: +49 (0) 30 93 69 54 - 0 www.swissbit.com page 10 d-12681 berlin fax: +49 (0) 30 93 69 54 - 55 email: info@swissbit.com of 13 register timing requirements and switching characte ristics 0c t a +70c v dd = +2.5v 0.2v register symbol parameter condition min max units notes f clock clock frequency - 200 mhz t pd clock to output time 1,1 2,8 ns t phl reset to output time 30pf to gnd and 50 ohms to vtt - 5 ns t w pulse duration ck, ck# high or low 2,5 - ns t act differential inputs active time - 22 ns 2 t inact differential inputs inactive time - 22 ns 3 setup time, fast slew rate 0,75 - ns 4,6 t su setup time, slow slew rate data before ck high, ck# low 0,9 - ns 5,6 hold time, fast slew rate 0,75 - ns 4,6 sstl (bit pattern by jesd82-3 or jesd82-4) t h hold time, slow slew rate data after ck high, ck# low 0,9 - ns 5,6 note: 1. the timing and switching specifications for the register listed above are critical for proper opera tion of the ddr sdram registered dimms. these are meant to be a subset of the parameters for the specific device used on the module. detailed information for this register is available in jedec standard jesd82-4. 2. data inputs must be low a minimum time of tact m ax, after reset# is taken high. 3. data and clock inputs must be held at valid leve ls (not floating) a minimum time of t inact max, after reset# is taken low. 4. for data signal input slew rate 3 1 v/ns. 5. for data signal input slew rate 3 0.5 v/ns and < 1v/ns. 6. ck, ck# signals input slew rate 3 1v/ns.30 pll clock driver timing requirements and switching characteristics 0c t a +70c v dd = +2.5v 0.2v parameter symbol min nominal max units notes operating clock frequency f ck 60 - 170 mhz 2,3 input duty cycle t dc 40 - 60 % stabilization time t stab - - 100 ms 4 cycle to cycle jitter t jitt cc -75 - 75 ps static phase offset t ? -50 0 50 ps 5 output clock skew tsko - - 100 ps period jitter t jitt per -75 - 75 ps 6 half-period jitter t jitt hper -100 - 100 ps 6 input clock slew rate t ls i 1,0 - 4 v/ns output clock slew rate t ls o 1,0 - 2 v/ns note: 1. the timing and switching specifications for the pll listed above are critical for proper operation of the ddr sdram registered dimms. these are meant to be a subset of the parameters for the specific device used on the module. detailed information for this pll is available in jedec stand ard jesd82. 2. the pll must be able to handle spread spectrum i nduced skew. 3. operating clock frequency indicates a range over which the pll must be able to lock, but in which i t is not required to meet the other timing parameters. (used for low speed sy stem debug.) 4. stabilization time is the time required for the integrated pll circuit to obtain phase lock of its feedback signal to its reference signal after power up. 5. static phase offset does not include jitter. 6. period jitter and half-period jitter specificati ons are separate specifications that must be met in dependently of each other.
data sheet rev.1.0 22.05.2008 swissbit germany ag wolfener stra?e 36 fon: +49 (0) 30 93 69 54 - 0 www.swissbit.com page 11 d-12681 berlin fax: +49 (0) 30 93 69 54 - 55 email: info@swissbit.com of 13 serial presence-detect matrix byte description 3200-3033 2700-2533 0 number of spd bytes used 0x80 1 total number of bytes in spd device 0x08 2 fundamental memory type 0x07 3 number of row addresses on assembly 0x0d 4 number of column addresses on assembly 0x0b 5 number of physical banks on dimm 0x02 6 module data width 0x48 7 module data width (continued) 0x00 8 module voltage interface levels (v ddq ) 0x04 9 sdram cycle time, (t ck ) (cas latency =2.5 (2700, 2100) ; cl=3* (3200) 0x50 0x60 10 sdram access from clock, (t ac ) (cas latency =2.5 (2700, 2100); cl=3* (3200)) 0x70 0x70 11 module configuration type 0x02 12 refresh rate/ type 0x82 13 sdram device width (primary sdram) 0x08 14 error- checking sdram data width 0x08 15 minimum clock delay, back- to- back random column access 0x01 16 burst lengths supported 0x0e 17 number of banks on sdram device 0x04 18 cas latencies supported 0x1c 0x0c 19 cs latency 0x01 20 we latency 0x02 21 sdram module attributes 0x26 22 sdram device attributes: general 0xc0 23 sdram cycle time, (t ck ) (cas latency=2(2700, 2100) cl=2,5*(3200)) 0x60 0x75 24 sdram access from ck, (t ac ) (cas latency=2(2700, 2100) cl=2.5*(3200) 0x70 0x70 25 sdram cycle time, (t ck ) (cas latency=1.5(2700, 2100) cl=2*(3200)) 0x75 0x00 26 sdram access from ck, (t ac ) (cas latency=1.5(2700, 2100) cl=2*(3200) 0x75 0x00 27 minimum row precharge time, (t rp ) 0x3c 0x48 28 minimum row active to row active, (t rrd ) 0x28 0x30 29 minimum ras# to cas# delay, (t rcd ) 0x3c 0x48 30 minimum ras# pulse width, (t ras ) 0x28 0x2a 31 module bank density 0x80
data sheet rev.1.0 22.05.2008 swissbit germany ag wolfener stra?e 36 fon: +49 (0) 30 93 69 54 - 0 www.swissbit.com page 12 d-12681 berlin fax: +49 (0) 30 93 69 54 - 55 email: info@swissbit.com of 13 serial presence-detect matrix (continued) byte description 3200-3033 2700-2533 32 address and command setup time, (t is ) 0x60 0x80 33 address and coomand hold time, (t ih ) 0x60 0x80 34 data/data mask input setup time, (t ds ) 0x40 0x45 35 data/data mask input hold time, (t dh ) 0x40 0x45 36-40 reserved 0x00 41 min active auto refresh time (t rc ) 0x37 0x3c 42 minimum auto refresh to active/ auto refresh command period, (t rfc) 0x46 0x48 43 sdram device max cycle time (t ckmax ) 0x30 44 sdram device max dqs-dq skew time (t dqsq ) 0x28 0x2d 45 sdram device max read data hold skew factor (t qhs ) 0x50 0x60 46-61 reserved 0x00 62 spd revision 0x11 63 checksum for bytes 0-62 0xd9 0x8c 64 manufacturer`s jedec id code 7f 65 manufacturer`s jedec id code 7f 66 manufacturer`s jedec id code 7f 67 manufacturer`s jedec id code (continued) da 72 manufacturing location x 73-90 module part number (ascii) sdr12872d1b62mt-xx 91 pcb identification code x 92 identification code (continued) x 93 year of manufacture in bcd x 94 week of manufacture in bcd x 95-98 module serial number x x 99-127 manufacturer-specific data (rsvd) part number code s d r 128 72 d1 b 6 2 mt - 50 * r 1 2 3 4 5 6 7 8 9 10 11 12 13 *rohs compl. swissbit ag ddr-400mhz sdram d dr 1 184 pin registered 2.5v chip vendor (micron) depth (1024mb) 2 module ranks width chip rev. f pcb-type (brda80a) chip organisation x8 * optional / additional information
data sheet rev.1.0 22.05.2008 swissbit germany ag wolfener stra?e 36 fon: +49 (0) 30 93 69 54 - 0 www.swissbit.com page 13 d-12681 berlin fax: +49 (0) 30 93 69 54 - 55 email: info@swissbit.com of 13 locations swissbit ag industriestrasse 4 C 8 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 72 66 fax: +41 (0)71 913 74 50 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 18 willett avenue, suite 203 port chester, ny 10573 usa phone: +1 914 935 1400 fax: +1 914 935 9865 _____________________________ swissbit na, inc. 7801 north lamar boulevard, suite e C 186 austin, tx 78752 usa phone: +1 512 302 9001 fax: +1 512 302 4808

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