? semiconductor components industries, llc, 2016 august, 2016 ? rev. 0 1 publication order number: NCP81158/d NCP81158 synchronous buck mosfet driver the NCP81158 is a high?performance dual mosfet gate driver in a small 3 mm x 3 mm package, optimized to drive the gates of both high?side and low?side power mosfets in a synchronous buck converter. the driver outputs can be placed into a high?impedance state via the tri?state pwm and en inputs. the NCP81158 comes packaged with an integrated boost diode to minimize external components. a vcc uvlo function guarantees the outputs are low when the supply voltage is low. features ? space?ef ficient 3 mm x 3 mm dfn8 thermally?enhanced package ? vcc range of 4.5 v to 5.5 v ? internal bootstrap diode ? 5 v 3?stage pwm input ? diode braking capability via en mid?state ? adaptive anti?cross conduction circuit protects against cross?conduction during fet turn?on and turn?off ? output disable control turns off both mosfets via enable pin ? vcc undervoltage lockout ? these devices are pb?free, halogen?free/bfr?free and are rohs compliant typical applications ? power solutions for notebook and desktop systems device package shipping ? ordering information NCP81158mntxg dfn8 (pb?free) 3000 / tape & reel dfn8 case 506bj marking diagram www. onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. 1 2 3 45 6 7 8 bst pwm sw vcc en drvh drvl gnd pinout diagram flag 9 1 81158 = specific device code a = assembly location l = wafer lot y = year w = work week = pb?free package 81158 alyw 1 (note: microdot may be in either location) 8
NCP81158 www. onsemi.com 2 bst pwm logic drvh sw anti?cross conduction vcc drvl vcc en uvlo zcd detection figure 1. block diagram pin descriptions pin no. symbol description 1 bst floating bootstrap supply pin for high side gate driver. connect the bootstrap capacitor between this pin and the sw pin. 2 pwm control input. the pwm signal has three distinctive states: low = low side fet enabled, mid = diode emulation enabled, high = high side fet enabled. 3 en logic input. a logic high to enable the part and a logic low to disable the part. three states logic input: en = high to enable the gate driver; en = low to disable the driver; en = mid to go into diode mode (both high and low side gate drive signals are low) 4 vcc power supply input. connect a bypass capacitor (0.1 f) from this pin to ground. 5 drvl low side gate drive output. connect to the gate of low side mosfet. 6 gnd bias and reference ground. all signals are referenced to this node. 7 sw switch node. connect this pin to the source of the high side mosfet and drain of the low side mosfet. 8 drvh high side gate drive output. connect to the gate of high side mosfet. 9 flag thermal flag. there is no electrical connection to the ic. connect to ground plane.
NCP81158 www. onsemi.com 3 application circuit figure 2. application circuit bst pwm en vcc drvh pad drvl gnd sw 5 v _ power vin pwm dron vccp q1 q2 q3 r1 1.02 r2 0.0 c2 0.1 uf c1 1uf r3 0.0 r4 2.2 c3 2700 pf l 235 nh c4 4.7 uf c5 4.7 uf c6 4.7 uf c7 390 uf NCP81158
NCP81158 www. onsemi.com 4 absolute maximum ratings electrical information symbol pin name v max v min v cc main supply voltage input 6.5 v 7.5 v < 80 ns ?0.3 v bst bootstrap supply voltage 35 v wrt/ gnd 40 v 50 ns wrt/ gnd 6.5 v wrt/ sw 7.7 v < 50 ns wrt/ sw ?0.3 v wrt/sw sw switching node (bootstrap supply return) 35 v 40 v 80 ns ?5 v ?10 v (200 ns) drvh high side driver output bst + 0.3 v sw + 7 v (< 80 ns) ?0.3 v wrt/sw ?2 v (< 200 ns) wrt/sw drvl low side driver output v cc + 0.3 v 7 v (< 80 ns) ?0.3 v dc ?5 v (< 200 ns) pwm drvh and drvl control input 6.5 v ?0.3 v en enable pin 6.5 v ?0.3 v gnd ground 0 v 0 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. *all signals referenced to agnd unless noted otherwise. thermal information symbol parameter value unit r ja thermal characteristic qfn package (note 1) 119 c/w t j operating junction temperature range (note 2) ?40 to 150 c t a operating ambient temperature range ?40 to +100 c t stg maximum storage temperature range ?55 to +150 c msl moisture sensitivity level ? qfn package 1 *the maximum package power dissipation must be observed. 1. 1 in 2 cu, 1 oz. thickness. 2. jesd 51?7 (1s2p direct?attach method) with 1 lfm. NCP81158 electrical characteristics (?40 c < t a < +100 c; 4.5 v < v cc < 5.5 v, 4.5 v < bst?swn < 5.5 v, 4.5 v < bst < 30 v, 0 v < swn < 21 v, unless otherwise noted) parameter test conditions min typ max unit supply voltage vcc operation voltage 4.5 5.5 v undervoltage lockout vcc start threshold 3.8 4.35 4.5 v vcc uvlo hysteresis 150 200 250 mv supply current shutdown mode i cc + i bst , en = gnd 1.0 2.0 a normal mode i cc + i bst , en = 5 v, pwm = osc 4.7 ma standby current i cc + i bst , en = high, pwm = low, no loading on drvh & drvl 0.9 ma standby current i cc + i bst , en = high, pwm = high, no loading on drvh & drvl 1.1 ma bootstrap diode forward voltage v cc = 5 v, forward bias current = 2 ma 0.1 0.4 0.6 v
NCP81158 www. onsemi.com 5 NCP81158 electrical characteristics (?40 c < t a < +100 c; 4.5 v < v cc < 5.5 v, 4.5 v < bst?swn < 5.5 v, 4.5 v < bst < 30 v, 0 v < swn < 21 v, unless otherwise noted) parameter unit max typ min test conditions pwm input pwm input high 3.4 v pwm mid?state 1.3 2.7 v pwm input low 0.7 v zcd blanking timer 350 ns high side driver output impedance, sourcing current v bst ?v sw = 5 v 0.9 1.7 output impedance, sinking current v bst ?v sw = 5 v 0.7 1.7 drvh rise time tr drvh v cc = 5 v, 3 nf load, v bst ?v sw = 5 v 16 25 ns drvh fall time tf drvh v cc = 5 v, 3 nf load, v bst ?v sw =5 v 11 18 ns drvh turn?off propag ation delay tpdl drvh c load = 3 nf 10 30 ns drvh turn?on propagation delay tpdh drvh c load = 3 nf 10 40 ns sw pulldown resistance sw to pgnd 45 k drvh pulldown resistance drvh to sw, bst?sw = 0 v 45 k low side driver output impedance, sourcing current 0.9 1.7 output impedance, sinking current 0.4 0.8 drvl rise time tr drvl c load = 3 nf 16 25 ns drvl fall time tf drvl c load = 3 nf 11 15 ns drvl turn?off pro pagation delay tpdl drvl c load = 3 nf 10 30 ns drvl turn?on propagation delay tpdh drvl c load = 3 nf 5.0 25 ns drvl pulldown resistance drvl to pgnd, v cc = pgnd 45 k en input input voltage high 3.3 v input voltage mid 1.35 1.8 v input voltage low 0.6 v input bias current ?1.0 1.0 a propagation delay time 20 40 ns sw node sw node leakage current 20 a zero cross detection threshold voltage ?6.0 mv product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. table 1. decoder truth table input zcd drvl drvh pwm high (enable high) zcd reset low high pwm mid (enable high) positive current through the inductor high low pwm mid (enable high) zero current through the inductor low low pwm low (enable high) zcd reset high low enable at mid x low low
NCP81158 www. onsemi.com 6 figure 3. gate timing diagram figure 4. timing diagram pwm drvh?sw drvl il pwm drvl drvh?sw tpdl drvl 90% tf drvl 10% 1v tpdh drvh 10% 90% tr drvh 1v 10% 90% 90% 10% tpdl drvh tf drvh tpdh drvl tr drvl application information the NCP81158 gate driver is a single?phase mosfet driver designed for driving n?channel mosfets in a synchronous buck converter topology. low?side driver the low?side driver is designed to drive a ground?referenced low?r ds(on) n?channel mosfet. the voltage supply for the low?side driver is internally connected to the vcc and gnd pins. high?side driver the high?side driver is designed to drive a floating low?r ds(on) n?channel mosfet. the gate voltage for the high?side driver is developed by a bootstrap circuit referenced to the sw pin. the bootstrap circuit is comprised of the integrated diode and an external bootstrap capacitor. when the NCP81158 is starting up, the sw pin is held at ground, allowing the 1v 1v
NCP81158 www. onsemi.com 7 bootstrap capacitor to charge up to vcc through the bootstrap diode. when the pwm input is driven high, the high?side driver will turn on the high?side mosfet using the stored charge of the bootstrap capacitor. as the high?side mosfet turns on, the sw pin rises. when the high?side mosfet is fully turned on, sw will settle to vin and bst will settle to vin + vcc (excluding parasitic ringing). bootstrap circuit the bootstrap circuit relies on an external charge storage capacitor (c bst ) and an integrated diode to provide current to the high?side driver. a multi?layer ceramic capacitor (mlcc) with a value greater than 100 nf should be used for c bst . power supply decoupling the NCP81158 can source and sink relatively large currents to the gate pins of the mosfets. in order to maintain a constant and stable supply voltage, a low?esr capacitor should be placed near the vcc and gnd pins. a mlcc between 1 f and 4.7 f is typically used. undervoltage lockout drvh and drvl are low until vcc reaches the vcc uvlo threshold, typically 4.35 v. once vcc reaches this threshold, the pwm signal will control drvh and drvl. there is a 200 mv hysteresis on vcc uvlo. there are pull?down resistors on drvh, drvl and sw to prevent the gates of the mosfets from accumulating enough charge to turn on when the driver is powered off. three?state en input placing en into a logic?high and logic?low will turn the driver on and off, respectively, as long as vcc is greater than the uvlo threshold. the en threshold limits are specified in the electrical characteristics table in this datasheet. setting the voltage on en to a mid?state level will pull both drvh and drvl low. setting en to the mid?state level can be used for body diode braking to quickly reduce the inductor current. by turning the ls fet off and having the current conduct through the ls fet body diode, the voltage at the switch node will be at a greater negative potential compared to having the ls fet on. this greater negative potential on switch node allows there to be a greater voltage across the output inductor, since the opposite terminal of the inductor is connected to the converter output voltage. the larger voltage across the inductor causes there to be a greater inductor current slew rate, allowing the current to decrease at a faster rate. three?state pwm input switching pwm between logic?high and logic?low states will allow the driver to operate in continuous conduction mode as long as vcc is greater than the uvlo threshold and en is high. the threshold limits are specified in the electrical characteristics table in this datasheet. refer to figure 21 for the gate timing diagrams and table 1 for the en/pwm logic table. when pwm is set above pwm hi , drvl will first turn off after a propagation delay of tpdl drvl . to ensure non?overlap between drvl and drvh, there is a delay of tpdh drvh from the time drvl falls to 1 v, before drvh is allowed to turn on. when pwm falls below pwm lo , drvh will first turn off after a propagation delay of tpdl drvh . to ensure non?overlap between drvh and drvl, there is a delay of tpdh drvl from the time drvh ? sw falls to 1 v, before drvl is allowed to turn on. when pwm enters the mid?state voltage range, drvl goes high after the non?overlap delay, and stays high for the duration of the zcd blanking + debounce timers. once these timers expire, sw is monitored for zero current detection and pulls drvl low once zero current is detected. thermal considerations as power in the NCP81158 increases, it might become necessary to provide some thermal relief. the maximum power dissipation supported by the device is dependent upon board design and layout. mounting pad configuration on the pcb, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. when the NCP81158 has good thermal conductivity through the pcb, the junction temperature will be relatively low with high power applications. the maximum dissipation the NCP81158 can handle is given by: p d(max) t j(max) t a r ja (eq. 1) since t j is not recommended to exceed 150 c, the NCP81158, soldered on to a 645 mm 2 copper area, using 1 oz. copper and fr4, can dissipate up to 1.05 w when the ambient temperature (t a ) is 25 c. the power dissipated by the NCP81158 can be calculated from the following equation: p d vcc n hs qg hs
n ls qg ls f
i standby (eq. 2) where n hs and n ls are the number of high?side and low?side fets, respectively, qg hs and qg ls are the gate charges of the high?side and low?side fets, respectively and f is the switching frequency of the converter.
NCP81158 www. onsemi.com 8 package dimensions ??? ??? ??? case 506bj?01 issue o *for additional information on our pb?free strategy and solderin g details, please download the on semiconductor soldering an d mounting techniques reference manual, solderrm/d. soldermask defined pin 1 reference a b c 0.10 2x 2x top view d e c 0.10 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. e2 bottom view b 0.10 8x l 14 0.05 c ab c d2 e k 85 8x 8x (a3) c c 0.05 8x c 0.05 side view a1 a seating plane dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.64 1.84 e 3.00 bsc e2 1.35 1.55 e 0.50 bsc k 0.20 ??? l 0.30 0.50 note 3 l detail a optional construction l1 detail a 0.00 0.03 note 4 detail b 3.30 8x dimension: millimeters 0.63 1.55 1.85 0.50 pitch 8x 0.35 mounting footprint detail a on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP81158/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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