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e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 features t wo independe nt operating channels device parameters comply with psi5-p10p-500/3l (psi5 spec 1.3) applicable for parallel and universal mode (standard) as well, as daisy chain mode (increased) channel output short circuit protected against 40v and gnd. channel output short circuit protected against every other channel. current detection with adapted current threshold data manchester coded operation with supply voltages of 5v and 3.3v typical spi interface over current switch off for every channel temperat ure switch off for every channel general description the circuit was developed to manage the connection and communication between a microcontroller unit (mcu) and up to six sensor satellites. it can be applied for example in a vehicle passenger restraint system. the device provide two independently operating channels. every channel manages the communication with a maximum of three sensor satellites. each channel supplies the connected sensor devices with a regulated dc voltage, which is derived from an external source. the sensor data are extracted by measuring the current, modulated by the connected sensor devices, supplied by the regulator and communicated to the mcu via spi interface. the current threshold is adapted to the quiescent current of the system. the data bits are coded using a manchester format. the device operates with an external 4mhz/8mhz clock. typical application elmos semiconductor ag data sheet 1 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. 981.07 mcu spi sensor1 sensor2 sensor3 gnd satfd1 4 sensor1 sensor2 sensor3 gnd satfd2 sat_sync
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 1 package 1.1 package pinout qfn20l5 (lead less package 5x5 20 leads) the device package follows jedec specification mo-220-k (variation vhhc-2). figure 1.1-1 package pinout elmos semiconductor ag data sheet 2 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. satfd1 v s y n c vcc agnd1 dgnd satfd2 vbus r e s e t b c l k miso mosi sck c s b t e s t s a t _ s y n c 1 a g n d 2 v 3 _ 3 t e s t b u s r e x t
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 1.2 pin function description pin no. name description 1 vbus supply voltage bus 2 n.c. not connected to die 3 satfd1 satellite channel feed 1 4 satfd2 satellite channel feed 2 5 agnd1 analogue ground 6 test test pin, connect to gnd 7 sat_sync sync pulse trigger input 8 resetb reset input, active low 9 clk system clock input 10 csb chip select input for spi 11 sck master out slave in, spi clock input 12 mosi master out slave in, spi data input 13 miso master in slave out, spi data output 14 dgnd digital ground 15 vcc input supply voltage, can be 5v or 3.3v. has to be be connected to v3_3 in case of 3.3v input voltage. (b uffer cap higher than 22nf recommended) 16 v3_3 internal 3.3v regulator output: - in case vcc = 5.0v: 47nf buffer cap recommended (22nf min) - in case vcc = 3.3v: v3_3 to be shorted to vcc 17 testbus output analogue test bus, do not connect 18 rext external resistor for reference current 19 agnd2 analogue ground 20 vsync sync supply input backside: exposed die pad connected to agnd1 / agnd2 via bulk elmos semiconductor ag data sheet 3 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 2 block diagram figure 2-1 block diagram elmos semiconductor ag data sheet 4 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. satfd1 satfd2 miso mosi sck csb band gap and bias 3.3v regulator decoder logic and spi vsync vcc agnd2 dgnd sync-pulse control and discharge regulator data comparator adaptive threshold temp. shut-off sync-pulse control and discharge regulator data comparator adaptive threshold temp. shut-off vbus resetb clk test sat_sync rext testbus agnd1 v3_3
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 3 operation conditions 3.1 absolute maximum ratings operating the device beyond these limits may cause permanent damage. no. parameter condition symbol min. max. unit 1 supply voltage sync pulse vsync -0.3 36 v 2 voltage supply bus vbus -0.3 36 v 3 voltage of satellite channel feed 1-2 continuous vsatfd1-2 -0.3 28 v 4 voltage of satellite channel feed 1-2 t<500ms vsatfd1-2 -1 40 v 5 input voltage mosi, csb, sck, miso sat_sync, clk, resetb, test, testbus, rext vmosi, vcsb, vsck, vmiso vsat_sync, vclk, vresetb, vtest, vtestbus, vrext -0,3 vcc+0.3v v 6 input voltage v3_3 -0.3 3.8 v 7 input voltage vcc vcc -0.3 6 v 8 junction temperature t j 150 c 9 thermal resistance (junctionCambient) qfn20l5 r tja 23 1) k/w 10 operating temperature ambient t amb -40 125 c 11 storage temperature t stg -55 150 c all voltages referred to dgnd, agnd1, agnd2, all gnd-pins have to be shorted 1) value is based on method according to jedec standard jesd-51-5 elmos semiconductor ag data sheet 5 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 3.2 recommended operating conditions parameters are guaranteed within the range of operating conditions unless otherwise specified. all voltages are referred to gnd, currents are specified positive, when flowing into the node, negative when flowing out of the node. 3.2.1 operating conditions parameter symbol min max unit bus voltage (normal mode) v sat_bus_sup 8.5 25 v bus voltage (increased mode) v sat_bus_sup 10 25 v sync pulse voltage (standard) v sat_sync_sup_std 14 35 v sync pulse voltage (increased) v sat_sync_sup_inc 15.5 35 v oscillator frequency clk 3.92/7.84 4.08/8.16 mhz vcc voltage (5v) vcc_5v 4,5 5.5 v vcc voltage (3v) vcc_3v 3 3.6 v capacitance v3_3 c v3_3 33 330 n f sat_sync duration time t sat_sync_duration 5 - s external resistor rext ? rext 9.7 10.3 kohm rext determines the short circuit currents and the data current threshold. all related parameters are ? specified for rext=10k+/-3%. a variation of +/-3% is assumed over temperature/ lifetime. this variation will shift the above mentioned parameters accordingly. elmos semiconductor ag data sheet 6 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 3.2.2 operating conditions for synchronous parallel bus m ode (psi5-p10p-500/3l) parameter symbol min. typ. max. unit. ecu bus capacitance ce+ceopt 15 35 nf ecu resistance re 5 12 ecu bus capacitance ceopt 0 22 - nf satellite capacitance cs 9 - 24 nf total bus capacitance ce+csx (x=1...3) 24 - 107 nf ecu connector resistance rce - 0.2 - satellite connector resistance rcs - 0.2 - single wire resistance r w /2 - 0.5 - overall wire resistance incl. wire 2*(rce+rw/2+rcs) - - 2.5 wire inductance lw - - 8.7 h wire capacitance cw - - 600 pf sync signal period t sync 495 500 505 s satellite bit rate functional range f sat_func =1/t bit 119 125 132 khz satellite bit duty cycle dc 47 50 53 % slot 1 start time (see figure 5.1-6) t slot1_start 44 - - s slot 1 end time 170.8 s gap time (see f igure 5.1-6 ) t gap> t bit 8,4 - - s slot 2 start time (see f igure 5.1-6 ) t slot2_start 177 181.3 - s slot 2 end time 318.4 s slot 3 start time (see f igure 5.1-6 ) t slot3_start 322 328.9 - s slot 3 end time (see f igure 5.1-6 ) t slot3_end - - 492 s satellite quiescent current range i sat_q_range -35 - -4 ma satellite modulation current range i sat_mod_range -30 -26 -22 ma ce: ecu connector capacitance, ce+ceopt >22nf needed to ensure system-level esd performance, re: series resistor, improves damping in case of long wires and large inductive loads, ? ceopt: capacitor at ic-pin, removes oscillations in short circuit conditions, min. and max. values for ce, re, ceopt needed to be in accordance to psi-5 specification. elmos semiconductor ag data sheet 7 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 figure 3.2-1 application for synchronous parallel bus mode (psi5-p10p-500/3l) elmos semiconductor ag data sheet 8 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. 981.07 rce wire 1 i sink cs sensor 1 vss wire 2 wire 3 rce rcs rcs rce rce rce rce rcs rcs rcs rcs i sink cs sensor 2 vss i sink cs sensor 3 vss re ce v sat_out_x ceopt
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 figure 3.2-2 wire substitution circuit figure 3.2-3 sensor substitution circuit elmos semiconductor ag data sheet 9 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. r w /2 r w /2 l w /2 l w /2 c w current sink cs1 rs1 cs2
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 4 detailed electrical specification 4.1 dc parameter 4.1.1 analogue voltage power supply and biasing circuit no. parameter symbol condition min. typ. max. unit 1 quiescent current consumption isup quies. i sat_bus_q +i sat_sync_q + i sat_vcc_q interfaces off - 3 4 ma 2 current consumption operating isup op. i sat_bus +i sat_sync + i sat_vcc interfaces on - 7 10 ma 3 bus quiescent current consumption i sat_bus_q interfaces off - 1 2 ma 4 bus current consumption operating i sat_bus without load - 3.5 6 ma 5 bus current consumption operating i sat_bus with load, 0 e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 4.1.2 digital voltage power supply no. parameter symbol condition min. typ. max. unit 1 quiescent current consumption i sat_vcc_q no clk - 1 ma 2 logic supply operating current i sat_vcc clk=4mhz/8mhz - 2 ma 4.1.3 channel interface parameter no. parameter symbol condition min. typ. max. unit 1 interface dc output voltage (standard ) (programmable via spi) v sat_out_x i sat_fdx 65ma, 6 6,5 7 v 2 interface dc output voltage (increased) (programmable via spi) v sat_out_x i sat_fdx 65ma, vbus min =10v 7,5 8 8,5 v 3 interface dc output voltage in disabled state v sat_out_x_dis - 0,5 v 4 interface ripple rejection from v bus_sup psrr v bus_sup 50khz f ripple 280khz, i sat_fdx <35ma ceopt=22nf, re=5ohm, ce=2.2nf, cs1=2nf, rs=5ohm, cs2=15nf 23 - db 5 interface ripple rejection from v bus_sup psrr v bus_sup 280khz f ripple 560khz i sat_fdx <35ma 20 - db 6 interface ripple voltage due to satellite current modulation v sat_ripple re=5ohm, ce=35nf, l=8,7h, iq=4ma, cs1 =2nf, rs=5ohm, cs2=15nf 260 mv pp 7 rsu regulator output current range i sat ? -65 0 ma 8 rsu output current limitation i sat_ocl rext=10kohm +/-3% -130 -110 -85 ma 9 satellite quiescent current measurement range i sat_q_range rext=10kohm +/-3% ? -37 -2 ma 10 satellite quiescent current measurement accuracy i sat_q_acc rext=10kohm +/-3% -1 -0,4 ma 11 data comparator threshold current range i sat_th_range rext=10kohm +/-3% -54,5 -2 ma 12 data comparator threshold i sat_th_r data current rising rext=10kohm +/-3% -17,5 -14,5 -11,5 ma elmos semiconductor ag data sheet 11 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 no. parameter symbol condition min. typ. max. unit 13 data comparator threshold i sat_th_f data current falling rext=10kohm +/-3% -14,5 -11,5 -8,5 ma 14 data detection current hysteresis i sat_th_hyst rext=10kohm +/-3% -4 -3 -2 ma 15 satfdx pull down current limit (discharge current of the line capacitor) i sat_pd rext=10kohm +/-3% 35 55 75 ma not tested in production interface will be switched off, if the quiescent current exceeds the upper limit, debouncing some 10ms due to ? the settling speed of the adaptive threshold, he bit will be set, see also 5.2.5.5 for all switch-off conditions 4.1.4 sync pulse generation no. parameter symbol condition min. typ. max. unit 1 sync pulse absolute voltage (standard) v sat_out_x_max 10,5 11,5 12,5 v 2 sync pulse absolute voltage (increased) v sat_out_x_max 12 13 14 v 3 sync signal sustain voltage see figure 5.1-3 v sat_out_x + 4.3v v sat_out_x + 4.9v v sat_out_x + 5.5v 4.1.5 reference voltage rext no. parameter symbol condition min. typ. max. unit 1 reference voltage vref rext=10kohm 1,18 1.23 1,3 v 2 short circuit current rext=0 -1 -0,5 ma the following parameters are directly depending on rext: 4.1.3.8-15, i.e. pull up current limitation, pull down current limitation, data threshold and hysteresis, and quiescent current measurement range 4.1.6 digital inputs and outputs spi no. parameter symbol condition min. typ. max. unit 1 input threshold low mosi, csb, sck, v thmosi_l v thcsb_l v thsck_l 0.8 - - v 2 input threshold high mosi, csb, sck, v thmosi_h v thcsb_h v thsck_h - - 2.0 v 3 output voltage low miso v outmiso_l iout=0.5ma - - 0.4 v 4 output voltage high miso v outmiso_h iout=-0.2ma vcc-0.4 - - v 5 pull-up-resistor csb 100 150 200 k w elmos semiconductor ag data sheet 12 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 4.1.7 external oscilla tor (clk) no. parameter symbol condition min. typ. max. unit 1 input threshold low clk v thclk_l 0.8 - - v 2 input threshold high clk v thclk_h - - 2.0 v 3 pull-down-resistor clk 100 150 200 k w 4.1.8 power on reset the power-on-reset is only related to v3_3. no. parameter symbol condition min. typ. max. unit 1 reset threshold high v por_r v3_3 rising, 2.85 v 2 reset threshold low v por_f v3_3 falling, 2.4 v 3 hysteresis v por_hyst 0.05 v not tested in production vpor_f/r is defined for vbus/vsync down to 0v. vcc=v3_ (in v5 and 3.3v supply mode) 4.1.9 external reset no. parameter symbol condition min. typ. max. unit 1 input threshold low resetb v thresetb_l 0.8 - - v 2 input threshold high resetb v thresetb_h - - 2.0 v 3 pull-down-resistor resetb 100 150 200 k w 4.1.10 trigger signal for sync pulse no. parameter symbol condition min. typ. max. unit 1 input threshold low sat_sync v thsync_l 0.8 - - v 2 input threshold high sat_sync v thsync_h - - 2.0 v 3 pull-down-resistor sat_sync 100 150 200 k w elmos semiconductor ag data sheet 13 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 4.1.11 rext check no. parameter symbol condition min. typ. max. unit 1 resistor at pin rext too low rext 1 k 2 resistor at pin rext too high rext 30 k hardware error bit will be set if rext is lower 1kohm or larger 30kohm, the interfaces will be switched off 4.1.12 vsatfdx over-voltage protection no. parameter symbol condition min. typ. max. unit 1 voltage at pin satfdx out of range v sat_out_x_oor_std standard mode 7.5 9.5 v 2 voltage at pin satfdx out of range v sat_out_x_oor_inc increased mode 9 11 v 3 pull-down current at satfd too large 35 70 ma hardware error bit is set if the voltage at satfdx is above the specified values. the hardware error bit is also set if the pull-down current is above the specified value. the affected interfaces will be switched off. will be activated at 0.5v above the output voltage satfdx. after a debouncing time of 512s, the channel will be switched off (see table in chapter 5.2.5.5 4.1.13 supply_check no. parameter symbol condition min. typ. max. unit 1 vbus v vbus_too_low 6 7 8.3 v 2 vsync v vsync_too_low 10 11 12 v hardware error bit will be set if the voltages are below the specified values. interfaces will be switched off elmos semiconductor ag data sheet 14 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 4.2 ac parameter 4.2.1 channel interface parameters no. parameter symbol condition min. typ. max. unit 1a interface (high/low- side) over current start up delay t sat_oc_sdel_st standard mode (sv=0) ? 5.12 -t clk 5.12 5.12 +t clk m s 1b interface (high/low side) over current start up delay t sat_oc_sdel_in increased mode (sv=1) ? 10.24 -t clk 10.24 10.24 +t clk ms 2a interface high side over current shut down delay t sat_oc_odel_st standard mode (sv=0) ? short to gnd 512 -t clk 512 512 +t clk s 2b interface high side over current shut down delay t sat_oc_odel_in increased mode (sv=1) ? short to gnd 10.24 -t clk 10.24 10.24 +t clk ms 3 interface low side over current shut down delay t sat_oc_odel_ls short to battery ? 512 -t clk 512 512 +t clk s 4 data detection delay difference between negative and positive edge t sat_th_del_delta ? - - 250 ns 5 sync pulse delay first slot t sat_sync_delay see figure 5.1-6 , 2.0 - 4 s 6 sync pulse jitter t jitter see figure 5.1-6 , ? ? 0 - 250 ns 7 rext out of range debouncing t oor_deb - 512 - s 8a vbus/vsync too low delay after power-on reset, depends on internal clock f osc_ (see 4.2.4.1) 0.57 0.85 2.0 m s 8b vbus/vsync too low delay interface operating, depends on external clock clk (see 3.2.1.8) - 32 - s the parameter t sat_sync_delay will be measured from the rising edge of the sat_sync signal (t sat_sync_start ) until the voltage at satfdx is equal vt0 (vt0=vsatfdx+0.5v). see figures 5.1-4 and 5.1-6 . ? not tested in production ? t clk = 250 ns plus external clock tolerance elmos semiconductor ag data sheet 15 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 4.2.2 sync pulse generation no. parameter symbol condition min. typ. max. unit 1 sync pulse rise time with resistive load t sat_sync_ris e transition from 10% to 90% of pulse amplitude, c=14.7nf, rload=400 3 4 6 s 2 sync slope slew rate rise t sl_rise see figure 5.1-4 24nf < c bus, max <107nf, 4ma e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 4.2.4 general spi operating conditions no. parameter symbol condition min. typ. max. unit 1 spi clock (sck) operating frequency f sck ? - 8.1 mhz 2 spi clock (sck) period t sck ? 123,4 - ns 3 clock (sck) high time t sckh ? 47,5 - ns 4 clock (sck) low time t sckl ? 47,5 - ns 5 clock (sck) fall time t fall ? 0 13 ns 6 clock (sck) rise time t rise ? 0 13 ns 7 data input setup time t setup ? 12.5 - ns 8 data input hold time t hold ? 30 - ns 9 enable (csb) lead time t lead ? 61,8 - ns 10 enable (csb) lag time t csb_lag ? 61,8 - ns 11 sequential transfer delay t td ? 371,1 - n s 12 capacitive load at spi pins miso c miso ? - 80 pf ? these timings are given by the mcu. the ic`s spi circuit is designed to be fully operational under these worse case timings. spi functionality test at wc timings is done during production test. 4.2.5 internal oscillator no. parameter symbol condition min. typ. max. unit 1 oscillator frequency f osc 0,5 1,2 1,8 mhz 4.2.6 over temperature switch off no. parameter symbol condition min. typ. max. unit 1 switch off threshold t off ?,? 170 o c 2 switch on threshold t on ? 160 o c 3 hysteresis ? 10 o c ? when the temperature switch off threshold of the affected channel, the hardware error bit will be set and the corresponding interface will be switched off. ? not tested in production elmos semiconductor ag data sheet 17 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5 functional description 5.1 rsu interface figure 5.1-1 satellite interface block diagram 5.1.1 functional description each of the four rsu interfaces provides a regulated voltage to the connected satellite sensor. the interfaces are short circuit protected to 40v and gnd. the four interfaces operate independently. distortion on one channel will not effect the operation of the others. the rsu interfaces can be activated and deactivated independently via an spi command. because enabling a channel results an in-rush current on the line, any time a channel is activated, a startup delay counter is started. during this entire delay time t sat_oc_sdel the manchester decoder, the sync pulse generation and the over-current detection for the particular channel are disabled. when the startup delay counter expires, the channel enters its normal operating mode. 5.1.2 voltage regulation the voltage regulator provides 2 different voltage settings: in the standard mode, the regulator provides 6.5v. this mode is intended to be used for universal ana parallel configuration. in increased mode the regulator provides an 8v supply. this mode is intended to be used for daisy-chain configuration. the selection is done by the spi-command line_supply_mode. elmos semiconductor ag data sheet 18 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. sync-pulse control and discharge regulator data comparator adaptive threshold temp. shut-off vsync vbus satfdx
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.1.3 current comparator the satellite sensors modulate the current through the rsu line, in order to realise a manchester coded data transmission. the low level of the current is represented by the quiescent current i sat_q_range of the sensors, while a high level is created by switching on a current sink to the line, which increases the current to i sat_op (see figure 5.1- 2 ). a current transition in the middle of the bit time represents the logical value of the transferred data. a high current-low current transition stand for a logical '1', a low current-high current transition for a logical '0'. this current can be detected by measuring the voltage drop via an internal shunt. the current threshold is automatically adapted to the quiescent current of the sensors in each rsu line. figure 5.1-2 current during operation elmos semiconductor ag data sheet 19 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. i sat_op t i sat i sat_q_range bit1 0 bit2 1 bit3 1 i i sat_th t bit
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.1.4 sync pulse generation each data transmission is initiated by a synchronisation signal generated by the device. the mcu will provide a trigger signal sat_sync, which initiates the device to rise the voltage on the bus from typically 6.5v to typically 11.5 v (resp. 8v to 13v) slew rate controlled for a time of typically 23 s. the figure 5.1-3 shows the timing of the sync pulse generation. figure 5.1-3 synchronisation pulse timing parameter symbol condition min. typ. max. unit sync signal start t 0 @v t0 =0.5v 0 s sync signal sustain start t 2 @v t2 =3.5v 7 s sync signal sustain time t 3 16 s discharge time limit t 4 35 s sync rise time t sync_rise 4.6 s elmos semiconductor ag data sheet 20 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. t v sat_outx phase1 sync start phase2 sync slope phase3 sync sustain phase4 sync discharge v sat_out_x_max upper boundary lower boundary t4 t3 t2 t0 v t2 v trig v t0 v sat_out_x t trig
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.1.5 current limitation the circuit provides an over current protection of the rsu interfaces. when the current measured by the current comparator exceeds typically 100 ma, the error flag he is set and the voltage will be turned off after a delay t sat_oc_del_xx . to allow in-rush current when the channel is turned on the error condition is masked for t sat_oc_sdel_xx . during this delay, the he-bit is not set. (xx refers to supply mode: standard or increased: refer to 4.2.1-1a,1b, 2a, 2b) 5.1.6 over voltage protection the rsu interfaces are voltage protected against 40v. when the output voltage increases to 0.5v above the nominal voltage, a pull down current is activated ( see 4. 1.12.3) . when the current reaches the specified limit the error flag oe is set and the voltage will be turned off after a delay t sat_oc_odel_ls . if a short to v+ occurs prior to the channel activation the error condition is masked for a delay t sat_oc_sdel_xx ). during this delay the oe bit is not set. (xx refers to supply-mode: standard or increased: refer to 4.2.1, 1a, .1b, 3) 5.1.7 synchronous parallel bus mode (psi5-p10p-500/3l) in parallel bus mode application, the sensors are connected in parallel to the bus line like shown in figure 5.1-4 . it is possible to connect up to three sensor to each channel of the 981.07. the sync cycle time is 500 s with a data transmission rate of 125kbit/s. the synchronisation pulse for the satellite channel feeds satfd1-satfd2 can be activated by mcu via the sat_sync pin of the device. when a rising edge is detected, the 981.07 outputs sync pulses on channels satfd1-satfd2 in sequence to reduce the average current inrush to the satellites as shown in figure 5.1-5 . the satellites can transmit from one to three messages per sync pulse received. the figure 5.1-6 shows the timing for one channel. figure 5.1-4 synchronous parallel bus mode configuration (psi5-p10p-500/3l) in order to avoid emc problems, the synchronisations pulses of the satellites will not be performed at the same time, but consecutively like it is shown in the figure below. elmos semiconductor ag data sheet 21 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. v sat_out_op t gnd s2 s1 s3 mcu 981.07 spi v sat_out_x s3 v sat_out_sync v sat_out_x t sync s1 s2 sat_sync
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 figure 5.1-5 satellite synchronisation pulses elmos semiconductor ag data sheet 22 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. satfd 2 satfd1 t t t 0 t sat_syn c t sync_del t sync_rise t sat_sync_delay t sat_sync_durati on t jitter v t0 t sat_sync_start v t0 v t2
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 figure 5.1-6 timing for synchronous parallel bus mode (psi5-p10p-500/3l) 5.1.8 daisy chain bus mode (psi5-d10p-500/3l) the device is able to operate in daisy chain bus configuration . in this configuration the sensors are connected in series (see figure 6.3/4). the chain contains switches, which can be used for auto addressing of the sensors. because of a possible voltage drop, via the switches, it is recommended to program the device output voltage to 8v. 5.1.9 bidirectional communication in the above mentioned operating modes, it is possible to communicate, not only from sensor to ecu, but also from ecu to sensor. the communication from mcu to rsu is made using a specifiec sync-pattern (please refer to psi-5 spec.) the sync-pattern is made using the spi-command sync_enable which allows masking the sync pulse independently on each satfd output. elmos semiconductor ag data sheet 23 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. v sat_out_x t sync t t slot1 start t slot3 end t slot2 start t slot3 start v sat_out_x_sync t slot t gap t emc
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2 control logic 5.2.1 block diagram figure 5.2-1 block diagram: control logic elmos semiconductor ag data sheet 24 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. global controller test logic reset logic spi manchester decoder register a register b register c channel configuration and status registers channel 2 channel 1 rxdx_int (x=1,2) channel controller satfdx_int (x=1,2) csb sck mosi miso
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.2 functional description the mcu a nd the 981.0 7 are communicating over an spi bus in a master-slave operation mode. the mcu acts always as master and transmits commands over the mosi (master out slave in) line. the 981.0 7 acts always as slave and sends back status or rsu data to the mcu over the miso (master in slave out) line. 5.2.3 spi communication the data transfer between the mcu and 981.07 is done serially with a four wire system: signal description direction mosi master out slave in mcu ? 981.0 7 miso master in slave out 981.0 7 ? mcu sck serial clock mcu ? 981.0 7 csb chip select (low active) mcu ? 981.0 7 bits are transmitted simultaneously to (mosi) and from (miso) the 981.07 when csb is active (low) and each bit is synchronised by the clock sck. the responses are transferred to the mcu in a single-stage pipeline fashion, where the response for a given request is transmitted in the frame immediately following the request as shown below in figure 5.2-2 . commands received during the transmission are executed by the 981.0 7 on the rising edge of csb. only commands with 16 clock cycles are executed. each transmission starts with a falling edge on csb and ends with the rising edge. during the transmission command and data shift are controlled by sck and csb according to the following rules: ? frame size is 16 bits ? commands and data are shifted msb first, lsb last ? each bit is sampled on the rising edge of sck (mosi line) ? each rsu-data-/status-bits is shifted out on the falling edge of sck (miso line) ? miso becomes active during csb='0' and is tristate during csb='1' incoming commands are validated on the rising edge of csb and executed in case that 16 clock cycles are counted during the transmission, glitches at csb do not lead to a re-execution of the previous command. the spi is reset in case of power-on-reset or external reset. the response on miso to the first command after external reset or internal reset is a non-sensor data error response with re bit is set, and the du bit is cleared (re=1, du=0). figure 5.2-2 : spi response latency elmos semiconductor ag data sheet 25 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.4 spi timing figure 5.2-3 shows the spi timing diagram. figure 5.2-3 : spi timing diagram 5.2.5 spi message format the 981.07 supports two message types: a sensor related message type which is used to retrieve data from the connected sensors and another message type for non sensor requests like configuration and control information. the message type is defined by the bit 13 (sen) in the mosi request frame. the sequence identifier (sqx) bits are only used by the mcu for controlling purposes. the transmitted sqx bits are sent back by miso during the following spi-protocol. elmos semiconductor ag data sheet 26 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. t csb t sck t miso t mosi 90% 10% 10% 90% t lead t sckh t sckl msb lsb t sck t a t v t hi t su 90% 10% 90% 10% t fall t rise t miso_l ag t td t csb_lag t dis msb lsb
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.5.1 spi sensor data request / response format 5.2.5.1.1 sensor data mosi request msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sq1 sq0 sen sq2 0 0 0 0 0 0 0 0 lc3 lc2 lc1 lc0 5.2.5.1.2 sensor data miso response msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sq2 sq1 sq0 p st1 st0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 status decode 0 0 unused 0 1 sensor data 1 0 reserved 1 1 es1 es0 exception data exception status code slave error status 0 0 0 0 oe nd cnc he me de reserved 0 1 x x x x x x x x reserved 1 0 x x x x x x x x reserved 1 1 x x x x x x x x elmos semiconductor ag data sheet 27 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.5.2 spi sensor data request / response bit definitions 5.2.5.2.1 sensor data request mosi bit definition name bit position definition sq2:sq0 15,14,12 sequence identifier-used for synchronising samples sen 13 sensor bit, defines request as sensor data request or non sensor data request lc3:lc0 3:0 local channel select 5.2.5.2.2 sensor data response miso bit definition name bit position definition sq2:sq0 15:13 sequence identifier-used for synchronising samples p 12 parity, ensures odd parity for bits 15:0 of miso st1:st0 11:10 status - identifies contents in d9:d0 of miso (sensor data, self test data, error etc.) es1:es0 9:8 exception status C identifies contents of exception data (receiver/ on board sensor, error status or satellite error) oe 5 over current error, over current of low side driver (short to battery) nd 4 no data (channel specific): sensor data not available cnc 3 condition not correct for operation (channel specific): as defined elsewhere request cannot be fulfilled because channel is off, or in the wrong mode etc. he 2 hardware error in slave (channel/channel pair specific): caused by hardware errors defined elsewhere, such as over temperature, over current of high side driver (short to gnd), reference out of range etc. me 1 manchester error (channel specific): incorrect number of bits, timing violation etc. in bit stream de 0 data error (channel specific): parity error in manchester data d9:d0 9:0 sensor data, for st1:st0=01 elmos semiconductor ag data sheet 28 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.5.3 spi non sensor data request / response 5.2.5.3.1 non sensor data mosi request msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 op1 op0 sen a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 x x x x x x x x x x x x x 2 0 1 0 write address write data 3 1 0 0 read address x x x x x x x x 4 1 1 0 x x x x x x x x x x x x x 1 reserved 2 write 3 read 4 test 5.2.5.3.2 non sensor data miso response msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 op1 op0 p st1 st0 es1 es0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 p 1 1 1 0 0 0 0 0 0 se re du 2 0 1 p 1 1 1 0 slave status 3 1 0 p 1 1 1 0 read data 4 1 1 p 1 1 1 0 x x x x x x x x 1 error response 2 write response 3 read response 4 test response elmos semiconductor ag data sheet 29 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.5.4 logical channel assignment the logical channel field is used to address one of the six possible satellites connected to the two physical channels of the 981.0 7 . each physical channel can support up to three satellites. each of these three satellites is assigned to a separate time slot on the bus. each time slot has a appropriate sensor data register (a, b, c). the 981.0 7 response to requests for undefined physical channels with an error message with the cnc bit is set (cnc=1). this illustrated in the table below. logical channel lc[3:0] physical channel time slot sensor data register 0000 1 1 a1 0001 1 2 b1 0010 1 3 c1 0011 undefined - - 0100 2 1 a2 0101 2 2 b2 0110 2 3 c2 other undefined - - elmos semiconductor ag data sheet 30 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.5.5 error and status bits the conditions for setting and clearing of status bits in sensor data request message are defined in the table below. bit description setting condition clearing condition channel behaviour oe over-current error satellite channel short to v+ condition ? external reset ? internal reset ? line_enable command with lex=0 (off) for the affected channel channel is deactivated nd no data ? no sensor data arrived since enabling of the channel ? second attempt to read sensor data from one logical channel, although no new sensor data has been received intermediately cleared after a new satellite data is received none cnc conditions not correct ? request for undefined channel ? request for a channel not yet turned on ? external reset ? internal reset ? requesting an activated channel none he hardware error ? satellite channel short to gnd condition ? satellite average iq too high ? channel over-temperature ? rext out of range ? clk malfunction ? vsync too low ? vbus too low ? external reset ? internal reset ? line_enable command with lex=0 (off) for the affected channel channel is deactivated me manchester error improper manchester data: ? invalid bit count ? invalid bit timing ? external reset ? internal reset ? cleared when read none de data error ? satellite data parity error ? external reset ? internal reset ? cleared when read none the next tables summarises the error handling and the error priority. elmos semiconductor ag data sheet 31 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 error logical channel activated logical channel defined, not activated undefined logical channel lc[3:0] xx11 undefined logical channel lc[3:0] 1xxx global asic he (clk, rext missing, vbus...) he cleared by clearing all lex=0 and error source disappear he cleared by clearing all lex and error source diappears cnc not possible, cnc channel he (sc to gnd ..) he cleared by clearing the corresponding lex=0 not possible, cnc not possible, cnc not possible, cnc channel oe (sc to vbat) oe cleared by clearing the corresponding lex=0 not possible, cnc not possible, cnc not possible, cnc manchester error me me cleared by spi- readout or lex off/on sequence not possible, cnc not possible, cnc not possible, cnc data error de de cleared by spi- readout or lex off/on sequence not possible, cnc not possible, cnc not possible, cnc no data nd cleared by spi- readout or lex off/on sequence cnc, cleared when lex=1 not possible, cnc not possible, cnc data received data cleared by spi- readout or lex off/on sequence not possible, cnc not possible, cnc not possible, cnc elmos semiconductor ag data sheet 32 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 the behaviour of hardware error handling is described in following table. hardware error he behaviour when device power on behaviour when line enable=1 sv=0 (standard mode) behaviour when line enable=1 sv=1 (increased/daisy chain mode) short to gnd (high side over current) mask when channel is deactivated ? mask for 5.12 ms after channel activation ? 512 us debouncing ? mask for 10.24 ms after channel activation ? 10.24 ms debouncing iq out of range (satellite quiescent current above upper limit) mask when channel is deactivated ? mask for 5.12 ms after channel activation ? no debouncing ? mask for 10.24 ms after channel activation ? no debouncing over temperature mask when channel is deactivated ? mask for 100 s after channel activation ? no debouncing ? mask for 100 s after channel activation ? no debouncing external resistor out of range mask for 1 ms ? 512 s debouncing ? 512 s debouncing no clk mask for 1 ms ? no debouncing ? no debouncing vbus/vsync too low delay mask for 1 ms ? 32 s debouncing ? 32 s debouncing the behaviour of over current error handling is described in following table. over current error oe behaviour when device power on behaviour when line enable=1 sv=0 (standard mode) behaviour when line enable=1 sv=1 (increased/daisy chain mode) short to v+ (low side over current) mask when channel is deactivated ? mask for 5.12 ms after channel activation ? 512 s debouncing ? mask for 10.24 ms after channel activation ? 512 s debouncing he and oe are reset with external or internal reset or spi_line_enable command with lex=0 (off) for the affected channel. v_sync and v_bus error can be active some seconds after power on and a he is set without any channel is activated. to activate a channel in this case first the he must be reset with the spi_line_enable command with lex=0 (off). elmos semiconductor ag data sheet 33 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.5.6 spi sensor non sensor data request / response bit definitions 5.2.5.6.1 slave command mosi bit definition name bit position definition op1:op0 14:13 opcode, defines operation ( read,write) sen 13 sensor bit, defines request as sensor data request or non sensor data request a4:a0 12:8 address, for read of write operation d7:d0 7:0 data, for write operation 5.2.5.6.2 slave responses miso bit definition name bit position definition op1:op0 14:13 opcode, identifies contents of read or write data in d7:d0. p 12 parity, ensures odd parity for bits 15:0 of miso st1:st0 11:10 status, always 11 for non sensor response es1:es0 9:8 exception status, always 10 for non sensor response d7:d0 7:0 read data / error data / status se 2 spi error, set to '1' for request (mosi) frame violations re 1 request error, set to '1' for illegal or unknown requests du 0 data unavailable, set to '1' if data for read request is not available elmos semiconductor ag data sheet 34 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.6 spi commands 5.2.6.1 sensor_data the sensor_data command is used to sample sensor data from the 981.07, and is the only command which uses the sensor data request/response format. the sampling moment is the first rising sck edge within the response frame. if the sensor data within the manchester decoder changes at the same time then this sampling is repeated at the second rising sck edge. details of this command are defined in section spi sensor data request / response format. 5.2.6.2 non_sensor_data the non_sensor_data command is used write configuration data into the 981.07 configuration registers and read back status information. details of this command are defined in section spi non sensor data request / response format. 5.2.6.2.1 line_enable the line_enable command is used to activate or deactivate the satellite receiver channels individually. the command is latched until a subsequent spi update, reset, or any condition which deactivates the channel, such as thermal, or over current shutdown. the response indicates the current state ( ) of the line activation and the over temperature status for each channel. by default all satellite channels are disabled. write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi 0 1 0 0 0 0 1 1 x x x x x x le2 le1 miso 0 0 1 p 1 1 1 0 0 0 ot2 ot1 0 0 le2 le1 read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi 1 0 0 0 0 0 1 1 x x x x x x x x miso 0 1 0 p 1 1 1 0 0 0 ot2 ot1 0 0 le2 le1 otx over temperature shutdown indicator 0 no over temperature shut down on channel x 1 over temperature shut down on channel x lex line enable 0 channel x off (default) 1 channel x on at the begin of the response. elmos semiconductor ag data sheet 35 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.6.2.2 line_supply_mode the line_supply_mode command is used to configure the satellite voltage of each channel and the frequency of the external oscillator . satellite voltages vsat_out of 6.5v or 8.0v can be adjusted . the default voltage is 6.5v. if a satellite voltage of 8v is requested the satellite voltage bit for the channel must be set. for every channel the svx bit influences some dc parameters in table fehler: referenz nicht gefunden and some ac parameters in table 4.2.1 . an external frequency of 4mhz or 8mhz can be adjusted . the default frequency is 4mhz. if an external frequency of 8mhz is requested the frequency select bit must be set. write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi 0 1 0 1 1 1 1 0 x x x f x x sv2 sv1 miso 0 0 1 p 1 1 1 0 0 0 0 f 0 0 sv2 sv1 read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi 1 0 0 1 1 1 1 0 x x x x x x x x miso 0 1 0 p 1 1 1 0 0 0 0 f 0 0 sv2 sv1 svx satellite voltage 0 vsat_out= 6.5v standard mode (default) 1 vsat_out= 8.0v increased mode (daisy chain) f frequency select 0 clk=4mhz (default) 1 clk=8mhz elmos semiconductor ag data sheet 36 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.6.2.3 sync_enable the sync_enable command is used to enable the sync pulses for the specified channels. it can be used for bidirectional communication between the mcu and the satellite sensors. the response indicates the current state ( ) of the line sync pulse enable bits for each channel. by default all sync pulses are enabled. the command is latched until a subsequent spi update, reset, or any condition which deactivates the channel, such as thermal, or over current shutdown. write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi 0 1 0 0 0 1 0 0 x x x x x x se2 se1 miso 0 0 1 p 1 1 1 0 0 0 0 0 0 0 se2 se1 read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi 1 0 0 0 0 1 0 0 x x x x x x x x miso 0 1 0 p 1 1 1 0 0 0 0 0 0 0 se2 se1 sex sync enable 0 sync pulse for channel x disable 1 sync pulse for channel x enable (default) at the begin of the response. 5.2.6.2.4 nop the nop command is used for retrieving the response from a previous command without altering anything within the rsu receiver. the response is a fixed write response with all data bits set to '0'. nop is always a write command. attempted read access to nop will result in a spi error with the re bit is set (re=1). write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi 0 1 0 1 0 1 1 1 x x x x x x x x miso 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi 1 0 0 1 0 1 1 1 x x x x x x x x miso 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 elmos semiconductor ag data sheet 37 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.6.2.5 sync_delay the sync_delay command is used to control the time delay between two consecutive rising edges of the four sync pulses. if the eight sd bits are interpreted as an unsigned integer number, then the delay between two consecutive sync pulses t sync_del can be calculated as t sync_del = 0.5*sd s the default value is sd=8 (decimal), corresponding to t sync_del = 4 s. the response indicates the current sd value. the command is latched until a subsequent spi update or reset happens. write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi 0 1 0 1 1 1 1 1 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 miso 0 0 1 p 1 1 1 0 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi 1 0 0 1 1 1 1 1 x x x x x x x x miso 0 1 0 p 1 1 1 0 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 5.2.6.2.6 grant_testmode the grant_testmode command must not be used except for elmos production test. to enter the device's test modes two conditions have to be satisfied: ? the test pin has to be pulled high. ? the grant_testmode request has to be the next spi frame that is issued. within test mode, the device provides extended functionality which is used for production test purposes. write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi 1 1 0 1 0 0 1 0 x x x x x x x x miso n.a. elmos semiconductor ag data sheet 38 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.6.3 spi failure mode 5.2.6.3.1 spi errors spi errors are defined as a condition, where the spi frame format is incorrect. when detected, the 981.0 7 response with an error response message on miso with the spi error (se) bit is set. the following conditions generate a spi error: ? incorrect number of spi sck cycles while csb is active (low). in case of zero sck cycles no error bit is set. ? sck is high at csb falling edge. 5.2.6.3.2 spi request errors spi request errors are defined as conditions where the contents of a spi request message are incorrect. when detected, the 981.07 responds with an error response message on miso with the request error (re) bit being set. the following conditions generate an spi request error: ? undefined command (incorrect address in bits [12:8]) elmos semiconductor ag data sheet 39 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.7 remote sensor decoder 5.2.7.1 functional description the remote sensor interface is a two-wire unidirectional current interface used for the connection of a remote sensing unit (rsu). the device includes four such interfaces which are fully independent on one another. 5.2.7.2 manchester code the input data is manchester 2 coded with a baud rate of 125 kbit/s (t bit = 8 m s). the rsu receiving unit of the 981.0 7 is clocked with clk or clk/2 to get a nominal sampling frequency of 4 mhz. every bit is coded by two consecutive pulses of equal length. a logical '1' is coded by a low pulse followed by a high pulse, a logical '0' is coded by a high pulse followed by a low pulse. figure 5.2-4 shows an example. example: figure 5.2-4 : manchester code elmos semiconductor ag data sheet 40 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. 0 0 1 0 1 1 0 1 1 0 1 manchester coded signal binary signal time bit time 0 0
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.2.7.3 message protocol format as shown in figure 5.2-5 each transmitted telegram consists of 2 start bits, 10 data bits and 1 parity bit. data bits are transferred with lsb first. both start bits are logical '0'. the parity is even and is calculated over data bits d0 to d9. the time per bit is 8 s and consequently the complete 13-bit data frame is transferred in 104s. figure 5.2-5 : message protocol format 5.2.7.4 manchester decoder the manchester decoder tolerates satellite communication as per psi5 specification for p10p-500/3l mode of operation. the received data bits are first stored in a receive register in order to check the consistency of the data word. depending on the time slot where the telegram is transmitted, the received data word is stored into the appropriate sensor data register (see 5.2.5.4 ). a manchester error (me) is set if two valid start bits are detected and the transmitted telegram has not exactly 13 valid bits or the bit timing is incorrect. a transmitted telegram which is not within one of the three time slots result also into a manchester error: start of transmission within end of transmission within manchester error is stored in sensor data register time slot 1 time slot 2 a time slot 2 time slot 3 b time slot 3 after time slot 3 c after time slot 3 after time slot 3 c a data error (de) is set when the parity bit is wrong. elmos semiconductor ag data sheet 41 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. x x s1 s2 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 p
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 5.3 external oscillator the received data messages are stored in data registers, which can be read out by the mcu via the spi interface. in order to realise a time base for the sampling of the satellite data, an external clock of typical 4mhz respectively 8mhz (clk) is provided to the device. in case of a disconnection of clk, the channels will be switched off. in case of disconnection of the oscillator the sensor data response is a hardware error. 5.4 power on reset the power-on reset enables the logic. the reset is only related to v3_3. the logic can operate without a supply from vbus and vsync. 5.5 over temperature switch off the circuit provides an over temperature protection independent for each channel. due to a failure like short circuit, the circuit will react as follows. when the chip temperature increases up to 170 o c, the over temperature protection will be activated and the affected satellite interface will be switched off. the temperature switch off operates independently from the external system clock (clk) and is only dependent on the internal oscillator (f osc ) . the failure mode is reported as an hardware error via spi. the hardware error bit can be cleared, by clearing the le bit in the line_enable command. the regulator can be reactivated manually by setting the le bit in the line_enable command to '1'. elmos semiconductor ag data sheet 42 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 6 application notes 6.1 recommended application circuits to ensure proper operation of the interfaces with the wiring harness and the sensors the following recommendations have to be taken into account. the regulator in the interface does not need a stabilisation capacitance to prevent instability. nevertheless external components are needed to reduce ringing at the output, especially in case of large inductors connected to the pin. figure 6.1-1 : recommended ecu-board circuitry re should be between 3.3ohms and 12ohms (5ohms are the minimum resistance conform to psi-5 specification). the resistor reduces the oscillations coming from the wiring harness. it damps the influence of the wiring inductor and leads to an, over the frequency range constant, termination resistor. the capacitor ce ensures a minimum input capacitance and is also mandatory to achieve a sufficient esd- performance. the next figure shows further possible ecu-circuits. the capacitor ceopt removes potential oscillations in short circuit conditions. if re is chosen to be less than 3.3ohms ceopt should be larger 4.7nf, with 10nf no oscillation in short circuit conditions have been observed figure 6.1-2 : further recommended ecu-board circuits elmos semiconductor ag data sheet 43 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. re ce satfdx agnd 98107 re ce re ce ceopt
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 the ecu-circuitry should be optimised for the connected wiring harness. the proposed circuits work well in case of point-to-point connection and parallel bus lines. for serial bus connections (and daisy-chain operation) the wiring harness, together with the sensor capacitors, form coupled lc-resonant circuits which can only hardly be damped by the resistor on the ecu-board. figure 6.1-3 : serial bus connection the oscillations which can occur in case of wiring harness shown in figure 6.3 can be damped by including additional series resistors in the wiring harness. figure 6.1-4 : serial bus connection with damping resistors the decoupling resistors damp the lc-resonant circuits (wire inductance + sensor capacitance). in the figure 6.4 a pair of resistors is shown. it is also possible to use only one resistor in the supply-line. the value of the resistor is about 2-4ohms. without damping the data current show oscillations at the rising and falling edge of the data current. this can lead to a disturbed communication and has to be avoided. elmos semiconductor ag data sheet 44 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. resistors for decoupling resistors for decoupling ecu sensors wire ecu sensors wire
e981.07 two channel sensor interface psi5 advance product information jul 26, 2011 7 esd and latchup 7.1 esd protection circuit 7.2 esd sensitivity classification test method 7.2.1 esd classification: human body model the esd protection circuitry is measured following aecq 100 (human body model) under following conditions: pins condition satfd1-2 vin= 3kv, r ext =1.5k , c ext =100pf others vin= 2kv, r ext =1.5k , c ext =100pf 7.2.2 system-level esd-test pins condition satfd1-2 vin= +/-4kv, 330ohm, 150pf against agnd1, 2, dgnd (all shorted) with ceopt=22nf, re=5, ce=2.2nf to gnd at satfd1,2 satfd1-2 vin= +/-8kv, 330ohm, 150pf against agnd1, 2, dgnd (all shorted) with ceopt=22nf, re=5, ce=2.2nf, to gnd at satfd1,2. an additional 33v zener diode in parallel to the output is needed. 7.3 latch-up pins condition satfd1-2, vbus, vsync, mosi, csb, sck, sat_sync, clk, resetb following jedec-78 elmos semiconductor ag data sheet 45 / 45 qm-no.: 25ds0050e.00 this document contains information on a new product. elmos semiconductor ag reserves the right to change specifications and information herein without notice.
elmos semiconductor ag warning C life support applications policy elmos semiconductor ag is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing elmos semiconductor ag products, to observe standards of safety, and to avoid situations in which malfunction or failure of an elmos semiconductor ag product could cause loss of human life, body injury or damage to property. in development your designs, please ensure that elmos semiconductor ag products are used within specified operating ranges as set forth in the most recent product specifica - tions. general disclaimer information furnished by elmos semiconductor ag is believed to be accurate and reliable. however, no responsibility is assumed by elmos semiconductor ag for its use, nor for any infringements of patents or other rights of third parties, which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of elmos semiconductor ag. elmos semiconductor ag reserves the right to make changes to this document or the products contained therein without prior notice, to improve performance, reliability, or manufac - turability . application disclaimer circuit diagrams may contain components not manufactured by elmos semiconductor ag, which are included as means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. the information in the applica - tion examples has been carefully checked and is believed to be entirely reliable. however, no responsibility is assumed for inaccuracies. fur - thermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of elmos semiconductor ag or others. contact information headquarters elmos semiconductor ag heinrich-hertz-str. 1 ? d-44227 dortmund (germany) +492317549100 : sales@elmos.de : www.elmos.de regional sales and application support office munich elmos semiconductor ag am geflgelhof 12 ? 85716 unterschlei?heim/eching +4989 3183700 sales office france elmos france sas 9/11 alle de l'arche ? la dfense ? 92671 courbevoie cedex (france) +33149971591 sales and application support office north america elmos na. inc. 32255 northwestern highway, suite 45 ? farmington hills, mi 48334 +12488653200 sales and application support office korea and japan elmos korea dongbu root building, 16-2, suite 509, ? sunae-dong, bundang-gu, seongnam-shi, kyonggi-do (korea) +82317141131 sales and application support office china elmos semiconductor technology (shanghai) co., ltd. 57-01e, lampl business centre, 57f, the exchange ? 1486 nanjing w rd. (299 tongren rd) ? jingan shanghai ? p.r.china 200040 +862161717358 sales and application support office singapore elmos semiconductor singapore pte ltd. 60 alexandra terrace ? #09-31 the comtech ? singapore 118502 +6566351141 ? elmos semiconductor ag, 2011. reproduction, in part or whole, without the prior written consent of elmos semiconductor ag, is prohibited.

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