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general description the max3632 burst-mode limiting amplifier is designedspecifically for 622mbps or 1244mbps gpon (g.984) optical line terminal (olt) receiver applications. together with the max3630/max3631 burst-mode tran- simpedance amplifiers (tias), a wide-dynamic-range burst-mode signal current (from a pin or avalanche photodiode) can be translated to a differential lvpecl output. the max3632 has an electrical input sensitivity of 4mv p-p that supports gpon class-b optical sensitivi- ty at 622mbps with a pin photodiode. an lvpecl-com-patible burst reset input ( rst ) connected to the limiting amplifier is used to control the offset correction loop ofthe max3632 as required for burst-mode operation, as well as to arm the threshold-setting circuitry of max3630/max3631 tias. the max3632 is available in a low-profile, 4mm x 4mm, 24-lead thin qfn package. it operates from a single +3.3v power supply over a -40? to +85? temperature range. applications 622mbps gpon olt receivers1244mbps gpon olt receivers features ? dc-coupled limiting amplifier for burst-modegpon applications ? operates with maxim? burst-modetransimpedance amplifier (max3630/max3631) ? lvpecl data output ? 4mv p-p input sensitivity ? lvpecl reset input ( rst ) ? lvpecl hold input for optional control modes ? 4mm x 4mm tqfn package max3632 622 mbps/1244mbps burst-mode limiting amplifier for gpon olt applications ________________________________________________________________ maxim integrated products 1 part temp range pin-package pkg code max3632etg -40 c to +85? 24 thin qfn t2444- 4 ordering information max3634* max3632 max3630/ max3631* tia +3.3v +3.3v +3.3v 4-pin to header 0.33 f in+in- out+ out- sdi+sdi- caz1 gnd caz2 v cc hold+ hold- rst+ rst- 100 50 50 cml (or lvpecl**) output olt controller v cc - 2v clock phase aligner *the max3630/max3631 and max3634 are future products.**see figure 5 for lvpecl interface. typical application circuit 19-3229; rev 0; 3/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. downloaded from: http:///
max3632 622 mbps/1244mbps burst-mode limiting amplifier for gpon olt applications 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v cc = +3.0v to +3.6v, t a = -40? to +85?. typical values at v cc = +3.3v, v in = 4mv p-p , and t a = +25?, unless otherwise noted. input (in+, in-) terminated with 100 resistors to v cc .) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. power-supply voltage (v cc ) ................................ -0.5v to +4.5v voltage at in+, in-, rst- , rst+ , hold+ , hold- , caz1, caz2 ...........................................-0.5v to (v cc + 0.5v) lvpecl output current (out+, out-) ..............................50ma continuous power dissipation (t a = +85?) derate 20.8mw/? above +85? ...............................1354mw operating junction temperature range ...........-40? to +125? storage temperature range ............................-55? to +150? lead temperature (soldering 10s) .................................+300? parameter sym b o l conditions min typ max units general specifications data rate 622, 1244 mbps power-supply current i cc (note 2) 80 100 ma low-frequency cutoff 30 khz caz leakage current 25 na power-supply noise rejection psnr f 10mhz (note 3) 24 db input specifications (in+, in-) minimum input offset tolerance (note 1) 5 mv input resistance r in differential 168 232 input sensitivity ber = 10 -10 , 2 23 -1 prbs 2 mv p-p output specifications (out+, out-) 622mbps 28 40 random jitter (notes 1, 4, 5) rj 1244mbps 18 22 ps rms 622mbps 14 30 deterministic jitter (notes 1, 4, 6) dj 1244mbps 14 30 ps p-p t a = 0? to +85? v cc - 1.81 v cc - 1.62 lvpecl output low voltage v ol terminated 50 to v cc - 2v t a = -40? to 0? v cc - 1.788 v cc - 1.588 v lvpecl output high voltage v oh terminated 50 to v cc - 2v v cc - 1.025 v cc - 0.88 v data output edge speed 20% to 80%(notes 1, 4, 5, 7) 150 265 ps downloaded from: http:///
max3632 622 mbps/1244mbps burst-mode limiting amplifier for gpon olt applications _______________________________________________________________________________________ 3 note 1: ac parameters are guaranteed by design and characterization. note 2: supply current is measured with lvpecl data outputs open. note 3: psnr is measured on the differential output signal while applying a 100mv p-p sinusoidal signal at the power supply with the input open, and the dc cancellation loop activated. note 4: input-data transition time controlled by 4th order bessel filter with f -3db = 0.75 x data rate. the deterministic jitter caused by this filter is not included in the dj specifications. note 5: measured with a repeating 0000011111 data pattern at 1244mbps. note 6: deterministic jitter is measured at the differential-output eye crossing. peak-to-peak input deterministic jitter is subtractedfrom peak-to-peak output deterministic jitter. note 7: each output (out+, out-) terminated with r load = 50 and c load = 4pf. note 8: the hold input transition time, 20% to 80%, must be less than 0.3ns for timing method 3. see figure 10. electrical characteristics (continued)(v cc = +3.0v to +3.6v, t a = -40? to +85?. typical values at v cc = +3.3v, v in = 4mv p-p , and t a = +25?, unless otherwise noted. input (in+, in-) terminated with 100 resistors to v cc .) parameter sym b o l conditions min typ max units lvpecl input specifications ( rst+ , rst- , hold+ , hold- ) (note 8) lvpecl-differential input voltage v in 200 1600 mv p-p lvpecl input common-moderange v cm v cc - 1.49 v cc - 1.32 v cc - v in /4 v lvpecl input current -150 190 ? typical operating characteristics (input signal is unfiltered, v cc = +3.3v, t a = +25?, unless otherwise specified.) supply current vs. temperature max3632 toc01 temperature ( c ) supply current (ma) 60 35 10 -15 70 80 90 100 110 120 60 -40 85 transfer function (output voltage vs. input voltage) max3632 toc02 differential input voltage (mv p-p ) differential output voltage (mv p-p ) 100 10 1 500 800 1100 1400 1700 2000 200 01 0 0 0 random jitter vs. input amplitude max3632 toc03 differential input amplitude (mv p-p ) random jitter (ps rms) 100 10 10 20 30 40 50 60 0 1 1000 467mhz input filter 933mhz input filter no input filter downloaded from: http:///
max3632 622 mbps/1244mbps burst-mode limiting amplifier for gpon olt applications 4 _______________________________________________________________________________________ typical operating characteristics (continued) (input signal is unfiltered, v cc = +3.3v, t a = +25?, unless otherwise specified.) deterministic jitter vs. input amplitude max3632 toc04 differential input amplitude (mv p-p ) deterministic jitter (ps p-p ) 100 10 10 15 20 25 30 35 40 45 5 11 0 0 0 2 7 -1 prbs + 72 cid input jitter measuredat eye crossing bit-error ratio vs. input amplitude max3632 toc05 differential input amplitude (mv p-p ) bit-error ratio 2.6 2.2 1.8 1.4 1.0e-09 1.0e-08 1.0e-07 1.0e-06 1.0e-05 1.0e-041.0e-10 1.0 3.0 1244mbps 622mbps electrical eye diagram (4mv p-p input, 622mbps) max3632 toc06 electrical eye diagram (800mv p-p input, 622mbps) max3632 toc07 electrical eye diagram (4mv p-p input, 1244mbps) max3632 toc08 electrical eye diagram (800mv p-p input, 1244mbps) max3632 toc09 reset timing diagram max3632 toc10 input data (in) reset signal (rst) common-mode reset output (in) data output (out) downloaded from: http:///
max3632 622 mbps/1244mbps burst-mode limiting amplifier for gpon olt applications _______________________________________________________________________________________ 5 pin description detailed description the max3632 burst-mode limiting amplifier is designedfor 622mbps or 1244mbps gpon olt receiver appli- cations. it operates, together with the max3630/ max3631 burst-mode transimpedance amplifiers, to convert current from a photodiode into an lvpecl out- put signal. the max3632 contains a data input stage, a gain stage, an offset correction loop, a reset and hold section, and an lvpecl output buffer. input stage the max3632 input stage provides a 200 differential termination and buffers the data input signal. using aproprietary common-mode signaling technique, the input stage of the max3632 also sends the burst-mode reset signal from the rst inputs ( rst+ , rst- ) to the max3630/max3631 tias. by using the common modeof the differential pair for the tias burst-mode reset sig- nal, the max3630/max3631 tias can be assembled into 4-pin to headers that reduce assembly costs and complexity. for proper operation of the reset signal, the max3630/max3631 data outputs (out+, out-) must be dc-coupled to the max3632 data inputs (in+, in-). pin name function 1, 6, 7, 13, 19, 24 gnd ground 2, 5, 10, 14, 17, 20, 21 v cc +3.3v supply voltage 3 in+ positive data input, common-mode reset output 4 in- negative data input, common-mode reset output 8 rst+ positive burst-mode reset input, lvpecl compatible 9 rst- negative burst-mode reset input, lvpecl compatible 11 hold+ positive offset correction loop hold input, lvpecl compatible 12 hold- negative offset correction loop hold input, lvpecl compatible 15 out- negative data output, lvpecl 16 out+ positive data output, lvpecl 18 n.c. no external connection. leave open. 22 caz2 offset correction loop capacitor connection. place a 330nf capacitor between caz1 andcaz2. 23 caz1 offset correction loop capacitor connection. place a 330nf capacitor between caz1 andcaz2. ep exposed paddle ground. must be soldered to the circuit board ground for proper thermal and electricalperformance (see exposed pad (ep) package section). max3632 200 c az in+ in- reset and hold logic / signaling input buffer gain stage caz1 caz2 offset correction output buffer out+ out- rst+ rst- hold+ hold- input stage figure 1. functional diagram downloaded from: http:///
max3632 gain stage/offset correction loop the high-bandwidth gain stage of the max3632 pro- vides approximately 64db of gain. the large gain of a limiting amplifier makes it susceptible to dc offsets in the signal path that are caused by pulse-width distor- tion of the input signal, as well as internal offsets. the offset correction loop of the max3632 cancels the inter- nal and external offsets in the signal path, which reduces the deterministic jitter at the output. reset and hold section the offset correction loop is a necessary component for proper operation of a high-gain limiting amplifier; howev- er, it introduces a low-frequency cutoff in the signal path. if the offset correction loop is not controlled, the low-fre- quency cutoff prohibits burst-mode operation. using the rst and optional hold input(s), the offset correction loop can be enabled or disabled, allowing proper opera- tion of the limiting amplifier in burst-mode applications. the lvpecl-compatible reset input ( rst ) is used to transmit a reset signal to the max3630/ max3631 tias. when the rst input transitions low, a reset signal is gen- erated by the internal logic and transmitted to themax3630/ max3631 tias as described above in the input stage section. the data input (in) must be a logic zero when rst is asserted during the guard time (figure 7). the rst signal is also used to disable (hold) the offset correction loop until the first transition is detected by thereset and hold logic, thus indicating the beginning of the next burst signal. the hold input ( hold ) may be used to provide alternative offset cancellation control modes.timing and operation of the rst and hold inputs are described in more detail in the applications information section. lvpecl output buffer the output buffer provides a high-speed lvpecl sig- nal. for burst-mode applications, each output (out+, out-) must be dc-coupled to an equivalent lvpecl termination. design procedure in and out terminations requirements the in+ and in- inputs (figure 2) of the max3632 mustbe dc-coupled to the max3630/max3631 data outputs for burst-mode operation. no external termination com- ponents are necessary between the max3632 and max3630/max3631 (see the typical applications circuit section). the proper termination for each output of the max3632 out+, out- (figure 3), is 50 to v cc - 2v. an equivalent lvpecl ter mination technique (e.g., thevenin termination) may be used as long as out+ and out- are dc-coupled to the load. for more informa- tion on pecl terminations and how to interface with other logic families, refer to maxim application note hfan- 01.0: introduction to lvds, pecl, and cml. 622 mbps/1244mbps burst-mode limiting amplifier for gpon olt applications 6 _______________________________________________________________________________________ max3632 v cc v cc v cc in+ 200 in- figure 2. simplified data input structure max3632 v cc v cc v cc v cc out+ out- figure 3. simplified data output structure downloaded from: http:///
rst and hold input termination requirements the max3632 rst and hold inputs are lvpecl com- patible and internally biased (high impedance; see figure 4). although the inputs are compatible with lvpecl signals, it is not necessary to drive the max3632 rst and hold inputs with a standard lvpecl signal. the rst and hold inputs of the max3632 operate properly as long as the specified common-mode voltageand differential voltage swings are met. figures 5 and 6 show how to connect an lvpecl or cml signals to the max3632 rst and hold inputs. for more information on interfacing a single-ended lvpeclor lvttl signal to the rst or hold input, see single- ended operation of rst and hold in the applications information section . selecting the offset-correction capacitor (c az ) the capacitor between caz1 and caz2 determines thetime constant and low-frequency cutoff (f oc ) of the off- set correction loop. to maintain stability, there must be a one decade separation between the data input fre- quency (f in ) and the low-frequency cutoff (f oc ) of the offset correction loop. for gpon systems operating at622mbps or 1244mbps, a 330nf capacitor (c az ) con- nected between pins 22 (caz2) and 23 (caz1) is rec- ommended. with this capacitor, the low-frequency cutoff of the offset correction loop is low enough (f oc < 30khz) to tolerate 72 cids within a burst signal. applications information rst and hold timing / operation the rst and hold lvpecl-compatible inputs of the max3632 provide three different modes for disabling (holding) the offset correction loop during routine opera- tions. the first mode of operation requires the single reset input, rst , which is the same signal used to create the reset signal for the max3630/ max3631 tias to arm its threshold setting circuitry. refer to the max3630/max3631 data sheet and the input stage section for additional information. for this method, illustrated infigure 7, the rst signal disables (holds) the offset cor- rection loop until the transition detector in the max3632identifies the beginning of the next burst. the burst- mode reset signal, rst , must occur entirely within the guard time interval to prevent corrupted data. the datainput (in) must be a logic zero when rst is asserted (figure 7). when operating in this mode, the hold input should be set to a valid lvpecl high (1600mv v hold+ - v hold - 200mv). if the functionality of the hold input is not used in the application, it can be con- max3632 622 mbps/1244mbps burst-mode limiting amplifier for gpon olt applications _______________________________________________________________________________________ 7 max3632 v cc v cc v cc 16k 5k 5k 24k rst+ or hold+ rst- or hold- figure 4. simplified rst and hold input structures max3632 v cc 130k 82 50 v cc 130 82 50 rst+ orhold+ rst- or hold- lvpecl source figure 5. interfacing rst / hold to differential lvpecl max3632 50 100 50 rst+ orhold+ rst- or hold- +3.3v cml source figure 6. interfacing rst / hold to differential cml downloaded from: http:///
max3632 nected to a valid lvpecl-high level using three externalresistors as shown in figure 8. the other two optional modes of burst operation use the hold input. for both methods, the hold input should be transitioned to a low prior to the end of aburst. using the hold input, the offset correction loop is held to a known good state between the end of adata burst and the burst-mode reset signal. when the hold input is transitioned high again, prior to the end of the guard time, the transition detector restarts the off-set cancellation loop at the beginning of the next burst (figure 9). when the hold input is transitioned high again after the end of the guard time, the offset correc-tion loop restarts (figure 10). this mode can be used to hold a valid offset for long periods during the ranging operations. the rst input is edge triggered and must be transi- tioned low during the guard time in all cases to ensureproper operation of the max3630/max3631 burst- mode tias. the transition time, 20% to 80%, of the sig- nal at the max3632 hold input, must be < 0.3ns for proper operation for method 3. single-ended operation of rst and hold the rst and hold inputs are designed to operate with a differential-lvpecl or -cml input signal and thisis the recommended mode of operation. however, it is possible to drive the rst and hold inputs with a sin- gle-ended lvpecl, lvttl, or lvcmos signal. 622 mbps/1244mbps burst-mode limiting amplifier for gpon olt applications 8 _______________________________________________________________________________________ input signalinternal / tia reset max3632 offset correction loop 11 00 active hold active data guard preamble data reset rst input hold input figure 7. rst timing method 1 max3632 v cc 29k 1k 6.2k hold+ hold- figure 8. asserting hold to a valid lvpecl high level downloaded from: http:///
max3632 622 mbps/1244mbps burst-mode limiting amplifier for gpon olt applications _______________________________________________________________________________________ 9 input signalinternal / tia reset max3632 offset correction loop 11 00 active hold active data guard preamble data reset rst input hold input figure 10. rst / hold timing method 3 input signalinternal / tia reset max3632 offset correction loop 11 00 active hold active data guard preamble data reset rst input hold input figure 9. rst or hold timing method 2 downloaded from: http:///
max3632 622 mbps/1244mbps burst-mode limiting amplifier for gpon olt applications 10 ______________________________________________________________________________________ to connect a single-ended lvpecl signal to rst (figure 11), connect a 130 resistor (r1) from rst+ or hold+ to v cc, and an 82 resistor (r2) from rst+ or hold+ to ground. the rst+ or hold+ pin must also be dc-coupled to the single-ended lvpecl source.connect a resistor (r3) from v cc to rst- or hold- and another resistor (r4) from rst- or hold- to ground. the parallel combination of r3 and r4 should be less than1k . choose the values of r3 and r4 to set the com- mon-mode voltage in the range defined in the electrical characteristics table. this configuration with typical val- ues is shown in figure 11.an lvttl or lvcmos signal may also be used if the transition time is fast enough. for single-ended opera- tion with an lvttl or lvcmos signal (figure 12), con- nect a 4k resistor (r6) from the rst+ or hold+ to the signal source, and a 1k resistor (r5) from rst+ or hold+ to v cc . a 1k resistor (r7) to v cc, and a 9k resistor (r8) to ground, should then be connected torst- or hold- . for typical lvttl or lvcmos specifi- cations of v cc to 2.8v for a high, and 0.4v to 0v for a low, the lvttl or lvcmos needs to source approxi- mately zero current and sink a maximum of approxi- mately 720? using this configuration. layout considerations use good high-frequency layout techniques and multi- ple-layer boards with uninterrupted ground planes to minimize emi and crosstalk. if the electrical length between the max3630/max3631 output and the max3632 input path delay is long compared to the input transition time, a controlled 200 differential-impedance transmission line should be used to interface the twodevices. a controlled-impedance transmission line of 50 single-ended (100 differential) should be used to interface the max3632 output (out+, out-) to otherdevices. the rst and hold inputs should also be con- nected to the lvpecl- or cml-signal source with a con- trolled impedance (50 single ended, 100 differential) transmission line. place the caz capacitor as close aspossible to pin 22 (caz2) and pin 23 (caz1). exposed pad (ep) package the exposed-pad on the 24-pin qfn provides a very lowthermal resistance path for heat removal from the ic. the pad is also electrical ground on the max3632 and must be soldered to the circuit board ground for proper ther- mal and electrical performance. refer to maxim application note hfan-08.1: thermal considerations for qfn and other exposed pad packages (available at www.maxim-ic.com). max3632 v cc r1 130 82 50 v cc r3 1.65k r4 2.55k rst+ orhold+ rst- or hold- single- ended lvpecl source figure 11. interfacing rst or hold to single-ended lvpecl max3632 v cc r5 1k r6 4k v cc r7 1k r8 9k rst+ orhold+ rst- or hold- lvtt / lvcmos input figure 12. interfacing rst or hold to single-ended lvttl/lvcmos downloaded from: http:///
max3632 622 mbps/1244mbps burst-mode limiting amplifier for gpon olt applications ______________________________________________________________________________________ 11 1 gnd 2 v cc 3 in+ 4 in- 5 v cc 6 gnd 18 n.c. 17 v cc 16 out+ 15 out- 14 v cc 13 gnd 7 gnd 8 9 10 v cc 11 12 rst+ rst- hold+ hold- 24 23 22 21 20 19 gndv cc caz1caz2 v cc gnd max3632 top view *the exposed pad must be connected to circuit board ground forproper thermal and electrical performance. pin configuration chip information transistor count: 1363 (1232 bipolar, 131 mos)process: sige bicmos downloaded from: http:///
max3632 622 mbps/1244mbps burst-mode limiting amplifier for gpon olt applications 12 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 24l qfn thin.eps package outline, 21-0139 2 1 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm downloaded from: http:///
max3632 622 mbps/1244mbps burst-mode limiting amplifier for gpon olt applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) package outline, 21-0139 2 2 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm downloaded from: http:///

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