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ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 1 introduction spartan?-7 fpgas are available in -2, -1, and -1l spee d grades, with -2 having the highest performance. the spartan-7 fpgas predominantly operate at a 1.0v core voltage. the -1l devices are screened for lower maximum static power and can operate at lower core voltages for lower dynamic power than the -1 devices. the -1l devices operate only at v ccint =v ccbram = 0.95v and have the same speed specifications as the -1 speed grade. spartan-7 fpga dc and ac characteristics are specifie d in commercial and industrial temperature ranges. except the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (t hat is, the timing characteristics of a -1i industrial speed grade device are the same as for a -1c commerc ial speed grade device). however, only selected speed grades and/or devices are available in each temperature range. for example, the -1l speed grade is only available in the indust rial (i) temperature range. all supply voltage and junction temp erature specifications are representative of worst-case conditions. the parameters included are common to po pular designs and typical applications. available device and package combinations can be found in the 7 series fpgas overview (ds180) [ref 1] . this spartan-7 fpga data sheet, part of an overall se t of documentation on the 7 series fpgas, is available on the xilinx website at www.xilinx.com/documentation . dc characteristics spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 advance product specification table 1: absolute maximum ratings (1) symbol description min max units fpga logic v ccint internal supply voltage. ?0.5 1.1 v v ccaux auxiliary supply voltage. ?0.5 2.0 v v ccbram supply voltage for the block ram memories. ?0.5 1.1 v v cco output drivers supply voltage for hr i/o banks. ?0.5 3.6 v v ref input reference voltage. ?0.5 2.0 v v in (2)(3)(4) i/o input voltage. ?0.4 v cco +0.55 v i/o input voltage (when v cco =3.3v) for v ref and differential i/o standards except tmds_33. (5) ?0.4 2.625 v v ccbatt key memory battery ba ckup supply. ?0.5 2.0 v s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 2 xadc v ccadc xadc supply relative to gndadc. ?0.5 2.0 v v refp xadc reference input rela tive to gndadc. ?0.5 2.0 v temperature t stg storage temperature (ambient). ?65 150 c t sol maximum soldering temperature for pb/sn component bodies. (6) ?+220c maximum soldering temperature for pb-free component bodies. (6) ?+260c t j maximum junction temperature. (6) ?+125c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other cond itions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for exte nded periods of time might affect device reliability. 2. the lower absolute voltage specification always applies. 3. for i/o operation, refer to the 7 series fpgas selectio resources user guide (ug471) [ref 2] . 4. the maximum limit applies to dc signals. for maxi mum undershoot and overshoot ac specifications, see table 4 . 5. see table 9 for tmds_33 specifications. 6. for soldering guidelines and thermal considerations, see the 7 series fpga packaging and pinout specification (ug475) [ref 3] . table 1: absolute maximum ratings (1) (cont?d) symbol description min max units s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 3 table 2: recommended operating conditions (1)(2) symbol description min typ max units fpga logic v ccint (3) for -2 and -1 (1.0v) devices: internal supply voltage. 0.95 1.00 1.05 v for -1l (0.95v) devices: internal supply voltage. 0.92 0.95 0.98 v v ccaux auxiliary supply voltage. 1.71 1.80 1.89 v v ccbram (3) for -2 and -1 (1.0v) devices: block ram supply voltage. 0.95 1.00 1.05 v for -1l (0.95v) devices: block ram supply voltage. 0.92 0.95 0.98 v v cco (4)(5) supply voltage for hr i/o banks. 1.14 ? 3.465 v v in (6) i/o input voltage. ?0.20 ? v cco +0.20 v i/o input voltage (when v cco = 3.3v) for v ref and differential i/o standards except tmds_33. (7) ?0.20 ? 2.625 v i in (8) maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. ?? 10 ma v ccbatt (9) battery voltage. 1.0 ? 1.89 v xadc v ccadc xadc supply relative to gndadc. 1.71 1.80 1.89 v v refp externally supplied reference voltage. 1.20 1.25 1.30 v temperature t j junction temperature operat ing range for commercial (c) temperature devices. 0? 85 c junction temperature operatin g range for industrial (i) temperature devices. ?40 ? 100 c notes: 1. all voltages are relative to ground. 2. for the design of the power distribution system consult the 7 series fpgas pcb design guide (ug483) [ref 4] . 3. if v ccint and v ccbram are operating at the same voltage, v ccint and v ccbram should be connected to the same supply. 4. configuration data is retained even if v cco drops to 0v. 5. includes v cco of 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v at 5%. 6. the lower absolute voltage specification always applies. 7. see table 9 for tmds_33 specifications. 8. a total of 200 ma per bank should not be exceeded. 9. v ccbatt is required only when using bitstream en cryption. if battery is not used, connect v ccbatt to either ground or v ccaux . s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 4 table 3: dc characteristics over recommended operating conditions symbol description min typ (1) max units v drint data retention v ccint voltage (below which configuration data might be lost). 0.75 ? ? v v dri data retention v ccaux voltage (below which configuration data might be lost). 1.5 ? ? v i ref v ref leakage current per pin. ? ? 15 a i l input or output leakage current per pin (sample-tested). ? ? 15 a c in (2) die input capacitance at the pad. ? ? 8 pf i rpu pad pull-up (when selected) at v in = 0v, v cco =3.3v. 90 ? 330 a pad pull-up (when selected) at v in = 0v, v cco =2.5v. 68 ? 250 a pad pull-up (when selected) at v in = 0v, v cco =1.8v. 34 ? 220 a pad pull-up (when selected) at v in = 0v, v cco =1.5v. 23 ? 150 a pad pull-up (when selected) at v in = 0v, v cco =1.2v. 12 ? 120 a i rpd pad pull-down (when selected) at v in =3.3v. 68 ? 330 a i ccadc analog supply current, analog ci rcuits in powered up state. ? ? 25 ma i batt (3) battery supply current. ? ? 150 na r in_term (4) thevenin equivalent resistance of programmable input termination to v cco /2 (untuned_split_40). 28 40 55 thevenin equivalent resistance of programmable input termination to v cco /2 (untuned_split_50). 35 50 65 thevenin equivalent resistance of programmable input termination to v cco /2 (untuned_split_60). 44 60 83 n temperature diode idea lity factor. ? 1.010 ? ? r temperature diode series resistance. ? 2 ? notes: 1. typical values are specified at nominal voltage, 25c. 2. this measurement represents the die capacitance at the pad, not including the package. 3. maximum value specified for worst case process at 25c. 4. termination resistance to a v cco /2 level. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 5 table 4: v in maximum allowed ac voltage overshoot and undershoot for hr i/o banks (1)(2) ac voltage overshoot % of ui at ?40c to 100c ac voltage undershoot % of ui at ?40c to 100c v cco +0.55 100 ?0.40 100 ?0.45 61.7 ?0.50 25.8 ?0.55 11.0 v cco + 0.60 46.6 ?0.60 4.77 v cco + 0.65 21.2 ?0.65 2.10 v cco + 0.70 9.75 ?0.70 0.94 v cco + 0.75 4.55 ?0.75 0.43 v cco + 0.80 2.15 ?0.80 0.20 v cco + 0.85 1.02 ?0.85 0.09 v cco + 0.90 0.49 ?0.90 0.04 v cco + 0.95 0.24 ?0.95 0.02 notes: 1. a total of 200 ma per bank should not be exceeded. 2. the peak voltage of the overshoot or undershoot, and the duration above v cco + 0.20v or below gnd ? 0.20v, must not exceed the values in this table. table 5: typical quiescent supply current (1)(2)(3) symbol description device speed grade units 1.0v 0.95v -2c/-2i -1c/-1i -1li i ccintq quiescent v ccint supply current. xc7s6 ma xc7s15 ma xc7s25 48 48 43 ma XC7S50 95 95 58 ma xc7s75 ma xc7s100 ma i ccoq quiescent v cco supply current. xc7s6 ma xc7s15 ma xc7s25 1 1 1 ma XC7S50 1 1 1 ma xc7s75 ma xc7s100 ma i ccauxq quiescent v ccaux supply current. xc7s6 ma xc7s15 ma xc7s25 14 14 14 ma XC7S50 22 22 19 ma xc7s75 ma xc7s100 ma s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 6 power-on/off power supply sequencing the recommended power-on sequence is v ccint , v ccbram , v ccaux , and v cco to achieve minimum current draw and ensure that the i/os are 3-stated at power-on. the recommended power-off sequence is the reverse of the power-on sequence. if v ccint and v ccbram have the same recommended voltage levels then both can be powered by the same supp ly and ramped simultaneously. if v ccaux and v cco have the same recommended voltage levels then both can be powe red by the same supply and ramped simultaneously. for v cco voltages of 3.3v in hr i/o banks and config uration bank 0 the following conditions apply. ? the voltage difference between v cco and v ccaux must not exceed 2.625v for longer than t vcco2vccaux for each power-on/off cycle to ma intain device reliability levels. ? the t vcco2vccaux time can be allocated in any percenta ge between the power-on and power-off ramps. there is no recommended sequence for supplies not discussed in this section. i ccbramq quiescent v ccbram supply current. xc7s6 ma xc7s15 ma xc7s25 2 2 1 ma XC7S50 2 2 1 ma xc7s75 ma xc7s100 ma notes: 1. typical values are specified at nomina l voltage, 85c junction temperature (t j ) with single-ended selectio? resources. 2. typical values are for blank co nfigured devices with no output current loads, no active input pull-up resistors, all i/o pins are 3-state and floating. 3. use the xilinx power estimator spreadsheet tool [ref 5] to estimate static power consumption for conditions other than those specified. table 5: typical quiescent supply current (1)(2)(3) (cont?d) symbol description device speed grade units 1.0v 0.95v -2c/-2i -1c/-1i -1li s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 7 table 6 shows the minimum current, in addition to i ccq , that is required by spartan-7 devices for proper power-on and configuration. if the current minimums shown in table 5 and table 6 are met, the device powers on after all four supplies have passed throug h their power-on reset threshold voltages. the fpga must not be configured until after v ccint is applied. once initialized and configured, use the xilinx power estimator spreadsheet tool [ref 5] to estimate current drain on these supplies. table 6: power-on current for spartan-7 devices device i ccintmin i ccauxmin i ccomin i ccbrammin units xc7s6 i ccintq + 120 i ccauxq + 40 i ccoq + 40 ma per bank i ccbramq + 60 ma xc7s15 i ccintq + 120 i ccauxq + 40 i ccoq + 40 ma per bank i ccbramq + 60 ma xc7s25 i ccintq + 120 i ccauxq + 40 i ccoq + 40 ma per bank i ccbramq + 60 ma XC7S50 i ccintq + 120 i ccauxq + 40 i ccoq + 40 ma per bank i ccbramq + 60 ma xc7s75 i ccintq + 170 i ccauxq + 40 i ccoq + 40 ma per bank i ccbramq + 60 ma xc7s100 i ccintq + 170 i ccauxq + 40 i ccoq + 40 ma per bank i ccbramq + 60 ma table 7: power supply ramp time symbol description conditions min max units t vccint ramp time from gnd to 90% of v ccint .0.250ms t vcco ramp time from gnd to 90% of v cco .0.250ms t vccaux ramp time from gnd to 90% of v ccaux .0.250ms t vccbram ramp time from gnd to 90% of v ccbram .0.250ms t vcco2vccaux allowed time per power cycle for v cco ?v ccaux > 2.625v. t j =125c (1) ? 300 ms t j =100c (1) ? 500 ms t j =85c (1) ? 800 ms notes: 1. based on 240,000 power cycles with a nominal v cco of 3.3v or 36,500 power cycles with a worst case v cco of 3.465v. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 8 dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet th eir specifications. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. table 8: selectio dc input and output levels (1)(2)(3) i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma, max ma, min hstl_i ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 8.00 ?8.00 hstl_i_18 ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 8.00 ?8.00 hstl_ii ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 16.00 ?16.00 hstl_ii_18 ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 16.00 ?16.00 hsul_12 ?0.300 v ref ?0.130 v ref + 0.130 v cco + 0.300 20% v cco 80% v cco 0.10 ?0.10 lvcmos12 ?0.300 35% v cco 65% v cco v cco + 0.300 0.400 v cco ?0.400 note 4 note 4 lvcmos15 ?0.300 35% v cco 65% v cco v cco + 0.300 25% v cco 75% v cco note 5 note 5 lvcmos18 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ?0.450 note 6 note 6 lvcmos25 ?0.300 0.7 1.700 v cco + 0.300 0.400 v cco ?0.400 note 5 note 5 lvcmos33 ?0.300 0.8 2.000 3.450 0.400 v cco ?0.400 note 5 note 5 lvttl ?0.300 0.8 2.000 3.450 0.400 2.400 note 6 note 6 mobile_ddr ?0.300 20% v cco 80% v cco v cco + 0.300 10% v cco 90% v cco 0.10 ?0.10 pci33_3 ?0.400 30% v cco 50% v cco v cco + 0.500 10% v cco 90% v cco 1.50 ?0.50 sstl135 ?0.300 v ref ?0.090 v ref + 0.090 v cco + 0.300 v cco /2?0.150v cco /2 + 0.150 13.00 ?13.00 sstl135_r ?0.300 v ref ?0.090 v ref + 0.090 v cco + 0.300 v cco /2?0.150v cco /2 + 0.150 8.90 ?8.90 sstl15 ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 v cco /2?0.175v cco /2 + 0.175 13.00 ?13.00 sstl15_r ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 v cco /2?0.175v cco /2 + 0.175 8.90 ?8.90 sstl18_i ?0.300 v ref ?0.125 v ref + 0.125 v cco + 0.300 v cco /2?0.470v cco /2 + 0.470 8.00 ?8.00 sstl18_ii ?0.300 v ref ?0.125 v ref + 0.125 v cco + 0.300 v cco /2?0.600v cco /2 + 0.600 13.40 ?13.40 notes: 1. tested according to relevant specifications. 2. 3.3v and 2.5v standards are only supported in hr i/o banks. 3. for detailed interface specific dc voltage levels, see the 7 series fpgas selectio resources user guide (ug471) [ref 2] . 4. supported drive strengths of 4, 8, or 12 ma in hr i/o banks. 5. supported drive strengths of 4, 8, 12, or 16 ma in hr i/o banks. 6. supported drive strengths of 4, 8, 12, 16, or 24 ma in hr i/o banks. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 9 table 9: differential selectio dc input and output levels i/o standard v icm (1) v id (2) v ocm (3) v od (4) v, min v, typ v, max v, min v, typ v, max v, min v, typ v, max v, min v, typ v, max blvds_25 0.300 1.200 1.425 0.100 ? ? ? 1.250 ? note 5 mini_lvds_25 0.300 1.200 v ccaux 0.200 0.400 0.600 1.000 1.200 1.400 0.300 0.450 0.600 ppds_25 0.200 0.900 v ccaux 0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400 rsds_25 0.300 0.900 1.500 0.100 0.350 0.600 1.000 1.200 1.400 0.100 0.350 0.600 tmds_33 2.700 2.965 3.230 0.150 0.675 1.200 v cco ?0.405v cco ?0.300v cco ? 0.190 0.400 0.600 0.800 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q ? q ). 3. v ocm is the output common mode voltage. 4. v od is the output differential voltage (q ? q ). 5. v od for blvds will vary significantly depending on topology and loading. table 10: complementary differential selectio dc input and output levels i/o standard v icm (1) v id (2) v ol (3) v oh (4) i ol i oh v, min v, typ v, max v, min v, max v, max v, min ma, max ma, min diff_hstl_i 0.300 0.750 1.125 0.100 ? 0.400 v cco ? 0.400 8.00 ?8.00 diff_hstl_i_18 0.300 0.900 1.425 0.100 ? 0.400 v cco ? 0.400 8.00 ?8.00 diff_hstl_ii 0.300 0.750 1.125 0.100 ? 0.400 v cco ? 0.400 16.00 ?16.00 diff_hstl_ii_18 0.300 0.900 1.425 0.100 ? 0.400 v cco ? 0.400 16.00 ?16.00 diff_hsul_12 0.300 0.600 0.850 0.100 ? 20% v cco 80% v cco 0.100 ?0.100 diff_mobile_ddr 0.300 0.900 1.425 0.100 ? 10% v cco 90% v cco 0.100 ?0.100 diff_sstl135 0.300 0.675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 13.0 ?13.0 diff_sstl135_r 0.300 0.675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 8.9 ?8.9 diff_sstl15 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 13.0 ?13.0 diff_sstl15_r 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 8.9 ?8.9 diff_sstl18_i 0.300 0.900 1.425 0.100 ? (v cco /2) ? 0.470 (v cco /2) + 0.470 8.00 ?8.00 diff_sstl18_ii 0.300 0.900 1.425 0.100 ? (v cco /2) ? 0.600 (v cco /2) + 0.600 13.4 ?13.4 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q ? q ). 3. v ol is the single-ended low-output voltage. 4. v oh is the single-ended high-output voltage. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 10 lvds dc specifications (lvds_25) table 11: lvds_25 dc specifications (1) symbol dc parameter conditions min typ max units v cco supply voltage. 2.375 2.500 2.625 v v oh output high voltage for q and q .r t =100 across q and q signals. ? ? 1.675 v v ol output low voltage for q and q .r t =100 across q and q signals. 0.700 ? ? v v odiff differential output voltage: (q ? q ), q = high (q ? q), q =high r t =100 across q and q signals. 247 350 600 mv v ocm output common-mode voltage. r t = 100 across q and q signals. 1.000 1.250 1.425 v v idiff differential input voltage: (q ? q ), q = high (q ? q), q =high 100 350 600 mv v icm input common-mode voltage. 0.300 1.200 1.500 v notes: 1. differential inputs for lvds_25 can be placed in banks with v cco levels that are different from the required level for outputs. consult the 7 series fpgas selectio resources user guide (ug471) [ref 2] for more information. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 11 ac switching characteristics all values represented in this data sheet are based on the speed specifications from the vivado? design suite as outlined in table 12 . switching characteristics are specified on a per-spee d-grade basis and can be designated as advance, preliminary, or production. each designation is defined as follows. advance product specification these specifications are based on simulations only an d are typically available so on after device design specifications are frozen. although speed grades with this designation are consider ed relatively stable and conservative, some under-rep orting might still occur. preliminary product specification these specifications are based on complete es (engin eering sample) silicon characterization. devices and speed grades with this designation are intended to gi ve a better indication of the expected performance of production silicon. the probability of under-repo rting delays is greatly reduced as compared to advance data. production product specification these specifications are released once enough producti on silicon of a particular device family member has been characterized to provide full correlation be tween specifications and devices over numerous production lots. there is no under-reporting of dela ys, and customers receive formal notification of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. testing of ac switching characteristics internal timing parameters are derived from meas uring internal test patt erns. all ac switching characteristics are representative of worst-case supply voltage and junction temperature conditions. for more specific, more precise, and worst-case guar anteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. unless otherwise noted, values apply to all spartan-7 fpgas. table 12: speed specification version by device 2016.3 device 1.15 xc7s6, xc7s15, xc7s25, XC7S50, xc7s75, xc7s100 s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 12 speed grade designations since individual family members are produced at di fferent times, the migration from one category to another depends completely on the status of the fabrication process for each device. table 13 correlates the current status of each spartan-7 device on a per speed grade basis. production silicon and software status in some cases, a particular family member (and speed grade) is released to production before a speed specification is released with th e correct label (advance, prelimin ary, production). any labeling discrepancies are corrected in subseq uent speed specification releases. table 14 lists the production released spartan-7 device, speed grade, and the minimum corresponding supported speed specification version and software revisions. the software and speed specifications listed are the minimum releases required for producti on. all subsequent releases of software and speed specifications are valid. table 13: spartan-7 device speed grade designations device speed grade, temperature range, and v ccint operating voltage advance preliminary production xc7s6 -2c (1.0v), -2i (1 .0v), -1c (1.0v), -1i (1.0v), and -1li (0.95v) (1) xc7s15 -2c (1.0v), -2i (1 .0v), -1c (1.0v), -1i (1.0v), and -1li (0.95v) (1) xc7s25 -2c (1.0v), -2i (1 .0v), -1c (1.0v), -1i (1.0v), and -1li (0.95v) (1) XC7S50 -2c (1.0v), -2i (1 .0v), -1c (1.0v), -1i (1.0v), and -1li (0.95v) (1) xc7s75 -2c (1.0v), -2i (1 .0v), -1c (1.0v), -1i (1.0v), and -1li (0.95v) (1) xc7s100 -2c (1.0v), -2i (1 .0v), -1c (1.0v), -1i (1.0v), and -1li (0.95v) (1) notes: 1. the lowest power -1li devices, where v ccint = 0.95v, are listed in the vivado design suite as -1lv. table 14: spartan-7 device production softwa re and speed specification release device v ccint operating voltage, speed grade, and temperature range 1.0v 0.95v -2c/-2i -1c/-1i -1li xc7s6 xc7s15 xc7s25 XC7S50 xc7s75 xc7s100 s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 13 performance characteristics this section provides the performance characte ristics of some common functions and designs implemented in spartan-7 fpgas. these values are subject to the same guidelines as the ac switching characteristics, page 11 . table 15: networking applications interface performances description v ccint operating voltage, speed grade, and temperature range units 1.0v 0.95v -2c/-2i -1c/-1i -1li sdr lvds transmitter (using oserdes; data_width = 4 to 8) 680 600 600 mb/s ddr lvds transmitter (using oserdes; data_width = 4 to 14) 1250 950 950 mb/s sdr lvds receiver (sfi-4.1) (1) 680 600 600 mb/s ddr lvds receiver (spi-4.2) (1) 1250 950 950 mb/s notes: 1. lvds receivers are typically bounded with certain applications where specific dynamic phase-al ignment (dpa) algorithms domina te deterministic performance. table 16: maximum physical interface (phy) rate for memory interface ip available with the memory interface generator (1) memory standard v ccint operating voltage, speed grade, and temperature range units 1.0v 0.95v -2c/-2i -1c/-1i -1li 4:1 memory controllers ddr3 800 667 667 mb/s ddr3l 800 667 667 mb/s ddr2 800 667 667 mb/s 2:1 memory controllers ddr3 800 667 667 mb/s ddr3l 800 667 667 mb/s ddr2 800 667 667 mb/s lpddr2 667 533 533 mb/s notes: 1. v ref tracking is required. for more information, see the zynq-7000 ap soc and 7 series fpgas memory interface solutions user guide (ug586) [ref 6] . s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 14 iob pad input/output/3-state table 17 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. ? t iopi is described as the delay from iob pad through the input buffer to the i-pin of an iob pad. the delay varies depending on the capa bility of the selectio input buffer. ? t ioop is described as the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on the ca pability of the selectio output buffer. ? t iotp is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the dela y varies depending on the selectio capability of the output buffer. in hr i/o banks, the in_term termination turn-on time is always faster than t iotp when the intermdisable pin is used. table 17: iob high range (hr) switching characteristics i/o standard t iopi t ioop t iotp units v ccint operating voltage and speed grade 1.0v 0.95v 1.0v 0.95v 1.0v 0.95v -2 -1 -1l -2 -1 -1l -2 -1 -1l lvttl_s4 1.34 1.41 1.41 3.93 4.18 4.18 3.96 4.20 4.20 ns lvttl_s8 1.34 1.41 1.41 3.66 3.92 3.92 3.69 3.93 3.93 ns lvttl_s12 1.341.411.413.653.903.903.683.913.91ns lvttl_s16 1.341.411.413.193.453.453.223.463.46ns lvttl_s24 1.341.411.413.413.673.673.443.683.68ns lvttl_f4 1.34 1.41 1.41 3.38 3.64 3.64 3.41 3.65 3.65 ns lvttl_f8 1.34 1.41 1.41 2.87 3.12 3.12 2.90 3.13 3.13 ns lvttl_f12 1.341.411.412.853.103.102.883.123.12ns lvttl_f16 1.341.411.412.682.932.932.712.952.95ns lvttl_f24 1.341.411.412.652.902.902.682.912.91ns lvds_25 0.810.880.881.411.671.671.441.681.68ns mini_lvds_25 0.81 0.88 0.88 1.40 1.65 1.65 1.43 1.66 1.66 ns blvds_25 0.81 0.88 0.88 1.96 2.21 2.21 1.99 2.23 2.23 ns rsds_25 (point to point) 0.81 0.88 0.88 1.40 1.65 1.65 1.43 1.66 1.66 ns ppds_25 0.810.880.881.411.671.671.441.681.68ns tmds_33 0.810.880.881.541.791.791.571.801.80ns pci33_3 1.321.391.393.223.483.483.253.493.49ns hsul_12_s 0.750.820.821.932.182.181.962.202.20ns hsul_12_f 0.750.820.821.411.671.671.441.681.68ns diff_hsul_12_s 0.76 0.83 0.83 1.93 2.18 2.18 1.96 2.20 2.20 ns diff_hsul_12_f 0.76 0.83 0.83 1.41 1.67 1.67 1.44 1.68 1.68 ns mobile_ddr_s 0.84 0.91 0.91 1.80 2.06 2.06 1.83 2.07 2.07 ns mobile_ddr_f 0.84 0.91 0.91 1.51 1.76 1.76 1.54 1.77 1.77 ns diff_mobile_ddr_s 0.78 0.85 0.85 1.82 2.07 2.07 1.85 2.09 2.09 ns s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 15 diff_mobile_ddr_f 0.78 0.85 0.85 1.57 1.82 1.82 1.60 1.84 1.84 ns hstl_i_s 0.75 0.82 0.82 1.74 1.99 1.99 1.77 2.01 2.01 ns hstl_ii_s 0.730.800.801.541.791.791.571.801.80ns hstl_i_18_s 0.750.820.821.411.671.671.441.681.68ns hstl_ii_18_s 0.75 0.81 0.81 1.54 1.79 1.79 1.57 1.80 1.80 ns diff_hstl_i_s 0.76 0.83 0.83 1.71 1.96 1.96 1.74 1.98 1.98 ns diff_hstl_ii_s 0.760.830.831.631.881.881.661.901.90ns diff_hstl_i_18_s 0.790.860.861.511.761.761.541.771.77ns diff_hstl_ii_18_s 0.78 0.85 0.85 1.58 1.84 1.84 1.61 1.85 1.85 ns hstl_i_f 0.75 0.82 0.82 1.22 1.48 1.48 1.25 1.49 1.49 ns hstl_ii_f 0.730.800.801.241.491.491.271.511.51ns hstl_i_18_f 0.750.820.821.261.511.511.291.521.52ns hstl_ii_18_f 0.75 0.81 0.81 1.24 1.49 1.49 1.27 1.51 1.51 ns diff_hstl_i_f 0.76 0.83 0.83 1.30 1.56 1.56 1.33 1.57 1.57 ns diff_hstl_ii_f 0.760.830.831.331.591.591.361.601.60ns diff_hstl_i_18_f 0.790.860.861.331.591.591.361.601.60ns diff_hstl_ii_18_f 0.78 0.85 0.85 1.33 1.59 1.59 1.36 1.60 1.60 ns lvcmos33_s4 1.341.411.413.934.184.183.964.204.20ns lvcmos33_s8 1.341.411.413.653.903.903.683.913.91ns lvcmos33_s12 1.34 1.41 1.41 3.21 3.46 3.46 3.24 3.48 3.48 ns lvcmos33_s16 1.34 1.41 1.41 3.52 3.77 3.77 3.55 3.79 3.79 ns lvcmos33_f4 1.341.411.413.383.643.643.413.653.65ns lvcmos33_f8 1.341.411.412.873.123.122.903.133.13ns lvcmos33_f12 1.34 1.41 1.41 2.68 2.93 2.93 2.71 2.95 2.95 ns lvcmos33_f16 1.34 1.41 1.41 2.68 2.93 2.93 2.71 2.95 2.95 ns lvcmos25_s4 1.201.271.273.263.513.513.293.523.52ns lvcmos25_s8 1.201.271.273.013.263.263.043.273.27ns lvcmos25_s12 1.20 1.27 1.27 2.60 2.85 2.85 2.63 2.87 2.87 ns lvcmos25_s16 1.20 1.27 1.27 2.94 3.20 3.20 2.97 3.21 3.21 ns lvcmos25_f4 1.201.271.272.873.123.122.903.133.13ns lvcmos25_f8 1.201.271.272.302.562.562.332.572.57ns lvcmos25_f12 1.20 1.27 1.27 2.29 2.54 2.54 2.32 2.55 2.55 ns lvcmos25_f16 1.20 1.27 1.27 2.13 2.39 2.39 2.16 2.40 2.40 ns lvcmos18_s4 0.830.890.891.741.991.991.772.012.01ns lvcmos18_s8 0.830.890.892.302.562.562.332.572.57ns lvcmos18_s12 0.83 0.89 0.89 2.30 2.56 2.56 2.33 2.57 2.57 ns table 17: iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units v ccint operating voltage and speed grade 1.0v 0.95v 1.0v 0.95v 1.0v 0.95v -2 -1 -1l -2 -1 -1l -2 -1 -1l s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 16 lvcmos18_s16 0.83 0.89 0.89 1.65 1.90 1.90 1.68 1.91 1.91 ns lvcmos18_s24 0.83 0.89 0.89 1.72 1.98 1.98 1.75 1.99 1.99 ns lvcmos18_f4 0.830.890.891.571.821.821.601.841.84ns lvcmos18_f8 0.830.890.891.802.062.061.832.072.07ns lvcmos18_f12 0.83 0.89 0.89 1.80 2.06 2.06 1.83 2.07 2.07 ns lvcmos18_f16 0.83 0.89 0.89 1.52 1.77 1.77 1.55 1.79 1.79 ns lvcmos18_f24 0.83 0.89 0.89 1.46 1.71 1.71 1.49 1.73 1.73 ns lvcmos15_s4 0.860.930.932.182.432.432.212.452.45ns lvcmos15_s8 0.860.930.932.212.462.462.242.482.48ns lvcmos15_s12 0.86 0.93 0.93 1.71 1.96 1.96 1.74 1.98 1.98 ns lvcmos15_s16 0.86 0.93 0.93 1.71 1.96 1.96 1.74 1.98 1.98 ns lvcmos15_f4 0.860.930.931.972.232.232.002.242.24ns lvcmos15_f8 0.860.930.931.721.981.981.751.991.99ns lvcmos15_f12 0.86 0.93 0.93 1.47 1.73 1.73 1.50 1.74 1.74 ns lvcmos15_f16 0.86 0.93 0.93 1.46 1.71 1.71 1.49 1.73 1.73 ns lvcmos12_s4 0.951.021.022.692.952.952.722.962.96ns lvcmos12_s8 0.951.021.022.212.462.462.242.482.48ns lvcmos12_s12 0.95 1.02 1.02 1.91 2.17 2.17 1.94 2.18 2.18 ns lvcmos12_f4 0.951.021.022.102.352.352.132.372.37ns lvcmos12_f8 0.951.021.021.661.921.921.691.931.93ns lvcmos12_f12 0.95 1.02 1.02 1.51 1.76 1.76 1.54 1.77 1.77 ns sstl135_s 0.75 0.82 0.82 1.47 1.73 1.73 1.50 1.74 1.74 ns sstl15_s 0.68 0.75 0.75 1.43 1.68 1.68 1.46 1.69 1.69 ns sstl18_i_s 0.75 0.82 0.82 1.79 2.04 2.04 1.82 2.06 2.06 ns sstl18_ii_s 0.750.820.821.431.681.681.461.701.70ns diff_sstl135_s 0.76 0.83 0.83 1.47 1.73 1.73 1.50 1.74 1.74 ns diff_sstl15_s 0.76 0.83 0.83 1.43 1.68 1.68 1.46 1.69 1.69 ns diff_sstl18_i_s 0.79 0.86 0.86 1.80 2.06 2.06 1.83 2.07 2.07 ns diff_sstl18_ii_s 0.790.860.861.511.761.761.541.771.77ns sstl135_f 0.75 0.82 0.82 1.24 1.49 1.49 1.27 1.51 1.51 ns sstl15_f 0.68 0.75 0.75 1.19 1.45 1.45 1.22 1.46 1.46 ns sstl18_i_f 0.75 0.82 0.82 1.24 1.49 1.49 1.27 1.51 1.51 ns sstl18_ii_f 0.750.820.821.241.491.491.271.511.51ns diff_sstl135_f 0.76 0.83 0.83 1.24 1.49 1.49 1.27 1.51 1.51 ns diff_sstl15_f 0.76 0.83 0.83 1.19 1.45 1.45 1.22 1.46 1.46 ns table 17: iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units v ccint operating voltage and speed grade 1.0v 0.95v 1.0v 0.95v 1.0v 0.95v -2 -1 -1l -2 -1 -1l -2 -1 -1l s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 17 table 18 specifies the values of t iotphz and t ioibufdisable . t iotphz is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (i.e., a high impedance state). t ioibufdisable is described as the iob delay from ibufdisable to o output. in hr i/o banks, the internal in_term termination turn-off time is always faster than t iotphz when the intermdisable pin is used. i/o standard adjustment measurement methodology input delay measurements table 19 shows the test setup parameters used for measuring input delay. diff_sstl18_i_f 0.79 0.86 0.86 1.35 1.60 1.60 1.38 1.62 1.62 ns diff_sstl18_ii_f 0.790.860.861.331.591.591.361.601.60ns table 18: iob 3-state output switching characteristics symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l t iotphz t input to pad high-impedance. 2.19 2.37 2.37 ns t ioibufdisable ibuf turn-on time from ibufdisable to o output. 2.30 2.60 2.60 ns table 19: input delay measurement methodology description i/o standard attribute v l (1) v h (1) v meas (3)(5) v ref (2)(4) lvcmos, 1.2v lvcmos12 0.1 1.1 0.6 ? lvcmos, 1.5v lvcmos15 0.1 1.4 0.75 ? lvcmos, 1.8v lvcmos18 0.1 1.7 0.9 ? lvcmos, 2.5v lvcmos25 0.1 2.4 1.25 ? lvcmos, 3.3v lvcmos33 0.1 3.2 1.65 ? lvttl, 3.3v lvttl 0.1 3.2 1.65 ? mobile_ddr, 1.8v mobile_ddr 0.1 1.7 0.9 ? pci33, 3.3v pci33_3 0.1 3.2 1.65 ? hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 v ref ?0.5 v ref +0.5 v ref 0.60 hstl, class i & ii, 1.5v hstl_i, hstl_ii v ref ?0.65 v ref +0.65 v ref 0.75 hstl, class i & ii, 1.8v hstl_i_18, hstl_ii_18 v ref ?0.8 v ref +0.8 v ref 0.90 table 17: iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units v ccint operating voltage and speed grade 1.0v 0.95v 1.0v 0.95v 1.0v 0.95v -2 -1 -1l -2 -1 -1l -2 -1 -1l s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 18 hsul (high-speed unterminated logic), 1.2v hsul_12 v ref ?0.5 v ref +0.5 v ref 0.60 sstl (stub-terminated transceiver logic), 1.2v sstl12 v ref ?0.5 v ref +0.5 v ref 0.60 sstl, 1.35v sstl135, sstl135_r v ref ?0.575 v ref +0.575 v ref 0.675 sstl, 1.5v sstl15, sstl15_r v ref ?0.65 v ref +0.65 v ref 0.75 sstl, class i & ii, 1.8v sstl18_i, sstl18_ii v ref ?0.8 v ref +0.8 v ref 0.90 diff_mobile_ddr, 1.8v diff_mobile_ddr 0.9 ? 0.125 0.9 + 0.125 0 (5) ? diff_hstl, class i, 1.2v diff_hstl_i_12 0.6 ? 0.125 0.6 + 0.125 0 (5) ? diff_hstl, class i & ii,1.5v diff_hstl_i, diff_hstl_ii 0.75 ? 0.125 0.75 + 0.125 0 (5) ? diff_hstl, class i & ii, 1.8v diff_hstl_i_18, diff_hstl_ii_18 0.9 ? 0.125 0.9 + 0.125 0 (5) ? diff_hsul, 1.2v diff_hsul_12 0.6 ? 0.125 0.6 + 0.125 0 (5) ? diff_sstl135/ diff_sstl135_r, 1.35v diff_sstl135, diff_sstl135_r 0.675 ? 0.125 0.675 + 0.125 0 (5) ? diff_sstl15/ diff_sstl15_r, 1.5v diff_sstl15, diff_sstl15_r 0.75 ? 0.125 0.75 + 0.125 0 (5) ? diff_sstl18_i/ diff_sstl18_ii, 1.8v diff_sstl18_i, diff_sstl18_ii 0.9 ? 0.125 0.9 + 0.125 0 (5) ? lvds_25, 2.5v lvds_25 1.2 ? 0.125 1.2 + 0.125 0 (5) ? blvds_25, 2.5v blvds_25 1.25 ? 0.125 1.25 + 0.125 0 (5) ? mini_lvds_25, 2.5v mini_lvds_25 1.25 ? 0.125 1.25 + 0.125 0 (5) ? ppds_25 ppds_25 1.25 ? 0.125 1.25 + 0.125 0 (5) ? rsds_25 rsds_25 1.25 ? 0.125 1.25 + 0.125 0 (5) ? tmds_33 tmds_33 3 ? 0.125 3 + 0.125 0 (5) ? notes: 1. input waveform switches between v l and v h . 2. measurements are made at ty pical, minimum, and maximum v ref values. reported delays reflect worst case of these measurements. v ref values listed are typical. 3. input voltage level from which measurement starts. 4. this is an input voltage reference that bears no relation to the v ref / v meas parameters found in ibis models and/or noted in figure 1 . 5. the value given is the differential input voltage. table 19: input delay measurement methodology (cont?d) description i/o standard attribute v l (1) v h (1) v meas (3)(5) v ref (2)(4) s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 19 output delay measurements output delays are measured with short output traces . standard termination was used for all testing. the propagation delay of the trace is characterized separa tely and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in figure 1 and figure 2 . parameters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate prediction of propagat ion delay in any given application can be obtained through ibis simulation, using this method: 1. simulate the output driver of choice into the generalized test setup using values from table 20 . 2. record the time to v meas . 3. simulate the output driver of choice into the ac tual pcb trace and load using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of step 2 and step 4 . the increase or decrease in delay yields the actual propagation delay of the pcb trace. x-ref target - figure 1 figure 1: single-ended test setup x-ref target - figure 2 figure 2: differential test setup v ref r ref v meas (voltage level when taking delay measurement) c ref (probe capacitance) output x16654-092616 r ref v meas + C c ref output x16640-092616 s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 20 table 20: output delay measurement methodology description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v) lvcmos, 1.2v lvcmos12 1m 0 0.6 0 lvcmos, 1.5v lvcmos15 1m 0 0.75 0 lvcmos, 1.8v lvcmos18 1m 0 0.9 0 lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 3.3v lvcmos33 1m 0 1.65 0 lvttl, 3.3v lvttl 1m 0 1.65 0 pci33, 3.3v pci33_3 25 10 1.65 0 hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 50 0 v ref 0.6 hstl, class i, 1.5v hstl_i 50 0 v ref 0.75 hstl, class ii, 1.5v hstl_ii 25 0 v ref 0.75 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hstl, class ii, 1.8v hstl_ii_18 25 0 v ref 0.9 hsul (high-speed unterminated logic), 1.2v hsul_12 50 0 v ref 0.6 sstl12, 1.2v sstl12 50 0 v ref 0.6 sstl135/sstl135_r, 1.35v sstl135, sstl135_r 50 0 v ref 0.675 sstl15/sstl15_r, 1.5v sstl15, sstl15_r 50 0 v ref 0.75 sstl (stub-series terminated logic), class i & class ii, 1.8v sstl18_i, sstl18_ii 50 0 v ref 0.9 diff_mobile_ddr, 1.8v diff_mobile_ddr 50 0 v ref 0.9 diff_hstl, class i, 1.2v diff_hstl_i_12 50 0 v ref 0.6 diff_hstl, class i & ii, 1.5v diff_hstl_i, diff_hstl_ii 50 0 v ref 0.75 diff_hstl, class i & ii, 1.8v diff_hstl_i_18, diff_hstl_ii_18 50 0 v ref 0.9 diff_hsul_12, 1.2v diff_hsul_12 50 0 v ref 0.6 diff_sstl135/diff_sstl135_r, 1.35v diff_sstl135, diff_sstl135_r 50 0 v ref 0.675 diff_sstl15/diff_sstl15_r, 1.5v diff_sstl15, diff_sstl15_r 50 0 v ref 0.75 diff_sstl18, class i & ii, 1.8v diff_sstl18_i, diff_sstl18_ii 50 0 v ref 0.9 lvds, 2.5v lvds_25 100 0 0 (2) 0 blvds (bus lvds), 2.5v blvds_25 100 0 0 (2) 0 mini lvds, 2.5v mini_lvds_25 100 0 0 (2) 0 ppds_25 ppds_25 100 0 0 (2) 0 rsds_25 rsds_25 100 0 0 (2) 0 tmds_33 tmds_33 50 0 0 (2) 3.3 notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. the value given is the differential output voltage. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 21 input/output logic switching characteristics table 21: ilogic switching characteristics symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l setup/hold t ice1ck /t ickce1 ce1 pin setup/hold with respect to clk. 0.54/0.02 0.76/0.02 0.76/0.02 ns t isrck /t icksr sr pin setup/hold with respect to clk. 0.70/0.01 1.13/0.01 1.13/0.01 ns t idock /t iockd d pin setup/hold with respect to clk without delay. 0.01/0.29 0.01/0.33 0.01/0.33 ns t idockd /t iockdd ddly pin setup/hold with respect to clk (using idelay). 0.02/0.29 0.02/0.33 0.02/0.33 ns combinatorial t idi d pin to o pin propagation delay, no delay. 0.11 0.13 0.13 ns t idid ddly pin to o pin prop agation delay (using idelay). 0.12 0.14 0.14 ns sequential delays t idlo d pin to q1 pin using flip-flop as a latch without delay. 0.44 0.51 0.51 ns t idlod ddly pin to q1 pin using flip-flop as a latch (using idelay). 0.44 0.51 0.51 ns t ickq clk to q outputs. 0.57 0.66 0.66 ns t rq_ilogic sr pin to oq/tq out. 1.08 1.32 1.32 ns t gsrq_ilogic global set/reset to q outputs. 7.60 10.51 10.51 ns set/reset t rpw_ilogic minimum pulse width, sr in puts. 0.72 0.72 0.72 ns, min s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 22 table 22: ologic switching characteristics symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l setup/hold t odck /t ockd d1/d2 pins setup/hold with respect to clk. 0.71/?0.11 0.84/?0.11 0.84/?0.11 ns t ooceck /t ockoce oce pin setup/hold with respect to clk. 0.34/0.58 0.51/0.58 0.51/0.58 ns t osrck /t ocksr sr pin setup/hold with respect to clk. 0.44/0.21 0.80/0.21 0.80/0.21 ns t otck /t ockt t1/t2 pins setup/hold with respect to clk. 0.73/?0.14 0.89/?0.14 0.89/?0.14 ns t otceck /t ocktce tce pin setup/hold with respect to clk. 0.34/0.01 0.51/0.01 0.51/0.01 ns combinatorial t odq d1 to oq out or t1 to tq out. 0.96 1.16 1.16 ns sequential delays t ockq clk to oq/tq out. 0.49 0.56 0.56 ns t rq_ologic sr pin to oq/tq out. 0.80 0.95 0.95 ns t gsrq_ologic global set/reset to q outputs. 7.60 10.51 10.51 ns set/reset t rpw_ologic minimum pulse widt h, sr inputs. 0.74 0.74 0.74 ns, min s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 23 input serializer/deserializer switching characteristics table 23: iserdes switching characteristics symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l setup/hold for control lines t iscck_bitslip / t isckc_bitslip bitslip pin setup/hold with respect to clkdiv. 0.02/0.15 0.02/0.17 0.02/0.17 ns t iscck_ce / t isckc_ce ce pin setup/hold with respect to clk (for ce1). 0.50/?0.01 0.72/?0.01 0.72/?0.01 ns t iscck_ce2 / t isckc_ce2 ce pin setup/hold with respect to clkdiv (for ce2). ?0.10/0.36 ?0.10/0.40 ?0.10/0.40 ns setup/hold for data lines t isdck_d / t isckd_d d pin setup/hold with respect to clk. ?0.02/0.14 ?0.02/0.17 ?0.02/0.17 ns t isdck_ddly / t isckd_ddly ddly pin setup/hold with respect to clk (using idelay). (1) ?0.02/0.14 ?0.02/0.17 ?0.02/0.17 ns t isdck_d_ddr / t isckd_d_ddr d pin setup/hold with respect to clk at ddr mode. ?0.02/0.14 ?0.02/0.17 ?0.02/0.17 ns t isdck_ddly_ddr / t isckd_ddly_ddr d pin setup/hold with respect to clk at ddr mode (using idelay). (1) 0.14/0.14 0.17/0.17 0.17/0.17 ns sequential delays t iscko_q clkdiv to out at q pin. 0.54 0.66 0.66 ns propagation delays t isdo_do d input to do output pin. 0.11 0.13 0.13 ns notes: 1. recorded at 0 tap value. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 24 output serializer/deserializer switching characteristics table 24: oserdes switching characteristics symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l setup/hold t osdck_d / t osckd_d d input setup/hold with respect to clkdiv. 0.45/0.03 0.63/0.03 0.63/0.03 ns t osdck_t / t osckd_t t input setup/hold with respect to clk. 0.73/?0.13 0.88/?0.13 0.88/?0.13 ns t osdck_t2 / t osckd_t2 t input setup/hold with respect to clkdiv. 0.34/?0.13 0.39/?0.13 0.39/?0.13 ns t oscck_oce / t osckc_oce oce input setup/hold with respect to clk. 0.34/0.58 0.51/0.58 0.51/0.58 ns t oscck_s sr (reset) input setup with respect to clkdiv. 0.52 0.85 0.85 ns t oscck_tce / t osckc_tce tce input setup/hold with respect to clk. 0.34/0.01 0.51/0.01 0.51/0.01 ns sequential delays t oscko_oq clock to out from clk to oq. 0.42 0.48 0.48 ns t oscko_tq clock to out from clk to tq. 0.49 0.56 0.56 ns combinatorial t osdo_ttq t input to tq out. 0.92 1.11 1.11 ns s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 25 input/output delay switching characteristics table 25: input/output delay switching characteristics symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l idelayctrl t dlycco_rdy reset to ready for idelayctrl. 3.67 3.67 3.67 s f idelayctrl_ref attribute refclk frequency = 200.00. (1) 200.00 200.00 200.00 mhz attribute refclk frequency = 300.00. (1) 300.00 300.00 300.00 mhz attribute refclk frequency = 400.00. (1) 400.00 n/a n/a mhz idelayctrl_ref_ precision refclk precision 10 10 10 mhz t idelayctrl_rpw minimum reset pulse width. 59.28 59.28 59.28 ns idelay t idelayresolution idelay chain delay resolution. 1/(32 x 2 x f ref )ps t idelaypat_jit pattern dependent period jitter in delay chain for clock pattern. (2) 000 ps per tap pattern dependent period jitter in delay chain for random data pattern (prbs 23). (3) 5 5 5 ps per tap pattern dependent period jitter in delay chain for random data pattern (prbs 23). (4) 9 9 9 ps per tap t idelay_clk_max maximum frequency of clk input to idelay. 680.00 600.00 600.00 mhz t idcck_ce / t idckc_ce ce pin setup/hold with respect to c for idelay. 0.16/0.13 0.21/0.16 0.21/0.16 ns t idcck_inc / t idckc_inc inc pin setup/hold with respect to c for idelay. 0.14/0.18 0.16/0.22 0.16/0.22 ns t idcck_rst / t idckc_rst rst pin setup/hold with respect to c for idelay. 0.16/0.11 0.18/0.14 0.18/0.14 ns t iddo_idatain propagation delay through idelay. note 5 note 5 note 5 ps notes: 1. average tap delay at 200 mhz = 78 ps, at 300 mhz = 52 ps, and at 400 mhz = 39 ps. 2. when high_performance mode is set to true or false. 3. when high_performance mode is set to true. 4. when high_performance mode is set to false. 5. delay depends on idelay tap setting. see the timing report for actual values. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 26 table 26: io_fifo switching characteristics symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l io_fifo clock to out delays t offcko_do rdclk to q outputs. 0.60 0.68 0.68 ns t cko_flags clock to io_fifo flags. 0.61 0.77 0.77 ns setup/hold t cck_d /t ckc_d d inputs to wrclk. 0.51/0.02 0.58/0.02 0.58/0.02 ns t iffcck_wren / t iffckc_wren wren to wrclk. 0.47/?0.01 0.53/?0.01 0.53/?0.01 ns t offcck_rden / t offckc_rden rden to rdclk. 0.58/0.02 0.66/0.02 0.66/0.02 ns minimum pulse width t pwh_io_fifo reset, rdclk, wrclk. 2.15 2.15 2.15 ns t pwl_io_fifo reset, rdclk, wrclk. 2.15 2.15 2.15 ns maximum frequency f max rdclk and wrclk. 200.00 200.00 200.00 mhz s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 27 clb switching characteristics table 27: clb switching characteristics symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l combinatorial delays t ilo an ? dn lut address to a. 0.11 0.13 0.13 ns, max t ilo_2 an ? dn lut address to amux/cmux. 0.30 0.36 0.36 ns, max t ilo_3 an ? dn lut address to bmux_a. 0.46 0.55 0.55 ns, max t ito an ? dn inputs to a ? d q outputs. 1.05 1.27 1.27 ns, max t axa ax inputs to amux output. 0.69 0.84 0.84 ns, max t axb ax inputs to bmux output. 0.66 0.83 0.83 ns, max t axc ax inputs to cmux output. 0.68 0.82 0.82 ns, max t axd ax inputs to dmux output. 0.75 0.90 0.90 ns, max t bxb bx inputs to bmux output. 0.57 0.69 0.69 ns, max t bxd bx inputs to dmux output. 0.69 0.82 0.82 ns, max t cxc cx inputs to cmux output. 0.48 0.58 0.58 ns, max t cxd cx inputs to dmux output. 0.59 0.71 0.71 ns, max t dxd dx inputs to dmux output. 0.58 0.70 0.70 ns, max sequential delays t cko clock to aq ? dq outputs. 0.44 0.53 0.53 ns, max t shcko clock to amux ? dmux outputs. 0.53 0.66 0.66 ns, max setup and hold times of clb flip-flops before/after clock clk t as /t ah an ? dn input to clk on a ? d flip-flops. 0.09/0.14 0.11/0.18 0.11/0.18 ns, min t dick /t ckdi ax ? dx input to clk on a ? d flip-flops. 0.07/0.21 0.09/0.26 0.09/0.26 ns, min ax ? dx input through muxs and/or carry logic to clk on a ? d flip-flops. 0.66/0.09 0.81/0.11 0.81/0.11 ns, min t ceck_clb / t ckce_clb ce input to clk on a ? d flip-flops. 0.17/0.00 0.21/0.01 0.21/0.01 ns, min t srck /t cksr sr input to clk on a ? d flip-flops. 0.43/0.04 0.53/0.05 0.53/0.05 ns, min set/reset t srmin sr input minimum pulse width. 0.78 1.04 1.04 ns, min t rq delay from sr input to aq ? dq flip-flops. 0.59 0.71 0.71 ns, max t ceo delay from ce input to aq ? dq flip-flops. 0.58 0.70 0.70 ns, max f tog toggle frequency (for expo rt control). 128610981098mhz s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 28 clb distributed ram switching characteristics (slicem only) clb shift register switching characteristics (slicem only) table 28: clb distributed ram switching characteristics symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l sequential delays t shcko clock to a ? b outputs. 1.09 1.32 1.32 ns, max t shcko_1 clock to amux ? bmux outputs. 1.53 1.86 1.86 ns, max setup and hold times before/after clock clk t ds_lram /t dh_lram a ? d inputs to clk. 0.60/0.30 0.72/0.35 0.72/0.35 ns, min t as_lram /t ah_lram address an inputs to clock. 0.30/0.60 0.37/0.70 0.37/0.70 ns, min address an inputs through muxs and/or carry logic to clock. 0.77/0.21 0.94/0.26 0.94/0.26 ns, min t ws_lram /t wh_lram we input to clock. 0.43/0.12 0.53/0.17 0.53/0.17 ns, min t ceck_lram /t ckce_lram ce input to clk. 0.44/0.11 0.53/0.17 0.53/0.17 ns, min clock clk t mpw_lram minimum pulse width. 1.13 1.25 1.25 ns, min t mcp minimum clock period. 2 .262.502.50ns, min notes: 1. t shcko also represents the clk to xmux output. refer to the timing report for the clk to xmux path. table 29: clb shift register switching characteristics symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l sequential delays t reg clock to a ? d outputs. 1.33 1.61 1.61 ns, max t reg_mux clock to amux ? dmux output. 1.77 2.15 2.15 ns, max t reg_m31 clock to dmux output via m3 1 output. 1.23 1.46 1.46 ns, max setup and hold times before/after clock clk t ws_shfreg / t wh_shfreg we input. 0.41/0.12 0.51/0.17 0.51/0.17 ns, min t ceck_shfreg / t ckce_shfreg ce input to clk. 0.42/0.11 0.52/0.17 0.52/0.17 ns, min t ds_shfreg / t dh_shfreg a ? d inputs to clk. 0.37/0.37 0.44/0.43 0.44/0.43 ns, min clock clk t mpw_shfreg minimum pulse width. 0.86 0.98 0.98 ns, min s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 29 block ram and fifo switching characteristics table 30: block ram and fifo switching characteristics symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l block ram and fifo clock-to-out delays t rcko_do and t rcko_do_reg clock clk to dout output (without output register). (1)(2) 2.13 2.46 2.46 ns, max clock clk to dout output (with output register). (3)(4) 0.74 0.89 0.89 ns, max t rcko_do_ecc and t rcko_do_ecc_reg clock clk to dout output with ecc (without output register). (1)(2) 3.04 3.84 3.84 ns, max clock clk to dout output with ecc (with output register). (3)(4) 0.81 0.94 0.94 ns, max t rcko_do_cascout and t rcko_do_c ascout_reg clock clk to dout output with cascade (without output register). (1) 2.88 3.30 3.30 ns, max clock clk to dout output with cascade (with output register). (3) 1.28 1.46 1.46 ns, max t rcko_flags clock clk to fifo flags outputs. (5) 0.87 1.05 1.05 ns, max t rcko_pointers clock clk to fifo pointers outputs. (6) 1.02 1.15 1.15 ns, max t rcko_parity_ecc clock clk to eccparity in ecc encode only mode. 0.85 0.94 0.94 ns, max t rcko_sdbit_ecc and t rcko_sdbit_ecc_reg clock clk to biterr (without output register). 2.81 3.55 3.55 ns, max clock clk to biterr (with output register). 0.76 0.89 0.89 ns, max t rcko_rdaddr_ecc and t rcko_rdaddr_ecc_reg clock clk to rdaddr output with ecc (without output register). 0.88 1.07 1.07 ns, max clock clk to rdaddr output with ecc (with output register). 0.93 1.08 1.08 ns, max setup and hold times before/after clock clk t rcck_addra / t rckc_addra addr inputs. (7) 0.49/0.33 0.57/0.36 0.57/0.36 ns, min t rdck_di_wf_nc / t rckd_di_wf_nc data input setup/hold time when block ram is configured in write_first or no_change mode. (8) 0.65/0.63 0.74/0.67 0.74/0.67 ns, min t rdck_di_rf / t rckd_di_rf data input setup/hold time when block ram is configured in read_first mode. (8) 0.22/0.34 0.25/0.41 0.25/0.41 ns, min t rdck_di_ecc / t rckd_di_ecc din inputs with block ram ecc in standard mode. (8) 0.55/0.46 0.63/0.50 0.63/0.50 ns, min t rdck_di_eccw / t rckd_di_eccw din inputs with block ram ecc encode only. (8) 1.02/0.46 1.17/0.50 1.17/0.50 ns, min s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 30 t rdck_di_ecc_fifo / t rckd_di_ecc_fifo din inputs with fifo ecc in standard mode. (8) 1.15/0.59 1.32/0.64 1.32/0.64 ns, min t rcck_injectbiterr / t rckc_injectbiterr inject single/double bit error in ecc mode. 0.64/0.37 0.74/0.40 0.74/0.40 ns, min t rcck_en /t rckc_en block ram enable (en) input. 0.39/0.21 0.45/0.23 0.45/0.23 ns, min t rcck_regce / t rckc_regce ce input of output register. 0.29/0.15 0.36/0.16 0.36/0.16 ns, min t rcck_rstreg / t rckc_rstreg synchronous rstreg input. 0.32/0.07 0.35/0.07 0.35/0.07 ns, min t rcck_rstram / t rckc_rstram synchronous rstram input. 0.34/0.43 0.36/0.46 0.36/0.46 ns, min t rcck_wea /t rckc_wea write enable (we) input (block ram only). 0.48/0.19 0.54/0.20 0.54/0.20 ns, min t rcck_wren / t rckc_wren wren fifo inputs. 0.46/0.35 0.47/0.43 0.47/0.43 ns, min t rcck_rden / t rckc_rden rden fifo inputs. 0.43/0.35 0.43/0.43 0.43/0.43 ns, min reset delays t rco_flags reset rst to fifo flags/pointers. (9) 0.98 1.10 1.10 ns, max t rrec_rst /t rrem_rst fifo reset recovery and removal timing. (10) 2.07/?0.81 2.37/?0.81 2.37/?0.81 ns, max maximum frequency f max_bram_wf_nc block ram (write first and no change modes) when not in sdp rf mode. 460.83 388.20 388.20 mhz f max_bram_rf_ performance block ram (read first, performance mode) when in sdp rf mode but no address overlap between port a and port b. 460.83 388.20 388.20 mhz f max_bram_rf_ delayed_write block ram (read first, delayed write mode) when in sdp rf mode and there is possibility of overlap between port a and port b addresses. 404.53 339.67 339.67 mhz f max_cas_wf_nc block ram cascade (write first, no change mode) when cascade but not in rf mode. 418.59 345.78 345.78 mhz f max_cas_rf_ performance block ram cascade (read first, performance mode) when in cascade with rf mode and no possibility of address overlap/one port is disabled. 418.59 345.78 345.78 mhz table 30: block ram and fifo switching characteristics (cont?d) symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 31 f max_cas_rf_ delayed_write when in cascade rf mode and there is a possibility of address overlap between port a and port b. 362.19 297.35 297.35 mhz f max_fifo fifo in all modes without ecc. 460.83 388.20 388.20 mhz f max_ecc block ram and fifo in ecc configuration. 365.10 297.53 297.53 mhz notes: 1. t rcko_dor includes t rcko_dow , t rcko_dopr , and t rcko_dopw as well as the b port equivalent timing parameters. 2. these parameters also apply to synchronous fifo with do_reg = 0. 3. t rcko_do includes t rcko_dop as well as the b port equivalent timing parameters. 4. these parameters also apply to multi-rate (asy nchronous) and synchronous fifo with do_reg = 1. 5. t rcko_flags includes the following parameters: t rcko_aempty , t rcko_afull , t rcko_empty , t rcko_full , t rcko_rderr , t rcko_wrerr . 6. t rcko_pointers includes both t rcko_rdcount and t rcko_wrcount . 7. the addr setup and hold must be met when en is asserted (even when we is deasserted). otherwise, block ram data corruption is possible. 8. these parameters include both a and b inputs as well as the parity inputs of a and b. 9. t rco_flags includes the following flags: aempty, afull, empty, full, rderr, wrerr, rdcount, and wrcount. 10. rden and wren must be held low prior to and during reset. the fifo reset must be asserted for at least five positive clock e dges of the slowest clock (wrclk or rdclk). table 30: block ram and fifo switching characteristics (cont?d) symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 32 dsp48e1 switching characteristics table 31: dsp48e1 switching characteristics symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l setup and hold times of data/control pins to the input register clock t dspdck_a_areg / t dspckd_a_areg a input to a register clk. 0.30/ 0.13 0.37/ 0.14 0.37/ 0.14 ns t dspdck_b_breg / t dspckd_b_breg b input to b register clk. 0.38/ 0.16 0.45/ 0.18 0.45/ 0.18 ns t dspdck_c_creg / t dspckd_c_creg c input to c register clk. 0.20/ 0.19 0.24/ 0.21 0.24/ 0.21 ns t dspdck_d_dreg / t dspckd_d_dreg d input to d register clk. 0.32/ 0.27 0.42/ 0.27 0.42/ 0.27 ns t dspdck_acin_areg / t dspckd_acin_areg acin input to a register clk. 0.27/ 0.13 0.32/ 0.14 0.32/ 0.14 ns t dspdck_bcin_breg / t dspckd_bcin_breg bcin input to b register clk. 0.29/ 0.16 0.36/ 0.18 0.36/ 0.18 ns setup and hold times of data pins to the pipeline register clock t dspdck_{a, b}_mreg_mult / t dspckd_{a, b}_mreg_mult {a, b} input to m register clk using multiplier. 2.76/ ?0.01 3.29/ ?0.01 3.29/ ?0.01 ns t dspdck_{a, d}_adreg / t dspckd_{a, d}_adreg {a, d} input to ad register clk. 1.48/ ?0.02 1.76/ ?0.02 1.76/ ?0.02 ns setup and hold times of data/control pins to the output register clock t dspdck_{a, b}_preg_mult / t dspckd_{a, b} _preg_mult {a, b} input to p register clk using multiplier. 4.60/ ?0.28 5.48/ ?0.28 5.48/ ?0.28 ns t dspdck_d_preg_mult / t dspckd_d_preg_mult d input to p register clk using multiplier. 4.50/ ?0.73 5.35/ ?0.73 5.35/ ?0.73 ns t dspdck_{a, b} _preg / t dspckd_{a, b} _preg a or b input to p register clk not using multiplier. 1.98/ ?0.28 2.35/ ?0.28 2.35/ ?0.28 ns t dspdck_c_preg / t dspckd_c_preg c input to p register clk not using multiplier. 1.76/ ?0.26 2.10/ ?0.26 2.10/ ?0.26 ns t dspdck_pcin_preg / t dspckd_pcin_preg pcin input to p register clk. 1.51/ ?0.15 1.80/ ?0.15 1.80/ ?0.15 ns setup and hold times of the ce pins t dspdck_{cea;ceb}_{areg;breg} / t dspckd_{cea;ceb}_{areg;breg} {cea; ceb} input to {a; b} register clk. 0.42/ 0.08 0.52/ 0.11 0.52/ 0.11 ns t dspdck_cec_creg / t dspckd_cec_creg cec input to c register clk. 0.34/ 0.11 0.42/ 0.13 0.42/ 0.13 ns t dspdck_ced_dreg / t dspckd_ced_dreg ced input to d register clk. 0.43/ ?0.03 0.52/ ?0.03 0.52/ ?0.03 ns s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 33 t dspdck_cem_mreg / t dspckd_cem_mreg cem input to m register clk. 0.21/ 0.20 0.27/ 0.23 0.27/ 0.23 ns t dspdck_cep_preg / t dspckd_cep_preg cep input to p register clk. 0.43/ 0.01 0.53/ 0.01 0.53/ 0.01 ns setup and hold times of the rst pins t dspdck_{rsta; rstb }_{areg; breg} / t dspckd_{rsta; rstb }_{areg; breg} {rsta, rstb} input to {a, b} register clk. 0.46/ 0.13 0.55/ 0.15 0.55/ 0.15 ns t dspdck_rstc_creg / t dspckd_rstc_creg rstc input to c register clk. 0.08/ 0.11 0.09/ 0.12 0.09/ 0.12 ns t dspdck_rstd_dreg / t dspckd_rstd_dreg rstd input to d register clk 0.50/ 0.08 0.59/ 0.09 0.59/ 0.09 ns t dspdck_rstm_mreg / t dspckd_rstm_mreg rstm input to m register clk 0.23/ 0.24 0.27/ 0.28 0.27/ 0.28 ns t dspdck_rstp_preg / t dspckd_rstp_preg rstp input to p register clk 0.30/ 0.01 0.35/ 0.01 0.35/ 0.01 ns combinatorial delays from input pins to output pins t dspdo_a_carryout_mult a input to carryout output using multiplier. 4.35 5.18 5.18 ns t dspdo_d_p_mult d input to p output using multiplier. 4.26 5.07 5.07 ns t dspdo_b_p b input to p output not using multiplier. 1.75 2.08 2.08 ns t dspdo_c_p c input to p output. 1.53 1.82 1.82 ns combinatorial delays from input pins to cascading output pins t dspdo_{a; b}_{acout; bcout} {a, b} input to {acout, bcout} output. 0.63 0.74 0.74 ns t dspdo_{a, b}_ca rrycascout_mult {a, b} input to carrycascout output using multiplier. 4.65 5.54 5.54 ns t dspdo_d_carrycascout_mult d input to carrycascout output using multiplier. 4.54 5.40 5.40 ns t dspdo_{a, b}_c arrycascout {a, b} input to carrycascout output not using multiplier. 2.03 2.41 2.41 ns t dspdo_c_carrycascout c input to carrycascout output. 1.81 2.15 2.15 ns combinatorial delays from cascadin g input pins to all output pins t dspdo_acin_p_mult acin input to p output using multiplier. 4.19 5.00 5.00 ns t dspdo_acin_p acin input to p output not using multiplier. 1.57 1.88 1.88 ns t dspdo_acin_acout acin input to acout output. 0.44 0.53 0.53 ns t dspdo_acin_carrycascout_mult acin input to carrycascout output using multiplier. 4.47 5.33 5.33 ns t dspdo_acin_carrycascout acin input to carrycascout output not using multiplier. 1.85 2.21 2.21 ns t dspdo_pcin_p pcin input to p output. 1.28 1.52 1.52 ns table 31: dsp48e1 switching characteristics (cont?d) symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 34 t dspdo_pcin_carrycascout pcin input to carrycascout output. 1.56 1.85 1.85 ns clock to outs from output register clock to output pins t dspcko_p_preg clk preg to p output. 0.37 0.44 0.44 ns t dspcko_carrycascout_preg clk preg to carrycascout output. 0.59 0.69 0.69 ns clock to outs from pipeline register clock to output pins t dspcko_p_mreg clk mreg to p output. 1.93 2.31 2.31 ns t dspcko_carry cascout_mreg clk mreg to carrycascout output. 2.21 2.64 2.64 ns t dspcko_p_adreg_mult clk adreg to p output using multiplier. 3.10 3.69 3.69 ns t dspcko_carrycasc out_adreg_mult clk adreg to carrycascout output using multiplier. 3.38 4.02 4.02 ns clock to outs from input register clock to output pins t dspcko_p_areg_mult clk areg to p output using multiplier. 4.51 5.37 5.37 ns t dspcko_p_breg clk breg to p output not using multiplier. 1.87 2.22 2.22 ns t dspcko_p_creg clk creg to p output not using multiplier. 1.93 2.30 2.30 ns t dspcko_p_dreg_mult clk dreg to p output using multiplier. 4.48 5.32 5.32 ns clock to outs from input register clock to cascading output pins t dspcko_{acout; bcout}_ {areg; breg} clk (acout, bcout) to {a,b} register output. 0.73 0.87 0.87 ns t dspcko_ca rrycascout_ {areg, breg}_mult clk (areg, breg) to carrycascout output using multiplier. 4.79 5.70 5.70 ns t dspcko_carryca scout_ breg clk breg to carrycascout output not using multiplier. 2.15 2.55 2.55 ns t dspcko_carrycascout_ dreg_mult clk dreg to carrycascout output using multiplier. 4.76 5.65 5.65 ns t dspcko_carryca scout_ creg clk creg to carrycascout output. 2.21 2.63 2.63 ns maximum frequency f max with all registers used. 550.66 464.25 464.25 mhz f max_patdet with pattern detector. 465.77 392.93 392.93 mhz f max_mult_nomreg two register multiply without mreg. 305.62 257.47 257.47 mhz f max_mult_nomreg_patdet two register multiply without mreg with pattern detect. 277.62 233.92 233.92 mhz f max_preadd_mult_noadreg without adreg. 346.26 290.44 290.44 mhz f max_preadd_mult_noadreg_patdet without adreg with pattern detect. 346.26 290.44 290.44 mhz f max_nopipelinereg without pipeline registers (mreg, adreg). 227.01 190.69 190.69 mhz f max_nopipelinereg_patdet without pipeline registers (mreg, adreg) with pattern detect. 211.15 177.43 177.43 mhz table 31: dsp48e1 switching characteristics (cont?d) symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 35 clock buffers and networks table 32: global clock switching characteristics (including bufgctrl) symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l t bccck_ce /t bcckc_ce (1) ce pins setup/hold. 0.13/0.40 0.16/0.41 0.16/0.41 ns t bccck_s / t bcckc_s (1) s pins setup/hold. 0.13/0.40 0.16/0.41 0.16/0.41 ns t bccko_o (2) bufgctrl delay from i0/i1 to o. 0.09 0.10 0.10 ns maximum frequency f max_bufg global clock tr ee (bufg). 628.00 464.00 464.00 mhz notes: 1. t bccck_ce and t bcckc_ce must be satisfied to assure glitch-free operation of the global clock when switching between clocks. these parameters do not apply to the bufgmux primitive that assures gl itch-free operation. the other gl obal clock setup and hold time s are optional; only needing to be satisfied if device operation requ ires simulation matches on a cy cle-for-cycle basis when switchin g between clocks. 2. t bgcko_o (bufg delay from i0 to o) values are the same as t bccko_o values. table 33: input/output clock switching characteristics (bufio) symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l t biocko_o clock to out delay from i to o. 1.26 1.54 1.54 ns maximum frequency f max_bufio i/o clock tree (bufio). 680.00 600.00 600.00 mhz table 34: regional clock buffer switching characteristics (bufr) symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l t brcko_o clock to out delay from i to o. 0.76 0.99 0.99 ns t brcko_o_byp clock to out delay from i to o with divide bypass attribute set. 0.39 0.52 0.52 ns t brdo_o propagation delay from clr to o. 0.85 1.09 1.09 ns maximum frequency f max_bufr (1) regional clock tree (bufr). 375.00 315.00 315.00 mhz notes: 1. the maximum input frequency to the bufr and bufmr is the bufio f max frequency. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 36 table 35: horizontal clock buffer switching characteristics (bufh) symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l t bhcko_o bufh delay from i to o. 0.11 0.13 0.13 ns t bhcck_ce / t bhckc_ce ce pin setup and hold. 0.22/0.15 0.28/0.21 0.28/0.21 ns maximum frequency f max_bufh horizontal clock buffer (bufh). 628.00 464.00 464.00 mhz table 36: duty cycle distortion and clock-tree skew symbol description device v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l t dcd_clk global clock tree duty -cycle distortion. (1) all 0.20 0.20 0.20 ns t ckskew global clock tree skew. (2) xc7s6 0.05 0.06 0.06 ns xc7s15 0.05 0.06 0.06 ns xc7s25 0.26 0.26 0.26 ns XC7S50 0.26 0.26 0.26 ns xc7s75 0.33 0.36 0.36 ns xc7s100 0.33 0.36 0.36 ns t dcd_bufio i/o clock tree duty cycle distortion. all 0.14 0.14 0.14 ns t bufioskew i/o clock tree skew across one clock region. all 0.03 0.03 0.03 ns t dcd_bufr regional clock tree duty cycle distortion. all 0.18 0.18 0.18 ns notes: 1. these parameters represent the worst-case duty cycle distortion observable at the i/o flip flops. for all i/o standards, ibis can be used to calculate any additional duty cycl e distortion that might be caused by asymmetrical rise/fall times. 2. the t ckskew value represents the worst-case clock-tree skew observable be tween sequential i/o elements. significantly less clock-tree skew exists for i/o registers that are close to each other and fed by the same or adjacent clock-tree branches. use the xilinx timin g analysis tools to evaluate clock skew spec ific to your application. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 37 mmcm switching characteristics table 37: mmcm specification symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l mmcm_f inmax maximum input clock frequency. 800.00 800.00 800.00 mhz mmcm_f inmin minimum input clock frequency. 10.00 10.00 10.00 mhz mmcm_f injitter maximum input clock period jitter. < 20% of clock input period or 1 ns max mmcm_f induty allowable input duty cycle: 10?49 mhz. 25 25 25 % allowable input duty cycle: 50?199 mhz. 30 30 30 % allowable input duty cycle: 200?399 mhz. 35 35 35 % allowable input duty cycle: 400?499 mhz. 40 40 40 % allowable input duty cycle: > 500 mhz. 45 45 45 % mmcm_f min_psclk minimum dynamic phase-shift clock frequency. 0.01 0.01 0.01 mhz mmcm_f max_psclk maximum dynamic phase-shift clock frequency. 500.00 450.00 450.00 mhz mmcm_f vcomin minimum mmcm vco frequency. 600.00 600.00 600.00 mhz mmcm_f vcomax maximum mmcm vco frequency. 1440.00 1200.00 1200.00 mhz mmcm_f bandwidth low mmcm bandwidth at typical. (1) 1.00 1.00 1.00 mhz high mmcm bandwidth at typical. (1) 4.00 4.00 4.00 mhz mmcm_t statphaoffset static phase offset of the mmcm outputs. (2) 0.12 0.12 0.12 ns mmcm_t outjitter mmcm output jitter. note 3 mmcm_t outduty mmcm output clock duty-cycle precision. (4) 0.20 0.20 0.20 ns mmcm_t lockmax mmcm maximum lock time. 100.00 100.00 100.00 s mmcm_f outmax mmcm maximum output frequency. 800.00 800.00 800.00 mhz mmcm_f outmin mmcm minimum output frequency. (5)(6) 4.69 4.69 4.69 mhz mmcm_t extfdvar external clock feedback va riation. < 20% of clock in put period or 1 ns max mmcm_rst minpulse minimum reset pulse width. 5.00 5.00 5.00 ns mmcm_f pfdmax maximum frequenc y at the phase frequency detector. 500.00 450.00 450.00 mhz mmcm_f pfdmin minimum frequency at the phase frequency detector. 10.00 10.00 10.00 mhz mmcm_t fbdelay maximum delay in the feedback path. 3 ns max or one clkin cycle mmcm switching characteristics setup and hold t mmcmdck_psen / t mmcmckd_psen setup and hold of phase-shift enable. 1.04/0.00 1.04/0.00 1.04/0.00 ns s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 38 pll switching characteristics t mmcmdck_psincdec / t mmcmckd_psincdec setup and hold of phase-shift increment/decrement. 1.04/0.00 1.04/0.00 1.04/0.00 ns t mmcmcko_psdone phase shift clock-to-out of psdone. 0.680.810.81 ns dynamic reconfiguration port (drp) for mmcm before and after dclk t mmcmdck_daddr / t mmcmckd_daddr daddr setup/hold. 1.40/0.15 1.63/0.15 1.63/0.15 ns, min t mmcmdck_di / t mmcmckd_di di setup/hold. 1.40/0.15 1.63/0.15 1.63/0.15 ns, min t mmcmdck_den / t mmcmckd_den den setup/hold. 1.97/0.00 2.29/0.00 2.29/0.00 ns, min t mmcmdck_dwe / t mmcmckd_dwe dwe setup/hold. 1.40/0.15 1.63/0.15 1.63/0.15 ns, min t mmcmcko_drdy clk to out of drdy. 0.72 0.99 0.99 ns, max f dck dclk frequency. 200.00 200.00 200.00 mhz, max notes: 1. the mmcm does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequen cies. 2. the static offset is measured between any mmcm outputs with identical phase. 3. values for this parameter are available in the clocking wizard [ref 7] . 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. 6. when clkout4_cas cade = true, mmcm_f outmin is 0.036 mhz. table 38: pll specification symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l pll_f inmax maximum input clock frequency. 800.00 800.00 800.00 mhz pll_f inmin minimum input clock frequency. 19.00 19.00 19.00 mhz pll_f injitter maximum input clock period jitter. < 20 % of clock input period or 1 ns max pll_f induty allowable input duty cycle: 19?49 mhz. 25 25 25 % allowable input duty cycle: 50?199 mhz. 30 30 30 % allowable input duty cycle: 200?399 mhz. 35 35 35 % allowable input duty cycle: 400?499 mhz. 40 40 40 % allowable input duty cycle: >500 mhz. 45 45 45 % pll_f vcomin minimum pll vco frequency. 800.00 800.00 800.00 mhz pll_f vcomax maximum pll vco frequency. 1866.00 1600.00 1600.00 mhz table 37: mmcm specification (cont?d) symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 39 pll_f bandwidth low pll bandwidth at typical. 1.00 1.00 1.00 mhz high pll bandwidth at typical. (1) 4.00 4.00 4.00 mhz pll_t statphaoffset static phase offset of the pll outputs. (2) 0.12 0.12 0.12 ns pll_t outjitter pll output jitter. note 3 pll_t outduty pll output clock duty-cycle precision. (4) 0.20 0.20 0.20 ns pll_t lockmax pll maximum lock time. 100.00 100.00 100.00 s pll_f outmax pll maximum output freque ncy. 800.00 800.00 800.00 mhz pll_f outmin pll minimum output frequency. (5) 6.25 6.25 6.25 mhz pll_t extfdvar external clock feedback va riation. < 20% of clock input period or 1 ns max pll_rst minpulse minimum reset pulse width. 5.00 5.00 5.00 ns pll_f pfdmax maximum frequency at the phase frequency detector. 500.00 450.00 450.00 mhz pll_f pfdmin minimum frequency at the phase frequency detector. 19.00 19.00 19.00 mhz pll_t fbdelay maximum delay in the feedback path. 3 ns max or one clkin cycle dynamic reconfiguration port (drp) for pll before and after dclk t plldck_daddr / t pllckd_daddr setup and hold of d address. 1.40/0.15 1.63/0.15 1.63/0.15 ns, min t plldck_di / t pllckd_di setup and hold of d input. 1.40/0.15 1.63/0.15 1.63/0.15 ns, min t plldck_den / t pllckd_den setup and hold of d enable. 1.97/0.00 2.29/0.00 2.29/0.00 ns, min t plldck_dwe / t pllckd_dwe setup and hold of d write enable. 1.40/0.15 1.63/0.15 1.63/0.15 ns, min t pllcko_drdy clk to out of drdy. 0.72 0.99 0.99 ns, max f dck dclk frequency. 200.00 200.00 200.00 mhz, max notes: 1. the pll does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequenc ies. 2. the static offset is measured between any pll outputs with identical phase. 3. values for this parameter are available in the clocking wizard [ref 7] . 4. includes global clock buffer. 5. calculated as fvco/128 assumi ng output duty cycle is 50%. table 38: pll specification symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 40 device pin-to-pin output parameter guidelines table 39: clock-capable clock input to output de lay without mmcm/pll (near clock region) (1) symbol description device v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l sstl15 clock-capable clock input to output de lay using output flip-flop, fast slew rate, without mmcm/pll. t ickof clock-capable clock input and outff at pins/banks closest to the bufgs without mmcm/pll (near clock region). (2) xc7s6 5.556.506.50ns xc7s15 5.55 6.50 6.50 ns xc7s25 5.55 6.44 6.44 ns XC7S50 5.71 6.62 6.62 ns xc7s75 5.73 6.71 6.71 ns xc7s1005.736.716.71ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops ar e clocked by the global clock net. 2. refer to the die level bank numbering overview section of the 7 series fpga packaging and pinout specification (ug475) [ref 3] . table 40: clock-capable clock input to output de lay without mmcm/pll (far clock region) (1) symbol description device v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l sstl15 clock-capable clock input to output de lay using output flip-flop, fast slew rate, without mmcm/pll. t ickoffar clock-capable clock input and outff at pins/banks farthest from the bufgs without mmcm/pll (far clock region). (2) xc7s6 5.55 6.50 6.50 ns xc7s15 5.55 6.50 6.50 ns xc7s25 5.55 6.44 6.44 ns XC7S50 5.71 6.62 6.62 ns xc7s75 6.01 7.02 7.02 ns xc7s100 6.01 7.02 7.02 ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops ar e clocked by the global clock net. 2. refer to the die level bank numbering overview section of the 7 series fpga packaging and pinout specification (ug475) [ref 3] . s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 41 table 41: clock-capable clock input to output delay with mmcm (1) symbol description device v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l sstl15 clock-capable clock input to output de lay using output flip-flop, fast slew rate, with mmcm. t ickofmmcmcc clock-capable clock input and outff with mmcm. (2) xc7s6 1.03 1.03 1.03 ns xc7s15 1.03 1.03 1.03 ns xc7s25 1.00 1.00 1.00 ns XC7S50 1.00 1.00 1.00 ns xc7s75 1.00 1.00 1.00 ns xc7s100 1.00 1.00 1.00 ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops ar e clocked by the global clock net. 2. mmcm output jitter is already included in the timing calculation. table 42: clock-capable clock input to output delay with pll (1) symbol description device v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l sstl15 clock-capable clock input to output de lay using output flip-flop, fast slew rate, with pll. t ickofpllcc clock-capable clock input and outff with pll. (2) xc7s6 0.85 0.85 0.85 ns xc7s15 0.85 0.85 0.85 ns xc7s25 0.83 0.83 0.83 ns XC7S50 0.83 0.83 0.83 ns xc7s75 0.83 0.83 0.83 ns xc7s100 0.83 0.83 0.83 ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops ar e clocked by the global clock net. 2. pll output jitter is already included in the timing calculation. table 43: pin-to-pin, clock-to-out using bufio symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l sstl15 clock-capable clock input to output delay us ing output flip-flop, fast slew rate, with bufio. t ickofcs clock to out of i/o clock. 5.61 6.64 6.64 ns s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 42 device pin-to-pin input parameter guidelines all devices are 100% functionally tested. values are expressed in nanoseco nds unless otherwise noted. table 44: global clock input setup and hold without mmcm/pll with zhold_delay on hr i/o banks symbol description device v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l input setup and hold time relative to global clock input signal for sstl15 standard. (1) t psfd / t phfd full delay (legacy delay or default delay) global clock input and iff (2) without mmcm/pll with zhold_delay on hr i/o banks. xc7s6 2.76/?0.43 3.17/?0.43 3.17/?0.43 ns xc7s15 2.76/?0.43 3.17/?0.43 3.17/?0.43 ns xc7s25 2.66/?0.41 3.11/?0.41 3.11/?0.41 ns XC7S50 2.66/?0.41 3.11/?0.41 3.11/?0.41 ns xc7s75 2.91/?0.37 3.36/?0.37 3.36/?0.37 ns xc7s100 2.91/?0.37 3.36/?0.37 3.36/?0.37 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the gl obal clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch. table 45: clock-capable clock input setup and hold with mmcm symbol description device v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l input setup and hold time relative to global clock input signal for sstl15 standard. (1)(2) t psmmcmcc / t phmmcmcc no delay clock-capable clock input and iff (3) with mmcm. xc7s6 2.73/?0.59 3.27/?0.59 3.27/?0.59 ns xc7s15 2.73/?0.59 3.27/?0.59 3.27/?0.59 ns xc7s25 2.69/?0.61 3.21/?0.61 3.21/?0.61 ns XC7S50 2.80/?0.62 3.35/?0.62 3.35/?0.62 ns xc7s75 2.81/?0.62 3.36/?0.62 3.36/?0.62 ns xc7s100 2.81/?0.62 3.36/?0.62 3.36/?0.62 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the gl obal clock input signal using the fastest process, lowest temperature, and highest voltage. 2. use ibis to determine any duty-cycle distortion incurred using various standards. 3. iff = input flip-flop or latch. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 43 table 46: clock-capable clock input setup and hold with pll symbol description device v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l input setup and hold time relative to clock-capable clock input signal for sstl15 standard. (1)(2) t pspllcc / t phpllcc no delay clock-capable clock input and iff (3) with pll. xc7s6 3.07/?0.17 3.69/?0.17 3.69/?0.17 ns xc7s15 3.07/?0.17 3.69/?0.17 3.69/?0.17 ns xc7s25 3.04/?0.19 3.63/?0.19 3.63/?0.19 ns XC7S50 3.15/?0.19 3.77/?0.19 3.77/?0.19 ns xc7s75 3.15/?0.19 3.78/?0.19 3.78/?0.19 ns xc7s100 3.15/?0.19 3.78/?0.19 3.78/?0.19 ns notes: 1. setup and hold times are measured over wo rst case conditions (process, voltage, temp erature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the gl obal clock input signal using the fastest process, lowest temperature, and highest voltage. 2. use ibis to determine any duty-cycle distortion incurred using various standards. 3. iff = input flip-flop or latch. table 47: data input setup and hold times relative to a forwarded clock input pin using bufio symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l input setup and hold time relative to a forwarded clock input pin using bufio for sstl15 standard. t pscs /t phcs setup and hold of i/o clock. ?0.38/1.46 ?0.38/1.73 ?0.38/1.76 ns table 48: sample window symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l t samp sampling error at receiver pins. (1) 0.64 0.70 0.70 ns t samp_bufio sampling error at receiver pins using bufio. (2) 0.40 0.46 0.46 ns notes: 1. this parameter indicates the total sampling error of the sparta n-7 fpgas ddr input registers, measured across voltage, temper ature, and process. the characterization methodology uses the mmcm to captur e the ddr input registers? edges of operation. these measureme nts include: - clk0 mmcm jitter - mmcm accuracy (phase offset) - mmcm phase shift resolution these measurements do not include package or clock tree skew. 2. this parameter indicates the total sampling error of the sparta n-7 fpgas ddr input registers, measured across voltage, temper ature, and process. the characterization me thodology uses the bufio clock network and idelay to capture the ddr input registers? edges of operation. these measurements do not include package or clock tree skew. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 44 additional package parameter guidelines the parameters in this section provide the necessary values for calculating timi ng budgets for spartan-7 fpga clock transmitter and re ceiver data-valid windows. table 49: package skew (1) symbol description device package value units t pkgskew package skew. (2) xc7s6 cpga196 ps csga225 ps tqga144 ps xc7s15 cpga196 ps csga225 ps tqga144 ps xc7s25 csga225 ps csga324 ps tqga144 ps XC7S50 csga324 ps fgga484 ps xc7s75 fgga484 ps fgga676 ps xc7s100 fgga484 ps fgga676 ps notes: 1. package delay information is available for these device/package combinations. this information can be used to deskew the pack age. 2. these values represent the worst-case skew between any two selectio resources in the package: shortest delay to longest delay from die pad to ball. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 45 xadc specifications the 7 series fpgas overview (ds180) [ref 1] lists the devices that cont ain a 7 series xadc dual 12-bit 1 msps analog-to-digital converter. table 50: xadc specifications parameter symbol comments/conditions min typ max units v ccadc = 1.8v 5%, v refp = 1.25v, v refn = 0v, adcclk = 26 mhz, ?55c t j 125c. typical values at t j = +40c. adc accuracy (1) resolution 12 ? ? bits integral nonlinearity (2) inl ?40c t j 100c ? ? 2 lsbs ?55c t j < ?40c; 100c < t j 125c ? ? 3 lsbs differential nonlinearity dnl no missing codes, guaranteed monotonic. ? ? 1 lsbs offset error unipolar ?40c t j 100c ? ? 8 lsbs ?55c t j < ?40c; 100c < t j 125c ? ? 12 lsbs bipolar ?55c t j 125c ? ? 4 lsbs gain error ??0.5% offset matching ??4lsbs gain matching ??0.3% sample rate ??1ms/s signal to noise ratio (2) snr f sample = 500 ks/s, f in = 20 khz 60 ? ? db rms code noise external 1.25v reference. ? ? 2 lsbs on-chip reference. ? 3 ? lsbs total harmonic distortion (2) thd f sample = 500 ks/s, f in = 20 khz 70 ? ? db analog inputs (3) adc input ranges unipolar operation. 0 ? 1 v bipolar operation. ?0.5 ? +0.5 v unipolar common mode range (fs input). 0 ? +0.5 v bipolar common mode range (fs input). +0.5 ? +0.6 v maximum external channel input ranges adjacent analog channels set within these ranges should not corrupt measurements on adjacent channels. ?0.1 ? v ccadc v full-resolution bandwidth frbw auxiliary channel full resolution bandwidth. 250 ? ? khz on-chip sensors temperature sensor error ?40c t j 100c ? ? 4 c ?55c t j < ?40c; 100c < t j 125c ? ? 6 c supply sensor error ?40c t j 100c ? ? 1 % ?55c t j < ?40c; 100c < t j 125c ? ? 2 % s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 46 conversion rate (4) conversion time: continuous t conv number of adcclk cycles. 26 ? 32 cycles conversion time: event t conv number of clk cycles. ? ? 21 cycles drp clock frequency dclk drp clock frequency. 8 ? 250 mhz adc clock frequency adcclk derived from dclk. 1 ? 26 mhz dclk duty cycle 40 ? 60 % xadc reference (5) external reference v refp externally supplied reference voltage. 1.20 1.25 1.30 v on-chip reference ground v refp pin to agnd, ?40c t j 100c 1.2375 1.25 1.2625 v ground vrefp pin to agnd, ?55c t j < ?40c; 100c < t j 125c 1.2251.251.275 v notes: 1. offset and gain errors are removed by enabling the xadc automa tic gain calibration feature. the values are specified for when this feature is enabled. 2. only specified for bitstream op tion xadcenhancedlinearity = on. 3. for a detailed description, see the adc chapter in the 7 series fpgas and zynq-7000 ap soc xadc dual 12-bit 1 msps analog-to-digital converter user guide (ug480) [ref 8] . 4. for a detailed description, see the timing chapter in the 7 series fpgas and zynq-7000 ap soc xadc dual 12-bit 1 msps analog-to-digital converter user guide (ug480) [ref 8] . 5. any variation in the reference voltage from the nominal v refp = 1.25v and v refn = 0v will result in a deviation from the ideal transfer function. this also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). however, for external ratiometric type applications allowing reference to vary by 4% is permitted. table 50: xadc specifications (cont?d) parameter symbol comments/conditions min typ max units s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 47 configuration switching characteristics table 51: configuration switching characteristics symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l power-up timing characteristics t pl (1) program latency. 5.00 5.00 5.00 ms, max t por (1) power-on reset (50 ms ramp rate time). 10/50 10/50 10/50 ms, min/max power-on reset (1 ms ramp rate time). 10/35 10/35 10/35 ms, min/max t program program pulse width. 250.00 250.00 250.00 ns, min cclk output (master mode) t icck master cclk output delay. 150.00 150.00 150.00 ns, min t mcckl master cclk clock low time duty cycle. 40/60 40/60 40/60 %, min/max t mcckh master cclk clock high time duty cycle. 40/60 40/60 40/60 %, min/max f mcck master cclk frequency. 100.00 100.00 100.00 mhz, max master cclk frequency for aes encrypted x16. (2) 50.00 50.00 50.00 mhz, max f mcck_start master cclk frequency at start of configuration. 3.00 3.00 3.00 mhz, typ f mccktol frequency tolerance, master mode with respect to nominal cclk. 50 50 50 %, max cclk input (slave modes) t scckl slave cclk clock minimum low time. 2.50 2.50 2.50 ns, min t scckh slave cclk clock minimum high time. 2.50 2.50 2.50 ns, min f scck slave cclk frequency. 100.00 100.00 100.00 mhz, max emcclk input (master mode) t emcckl external master cclk low time. 2.50 2.50 2.50 ns, min t emcckh external master cclk high time. 2.50 2.50 2.50 ns, min f emcck external master cclk frequency. 100.00 100.00 100.00 mhz, max internal configuration access port f icapck internal configuration acce ss port (icape2) clock frequency. 100.00 100.00 100.00 mhz, max master/slave serial mode programming switching t dcck / t cckd d in setup/hold. 4.00/0.00 4.00/0.00 4.00/0.00 ns, min t cco d out clock to out. 8.00 8.00 8.00 ns, max selectmap mode programming switching t smdcck / t smcckd d[31:00] setup/hold. 4.00/0.00 4.00/0.00 4.00/0.00 ns, min s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 48 t smcscck / t smcckcs csi_b setup/hold. 4.00/0.00 4.00/0.00 4.00/0.00 ns, min t smwcck / t smcckw rdwr_b setup/hold. 10.00/0.00 10.00/0.00 10.00/0.00 ns, min t smckcso cso_b clock to out (330 pull-up resistor required). 7.00 7.00 7.00 ns, max t smco d[31:00] clock to out in readback. 8.00 8.00 8.00 ns, max f rbcck readback frequency. 100.00 100.00 100.00 mhz, max boundary-scan port timing specifications t taptck / t tcktap tms and tdi setup/hold. 3.00/2.00 3.00/2.00 3.00/2.00 ns, min t tcktdo tck falling edge to tdo output. 7.00 7.00 7.00 ns, max f tck tck frequency. 66.00 66.00 66.00 mhz, max spi flash master mode programming switching t spidcc / t spiccd d[03:00] setup/hold. 3.00/0.00 3.00/0.00 3.00/0.00 ns, min t spiccm mosi clock to out. 8.00 8.00 8.00 ns, max t spiccfc fcs_b clock to out. 8.00 8.00 8.00 ns, max startupe2 ports t usrcclko startupe2 usrcclko input to cclk output. 0.50/6.70 0.50/7.50 0.50/7.50 ns, min/max f cfgmclk startupe2 cfgmclk output frequency. 65.00 65.00 65.00 mhz, typ f cfgmclktol startupe2 cfgmclk output frequency tolerance. 50 50 50 %, max device dna access port f dnack dna access port (dna_port). 100.00 100.00 100.00 mhz, max notes: 1. to support longer delays in configuration, use the design solutions described in the 7 series fpga configuration user guide (ug470) [ref 9] . 2. see the 7 series fpgas overview (ds180) [ref 1] for a list of devices that support bitstream encryption. table 51: configuration switching characteristics (cont?d) symbol description v ccint operating voltage and speed grade units 1.0v 0.95v -2 -1 -1l s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 49 efuse programming conditions table 52 lists the programming conditio ns specifically for efuse. for more information, see the 7series fpga configuration user guide (ug470) [ref 9] . references 1. 7 series fpgas overview ( ds180 ) 2. 7 series fpgas selectio resources user guide ( ug471 ) 3. 7 series fpga packaging and pinout specification ( ug475 ) 4. 7 series fpgas pcb design guide ( ug483 ) 5. xilinx power estimator spreadsheet tool ( xpe ) 6. zynq-7000 ap soc and 7 series fpgas memo ry interface solutions user guide ( ug586 ) 7. see the clocking wizard in vivado software. 8. 7 series fpgas and zynq-7000 ap soc xadc dual 12- bit 1 msps analog-to-digital converter user guide ( ug480 ) 9. 7 series fpga configuration user guide ( ug470 ) table 52: efuse programming conditions (1) symbol description min typ max units i fs v ccaux supply current ? ? 115 ma t j temperature range 15 ? 125 c notes: 1. the fpga must not be configured during efuse programming. s e n d f e e d b a c k
spartan-7 fpgas data sheet: dc and ac switching characteristics ds189 (v1.0) september 27, 2016 www.xilinx.com advance product specification 50 revision history the following table shows the revision history for this document: please read: important legal notices the information disclosed to you hereunder (the ?materials?) is provided solely for the selectio n and use of xilinx products. t o the maximum extent permitted by applicable law: (1) materials are ma de available "as is" and with al l faults, xilinx hereby disclai ms all warranties and conditions, express, implied, or statutory, including but no t limited to warranties of merchantability, non-infringement, or fitness for any part icular purpose; and (2) xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) fo r any loss or damage of any kind or nature related to, arising under, or in connection with, th e materials (including your use of the ma terials), including for any direct, indire ct, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or xilinx h ad been advised of the possibility of the same . xilinx assumes no obligation to correct an y errors contained in the materials or t o notify you of updates to the mate rials or to product specifications. you may not reproduce, modify, distribute, or publicly dis play the materials without prior written consent. certain products are subject to the terms and conditio ns of xilinx?s limited warra nty, please refer to xilinx?s terms of sale which can be viewed at www.xilinx.com/legal.htm#tos ; ip cores may be subject to warranty and support terms contained in a license issued to you by xilinx. xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-saf e performance; you assume sole risk and lia bility for use of xilinx products in su ch critical applications, please refer to xilinx?s terms of sale which can be viewed at www.xilinx.com/legal.htm#tos . ? copyright 2016 xilinx, inc. xilinx, the xili nx logo, artix, ise, kintex, spartan, vi rtex, vivado, zynq, an d other designated brands included herein are trademarks of xilinx in the united states and other countries. a ll other trademarks are the property of the ir respective owners. automotive applications disclaimer automotive products (identif ied as "xa" in the part number) are not warranted for use in the deployment of airbags or for use in applications th at affect control of a vehicle ("safety application") unless there is a safety concept or redundancy feature consistent wi th the iso 26262 automotive safety standard ("safety design"). customer shall, prior to using or distribu ting any systems that incorporate products, thoroughly test such systems for safety purposes. use of products in a safety application without a safety design is fully at the risk of customer, subject only to applicable laws and regulations governing limitations on product liability. date version description of revisions 09/27/2016 1.0 initial xilinx release. s e n d f e e d b a c k

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