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6.8 ghz wideband synthesizer with integrated vco data sheet adf4356 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2016 analog devices, inc. all rights reserved. technical support www.analog.com features rf o utput frequency range: 53.125 mhz to 6 8 0 0 mhz int eger channel: ? 227 dbc/hz f rac tional channel : ? 225 dbc/hz integrated rms jitter (1 khz to 20 mhz) : 97 fs for 6 ghz o utput fractional - n synthesizer and i nteger - n synthesizer pin compatible to the adf4355 high resolution , 52- bit modulus phase frequency detec tor (pfd) operation to 125 mhz reference input frequency operation to 600 mhz maintains frequency lock over ? 40 c to + 85 c low phase noise , voltage controlled oscillator ( vco ) programmable di vide by 1 , 2 , 4 , 8 , 16 , 32 , or 64 output analog and digital power supplies: 3.3 v charge pump and vco power supplies: 5 .0 v typical logic compatibility: 1.8 v programmable output power level rf output mute function supported in the adisimpll design tool applications wireless infrastructure ( lt e, w - cdma, td - scdma, w i max, gsm, pcs, dcs) point to point/point to multipoint microwa ve links satellite s /vsat s test equipment/ i nstrumentation clock generation general description the adf4356 allows implementation of fractional - n or integer - n phase - locked loop (pll) frequency synthesizers when used with an external loop filter and an external reference frequency. a series of frequency di viders at another frequency output permits operation from 53.125 mhz to 6800 mhz. the adf4356 has an integrated vco with a fundamen tal output frequency ranging from 3400 m hz to 6800 mhz . in addition, the vco frequency is connecte d to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate rf output frequencies as low as 53.125 mhz. for applications that require isolation, the rf output stage can be mute d . the mute function is both pin - and software - controllable. control of all on - chip registers is through a simple 3 - wire interface. the adf4356 operates with analog and digital power supplies ranging from 3.15 v to 3.45 v, with charge pump and vco supplies from 4.75 v to 5.25 v. t h e adf4356 also conta ins hardware and software power - down modes. functional block diagram muxout cp out c reg2 c reg1 v bias v regvco clk ref in a ref in b data le av dd dv dd dv dd v p a gnd ce sd gnd cp gnd a gndrf a gndvco v vco v rf v tune v ref rf out a+ rf out a? rf out b+ rf out b? phase comparator charge pump output stage output stage pdb rf multiplexer multiplexer 10-bit r counter 2 divider 2 doubler function latch data register integer value n counter fraction value third-order fractional interpolator modulus value multiplexer lock detect 1/2/4/8/16/ 32/64 adf4356 vco core 15084-001 figure 1.
adf4356 data sh eet rev. 0 | page 2 of 35 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 tran sistor count ........................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 12 reference input section ............................................................. 12 rf n divider ............................................................................... 12 phase frequency detector (pfd) and charge pump ............ 13 muxout and lock detect ...................................................... 13 input shift registers ................................................................... 13 program modes .......................................................................... 14 vco .............................................................................................. 14 output stage ................................................................................ 14 register maps .................................................................................. 16 register 0 ..................................................................................... 18 register 1 ..................................................................................... 19 register 2 ..................................................................................... 19 register 3 ..................................................................................... 20 register 4 ..................................................................................... 21 register 5 ..................................................................................... 22 register 6 ..................................................................................... 23 register 7 ..................................................................................... 25 register 8 ..................................................................................... 26 register 9 ..................................................................................... 26 register 10 ................................................................................... 27 register 11 ................................................................................... 28 register 12 ................................................................................... 28 register 13 ................................................................................... 29 register initial ization sequence ............................................... 29 frequency update sequence ..................................................... 30 rf synthesizer a worked example ...................................... 30 reference doubler and reference divider ............................. 31 spurious optimization and fast lock ..................................... 31 optimizing jitter ......................................................................... 31 spur mechanisms ....................................................................... 31 lock time .................................................................................... 31 applications infor mation .............................................................. 33 power supplies ............................................................................ 33 printed circuit board (pcb) design guidelines for a chip - scale package .............................................................................. 33 output matching ........................................................................ 34 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 35 revision history 10/ 2016 rev ision 0 initial version
data sheet adf4356 rev. 0 | page 3 of 35 specifications av dd = dv dd = v rf = 3.3 v 5%, 4.75 v v p = v vco 5. 2 5 v, a gnd = cp gnd = a gndvco = sd gnd = a gndrf = 0 v, r set = 5.1 k?, dbm referred to 50 ?, t a = t min to t max , unless otherwise noted. table 1 . parameter symbol min typ max unit test conditions/comments ref in a/ref in b characteristics input frequency range for f < 10 mhz, ensure slew rate > 21 v/s single - ended mode 10 250 mhz differential mode 10 600 mhz input sensitivity single - ended mode 0.4 av dd v p -p ref in a biased at av dd /2; ac coupling ensures av dd /2 bias differential mode 0.4 1.8 v p -p lvds and lvpecl compatible, ref in a/ ref in b biased at 2.1 v; ac coupling ensures 2.1 v bias input capacitance single - ended mode 6.9 pf differential mode 1.4 pf input current 100 a single - ended reference programmed 250 a differential reference programmed phase frequency detector 125 mhz charge pump (cp) cp current, sink/source i cp r set = 5.1 k? , this resistor is internal in the adf4356 high value 4.8 ma low value 0.3 ma r set range 5.1 k? fixed current matching 3 % 0.5 v v cp 1 v p ? 0.5 v i cp vs. v cp 3 % 0.5 v v cp 1 v p ? 0.5 v i cp vs. temperature 1.5 % v cp 1 = 2.5 v logic inputs input voltage high v inh 1.5 dv dd v low v inl 0.6 v input current i inh /i inl 1 a input capacitance c in 3.0 pf logic outputs output high voltage v oh dv dd ? 0.4 v 1.5 1.8 v 1.8 v output selected output high current i oh 500 a output low voltage v ol 0.4 v i ol 2 = 500 a power supplies see table 7 and table 8 analog power av dd 3.15 3.3 3.45 v digital power and rf supply voltage dv dd , v rf av dd voltages must equal av dd cp and vco supply voltage v p , v vco 4.75 5.0 5.25 v v p must equal v vco cp supply power current i p 8 9 di dd + ai dd 3 82 92 ma output dividers 6 to 36 ma each output divide by 2 consumes 6 ma supply current i vco 70 90 ma
adf4356 data sh eet rev. 0 | page 4 of 35 parameter symbol min typ max unit test conditions/comments rf out a+/rf out a? supply current i rf out x rf output a e nabled /rf output b d isabled 22 27 ma ?4 dbm setting 33 38 ma ?1 dbm setting 44 49 ma 2 dbm setting 55 60 ma 5 dbm setting rf out a+/rf out a? plus rf out b +/rf out b ? supply current i rf out x rf output a e nabled/rf output b e nabled 48 56 ma ?4 dbm setting 65 74 ma ?1 dbm setting 82 91 ma 2 dbm setting 99 108 ma 5 dbm setting low power sleep mode 5 m a hardware power - down selected 20 m a software power - down selected rf output characteristics vco frequency range 3400 6800 mhz fundamental vco range rf output frequency 53.125 6800 mhz vco sensitivity k v 25 mhz/v frequency pushing (open - loop) 1 2 mhz/v frequency pulling (open - loop) 0.5 mhz voltage standing wave ratio (vswr) = 2:1 rf out a+/rf out a? harmonic content second ?2 6 dbc fundamental vco output (rf out a+) ?2 9 dbc divided vco output (rf out a+) third ? 32 dbc fundamental vco output (rf out a+) ?1 4 dbc divided vco output (rf out a+) rf output a power 4 7 dbm rf out a+ = 1 ghz; 7. 4 nh inductor to v rf ? 2 dbm rf out a+ = 6.8 ghz; 7. 4 nh inductor to v rf power variation 1 db rf out a+ = 5 ghz power variation over frequency 5 db rf out a+ = 1 ghz to 6.8 ghz rf output b power 4 4 dbm rf out b+ = 1 ghz; 7. 4 nh inductor to v rf ? 2 dbm rf out b + = 6.8 ghz; 7. 4 nh inductor to v rf power variation 1 db rf out b + = 5 ghz power variation over frequency 5 rf out b + = 1 ghz to 6.8 ghz level of signal with rf output disabled ? 53 dbm rf out a+ = 1 ghz ? 20 dbm rf out a+= 6.8 ghz noise characteristics fundamental vco phase noise performance vco noise in open - loop conditions ?11 5 dbc/hz 100 khz offset from 3.4 ghz carrier ?13 5 dbc/hz 800 khz offset from 3.4 ghz carrier ?13 7 dbc/hz 1 mhz offset from 3.4 ghz carrier ?155 dbc/hz 10 mhz offset from 3.4 ghz carrier ?113 dbc/hz 100 khz offset from 5.0 ghz carrier ?133 dbc/hz 800 khz offset from 5.0 ghz carrier ?135 dbc/hz 1 mhz offset from 5.0 ghz carrier ?153 dbc/hz 10 mhz offset from 5.0 ghz carrier ?110 dbc/hz 100 khz offset from 6.8 ghz carrier ?130 dbc/hz 800 khz offset from 6.8 ghz carrier ?132 dbc/hz 1 mhz offset from 6.8 ghz carrier ?150 dbc/hz 10 mhz offset from 6.8 ghz carrier
data sheet adf4356 rev. 0 | page 5 of 35 parameter symbol min typ max unit test conditions/comments normalized in - band phase noise floor fractional channel 5 ?225 dbc/hz integer channel 6 ?227 dbc/hz normalized 1/f noise, pn 1_f 7 ?121 dbc/hz 10 khz offset; normalized to 1 ghz integrated rms jitter (1 khz to 20 mhz) 8 97 fs spurious signals d ue to pfd frequency ? 85 dbc 1 v cp is the v oltage at the c p out pin. 2 i ol is the output low current. 3 t a = 25c; av dd = dv dd = v rf = 3.3 v; v vco = v p = 5.0 v; prescaler = 4/5; f ref in = 122.88 mhz; f pfd = 61.44 mhz; and f rf = 1650 mhz. 4 rf ou tput power using the ev - adf4356 s d1z evaluation board is measured into a spectrum analyzer . unused rf output pins are terminated in 50 ?. 5 use t his value to calculate the phase noise for any application. to calculate in - band phase noise performance as seen at the vco output, use the following formula: ?22 5 + 10log(f pfd ) + 20l ogn. the value given is the lowest noise mode for the fractional channel. 6 use t his value to calculate the phase noise for any application. to calculate in - band phase noise performance as seen at the vco output, use the following formula: ?22 7 + 10log(f p fd ) + 20logn. the value given is the lowest noise mode for the integer channel. 7 the pll phase noise is composed of 1/f (flicker) noise plus the normalized pll noise floor. the formula for calculating the 1 /f noise contribution at an rf frequency (f rf ) an d at a frequency offset (f) is given by pn = p 1_f + 10log(10 khz/f) + 20log(f rf /1 ghz). both the normalized phase noise floor and flicker noise are modeled in the adisimpll design tool. 8 integrated rms jitter using the ev - adf4356 s d1z evaluation board is measured into a spectrum analyzer. t he ev - adf4356 s d1z eval uation board is configured to accept a single ended refin (sma 100) = 160 mhz, vco frequency = 6 ghz, pfd frequency = 80 mhz, charge pump current = 0. 9 ma, and bleed current is off. the loop filter is configured for an 80 khz loop filter bandwidth. unused rf output pins are terminated in 50 ?. timing characteristics av dd = dv dd =v rf = 3.3 v 5%, 4.75 v v p = v vco 5.25 v, a gnd = cp gnd = a gndvco = sd gnd = a gndrf = 0 v, r set = 5.1 k?, dbm referred to 50 ?, t a = t min to t max , unless otherwise noted. table 2 . write timing param eter limit unit description f clk 50 mhz max serial peripheral interface clk frequency t 1 1 0 ns min le setup time t 2 5 ns min data to clk setup time t 3 5 ns min data to clk hold time t 4 10 ns min clk high duration t 5 10 ns min clk low duration t 6 10 ns min clk to le setup time t 7 20 or (2/f pfd ), whichever is longer ns min le pulse width write timing diagram clk dat a le db31 (msb) db30 db1 (contro l bit c2) db0 (lsb) (contro l bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 db2 (contro l bit c3) db3 (contro l bit c4) 15084-002 figure 2. write timing diagram
adf4356 data sh eet rev. 0 | page 6 of 35 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating v rf , dv dd , av dd to gnd 1 ?0.3 v to +3.6 v av dd to dv dd ?0.3 v to +0.3 v v p , v vco to gnd 1 ?0.3 v to +5.8 v cp out to gnd 1 ? 0.3 v to v p + 0.3 v digital input/output voltage to gnd 1 ?0.3 v to dv dd + 0.3 v analog input/output voltage to gnd 1 ?0.3 v to av dd + 0.3 v ref in a, ref in b to gnd 1 ?0.3 v to a v dd + 0.3 v ref in a to ref in b 2.1 v operating temperature range ?40c to +85c storage temperature range ?65c to +125c maximum junction temperature 150c reflow soldering peak temperature 260c time at peak temperature 40 sec electrostatic discharge ( esd ) charged device model 1 00 0 v human body model 2 0 00 v 1 gnd = a gnd = sd gnd = a gndrf = a gndvco = cp gnd = 0 v. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. th e adf4356 is a high performance rf integrated circuit with an esd rating of 2 kv and is esd sensitive. take p roper precautions for handling and assembly. thermal resistance thermal performance is directly linked to printed circuit board (pcb) design and operating environment. careful attention to pcb thermal design is required. table 4 . thermal resistance package type ja unit cp -32-12 1 27.3 c/w 1 test condition 1: thermal impedance simulated values are based on use of a pcb with the t hermal i mpedance p addle s oldered to gnd 1 . transistor count the transistor count for the adf4356 is 134,486 (cmos) and 3874 (bipolar). esd caution
data sheet adf4356 rev. 0 | page 7 of 35 pin configuration an d function descripti ons notes 1. nic = not internally connected. 2. the exposed pad must be connected to a gnd . 24 23 22 21 20 19 18 17 v bias v ref nic a gndvco v tune v regvco a gndvdo v vco 1 2 3 4 5 6 7 8 clk data le ce av dd v p cp out cp gnd 9 10 11 12 13 14 15 16 a gnd v rf rf out a+ rf out a? a gndrf rf out b+ rf out b? av dd 32 31 30 29 28 27 26 25 c reg 2 sd gnd muxout ref in a ref in b dv dd pdb rf c reg 1 adf4356 top view (not to scale) 15084-003 figure 3. pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 clk serial clock input. data is clocked into the 32 - bit shift register on the clk rising edge. this input is a high impedance cmos input. 2 data serial data input. the serial data is loaded most significant bit ( msb ) first with the four lsbs as the control bits. this input is a high impedance cmos input. 3 le load enable, cmos input. when le goes high, the data stored in the shift register is loaded into the register that is selected by the four lsbs. 4 ce chip enable. a logic low on this pin powers down the device and puts the charge pump into three - state mode. a logic high on this pin powers up the device, depending on the status of the powe r - down bits.
adf4356 data sh eet rev. 0 | page 8 of 35 pin no. mnemonic description 20 v tune control input to the vco. this voltage determines the output frequency and is derived from filtering the cp out output voltage. the capacitance at this pin (v tune input capacitance) is 9 pf. 22 n i c no internal connection . for existing designs that currently use the adf4355 , to upgrade to the adf4356 , the r set resistor can be left connected to this pin. 23 v ref internal compensation node. dc b iased at half the tuning range. c onnect decoupling capacitors t o the ground plane as close to this pin as possible. 24 v bias reference voltage. c onnect a 100 nf d ecoupling capacitor to the ground plane as close to this pin as possible. 25, 32 c reg 1 , c reg 2 output s from the ldo r egulator . c reg 1 and c reg 2 are the s upply voltage s to the digital circuits. nominal voltage of 1.8 v. d ecoupling capacitor s of 100 nf connected to a gnd are required for these pins . 26 pdb rf rf power - down. a logic low on this pin mutes the rf outputs. this mute function is also software - controllable. do not leave this pin floating . 27 dv dd digital power supply. this pin must be at the same voltage as av dd . place decoupling capacitors to the ground plane as close to this pin as possible. 28 ref in b complementary reference input. if unused , ac couple this pin to a gnd . 29 ref in a reference input. 30 muxout multiplexer output. the multiplexer output allows the digital lock detect, the analog lock detect, scaled rf, or the scaled reference frequency to be externally accessible . 31 sd gnd di gital - modulator ground. sd gnd is the g round return path for th e - mo dulator. ep exposed pad. the exposed pad must be connected to a gnd .
data sheet adf4356 rev. 0 | page 9 of 35 typical performance characteristics ?170 ?150 ?130 ?110 ?90 ?70 ? 50 1k 10k 100k 1m 10m 100m frequency offset from carrier (hz) phase noise (dbc/hz) 15084-004 figure 4. open-loop vco phase noise, 3.4 ghz ?170 ?150 ?130 ?110 ?90 ?70 ? 50 1k 10k 100k 1m 10m 100m frequency offset from carrier (hz) phase noise (dbc/hz) 15084-005 figure 5. open-loop vco phase noise, 5.0 ghz ?170 ?150 ?130 ?110 ?90 ?70 ? 50 1k 10k 100k 1m 10m 100m frequency offset from carrier (hz) phase noise (dbc/hz) 15084-006 figure 6. open-loop vco phase noise, 6.8 ghz ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ? 80 1k 10k 100k 1m 10m 100m frequency (hz) phase noise (dbc/hz) div1 div2 div4 div8 div16 div32 div64 15084-007 figure 7. closed-loop phase noise, rf out b+ (100 nh inductors), fundamental vco and dividers, vco = 3.4 ghz, pfd = 61.44 mhz, loop bandwidth = 40 khz ?170 ?150 ?130 ?110 ?90 ? 50 ?70 1k 10k 100k 1m 10m 100m frequency (hz) phase noise (dbc/hz) div1 div2 div4 div8 div16 div32 div64 15084-008 figure 8. closed-loop phase noise, rf out b+ (100 nh inductors), fundamental vco and dividers, vco = 5.0 ghz, pfd = 61.44 mhz, loop bandwidth = 40 khz ?170 ?150 ?130 ?110 ?90 ? 50 ?70 1k 10k 100k 1m 10m 100m frequency (hz) phase noise (dbc/hz) div1 div2 div4 div8 div16 div32 div64 15084-009 figure 9. closed-loop phase noise, rf out b+ (100 nh inductors), fundamental vco and dividers, vco = 6.8 ghz, pfd = 61.44 mhz, loop bandwidth = 40 khz
adf4356 data sh eet rev. 0 | page 10 of 35 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 1000 2000 3000 4000 5000 6000 7000 level (dbm) target frequency (mhz) ?40c +25c +85c 15084-010 figure 10 . output power vs. frequency, rf out a+/rf out a? (7. 4 nh inductors, 10 pf ac coupling capacitors, board measurement ) 10 ?60 ?50 ?40 ?30 ?20 ?10 0 1000 2000 3000 4000 5000 6000 7000 level of harmonic (dbm) target frequency (mhz) fifth harmonic fourth harmonic third harmonic second harmonic 15084-0 1 1 figure 11 . rf out a+/rf out a harmonics vs. frequency (7.4 nh inductors, 10 pf ac coupling capacitors, board measurement ) 6 ?8 ?6 ?4 ?2 0 2 4 0 1000 2000 3000 4000 5000 6000 7000 level (dbm) frequency (mhz) 15084-012 figure 12 . rf out b +/rf out b power vs. frequency (100 nh inductors, 10 pf ac coupling capacitors, board measurement) 10 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 0 1000 2000 3000 4000 5000 6000 7000 output power (dbm) frequency (mhz) rf out b? rf out b+ rf out a? rf out a+ 15084-013 figure 13 . rf out a+/rf out a power vs. rf out b+/rf out b power (7.4 nh inductors, 10 pf ac coupling capacitors, board measurement) 250 0 50 100 150 200 0 1000 2000 3000 4000 5000 6000 7000 rms jitter/noise (fs) output frequency (mhz) 15084-014 1khz to 20mhz 12khz to 20mhz fi gure 14 . rms jitter /noise vs. ou tput frequency, pfd freque ncy = 61.44 mhz, loop filter = 4 0 khz ?40 ?110 ?100 ?90 ?80 ?70 ?60 ?50 0 1000 2000 3000 4000 5000 6000 7000 worst case pfd/ref spur (dbc) target frequency (mhz) pfd = 122.88mhz pfd = 61.44mhz pfd = 30.72mhz 15084-015 figure 15 . pfd spur amplitude vs. rf out a+/rf out a output frequency, pfd = 30.72 mhz, pfd = 61.44 mhz, pfd = 122.88 mhz, loop filter = 4 0 khz
data sheet adf4356 rev. 0 | page 11 of 35 ?60 ?180 ?160 ?140 ?120 ?100 ?80 1k 100m 10m 1m 100k 10k noise and spur power (dbc/hz) frequency (hz) 15084-016 figure 16 . fractional - n spur performance, gsm1800 band, rf out a+ = 1550.2 mhz, ref in = 122.88 mhz, pfd = 61.44 mhz, output divide by 4 selec ted, loop filter bandwidth = 4 0 khz, channel spacing = 20 khz ?60 ?180 ?160 ?140 ?120 ?100 ?80 1k 100m 10m 1m 100k 10k noise and spur power (dbc/hz) frequency (hz) 15084-017 figure 17 . fractional - n spur performance, w - cdma band, rf out a+ = 2113.5 mhz, ref in = 122.88 mhz, pfd = 61.44 mhz, output divide by 2 selected, loop filter bandwidth = 4 0 khz, channel spacing = 20 khz ?60 ?160 ?150 ?130 ?110 ?90 ?70 ?140 ?120 ?100 ?80 1k 10m 1m 100k 10k noise and spur power (dbc/hz) frequency (hz) 15084-018 figure 18 . fractional - n spur performance, rf out a+ = 2.591 ghz, ref in = 122.88 mhz, pfd = 61.44 mhz, output divide by 2 sele cted, loop filter bandwidth = 4 0 khz, channel spacing = 20 khz ?1 4 3 2 1 0 frequency (mhz) time (ms) 4150 4200 4250 4300 4350 4400 4450 4500 4550 4600 4650 15084-019 1 figure 19 . lock time for 250 mhz jump from 4150 mhz to 4400 mhz, loop bandwidth = 23 khz
adf4356 data sheet rev. 0 | page 12 of 35 theory of operation reference input section figure 20 shows the reference input stage. the reference input can accept both single-ended and differential signals. use the reference mode bit (register 4, bit db9) to select the signal. to use a differential signal on the reference input, program this bit high. in this case, sw1 and sw2 are open, sw3 and sw4 are closed, and the current source that drives the differential pair of transistors switches on. the differential signal buffers and provides an emitter-coupled logic (ecl) to the cmos converter. when a single-ended signal is used as the reference, program bit db9 in register 4 to 0. connect the single-ended reference signal to ref in a. in this case, sw1 and sw2 are closed, sw3 and sw4 are open, and the current source that drives the differential pair of transistors switches off. 2.5k ? 2.5k ? ref in a ref in b av dd bias generator buffer 85k ? sw2 sw3 sw1 reference input mode sw4 ecl to cmos buffer to r counter multiplexer 15084-020 figure 20. reference input stage, differential mode rf n divider the rf n divider allows a division ratio in the pll feedback path. determine the division ratio by the int, frac1, frac2, and mod2 values that this divider comprises. third-order fractional interpolator frac1 reg int reg rf n counter from vco output/ output dividers to pfd n counter frac2 value mod2 value n = int + frac1 + mod1 frac2 mod2 15084-021 figure 21. rf n divider int, fracx, modx, and r counter relationship the int, frac1, frac2, mod1, and mod2 values, in conjunction with the r counter, make it possible to generate output frequencies spaced by fractions of the pfd frequency (f pfd ). for more information, see the rf synthesizera worked example section. calculate the rf vco frequency (vco out ) by vco out = f pfd n (1) where: vco out is the output frequency of the vco (without using the output divider). f pfd is the frequency of the phase frequency detector. n is the desired value of the feedback counter, n. calculate f pfd by f pfd = ref in ((1 + d )/( r (1 + t ))) (2) where: ref in is the reference input frequency. d is the ref in doubler bit. r is the preset divide ratio of the binary 10-bit programmable reference counter (1 to 1023). t is the ref in divide by 2 bit (0 or 1). n comprises mod1 mod2 frac2 frac1 intn ? ?? (3) where: int is the 16-bit integer value (23 to 32,767 for the 4/5 prescaler, and 75 to 65,535 for the 8/9 prescaler). frac1 is the numerator of the primary modulus (0 to 16,777,215). frac2 is the numerator of the 28-bit auxiliary modulus (0 to 268,435,455). mod2 is the programmable, 28-bit auxiliary fractional modulus (2 to 268,435,455). mod1 is a 24-bit primary modulus with a fixed value of 2 24 = 16,777,216. equation 3 results in a very fine frequency resolution with no residual frequency error. to apply this formula, take the following steps: 1. calculate n by dividing vco out /f pfd . 2. the integer value of this number forms int. 3. subtract the int value from the full n value. 4. multiply the remainder by 2 24 . 5. the integer value of this number forms frac1. 6. calculate mod2 based on the channel spacing (f chsp ) by mod2 = f pfd / gcd ( f pfd , f chsp ) (4) where: gcd(f pfd , f chsp ) is the greatest common divider of the pfd frequency and the channel spacing frequency. f chsp is the desired channel spacing frequency. 7. calculate frac2 by the following equation: frac2 = (( n ? int ) 2 24 ? frac1 )) mod2 (5)
data sheet adf4356 rev. 0 | page 13 of 35 the frac2 and mod2 fraction results in outputs with zero frequency error for channel spacings when f pfd /gcd( f pfd / f chsp ) < 268,435,455 (6) where: f pfd is the frequency of the phase frequency detector. gcd is a greatest common denominator function. f chsp is the desired channel spacing frequency. if zero frequency error is not required, the mod1 and mod2 denominators operate together to create a 52-bit resolution modulus. int n mode when frac1 and frac2 are 0, the synthesizer operates in integer-n mode. r counter the 10-bit r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 1023 are allowed. phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 22 is a simplified schematic of the phase frequency detector. the pfd includes a fixed delay element that sets the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and provides a consistent reference spur level. set the phase detector polarity to positive on this device because of the positive tuning of the vco. u3 clr2 q2 d2 u2 down up high high cp ?in +in charge pump delay clr1 q1 d1 u1 15084-022 figure 22. pfd simplified schematic muxout and lock detect the output multiplexer on the adf4356 allows the user to access various internal points on the chip. the m3, m2, and m1 bits in register 4 control the state of muxout. figure 23 shows the muxout section in block diagram form. sd gnd dv dd control mux muxout a nalog lock detect digital lock detect r divider output n divider output sd gnd reserved three-state output dv dd 15084-023 figure 23. muxout schematic input shift registers the adf4356 digital section includes a 10-bit r counter, a 16-bit rf integer-n counter, a 24-bit frac1 counter, a 28-bit auxiliary fractional counter, and a 28-bit auxiliary modulus counter. data clocks into the 32-bit shift register on each rising edge of clk. the data clocks in msb first. data transfers from the shift register to one of 13 latches on the rising edge of le. the state of the four control bits (c4, c3, c2, and c1) in the shift register determines the destination latch. as shown in figure 2, the four least significant bits (lsbs) are db3, db2, db1, and db0. the truth table for these bits is shown in table 6. figure 26 and figure 27 summarize the programming of the latches. table 6. truth table for the c4, c3, c2, and c1 control bits control bits register c4 c3 c2 c1 0 0 0 0 register 0 0 0 0 1 register 1 0 0 1 0 register 2 0 0 1 1 register 3 0 1 0 0 register 4 0 1 0 1 register 5 0 1 1 0 register 6 0 1 1 1 register 7 1 0 0 0 register 8 1 0 0 1 register 9 1 0 1 0 register 10 1 0 1 1 register 11 1 1 0 0 register 12 1 1 0 1 register 13
adf4356 data sheet rev. 0 | page 14 of 35 program modes table 6 and figure 28 through figure 41 show how the program modes must be set up for the adf4356 . the following settings in the adf4356 are double-buffered: main fractional value (frac1), auxiliary modulus value (mod2), auxiliary fractional value (frac2), reference doubler, reference divide by 2 (rdiv2), r counter value, and charge pump current setting. two events must occur before the adf4356 uses a new value for any of the double-buffered settings. first, the new value must latch into the device by writing to the appropriate register, and second, a new write to register 0 must be performed. for example, to ensure that the modulus value loads correctly, every time that the modulus value updates, register 0 must be written to. the rf divider select in register 6 is also double buffered, but only if db14 of register 4 is high. vco the vco core in the adf4356 consists of four separate vcos, each of which uses 256 overlapping bands, which allows the device to cover a wide frequency range without large vco sensitivity (k v ) and without resulting poor phase noise and spurious performance. the correct vco and band are chosen automatically by the vco and band select logic when register 0 is updated and auto- calibration is enabled. the r counter output is used as the clock for the band select logic. after band selection, normal pll action resumes. the nominal value of k v is 25 mhz/v when the n divider is driven from the vco output, or the k v value is divided by d. d is the output divider value if the n divider is driven from the rf output divider (chosen by programming bits[db23:db21] in register 6). the vco shows variation of k v as the tuning voltage, v tune , varies within the band and from band to band. for wideband applications covering a wide frequency range (and changing output dividers), a value of 25 mhz/v provides the most accurate k v , because this value is closest to the average value. figure 24 shows how k v varies with fundamental vco frequency along with an average value for the frequency band. users may prefer this figure when using narrow-band designs. average vco sensitivity linear trend line frequency (ghz) 0 10 20 30 40 50 3.43.84.24.65.05.45.86.26.6 vco sensitivity, k v (mhz/v) 15084-024 figure 24. vco sensitivity, k v vs. frequency output stage the rf out a+ and rf out a? pins of the adf4356 connect to the collectors of an npn differential pair driven by buffered outputs of the vco, as shown in figure 25. in this scheme, the adf4356 contains internal 50 resistors connected to the v rf pin. to optimize the power dissipation vs. the output power requirements, the tail current of the differential pair is programmable using bits[db2:db1] in register 6. four current levels can be set. these levels give approximate output power levels of ?4 dbm, ?1 dbm, +2 dbm, and +5 dbm, respectively. levels of ?4 dbm, ?1 dbm, an d +2 dbm can be achieved using a 50 resistor to v rf and ac coupling into a 50 load. for accurate power levels, refer to the typical performance characteristics section. an output power of 5 dbm requires an external shunt inductor to provide higher power levels; however, this addition results in less wideband performance using the internal bias only. terminate the unused complementary output with a similar circuit to the used output. vco rf out a+ rf out a? v rf v rf 50? 50? buffer/ divide by 1/2/4/8/ 16/32/64 15084-025 figure 25. output stage another feature of the adf4356 is that the supply current to the rf out a+/rf out a? output stage can shut down until the adf4356 achieves lock as measured by the digital lock detect circuitry. the mute till lock detect (mtld) bit (bit db11) in register 6 enables this function. the rf out b+/rf out b? pins are duplicate outputs that can be used independently or in addition to the rf out a+/rf out a? pins.
data sheet adf4356 rev. 0 | page 15 of 35 table 7 . total i dd ( rf output a enabled/rf output b disabled ) 1 divide by rf out a off rf out a = ? 4 dbm rf out a = ?1 dbm rf out a = 2 dbm rf out a = 5 dbm 5 v supply (i vco and i p ) 78 ma 78 ma 78 ma 78 ma 78 ma 3.3 v supply (ai dd , di dd , and i rf ) 1 84.8 106.2 117.3 128.2 138.9 2 94.1 114.9 125.7 136.4 146.5 4 103.9 124.9 136.2 147.3 158.0 8 111.9 132.9 144.3 155.6 166.8 16 116.9 138.0 149.5 160.7 171.8 32 120.9 142.0 153.6 164.8 176.1 64 123.3 144.4 156.0 167.3 178.4 1 rf out a refers to rf out a+/rf out a?. table 8 . total i dd ( rf output a enabled/ rf output b enabled ) 1 divide by rf out a / rf out b off rf out a/rf out b = ?4 dbm rf out a/rf out b = ? 1 dbm rf out a / rf out b = 2 dbm rf out a/rf out b = 5 dbm 5 v supply (i vco and i p ) 78 ma 78 ma 78 ma 78 ma 78 ma 3.3 v supply (ai dd , di dd , and i rf ) 1 84.9 133.5 150.0 166.3 182.1 2 94.2 142.4 159.8 177.2 193.6 4 104.0 151.9 169.5 187.0 204.0 8 112.0 159.7 177.3 194.7 211.6 16 117.0 164.5 182.2 199.5 216.5 32 121.0 168.4 186.1 203.5 220.4 64 123.4 170.8 188.6 205.8 222.8 1 rf out a refers to rf out a+/rf out a? and rf out b refers to rf out b+/rf out b?.
adf4356 data sh eet rev. 0 | page 16 of 35 register map s 1 dbr = double buffered register?buffered by the write to register 0. 2 dbb = double buffered bits?buffered by a write to register 0 when bit db14 of register 4 is high. 16-bit integer value (int) 14-bit auxiliary modulus msb value (mod2_lsb) 14-bit auxiliary fractional lsb value (frac2_lsb) current setting dbr 1 dbr 1 rf output b enable reserved rf divider select 2 charge pump bleed current bleed polarity reference doubler dbr 1 sd load reset phase resync phase adjust rdiv2 dbr 1 double buff ref mode power-down mux logic pd polarity cp three- state counter reset negative bleed gated bleed rf output b select feedback select register 0 register 1 register 2 register 3 register 4 register 5 register 6 rf output b power rf output a power db0 c1(0) db1 c2(1) db2 c3(1) db3 c4(0) db4 d1 db5 db6 d2 d3 db7 d4 db8 d5 db9 d6 db10 0 db11 d8 db12 0 db13 bl1 db14 bl2 db15 bl3 db16 bl4 db17 bl5 db18 bl6 db19 bl7 db20 bl8 db21 d10 db22 d11 db23 d12 db24 d13 db25 d14 db26 1 db27 0 db28 1 db29 db30 bl9 bl10 db31 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 pr1 ac1 0 0 0 0 0 0 0 0 0 0 c1(0) c2(0) c3(0) c4(0) f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 0 0 0 0 c1(1) c2(0) c3(0) c4(0) c1(0) c2(1) c3(0) c4(0) m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 c1(0) c2(0) c3(1) c4(0) c1(1) c2(1) c3(0) c4(0) u1 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 p23 p24 pa1 pr1 sd1 0 u2 u3 u4 u5 u6 cp1 cp2 cp3 cp4 d1 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 rd1 rd2 m1 m2 m3 0 0 c1(1) c2(0) c3(1) c4(0) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 bp1 control bits reserved reserved reserved reserved muxout 10-bit r counter dbr 1 dbr 1 24-bit phase value (phase) control bits control bits control bits control bits 24-bit main fractional value (frac1) control bits control bits reserved reserved reserved autocal prescaler mtld rf output a enable 15084-026 figure 26 .
data sheet adf4356 rev. 0 | page 17 of 35 register 7 register 8 register 9 register 10 register 11 register 12 register 13 14-bit auxiliary modulus msb value (mod2_msb) dbr 1 14-bit auxiliary fractional msb value (frac2_msb) dbr 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 1 0 0 0 0 0 0 0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 c3(1) c2(0) c1(0) c4(1) m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 c3(1) c2(0) c1(1) c4(1) control bits phase resync clock value reserved control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 sl1 sl2 sl3 sl4 sl5 al1 al2 al3 al4 al5 tl1 tl2 tl3 tl4 tl5 tl6 tl7 tl8 tl9 tl10 vc1 vc2 vc3 vc4 vc5 vc6 vc7 vc8 c3(0) c2(0) c1(1) c4(1) c3(0) c2(1) c1(0) c4(1) adc clock divider reserved automatic level calibration timeout timeout vco band division control bits synthesizer lock timeout control bits adc conversion adc enable ae1 ae2 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 15084-027 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 rese r ved rese r ved control bits 0 1 0 0 0 0 0 c3(0) c2(1) c1(1) c4(1) 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 vh vco band hold db3 1 db3 0 db2 9 db2 8 db2 7 db2 6 db2 5 db2 4 db2 3 db2 2 db2 1 db2 0 db1 9 db1 8 db1 7 db1 6 db1 5 db1 4 db1 3 db1 2 db1 1 db1 0 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 0 0 0 0 0 0 0 0 0 0 0 ld1 c3 ( 1 ) c2 (1) c1 ( 1 ) c o n t r o l b it s reserved reserved c 4(0) ld2 ld3 frac-n ld precision ld mode lol mode lol ld4 ld5 ld cycle count 0 0 0 0 0 0 0 0 le sync le sel le1 le2 r ese r ved 1 sync edge db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 reserved control bits 1 0 1 0 0 0 1 0 0 1 c3(0) c2(0) c1(0) c4(1) 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 figure 27 . register summary (register 7 to register 1 3)
adf4356 data sheet rev. 0 | page 18 of 35 16-bit integer value (int) db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 n1n2n3n4n5 n6 n7n8n9n10n11n12n13 n14 n15n16 n1 integer value (int) n2n3n4n5 .... n15n16 0 not allowed 0000 .... 00 1 not allowed 0000 .... 00 0 not allowed 1000 .... 00 ..... .... .... .. 0 not allowed 1101 .... 00 123 1101 .... 00 02 4 0011 .... 00 ..... .... .... .. 1 65533 0111 .... 11 0 65534 1111 .... 11 1 65535 int min = 75 with prescaler = 8/9 1111 .... 11 pr1 pr1 0 1 4/5 8/9 prescaler ac1 0000000000 c1(0) c2(0) c3(0) c4(0) reserved control bits autocal prescaler ac1 0 1 disabled disabled vco autocal 15084-028 figure 28. register 0 register 0 control bits with bits[c4:c1] set to 0000, register 0 is programmed. figure 28 shows the input data format for programming this register. reserved bits[db31:db22] are reserved and must be set to 0. automatic calibration (autocal) write to register 0 to enact (by default) the vco automatic calibration, and to choose the appropriate vco and vco subband. write 1 to the ac1 bit (bit db21) to enable the automatic calibration, which is the recommended mode of operation. set the ac1 bit (bit db21) to 0 to disable the automatic calibration, which leaves the adf4356 in the same band it was already in when register 0 is updated. disable the automatic calibration only for fixed frequency applications, phase adjust applications, or very small (<10 khz) frequency jumps. toggling autocal is also required when changing frequency. see the frequency update sequence section for more information. prescaler value the dual modulus prescaler (p/p + 1), along with the int, fracx, and modx counters, determines the overall division ratio from the vco output to the pfd input. the pr1 bit (bit db20) in register 0 sets the prescaler value. operating at cml levels, the prescaler takes the clock from the vco output and divides it down for the counters. it is based on a synchronous 4/5 core. when the prescaler is set to 4/5, the maximum rf frequency allowed is 7 ghz. the prescaler limits the int value; therefore, if p is 4/5, n min is 23, and if p is 8/9, n min is 75. 16-bit integer value the 16 int bits (bits[db19:db4]) set the int value, which determines the integer part of the feedback division factor. the int value is used in equation 3 (see the int, fracx, modx, and r counter relationship section). all integer values from 23 to 32,767 are allowed for the 4/5 prescaler. for the 8/9 prescaler, the minimum integer value is 75, and the maximum value is 65,535.
data sheet adf4356 rev. 0 | page 19 of 35 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 0 0 0 0 c1(1) c2(0) c3(0) c4(0) reserved dbr 1 24-bit main fractional value (frac1) control bits main fractional value (frac1) f1 f12 .... f23 f24 0 0 0 .... 0 0 1 1 0 .... 0 0 2 0 1 .... 0 0 3 1 1 .... 0 0 . . . .... . . . . . .... . . . . . .... . . 16777212 0 0 .... 1 1 16777213 1 1 .... 1 1 16777214 1 1 .... 1 1 16777215 1 dbr = double buffered register?buffered by the write to register 0. 1 1 .... 1 1 15084-029 figure 29 . register 1 frac2_lsb word f1 f2 .... f13 f14 0 0 0 .... 0 0 1 1 0 .... 0 0 2 0 1 .... 0 0 3 1 1 .... 0 0 . . . .... . . . . . .... . . . . . .... . . 16381 0 0 .... 1 1 16382 1 0 .... 1 1 16382 0 1 .... 1 1 16383 1 dbr = double buffered register?buffered by the write to register 0. 1 1 .... 1 1 mod2_lsb value m1 m2 .... m13 m14 not allowed 0 0 .... 0 0 not allowed 1 0 .... 0 0 2 0 1 .... 0 0 3 1 1 .... 0 0 . . . .... . . . . . .... . . . . . .... . . 16380 0 0 .... 1 1 16381 1 0 .... 1 1 16382 0 1 .... 1 1 16383 1 1 .... 1 1 14-bit auxiliary modulus msb value (mod2_lsb) 14-bit auxiliary fractional lsb value (frac2_lsb) db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 c1(0) c2(1) c3(0) c4(0) m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 control bits 15084-030 figure 30 . register 2 register 1 control bits with bits[c4:c1] set to 0001, register 1 is programmed. figure 29 shows the input data format for programming this register. reserved bits[db31:db28] are reserved and must be set to 0. 24- bit main fractional value the 24 frac1 bits ( b its [ db 27: db 4] ) set the numerator of the fraction that is input to the - modulator. this fraction, along with the int value, specifies the new frequency channel that the synthesizer locks to, as shown in the rf synthesizer a worke d example section. frac1 values from 0 to (mod1 ? 1) cover chan nels over a frequency range equal to the pfd reference frequency. register 2 control bits with bits[c4:c1] set to 0010, regis ter 2 is programmed. figure 30 s hows the input data format for programming this register. 14- bit auxiliary fractional lsb value (frac2 _lsb ) use t his value with the auxili ary fractional msb value (r egister 13 , b its [ db 31: db 18]) to generate the total a uxiliary f ractional value. frac2 = ( frac2_msb 2 14 ) + frac2_lsb frac2 must be less than the mod 2 value programmed in register 2. 14- bit auxiliary modul us lsb value (mod2 _lsb ) use t his value with the aux iliary modulus msb value (r egister 13, b its [ db 17: db 4]) to generate total auxiliary modulus value. mod2 = ( mod2 _ msb ) 2 14 + mod2 _ lsb use mod2 to correct any residual error due to the main fractional modulus.
adf4356 data sh eet rev. 0 | page 20 of 35 sd load reset phase resync phase adjust db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 c1(1) c2(1) c3(0) c4(0) p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 p23 p24 pa1 pr1 sd1 0 dbr 1 24-bit phase value (phase) control bits reserved phase value (phase) p1 p2 .... p23 p24 0 0 0 .... 0 0 1 1 0 .... 0 0 2 0 1 .... 0 0 3 1 1 .... 0 0 . . . .... . . . . . .... . . . . . .... . . 16777212 0 0 .... 1 1 16777213 1 0 .... 1 1 16777214 0 1 .... 1 1 16777215 1 dbr = double buffered register?buffered by the write to register 0. 1 1 .... 1 1 pa1 0 1 disabled enabled phase adjust pr1 0 1 disabled enabled phase resync sd1 0 1 on register0 update disabled sd load reset 15084-031 figure 31 . register 3 register 3 control bits with bits[c4:c1] set to 0011, register 3 is programmed. figure 31 shows the input data format for programming this register. reserved bit db31 is reserved and must be set to 0. sd load reset when writing to register 0, the - m odulator reset s . for applicat ions in which the phase is continually adjusted, this may not be desirable ; therefore, in these cases , the - r eset can be disabled by writing a 1 to the sd1 bit (bit db30) . phase resync to use the phase resynchronization feature, the pr1 bit (bit db29) must be set to 1. if unused, the bit can be programmed to 0. the phase resync activation t im eo ut v alue must also be used in register 12 to ensure that the resynchronization feature is applied after the pll settle s to the final frequency. if the pll has not settled to the final frequency, phase resync may not function correctly. resynchronization is useful in phased array and beam forming applications. it ensures repeatability of output phase when programming the same frequency. in phase critical applicat ions that use frequencies r equiring the output divider (<3 4 00 mhz), it is necessary to feed the n divider with the divided vco frequency as distinct from the fundamental vco frequency , which is achieved by programming the d13 bit ( bit db24) in register 6 t o 0, which ensures divided feedback to the n divider. for resync applications, enable the - modulator load reset (sd l oad r eset) in register 3 by setting db30 to 0. t he phase of the rf output frequency can be adjust ed in 24 - bit steps from 0 (0) to 360 (2 24 ? 1) relative to the resync phase . for phase adjustment applications, the phase is set by b its [ p24 : p1 ]. ( phase value /16,777,216) 360 practically, this means that repeatable adjustable phase values ca n be achieved by using the resync feature with d ifferent phase values. phase adjust ment to adjust the relative output phase of the adf4356 on each register 0 update, set the pa1 bit (bit db28) to 1. this feature d iffers from the resynchronization feature in that it is useful when a djustments to phase ar e made continually in an application. for this function, disable the vco automatic calibration by setting the ac1 bit (bit db21) in register 0 to 1, and disable the sd load reset by setting the sd1 bit (bit db30) in register 3 to 1. 24- bit phase value t he phase of the rf output frequency can adjust in 24 - bit steps , f rom 0 (0) to 360 (2 24 ? 1). for phase adjust applications , the phase is set by ( phase value /16,777,216) 360 when the phase value is programmed to r egister 3, each subsequent adjustment o f r egister 0 increments the phase by the value in th is equation.
data sheet adf4356 rev. 0 | page 21 of 35 rd 2 r e f e r e nc e d o ub l er 0 d i s ab l ed 1 e nab l ed rd 1 r e f e r e nc e d i v i d e b y 2 0 d i s ab l ed 1 e nab l ed c p4 c p3 c p2 c p1 i c p ( ma ) 5 . 1k ? 0 0 0 0 0 . 30 0 0 0 1 0 . 60 0 0 1 0 0 . 90 0 0 1 1 1 . 20 0 1 0 0 1 . 50 0 1 0 1 1 . 80 0 1 1 0 2 . 10 0 1 1 1 2 .40 1 0 0 0 2 . 70 1 0 0 1 3 . 00 1 0 1 0 3 . 30 1 0 1 1 3 . 60 1 1 0 0 3.9 . 90 1 1 0 1 4 . 20 1 1 1 0 4 . 50 1 1 1 1 4. . 80 r1 0 r 9 .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. r 2 r 1 r d i v i d er ( r ) 0 0 0 1 1 0 0 1 0 2 . . . . . . . . . . . . . . . 1 1 0 0 102 0 1 1 0 1 102 1 1 1 1 0 102 2 1 1 1 1 102 3 db 3 1 db 30 db 2 9 db 2 8 db 2 7 db 2 6 db 2 5 db 2 4 db 2 3 db 2 2 db 2 1 db 20 db 1 9 db 1 8 db1 7 db1 6 db1 5 db1 4 db1 3 db1 2 db1 1 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 0 0 m3 m2 m1 rd 2 rd 1 r1 0 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 d 1 c p4 c p3 c p2 c p1 u 6 u 5 u 4 u 3 u 2 u 1 c3 (1) c2 (0) c1 ( 0 ) rdiv2 reference doubler curr e n t se tti n g 10 - b it r c o un t er c o n t r o l b it s mux logic pd polarity power-down cp three- state counter reset ref mode m u x o u t double buff u 5 l d p 0 1.8v 1 3.3v u 4 p d p ol ar it y 0 n e g a ti ve 1 p o s iti ve u 3 p ow e r d ow n 0 d i s ab l ed 1 e nab l ed u 2 c p t hr ee-s t a t e 0 d i s ab l ed 1 e nab l ed u 1 c o un t er r eset 0 d i s ab l ed 1 e nab l ed d 1 double buffered register 6, bits[db23:db21] 0 disabled 1 e nab l ed u 6 refin 0 single 1 diff m3 m2 m1 o u t p u t 0 0 0 t hr ee-s t a t e o u t p u t 0 0 1 dv dd 0 1 0 sd gnd 0 1 1 r d i v i d e r o u t p u t 1 0 0 n d i v i d e r o u t p u t 1 0 1 ana log lo ck d e t e c t 1 1 0 d igi t a l lo ck d e t e c t 1 1 1 r ese r ved db 0 c 4( 0 ) reserved dbr dbr dbr dbr 1 dbr = double buffered register?buffered by the write to register 0. 15084-032 figure 32 . register 4 register 4 control bits with bits[c4:c1] set to 0100, register 4 is programmed. figure 32 shows the input data format for programming this register. reserved bits[db31:db30] are reserved and must be set to 0. muxout the on - chip multiplexer (muxout) is controlled by bits[db29:db27] . f or additional details , see figure 32. when changing frequency, that is, writing r egister 0, muxout must not be set to n divider output or r divider output . if needed, enable these functions after locking to the new frequency. reference doubler setting the rd2 bit (bit db26 ) to 0 feeds the reference frequency signal directl y to the 10 - b it r counter, disabling the doubler. setting this bit to 1 multiplies the reference frequency by a factor of 2 before feeding it into the 10 - bit r counter. when the doubler is disabled, the ref in falling edge is the active edge at the pfd input to the frac tional synthesizer. when the doubler is enabled, both the rising and falling edges of the reference frequency become active edges at the pfd input. the maximum allow able reference frequency when the doubler is enabled is 8 0 mhz. rdiv2 setting the rdiv2 bit (bit db25) to 1 inserts a divide by 2 , toggle flip - flop between the r counter and pfd, which extends the maximum reference frequency input rate. this function provides a 50% duty cycle signal at the pfd input. 10- bit r counter the 10 - bit r counter divides the input reference frequency (ref in ) to produce the reference clock to the pfd. division ratios range from 1 to 1023. double buffer the d1 bit (bit db14 ) enables or disables double buffering of the rf divider select bits ( bits[db23:db21] ) in register 6 . the program modes section explains how double buffering works. charge pump current setting the cp4 to cp1 bits ( bits[db13:db10] ) set the charge pump current. set t his value to the charge pump current that the loop filter is designed with (see figure 32 ). for the lowest spurs, the 0.9 ma setting is recommended.
adf4356 data sh eet rev. 0 | page 22 of 35 reference mode the adf4356 permits use of either differential or single - ended reference sources. for optimum integer boundary spur performance, it is recommended to use the single - ended setting for all references up to 250 mhz (even if using a diffe rential refere nce signal). use the d ifferential setting for reference frequencies above 250 mhz. level select to assist wit h logic compatibility, muxout is programm able to two logic levels . set the u5 bit (bit db8) to 0 to select 1.8 v logic, and set it to 1 to select 3.3 v logic . phase detector polarity the u4 bit ( bit db7 ) sets the phase detector polarity. when a passive loop filter or a non inverting active loop filter is used, set db7 to 1 (positive) . if an active filter with an inverting characteristic is us ed, set this bit to 0 (negative) . power - down the u3 bit ( bit db6 ) sets the programmable power - down mode. setting db6 to 1 performs a power - down. setting db6 to 0 returns the synthesizer to normal operation. in software power - down mode, the adf4356 retains all information in its registers. the register contents are only lost if the supply voltages are removed. when power - down activate s , the following events occur: ? the s ynthesizer counters are forced to their load state conditions. ? the vco power s down. ? the c harge pump is forced into three - state mode. ? the d igital lock detect circuitry reset s. ? the rf out a+/rf out a? and r f out b+/rf out b? output stages are disabled. ? the i nput registers remain active and capable of loading and latching data. charge pump three - state setting the u2 bit (b it db5 ) to 1 puts the charge pump into three - state mode. set db5 to 0 for normal operation. counter reset the u1 bit ( bit db4 ) resets the r counter, n counter , and vco band select of the adf4356 . when db4 is set to 1, the rf synthesizer n counter , r counter , and vco band select are reset. fo r normal operation, set db4 to 0. register 5 the bits in register 5 are reserved and must be programmed as d escribed in figure 3 3 , using a hexadecimal word of 0x008000 2 5. 15084-033 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 db22 db23 db24 db25 db26 db27 db28 db29 db30 db31 c1(1) c2(0) c3(1) c4(0) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 reserved control bits figure 33 . register 5 ( 0x00800025 )
data sheet adf4356 rev. 0 | page 23 of 35 d3 0 disabled 1 enabled db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 bp1 0 1 d14 d13 d12 d11 d10 bl1 0 d8 d3 d2 d1 c4(0) c3(1) c2(1) control bits charge pump bleed current mtld rf divider selec t 1 feedback rf output b select select reserved d 2 d 1 0 0 ?4dbm 0 1 ?1dbm 1 0 +2dbm 1 1 +5dbm d6 0 1 d8 mute till lock detect 0 mute disabled 1 mute enabled d13 feedback select 0 fundamental 1 divided d14 rf output b select 0 fundamental 1 mirror rfouta c1(0) d12 d11 rf divider select 0 0 1 0 0 2 0 1 4 0 1 8 d10 0 1 0 1 1 1 1 0 0 1 16 32 64 0 1 0 bleed polarity bl8 bl7 .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. bl2 bl1 bleed current 0 0 0 1 1 (3.75a) 0 0 1 0 2 (7.5a) . . . . . . . . . . . . . . . 1 1 0 0 (945a) 252 1 1 0 1 253 (948.75a) 1 1 1 0 254 (952.5a) 1 1 1 1 255 (956.25a) bl2 bl3 bl4 bl5 bl6 bl7 bl8 negative bleed bl9 bl9 negative bleed 0 enabled 1 disabled reserved 1 gated bleed bl10 gated bleed 0 enabled 1 disabled bp1 bleed polarity 0 positive 1 negative bl10 1 bits[db23:db21] are buffered by a write to register 0 when the double buffer bit, bit db14 of register 4, is enabled. rf output a power rf output a enable rf output b power rf output b enable 0 rf output a enable 0 0 ?4dbm 0 1 ?1dbm 1 0 +2dbm 1 1 +5dbm rf output b power rf output a power rf output b enable disabled enabled d6 reserved d5 d4 d5 d4 15084-034 figure 34 . register 6 register 6 control bits with [c4:c1] set to 0110, register 6 is programmed. figure 34 shows the input data format for programming this register. bleed polarity db31 sets the polarity of the charge pump bleed current. gated bleed bleed currents can be used for improving phase noise and spurs ; however, due to a potential impact on lock time, the gated bleed bit , bl10 (bit db30 ) , if set to 1, ensures bleed currents are not switched on until the digital lock detect asserts logic high. note that t his function requires digital lock detect to be enabled. negative bleed use of constant negative bleed is recommended for most fractional - n applications because it improves the linearity of the charge pump , leading to lower noise and spurious signals than leaving it off. to enable negative bleed, writ e 1 to bl9 (bit db29 ) , and to disable negative bleed , w rit e 0 to bl9 (bit db29) . do not u se negative bleed when operating in integer - n mode, that is, frac1 = frac2 = 0. d o not use negative bleed for f pfd greater than 100 mhz. reserved bits[db28:d b26] are reserved and must be set to 101 . bit db12 is reserved and must be set to 0. bit db10 is reserved and must be set to 0. rf output b select d14 (bit db25) enables the rf output b (rf out b+/rf out b?) to selects the fundamental output from the vco . when this bit is disabled, rf out b+/rf out b? is a duplicate of rf out a+/rf out a?. feedback select d13 (bit db24 ) selects the feedback from the output of the vco to the n counter. when d13 is set to 1, the signal is taken directly from the vco. when th is bit is set to 0, the signal is taken from th e output of the output dividers. the dividers enable covera ge of the wide frequency band (54 m hz to 6800 m hz). when the divider is enabled and the feedback signal is taken from the output, the rf output signal s of two separately con fig ured plls are in phase. divided feedback is useful in some applications where the positive interference of signals is required to increase the power. divider select d1 2 to d1 0 ( bits[db23:db21] ) select the value of the rf output divider (see figure 34).
adf4356 data sh eet rev. 0 | page 24 of 35 charge pump bleed current bl8 to bl1 ( bits[db20:db13] ) control the level of the bleed current added to the charge pump output. this current o ptimize s the phase noise and spurious levels from the device. calculate t he optimal bleed set ting using the following rule. bleed value = f loor (24 ( f pfd /61.44 mhz) ( i cp /0.9 ma)) if f pfd > 1 00 mhz, disable bleed current using db29. where: bleed value is the value programmed to bits[db20:db13]. f loor() is a function to round down to the nearest integer value . f pfd is the pfd frequency. i cp is the value of charge pump current setting, bits[db13:db10] of register 4. mute till lock detect when d8 (bit db11) is set to 1, the supply current to the rf output stage is shut down until the device achieves lock, as determined by the digital lock detect circuitry. rf output b enable d 6 (bit db 9 ) enables or disables rf o utput b ( rf out b+/rf out b? ). if db10 is set to 0, rf o utput b is enabled . i f db10 is set to 1, the rf o utput b is disabled. rf output b power d5 and d4 (bits[db8:db7]) set the value of the rf output b (rf out b+/rf out b?) power level (see figure 34). rf output a enable d3 (bit db6 ) enables or disables rf o utput a (rf out a + / rf out a? ). i f db 3 is set to 0, rf o utput a is disabled . i f db6 is set to 1, rf o utput a is enabled. rf output a power d2 and d1 (bits [db5:db4] ) set the value of the rf o utput a ( rf out a+/rf out a? ) power level (see figure 34) .
data sheet adf4356 rev. 0 | page 25 of 35 db3 1 db3 0 db2 9 db2 8 db2 7 db2 6 db2 5 db2 4 db2 3 db2 2 db2 1 db2 0 db1 9 db1 8 db1 7 db1 6 db1 5 db1 4 db1 3 db1 2 db1 1 db1 0 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 0 0 0 0 0 0 0 0 0 0 0 ld1 c3 (1 ) c2 (1) c1 (1 ) c o n t r o l b it s reserved ld3 ld2 fractional-n ld precision 0 0 5.0ns 0 1 6.0ns 1 0 8.0ns 1 1 12.0ns ld1 0 fractional-n 1 integer-n (2.9ns) c 4(0) lock detect mode ld2 ld3 frac-n ld precision ld mode lol 0 disabled 1 enabled loss of lock mode lol mode lol ld5 ld4 lock detect cycle count 0 0 1024 0 1 2048 1 0 4096 1 1 8192 ld4 ld5 ld cycle count 0 0 0 0 0 0 0 0 reserved le sync le sel le1 le2 le2 0 1 le sync to reference falling edge le sync to reference rising edge le1 0 disabled 1 le synced to ref in le synchronization le sel sync edge r ese r ved 1 sync edge 15084-035 figure 35 . register 7 register 7 co ntrol bits with bits[c4:c1] set to 0111, register 7 is programmed. figure 35 shows the input data format for programming this register. reserved bits[db31:db2 8 ] are reserved and must be set to 0. db26 is reserved and must be set to 1. db26 is reserved and must be set to 1. bits[db24:db10] are reserved and must be set to 0. le s el sync edge bit db27 allows selection of the synchronization load enable (le) edge to the falling or rising edge of the reference clock, which is useful for applications that require synchroniza tion to a common reference edge (s ee figure 35) . to use this bit , le s ync (bit db25) must be set to 1. le sync when set to 1, bit db25 ensures that the load enable (le) edge is synchronized internally with the rising edge of reference inp ut frequency. this synchronization prevents the rare event of reference and rf dividers loading at the same time as a falling edg e of the reference frequency, which can lead to longer lock times. fractional - n lock det ect (ld) cycle count ld5 and ld4 (bits [db9:db8]) set the number of consecutive cycles counted by the lock detect circuitry before asserting lock detect high (s ee figure 35 for details ) . loss of lock (lol) mode set the lol mode bit (bit db7) to 1 when the application is a fixed frequency application in which the reference (ref in ) is likely to be removed, such a s a clocking application. the standard lock detect circuit assumes that ref in is always present; however, this may not be the case with clocking applications. to enable this functionality, set db7 to 1. fractional - n lock detect (ld) precision ld3 and ld2 (bits[db6:db5]) set the precision of the lock detect circuitry in fractional - n mode. ldp is available at 5 ns, 6 ns, 8 ns, or 12 ns. if bleed currents are used, use 12 ns. lock detect (ld) mode t to 0, lock detect precision is set by fractional - n lock det ect precision as described in the fractional - n lock detect (ld) precision section. if db4 is set to 1, lock detect precision is 2.9 ns long, which is more appropriate for integ er - n applications.
adf4356 data sh eet rev. 0 | page 26 of 35 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 reserved control bits 1 0 1 0 0 0 1 0 0 1 c3(0) c2(0) c1(0) c4(1) 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 15084-036 figure 36 . register 8 ( 0x15596568 ) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 vc5 vc4 vc3 vc2 vc1 timeout control bits tl10 tl9 tl8 tl7 tl6 tl5 tl4 tl3 tl2 tl1 al5 al4 al3 al2 al1 sl5 sl4 sl3 sl2 sl1 c3(0) c2(0) c1(1) c4(1) vc6 vc7 vc8 tl10 tl9 .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. tl2 tl1 timeout 0 0 0 1 1 0 0 1 0 2 . . . . . . . . . . . . . . . 1 1 0 0 1020 1 1 0 1 1021 1 1 1 0 1022 1 1 1 1 1023 al5 al4 .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. al2 al1 alc wait 0 0 0 1 1 0 0 1 0 2 . . . . . . . . . . . . . . . 1 1 0 0 28 1 1 0 1 29 1 1 1 0 30 1 1 1 1 31 vc8 vc7 .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. vc2 vc1 vco band div 0 0 0 1 1 0 0 1 0 2 . . . . . . . . . . . . . . . 1 1 0 0 252 1 1 0 1 253 1 1 1 0 254 1 1 1 1 255 vco band division sl5 sl4 .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. sl2 sl1 slc wait 0 0 0 1 1 0 0 1 0 2 . . . . . . . . . . . . . . . 1 1 0 0 28 1 1 0 1 29 1 1 1 0 30 1 1 1 1 31 synthesizer lock timeout automatic level calibration timeout 15084-037 figure 37 . register 9 register 8 the bits in this register are reserved and must be programmed as shown in figure 36 , using a hexadecimal word of ( 0x15596568) . register 9 for a worked example and more information, see the lock time section. control bits with bits[c4:c1] set to 1001 , register 9 is programmed. figure 37 shows the input data format for programming this register. vco band division vc8 to vc1 ( bits[db31:db24] ) set the value of the vco band division clock. determine t he value of this clock by vco band div ision = ceiling( f pfd / 1 ,6 00 ,000) timeout tl10 to tl1 ( bits[db23:db14] ) set the timeout value for the vco band select. auto matic level calibration (alc) timeout al5 to al1 ( bits[db13:db9] ) set the timer value used for the automatic level calibration of the vco. t his function combines the pfd frequency , the t imeout variable, and alc wait variable . cho o se the alc such that the following equation is always greater than 50 s. alc wait > ( 50 s f pfd )/ timeout synth esizer l ock timeout sl5 to sl1 ( bits[db8:db4] ) set the synthesizer lock timeout value. this value allow s the v tune force to settle on the v tune pin. t he value must be 20 s. calculate t he value using the following equation : synthesizer lock timeout > (20 s f pfd )/ timeout
data sheet adf4356 rev. 0 | page 27 of 35 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 00 0 00 reserved control bits 110 0000000 c3(0) c2(1) c1(0) c4(1) 000 ae1 ae2ad1 ad2 ad3 ad4 ad5 ad6 adc enable adc conversion ad7 ad8 adc clock divider ad8 ad7 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ad2 ad1 adc clk div 00 011 00 102 .. ... .. ... .. ... 1 1 0 0 252 1 1 0 1 253 1 1 1 0 254 1 1 1 1 255 ae1 adc 0disabled 1enabled ae2 adc conversion 0disabled 1enabled 15084-038 figure 38. register 10 register 10 control bits with bits[c4:c1] set to 1010, register 10 is programmed. figure 38 shows the input data format for programming this register. reserved bits[db31:db14] are reserved. bits[db23:db22] must be set to 11, and all other bits in this range must be set to 0. adc clock divider (adc_clk_div) an on-board analog-to-digital converter (adc) determines the v tune setpoint relative to the ambient temperature of the adf4356 environment. the adc ensures that the initial tuning voltage in any application is chosen correctly to avoid any temperature drift issues. the adc uses a clock that is equal to the output of the r counter (or the pfd frequency) divided by adc_clk_div. ad8 to ad1 (bits[db13:db6]) set the value of this divider. on power-up, the r counter is not programmed; however, in these power-up cases, it defaults to r = 1. choose the value such that adc_clk_div = ceiling((( f pfd /100,000) ? 2)/4) where ceiling() is a function that rounds up to the nearest integer. for example, for f pfd = 61.44 mhz, set alc_clk_div = 154 so that the adc clock frequency is 99.417 khz. if adc_clk_div is greater than 255, set it to 255. adc conversion enable ae2 (bit db5) ensures that the adc performs a conversion when a write to register 10 is performed. it is recommended to enable this mode. adc enable ae1 (bit db4), when set to 1, powers up the adc for the temperature dependent v tune calibration. it is recommended to always use this function.
adf4356 data sh eet rev. 0 | page 28 of 35 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 rese r ved rese r ved control bits 0 1 0 0 0 0 0 c3(0) c2(1) c1(1) c4(1) 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 vh vh vco band hold 0 1 normal operation vco band hold vco band hold 15084-039 figure 39 . register 11 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 p13 p12 p 1 1 p10 p9 phase resync clock value control bits p8 p7 p6 p5 p4 p3 p2 p1 0 1 0 1 c3(1) c2(0) c1(0) c4(1) p14 p15 p16 p17 p18 p19 p20 p20 p19 ... p5 p4 p3 p2 p1 resync clock 0 0 ... 0 0 0 0 0 not allowed 0 0 ... 0 0 0 0 1 1 0 0 ... 0 0 0 1 0 2 . . ... . . . . . ... 0 0 ... 1 0 1 1 0 22 0 0 ... 1 0 1 1 1 23 0 0 ... 1 1 0 0 0 24 . . ... . . . . . ... 1 1 ... 1 1 1 0 1 65533 1 1 ... 1 1 1 1 0 65534 1 1 ... 1 1 1 1 1 1048575 rese r ved 1 1 1 1 15084-040 figure 40 . register 12 register 11 control bits with bits[c4:c1] set to 1011, register 11 is programmed. figure 39 s hows the input data format for programming this register. reserved bits[db31:db 25 ] are rese rved a nd must be set to 0 . bit db22, bit db2 1, bit db16 , and bit db13 must be set to 1, and all oth er bits in this range (bits [db23:db4 ] ) must be set to 0. vco band hold vh (bit db 2 4), when set to 1, prevents a reset of the vco core, band , and bias during a counter reset. vco b and h old is required for applications that use external plls. register 12 control bits with bits[c4:c1] set to 1100, register 12 is programmed. figure 40 s hows the input data format for programming this register. phase resync clock value p20 to p1 ( bits[db31:db1 2 ] ) set the timeout counter for activation of phase resync. this value must be set such that a resync happens immediately after (and not before) the pll has achieved lock after reprogramming. c alculate the timeout valu e using the following equation : time out value = phase resync clock value / f pfd when not using phase resync , set these bits to 1 for normal operation . reserved bits [ db1 1 :db4] are reserved . bit db10 and bit s[ db 8:db4 ] must be set to 1, and all other bits in this range must be set to 0.
data sheet adf4356 rev. 0 | page 29 of 35 m14 m13 .......... m2 m1 mod2_msb value 0 0 .......... 0 0 0 0 .......... 0 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 16380 1 1 .......... 0 1 16381 1 1 .......... 1 0 16382 1 1 ......... 1 1 16383 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 14-bit auxiliary modulus msb value (mod2_msb) control bits m14 m13 m12 m11 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 c3(1) c2(0) c1(1) c4(1) db r db r f14 f13 .......... f2 f1 frac2_msb word 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 16381 1 1 .......... 0 1 16382 1 1 .......... 1 0 16382 1 1 ......... 1 1 16383 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f12 f13 f14 14-bit auxiliary fractional msb value (frac2_lsb) 1 dbr = double buffered register?buffered by the write to register 0. 0 1 15084-041 figure 41 . register 13 register 13 control bits with [c4:c1] set to 1101 , register 13 is programmed. figure 41 s hows the input data format for programming this register. 14- bit auxiliary fractional msb value (frac2_msb) this value is used with the a uxiliary f ractional lsb value (r egister 2 , b its [ db 31: db 18]) to generate the total a uxiliary f ractional frac2 value . frac2 = ( frac2 _ msb 2 14 ) + frac2 _ lsb th ese bits can be set to all zeros to ensure soft ware compatibility with the adf4 355. 14- bit auxiliary modulus msb value (mod2_msb) thi s value is used with the auxiliary f ractional msb value (r egister 2, b its [ db 17: db 4]) to generate the total a ux iliary m odulus mod2 value. mod2 = ( mod2 _ msb 2 14 ) + mod2 _ lsb register initializat ion sequence at initial power - up, after the correct application of voltages to the supply pins, the adf4356 registers must be programmed in sequence. for f 75 mhz, use the following sequence: 1. register 13 . 2. register 12 . 3. register 11 . 4. register 10 . 5. register 9 . 6. register 8 . 7. register 7 . 8. register 6 . 9. register 5 . 10. register 4 . 11. register 3 . 12. register 2 . 13. register 1 . 14. ensure that >16 adc_clk cycles have elapsed between the write of register 10 and register 0 . for example, if adc_clk = 99.417 khz, wait 16/99,417 sec = 161 s. see the register 10 section for more information. 15. register 0 . for f pfd > 75 mhz (initially lock w ith halved f pfd ) , use the following sequence: 1. register 1 3 (for halved f pfd ) . 2. register 12 . 3. register 11 . 4. register 10 . 5. register 4 (with the r divider doubled to halve f pfd ). 6. register 9 . 7. register 8 . 8. register 7 . 9. register 6 (for the desired f pfd ) . 10. register 5 . 11. register 4 (with the r divider doubled to halve f pfd ). 12. register 3 . 13. register 2 (for halved f pfd ). 14. register 1 (for halved f pfd ). 15. ensure that >16 adc_clk cycles have elapsed between the write of register 10 and register 0. for example, if adc_clk = 99.417 khz , wait 16/99 , 417 sec = 161 s. see the register 10 section for more information . 16. register 0 (for halved f pfd ; autocalibration enabled). 17. register 1 3 (for the desired f pfd ) . 18. register 4 (with the r divider set for the desired f pfd ). 19. register 2 (for the desired f pfd ) . 20. register 1 (for the desired f pfd ) . 21. register 0 (for the desired f pfd ; autocalibration disabled ) .
adf4356 data sh eet rev. 0 | page 30 of 35 frequency update sequence frequency updates require updating the auxiliary modulator ( mod2) in register 2, the fractional value (frac1) in register 1, and the integer value (int) in register 0. it is recommended to perform a temperature dependent v tune calibration by updating register 10 first. therefore, for f pfd 75 mhz , the sequence must be as follows: 1. register 13. 2. register 10 . 3. register 2 . 4. register 1 . 5. ensure that >16 adc_clk cycles have elapsed between the write of register 10 and register 0. for example, if adc_clk = 99.417 khz, wait 16/99,417 sec = 161 s. see the register 10 s ection for more information. 6. register 0 . for f pfd > 75 mhz (initially lock with halved f pfd ) , the sequence must be as follows: 1. register 13 ( for halved f pfd ). 2. register 10. 3. register 2 (for hal ved f pfd ). 4. register 1 (for halved f pfd ). 5. ensure that >16 adc_clk cycles have elapsed between the write of register 10 and register 0. for example, if adc_clk = 99.417 khz, wait 16/99,417 sec = 161 s. see the register 10 section for more information. 6. register 0 (for halved f pfd ; autocalibration enabled). 7. register 13 (for the desired f pfd ). 8. register 2 (for the desired f pfd ). 9. register 1 (for the desired f pfd ). 10. register 0 (for desired f pfd ; autocalibration disabled). the frequency change occurs on the write to r egister 0 . rf synthesizer a worked example use the following equations to program the adf4356 synthesizer: ( ) divider rf f mod1 mod2 frac2 frac1 int rf pfd out / + + = rf out is the rf output frequency . int is the integer division factor. frac1 is the fractionality. frac2 is the auxiliary fractionality ( frac2 = (frac2_msb 2 14 ) + frac2_lsb ) . mod2 is the auxiliary modulus ( mod2 = (mod2_msb 2 14 ) + mod2_lsb ) . mod1 is the fixed 24 - bit modulus. rf divider is the output divider that divides down the vco frequency. f pfd = ref in ((1 + d )/( r (1 + t ))) ( 8 ) where: ref in is the reference frequency input. d is the ref in doubler bit. r is the ref in reference division factor. t is the reference divide by 2 bit (0 or 1). for example, in a universal mobile telecommunication system (umts) where a 2112.8 mhz rf frequency output (rf out ) is required, a 122.88 mhz reference frequency input (ref in ) is available. note that the adf4356 vco operates in the frequency range of 3 400 m hz to 68 00 m hz. therefore, the rf divider of 2 must be used (vco frequency = 4225.6 mhz, rfout = vco frequency/rf divider = 4225.6 mhz/2 = 2112.8 mhz). the feedback path is also important. in this example, the vco output is fed bac k before the output divider (see figure 42). in this example, the 122.88 mhz reference signal is divided by 2 to generate f pfd of 61.44 mhz. the desired channel spaci ng is 200 khz. pfd n divider rf out f pfd vco 2 15084-042 figure 42 . loop closed before output divider the worked example is as follows: n = vco out / f pfd = 4225.6 mhz/ 61.44 mhz = 68.7760416666666667 int = int( vco frequency / f pfd ) = 68 frac = 0.7760416666666667 mod1 = 16,777,216 frac1 = int( mod1 frac ) = 13 ,019,818 remainder = 0.6666666667 or 2/3 mod2 = f pfd /gcd( f pfd , f chsp ) = 61.44 mhz/gcd(61.44 mhz, 200 khz) = 1536 frac2 = remainder 1536 = 1024 from equation 8 , f pfd = (122.88 mhz (1 + 0)/2) = 61.44 mhz ( 9 ) 2112.8 mhz = 61.44 mhz (( int + ( frac1 + frac2 / mod2 )/ 2 24 ))/2 ( 10) where: int = 68 frac1 = 13,019,81 8 frac2 = 1024 mod2 = 1536 rf divider = 2
data sheet adf4356 rev. 0 | page 31 of 35 reference doubler an d reference divider the on - chip reference doubler allows the input reference signal to be doubled. th e doubler is useful for increasing the pfd comparison frequency. to improve the noise performance of the system , increase the pfd frequency. doubling the pfd frequency typically improves noise performance by 3 db. the reference divide by 2 divides the reference signal by 2, resulting in a 50% duty cycle pfd frequency. spurious optimizatio n and fast lock narrow loop bandwidths can filter unwanted spurious signals ; however, these bandwidths typically have a long lock time. a wider loop band width achieves fa ster lock times but may lead to increased spurious signals inside the loop bandwidth. optimizing jitter for lowest jitter applications, use the highest possible pfd frequency to minimize the contribution of in - band noise from the pl l. set t he pll filter bandwidth such that the in - band noise of t he pll intersects with the open - loop noise of the vco , minimizing the contribution of both to the overall noise. use t he adisimpll desi gn tool for this task. spur mechanisms this section describes the two different spur mechanisms that arise with a fractional - n synthesizer and how to minimize them in the adf4356 . integer boundary spurs one mechanism for fractional spur creation is the interactions between the rf vco frequency and the reference frequency. when these frequencies are not integer related (the purpose of a fractional - n synthesizer), spur sidebands appear on the vco output spectr um at an offset frequency that corresponds to the beat note or the difference in frequency between an integer multiple of the reference and the vco frequency. these spurs are attenuate d by the loop filter and are more noticeable on channels close to intege r multiples of the reference where the difference frequency can be inside the loop bandwidth ( thus the name , integer boundary spurs). reference spurs reference spurs are generally not a problem in fractional - n synthesizers because the reference offset is f ar outside the loop bandwidth. however, any reference feedthrough mechanism that bypasses the loop can cause a problem. feedthrough of low levels of on - chip reference switching noise, through the prescaler back to the vco, can result in reference spur leve ls as high as ?8 5 dbc. lock time the pll lock time divide s into a number of settings. all of these settings are modeled in the adisimpll design tool . much faster lock times than those detailed in this data sheet are possible; c ontact analog devices for more information. lock time a worked example assume that f pfd = 61.44 mhz, vco band div = c eiling( f pfd / 1,600, 000) = 39 where c eiling() is a function that rounds up to the nearest integer. by com bining alc wait > (50 s f pfd )/ timeout synthesizer lock timeout > (20 s f pfd )/ timeout it is found that alc wait = 2.5 synthesizer lock timeout the alc w ait and synthesizer lock timeout values must be set to fulfill this equation. b oth values are 5 bits wide; therefore, the maximum value for either is 31. there are several suitable values . the following values meet the criteria: alc wait = 30 synthesizer lock timeout = 12 finally, alc w ait > (50 s f pfd )/timeout , is re arranged for timeout = c eiling (( f pfd 50 s)/ alc wait ) timeout = c eiling ((61.44 mhz 50 s)/ 30) = 103 synth esizer lock timeout the synth esizer lock timeout ensure s that the vco calibration dac , which forces v tune , has settled to a steady value for the band select circuitry . the timeout and synthesizer lock timeout variables programmed in r egister 9 select the length of time the dac is allowed to settle to the final voltage, before the vco calibration process c ontinue s to the next phase , which i s vco band selection . the pfd frequency is the clock for this logic, and the duration is set by pfd f timeout lock r synthesize timeout vco band selection use the pfd frequency again as the clock for the band selection process. calculate this value by f pfd /( vco band selection 16) < 1 0 0 khz the b and select ion takes 11 cycles of the previously calculated value. calculate t he duration by 11 ( vco band selection 16)/ f pfd auto matic level calibration timeout use t he auto matic level calibration (alc) function to choose the correct bias current in the adf4356 vco core. calculate t he time taken by 30 alc wait t imeout / f pfd
adf4356 data sh eet rev. 0 | page 32 of 35 pll low - pass filter settling time the time taken for the loop to settle is in versely proportional to the low - pass filter bandwidth. th e settling time is also modeled in the adisimpll design tool . the total lock time for changing frequencies is the sum of the four separate times (synth esizer lock, vco band selection, alc timeout , and pll settling time) and is all modeled in the adisimpll design tool .
data sheet adf4356 rev. 0 | page 33 of 35 applications informa tion power supplies the adf4356 contains four multiband vcos that cover an octave range of frequencies. to ensure the best performance, it is vital to connect a low noise regulator, such as the adm7150 or the adm7170 to the v vco pin. connect the same regulator to pa ckage pins v vco , v regvco , and v p . for the 3.3 v supply pins, use two adm7170 regulators, one for the dv dd and av dd supplies and one for v rf . figure 43 shows the recommended connections. printed circuit boar d ( pcb ) design guidelines for a chip - scale package the lands on the 32 - lead , lead frame chip scale package are rectangular. the pcb pad for these lands must be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. center e ach land on the pad to maximize the solder joint size. the bottom of the chip scale packag e has a central exposed thermal pad. the thermal pad on the pcb must be at least as large as the exposed pad. on the pcb, there must be a minimum clearance of 0.25 mm between the thermal pad and the inner edges of the pad pattern. this clearance ensures th e avoidance of shorting. to improve the thermal performance of the package, use t hermal vias on the pcb thermal pad. if vias are used, incorporate the m into the thermal pad at the 1.2 mm pitch grid. the via diameter must be between 0.3 mm and 0.33 mm, and the via barrel must be plated with 1 oz. of copper to plug the via. for a microwave pl l and vco synthesizer , such as the adf4356 , take care with the board stack - up and layout. do not consider using fr4 material because it is too lossy above 3 ghz. instead, rogers 4350, rogers 4003, or rogers 3003 dielectric material is suitable. take c are with the rf output traces to minimize discont inuities and ensure the best signal integrity. via placement and grounding are critical. 100? v out = 5.0v v in = 6.0v vout ref gnd ref_sense vreg byp en on off vin c out 1f c in 1f c reg 10f c byp 1f 430? 68? spi-compatible serial bus v rf = 3.3v v in = 6.0v vout ref gnd ref_sense vreg byp en on off vin c out 1f c in 1f c reg 10f c byp 1f v out = 3.3v v in = 6.0v vout ref gnd ref_sense vreg byp en on off vin c out 1f c in 1f c reg 10f c byp 1f adf4356 adm7150 17 8 1nf 1nf fref in ref in a ref in b ref out b+ ref out b? ref out a+ v rf 1nf 1nf 7.5nh 7.5nh ref out a? clk data le fref in 1nf 1nf 29 28 1 2 3 nic cp gnd 31 sd gnd a gndrf 9 13 18 21 agnd 24 v bias 23 v ref 19 v regvco 0.1f 10pf 22 v vco v p av dd dv dd av dd ce pdb rf v rf c reg 1 c reg 2 muxout 100nf 6 27 5 16 4 26 10 32 25 30 14 15 11 12 v tune 20 cp out 7 100nf 0.1f 10pf 0.1f 33nf 6800pf 1f 10pf adm7150 adm7150 lock detect 15084-043 figure 43 . power supplies
adf4356 data sh eet rev. 0 | page 34 of 35 output matching the low frequency output can simply be ac - coupled to the next circuit , if desired ; however, if a higher output power is required, use a pull - up induct or to increase the output power level. rf out a+ v rf 50? 100pf 7.5nh 15084-044 figure 44 . optimum output stage when differential outputs are n ot require d, terminate the unused output or combine it with both outputs using a balun. for lower frequencies below 2 ghz , i t is recommended to use a 100 nh inductor on the rf out a +/rf out a? pins and a 100 pf ac c oupling capacitor . the rf out a+/rf out a? pins are a differential circuit . p rovide each output with the same (or similar) components where possible , such as the same shunt inductor value, bypass capacitor , and termination. the rf out b+/rf out b? outputs can be treated the same as the rf out a+/rf out a? output s . if unused, leave both rf out b+/rf out b? pins open.
data sheet adf4356 rev. 0 | page 35 of 35 outline dimensions 0.50 0.40 0.30 01-26-2016-b 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.25 min 3.75 3.60 sq 3.55 compliant to jedec standards mo-220- whhd-5 . pkg-004570 figure 45 . 32 - lead lead frame chip scale package [lfcsp] 5 mm 5 mm body and 0.75 mm package height (cp - 32 - 12 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adf4356 bcpz ?40c to +85c 32- lead lead frame chip scale package [lfcsp] cp -32-1 2 adf4356 bcpz - rl7 ?40c to +85c 32- lead lead frame chip scale package [lfcsp] cp -32-1 2 ev - adf4356 sd1z evaluation board 1 z = rohs compliant part. ? 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d15084 - 0- 10/16(0)

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