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| [AK4490EN] 015013666 - e - 01 2015/1 2 - 1 - 1. general description the ak4490 en is a new generation premium 32 - bit 2ch dac with new technologies , achieving industry s leading level low distortion characteristics and wide dynamic range. the ak4490 en integrates a newly developed switched capaci tor filter osr doubler , making it capable of supporting wide range signals and achieving low out - of - band noise while realizing low power consumption. moreover, the ak4490 en has five types of 32 - bit digital filters, realizing simple and flexible sound tun ing in wide range of applications. the ak4490 en accepts up to 768khz pcm data and 11.2 m hz dsd data, ideal for a high - resolution audio source playback that are becoming widespread in network audios and usb - dacs . application: av receivers, cd/sacd player, n etwork audios, usb dac s, usb headphones, sound plate s /bar s, measurement equipment, control systems, public audio s (pa), smart cellular phones, ic - reco r der s , bluetooth headphone s , hd audio/voice conference systems 2. features ? 256 x over sampling ? sampling r ate: 30khz ? ? 3 2 - b it 8x digital filter - ripple: ? ? high tolerance to clock jitter ? low distortion differential output ? 2.8mhz, 5.6mhz and 11.2mhz dsd input support - filter (fc=50khz, fc=150khz, 2.8mhz mode) ? digital de - emphasis for 32, 44.1, 48khz sampling ? soft mute ? digital attenuator (255 levels and 0.5db step + mute ) ? mono mod e ? external digital filter mode ? thd+n: - 1 1 2 db ? dr, s/n: 12 0 db ( mono mode: 12 3 db) ? i/f format: 24/32bit msb justified, 16/20/24/32bit lsb justified, i 2 s, dsd ? master clock: 30khz ~ 32khz : 256fs , 384fs , 512fs , 768fs , 1024fs or 1152fs 30khz ~ 54khz : 25 6fs , 384fs , 512fs or 768fs 30khz ~ 96 khz: 256fs , 384fs or 512fs 30khz ~ 108khz: 256fs or 384fs 108khz ~ 192 khz: 128fs , 192fs or 256fs 108khz ~ 216khz: 128fs or 192fs 384khz: 32fs, 48fs, 64fs or 96 fs 768khz: 16fs, 32fs, 48fs or 64fs ? power supply: dvdd=avd d= 3.0 ? ? ? ? digital input level: c mo s ? package: 4 8 - pin qf n AK4490EN premium 32 - bit 2ch dac
[AK4490EN] 015013666 - e - 01 2015/1 2 - 2 - 3. table of contents 1. general description ................................ ................................ ................................ ............................ 1 2. features ................................ ................................ ................................ ................................ .............. 1 3. table of contents ................................ ................................ ................................ ................................ 2 4. block diagram ................................ ................................ ................................ ................................ ..... 4 5. pin configurations and functions ................................ ................................ ................................ ....... 5 pin layout ................................ ................................ ................................ ................................ .......... 5 pin functions ................................ ................................ ................................ ................................ ...... 6 handling of unused pin ................................ ................................ ................................ ..................... 8 6. absolute maximum ratings ................................ ................................ ................................ ................ 9 7. recommended operating conditions ................................ ................................ ................................ . 9 8. electrical characteristics ................................ ................................ ................................ ................... 10 analog characteristics ................................ ................................ ................................ ..................... 10 sharp roll - off filter characteristics (fs=44.1khz) ................................ ................................ .......... 11 sharp roll - off filter cha racteristics (fs=96khz) ................................ ................................ ............. 11 sharp roll - off filter characteristics (fs=192khz) ................................ ................................ ........... 11 short delay sharp roll - off filter characteristics (fs=44.1khz) ................................ ...................... 13 short delay sh arp roll - off filter characteristics (fs=96khz) ................................ ......................... 13 short delay sharp roll - off filter characteristics (fs=192khz) ................................ ....................... 13 slow roll - off filter characteristics (fs=44.1khz) ................................ ................................ ............ 15 slow roll - off filter characteristics (fs=96khz) ................................ ................................ ............... 15 slow roll - off filter characteristics (fs=192khz) ................................ ................................ ............. 15 short delay slow roll - off filter characteristics (fs=44.1khz) ................................ ........................ 17 short delay slow roll - off filter characteristics (fs=96khz) ................................ ........................... 17 short delay slow roll - off filter characteristics (fs=192khz) ................................ ......................... 17 dsd mode characteristics ................................ ................................ ................................ ............... 19 dc characteristics ................................ ................................ ................................ ........................... 19 switching characteristics ................................ ................................ ................................ ................. 20 timing diagram ................................ ................................ ................................ ................................ 22 9. functional descriptions ................................ ................................ ................................ ..................... 27 d/a conversion mode ................................ ................................ ................................ ...................... 27 system clock ................................ ................................ ................................ ................................ ... 27 audio interface format ................................ ................................ ................................ ..................... 35 d/a conversion mode switching timing ................................ ................................ ......................... 40 de-emphasis filter ................................ ................................ ................................ ........................... 41 output volume (pcm, dsd) ................................ ................................ ................................ ............ 41 zero detection (pcm, dsd , ex df i/f ) ................................ ................................ .......................... 42 mono output (pcm, dsd, ex df i/f) ................................ ................................ ............................. 42 sound quality control (pcm, dsd, ex df i/f) ................................ ................................ ............... 42 characteristics (dsd) ................................ ................................ ................................ ...................... 43 soft mute operation (pcm, dsd) ................................ ................................ ................................ .... 44 system reset ................................ ................................ ................................ ................................ ... 44 power on/off timing ................................ ................................ ................................ ...................... 45 reset function ................................ ................................ ................................ ................................ . 46 synchronize function ................................ ................................ ................................ ....................... 48 register control interface ................................ ................................ ................................ ................ 50 register map ................................ ................................ ................................ ................................ .... 55 register definitions ................................ ................................ ................................ .......................... 55 10. recommended external circuits ................................ ................................ ................................ ... 61 11. package ................................ ................................ ................................ ................................ ......... 66 outline dimensions ................................ ................................ ................................ .......................... 66 [AK4490EN] 015013666 - e - 01 2015/1 2 - 3 - material & lead finish ................................ ................................ ................................ ....................... 66 marking ................................ ................................ ................................ ................................ ............. 67 12. ordering guide ................................ ................................ ................................ .............................. 67 ordering guide ................................ ................................ ................................ ................................ . 67 13. revision history ................................ ................................ ................................ ............................. 67 important notice ................................ ................................ ................................ .............................. 68 [AK4490EN] 015013666 - e - 01 2015/1 2 - 4 - 4. block diagram block diagram mclk s data/dsdl /di nl csn/smute bi ck /dclk /bck cclk/dem0 cdti/dem1 vss r vddr pdn avdd scf scf clock divider d vss dvdd wck cad1/ acks psn dzfl/dif 0 cad0/ dif2 vss l vddl vcml aoutrn vcmr vrefhl vrefll vreflr vrefll a vss aoutlp aoutln aoutrp pcm data interface dsd data interface external df interface interpolator control register bias vref lr ck /dsdr/dinr sslow dzf r /dif 1 datt soft mute ? ? ? modulator volume pass dsdd bit 1 normal path dsdd bit 0 fs=384khz, 768khz t vdd [AK4490EN] 015013666 - e - 01 2015/1 2 - 5 - 5. pin configurations and functions pin layout vrefhl vrefhl nc avdd avss mclk tvdd dvss aoutlp aoutln vddl vddl vssl vssl vddr nc nc pdn bick/dclk /bck sdata/dsdl /dinl lrck/dsdr /dinr sslow /wck smute/csn vrefhr nc acks/cad1 dem1 dem0 i2c psn dif2/cad0 ak4 490 en top view 40 41 42 43 44 45 46 47 36 35 34 20 19 18 17 16 15 14 13 33 32 31 30 29 1 2 3 4 5 6 7 8 48 vrefhr 21 sd/cclk/scl 9 vssr vssr dvdd slow/cdti/sda dif0/dzfl 10 11 dif1/dzfr 12 vr eflr vreflr 23 22 vcomr 24 vcoml vrefll vrefll 37 38 39 aoutrp 28 27 26 25 vddr aoutrn lrck 18 [AK4490EN] 015013666 - e - 01 2015/1 2 - 6 - pin functions no. pin name i/o function 1 nc - no internal bonding. connect to gnd. 2 nc - no internal bonding. connect to gnd . 3 pdn i power - down mode pin when at = ) =l) = ) = psn=l, i2c= = ) = = = ) = = = ) = ) = ) = ) = ) = ) = ) [AK4490EN] 015013666 - e - 01 2015/1 2 - 7 - 17 dem1 i de - emphasis enable 1 pin in parallel control mode ( psn = ) = ) l: manual setting mode, h: auto setting mode = ) ? ? ? ? ? ? [AK4490EN] 015013666 - e - 01 2015/1 2 - 8 - handling of unused pin the unused i/o pins should be processed appropriately as below. (1) parallel mode (pcm mode only) classification pin name setting analog aoutlp, aoutln these pins must be open. aoutrp, aoutrn these pins must be open. digital i2c this pin must be connected to dvss or open . (2) serial m ode 1. pcm mode classification pin name setting analog aoutlp, aoutln these pins must be open. aoutrp, aoutrn these pins must be open. digital dem1 th is pin must be connected to dvss or open . dem0 this pin must be connected to tvdd or open. smute/csn this pin must be connected to tvdd or dvss , w hen this pin is i2c= i2c= i2c= pull - down pin list pull - down pin 1 5 , 1 7 , 1 8 [AK4490EN] 015013666 - e - 01 2015/1 2 - 9 - 6. absolute maximum ratings ( avss=dvs s=vssl=vssr=vrefll=vreflr= 0v ; note 2 ) parameter symbol m in . m ax . unit power supplies: analog analog digital input buffer |avss ? ? ? ? ? ? ? ? ? ? ? ? f or more decoupling capacitors between vddl/vddr and vssl/vssr to suppress affections by a static electricity noise or an over voltage (includes over shooting) that exceeds absolute maximum ratings. warning: operation at or beyond these limits may resul t in permanent damage to the device. normal operation i s not guaranteed at these extremes. 7. recommended operating conditions ( avss=dvss=vssl=vssr =vrefll=vreflr =0v ; note 2 ) parameter symbol m in . t yp . m ax . unit powe r supplies ( note 5 ) analog analog digital input buffer avdd vddl/r dvdd tvdd 3.0 4.75 3.0 1.6 3.3 5.0 3.3 1.8 3.6 5.25 3.6 dvdd v v v voltage reference ( note 6 ) ? pdn pin = l 2. tvdd ( 1.8 v) power - up 3. av dd , dvdd ( 3 v) power - up 4 . vrefhl/r and v ddl/r (5v) power - up 5 . the pdn pin is allowed to be h after all power supplies are applied and settled. otherwise power up the 1.8 v power suppl y, the 3.3v po wer supplies and the 5v power supplies at the same time . [AK4490EN] 015013666 - e - 01 2015/1 2 - 10 - 8. electrical characteristics analog characteristics ( ta= 25 ? c ; a vdd= dvdd=3. 3 v; tvdd=1.8v; avss= dvss=vssl/r=0v; vrefhl/r=vddl/r=5v, vrefll/r= vssl/r =0v ; input data = 24bit; r l ? 1k ? ; bick=64fs; signal frequency = 1khz; sampling frequency = 44.1khz ; measurement bandwidth = 20hz ~ 20kh z; external circuit : figure 41 ; unless otherwise specified.) parameter m in . t yp . m ax . unit resolution - - 32 bits dynamic characteristics ( note 7 ) thd+n fs= 44.1khz bw=20khz 0dbfs ? ? ? ? ? dc accuracy interchannel gain mismatch - 0.15 0.3 db gain drift ( note 10 ) - - 20 ppm/ ? ? ? ? ? power supplies power supply current normal operation (pdn pin = ? ? vrefl) is held +5v externally. note 11 . full-scale voltage(0db). output voltage scales with the voltage of (vrefhl/r ? vrefl l/r). aout (typ.@0db) = (aout+) ? (aout ? ) = ? 2.8vpp ? (vrefhl/r ? vrefll/r)/5. note 12 . regarding load resistance, ac load is 1k ? (min) with a dc cut capacitor ( figure 41 ). dc load is 1.5k ohm (min) without a dc cut capacitor ( figure 40 ). the load resistance value is with respect to ground . analog characteristics are sensitive to capacitive load that is connected to the output pin. therefore the capa citive load must be minimized. note 13 . in the power down mode. the p s n pin = dvdd, and all other digital input pins including clock pins (mclk, bick and lrck) are held dvss . [AK4490EN] 015013666 - e - 01 2015/1 2 - 11 - sharp roll - off filter characteristics (fs=44.1khz) ( ta= 25 ? c ; a vdd=dvdd=3.0~3.6v, tvdd=1.6v ? dvdd, vrefhl/r=vddl/r=4.75 ? 5.25v ; normal speed mode; dem=off; sd bit= 0 or sd pin = l , slow bit= 0 or slow pin = l ) parameter symbol m in . t yp . m ax . unit digital filter passband ( note 14 ) ? ? ? digital filter + scf frequency response: 0 ? sharp roll - off filter characteristics (fs=96khz) ta= 25 ? c ; a vdd=dvdd=3.0~3.6v, tvdd=1.6v ? dvdd, vrefhl/r=vddl/r=4.75 ? 5.25v ; double speed mode; dem=off; sd bit= 0 or sd pin = l , slow bit= 0 or slow pin = l ) parameter symbol m in . t yp . m ax . unit d igital filter passband ( note 14 ) ? ? ? digital filter + scf frequency response: 0 ? sharp roll - off filter characteristics (fs=192khz) ( ta= 25 ? c ; a vdd=dvdd=3.0~3.6v, tvdd=1.6v ? dvdd, vrefhl/r=vddl/r=4.75 ? 5.25v ; quad speed mode; dem=off; sd bit= 0 or sd pin = l , slow bit= 0 or slow pin = l ) parameter symbol m in . t yp . m ax . unit d igital filter passband ( note 14 ) ? ? ? digital filter + scf frequency response: 0 ? ? 0.01db), sb=0.546fs. note 15 . the calculating delay time which occurred by digital filtering. this time is from setting the 16/20/24 /32 b it data of both channels to the output of analog signal. [AK4490EN] 015013666 - e - 01 2015/1 2 - 12 - figure 1 . sharp roll - off filter frequency response figure 2 . sharp roll - off filter passband ripple [AK4490EN] 015013666 - e - 01 2015/1 2 - 13 - short delay sharp roll - off filter characteristics (fs=44.1khz) ( ta= 25 ? c ; a vdd= dvdd=3.0~3.6v, tvdd=1.6v ? dvdd, vrefhl/r=vddl/r=4.75 ? 5.25v ; normal speed mode; dem=off; sd bit= 1 or sd pin = h , slow bit= 0 or slow pin = l ) parameter symbol m in . t y p . m ax . unit digital filter passband ( note 14 ) ? ? ? digital filter + scf frequency response : 0 ? short delay sharp roll - off filter characteristics (fs=96khz) ( ta= 25 ? c ; a vdd=dvdd=3.0~3.6v, tvdd=1.6v ? dvdd, vrefhl/r=vddl/r=4.75 ? 5.25v ; double speed mode; dem=off; sd bit= 1 or sd pin = h , slow bit= 0 or slow pin = l ) parameter symbol m in . t y p . m ax . unit digital filter passband ( note 14 ) ? ? ? digital filter + scf frequency response : 0 ? short delay sharp roll - off filter characteristics (fs=192khz) ( ta= 25 ? c ; a vdd=dvdd=3.0~3.6v, tvdd=1.6v ? dvdd, vrefhl/r=vddl/r=4.75 ? 5.25v ; quad speed mode; dem=off; sd bit= 1 or sd pin = h , slow bit= 0 or slow pin = l ) parameter symbol m in . t yp . m ax . unit digital filter passband ( note 14 ) ? ? ? digital filter + scf frequency response : 0 ? [AK4490EN] 015013666 - e - 01 2015/1 2 - 14 - fig ure 3 . short delay sharp roll - off filter frequency response figure 4 . short delay sharp roll - off filter passband ripple [AK4490EN] 015013666 - e - 01 2015/1 2 - 15 - slow roll - off filter characteristics (fs=44.1khz) ( ta= 25 ? c ; a vdd=dvdd=3.0 ? 3.6, tvdd=1.6v ? dvdd, vrefhl/r=vddl/r=4.75 ? 5.25v ; normal speed mode; dem=off; sd bit= 0 or sd pin = l , slow bit= 1 or slow pin = h ) parameter symbol m in . t yp . m ax . unit digital filter passband ( note 16 ) ? ? ? digital filter + scf frequency response: 0 ? slow roll - off filter characteristics (fs=96khz) ( ta= 25 ? c ; a vdd=dvdd=3.0 ? 3.6, tvdd= 1.6v ? dvdd, vrefhl/r=vddl/r=4.75 ? 5.25v ; double speed mode; dem=off; sd bit= 0 or sd pin = l , slow bit= 1 or slow pin = h ) parameter symbol m in . t yp . m ax . unit digital filter passband ( note 16 ) ? ? ? digital filter + scf frequency response: 0 ? slow roll - off filter characteristics (fs=192khz) ( ta= 25 ? c ; a vdd=dvdd=3.0 ? 3.6, tvdd=1.6v ? d vdd, vrefhl/r=vddl/r=4.75 ? 5.25v ; quad speed mode; dem=off; sd bit= 0 or sd pin = l , slow bit= 1 or slow pin = h ) parameter symbol m in . t yp . m ax . unit digital filter passband ( note 16 ) ? ? ? digital filter + scf frequency response: 0 ? ? 0.01db), sb=0. 8889 fs. note 17 . the calculating delay time which occurred by digital filtering. this time is from setting the 16/20/24 /32 bit data of both channels to the output of analog signal. [AK4490EN] 015013666 - e - 01 2015/1 2 - 16 - figure 5 . slow roll - off filter frequency response figure 6 . s low roll - off filter passband ripple [AK4490EN] 015013666 - e - 01 2015/1 2 - 17 - short delay slow roll - off filter characteristics (fs=44.1khz) ( ta= 25 ? c ; a vdd=dvdd=3.0 ? 3.6, tvdd=1.6v ? dvdd , vrefhl/r=vddl/r= 4.75 ? 5.25 v ; normal speed mode; dem=off; sd bit= 1 or sd pin = h , slow bit= 1 or slow pin = h ) parameter symbol m in . t yp . m ax . unit digital filter passband ( note 18 ) ? ? ? digital filter + scf frequency response : 0 ? short delay slow roll - off filter characteristics (fs=96khz) ( ta= 25 ? c ; a vdd=dvdd=3.0 ? 3.6, tvdd=1.6v ? dvdd, vrefhl/r=vddl/r=4.75 ? 5.25v ; double speed mode; dem=off; sd bit= 1 or sd pin = h ) parameter symbol m in . t yp . m ax . unit digital filter passband ( note 18 ) ? ? ? digital filter + scf frequency response : 0 ? short delay slow roll - off filter characteristics (fs=192khz) ( ta= 25 ? c ; a vdd=dvdd=3.0 ? 3.6, tvdd=1.6v ? dvdd, vrefhl/r=vddl/r=4.75 ? 5.25v ; quad speed mode; dem=o ff; sd bit= 1 or sd pin = h ) parameter symbol m in . t yp . m ax . unit digital filter passband ( note 18 ) ? ? ? digital filter + scf frequency response : 0 ? ? 0.01db), sb=0. 88 66 fs. note 19 . the calculating delay time which occurred by digital filtering. this time is from setting the 16/20/24 /32 bit data of both channels to the output of analog signal. [AK4490EN] 015013666 - e - 01 2015/1 2 - 18 - figure 7 . short delay slow roll - off filter frequency response figure 8 . short delay s low roll - off filter passband ripple [AK4490EN] 015013666 - e - 01 2015/1 2 - 19 - dsd mode characteristics ( ta= - 40~85 ? c ; a vdd=dvdd=3.0 ? 3.6, tvdd=1.6v ? dvdd, vrefhl/r=vddl/r=4.75 ? 5.25v; fs=44.1khz ; dp bit=1 , dsdf bit= 0 ) parameter m in . t yp . m ax . unit digital filter respon se frequency response ( note 21 ) 20khz - - 0.4 - db 50khz - - 2.8 - db 100khz - - 15.5 - db ( ta= - 40~85 ? c ; a vdd=dvdd=3.0 ? 3.6, tvdd=1.6v ? dvdd, vrefhl/r=vddl/r=4.75 ? 5.25v ; fs=44.1khz ; d p bit=1 , dsdf bit = 1 , dsdd bit= 1 ) parameter m in . t yp . m ax . unit digital filter response frequency response ( note 21 ) 20khz - - 0.05 - db 50khz - - 0.29 - db 100khz - - 1.16 - db 150khz - - 2.8 - db note 20 . the peak level of dsd signal should be in the range of 25% ~ 75% d uty according to the sacd format book (scarlet book). note 21 . the output level is assumed as 0db when a 1khz 25% ~ 75% d uty sine wave is input. dc ch aracteristics ( ta= 25 ? c ; a vdd=dvdd= 3.0 ? 3.6 , tvdd=1.6v ? dvdd , vrefhl/r=vddl/r= 4.75 ? 5.25v ) parameter symbol m in . t yp . m ax . unit tvdd=1. 6 ? ? ? ? ? ? ? ? ? ? . therefore t he dem1, i2c, acks /cad1 , dem0 and psn pins are not included . [AK4490EN] 015013666 - e - 01 2015/1 2 - 20 - switching characteristics ( ta= 25 ? c ; a vdd=dvdd= 3.0 ? 3.6 , tvdd=1.6v ? dvdd , vrefhl/r=vddl/r= 4.75 ? 5.25v ) parameter symbol m in . t yp . m ax . unit master clock timing fclk dclk 7.7 40 49.152 60 mhz % frequency duty cycle lrck frequency ( note 23 ) 1152fs, 512fs or 768fs 256fs or 384fs 128fs or 192fs 64 fs 64 fs duty cycle fsn fsd fsq fsoc fssd duty 30 54 108 45 384 768 54 108 216 55 khz khz khz khz khz % pcm audio interface timing bick period 1152fs, 512fs or 768fs 256fs or 384fs 128fs or 192fs 64 fs 64 fs bick pulse width low bick pulse width high bick ? ? tbck tbck tbck tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fsn 1/64fsd 1/64fsq 1/64fso 1/64fsh 9 9 5 5 5 5 ns ns ns ns ns ns ns ns ns ns ns external digital filter mode bick period bck pulse width low bck pulse width high bck ? ? tb tbl tbh tbw twb twck twch tdh tds 27 10 10 5 5 54 54 5 5 ns ns ns ns ns ns ns ns ns dsd audio interface timing (64 mode , dsdsel 1 - 0 bit s = 00 ) dclk period dclk pulse width low dclk pulse width high dclk edge to dsdl/r ( note 25 ) tdck tdckl tdckh tddd 160 160 ? dsd audio interf ace timing (128 mode , dsdsel 1 - 0 bit s = 01 ) dclk period dclk pulse width low dclk pulse width high dclk edge to dsdl/r ( note 25 ) tdck tdckl tdckh tddd 8 0 80 ? [AK4490EN] 015013666 - e - 01 2015/1 2 - 21 - dsd audio interface timing (256 mode, dsdsel 1 - 0 bit = 10 ) dclk period dclk pulse width low dclk pulse width high dclk edge to dsdl/r ( note 25 ) tdck tdckl tdckh tddd 40 40 ? control interface timing cclk period cclk pulse width low pulse width high cdti setup t ime cdti hold time csn high time csn ? ? ? ? control interfac e timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 26 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 - 400 - - - - - - - 0.3 0.3 - 50 400 khz ? ? ? ? ? ? ? ? ? ? reset timing pdn pulse width ( note 27 ) tpd 150 ns note 23 . when the 1152fs , 512fs or 768fs /256fs or 384fs / 128fs or 192fs are switched, the ak4490 en should be reset by the pdn pin or rstn bit. note 24 . bick rising edge must not occur at the same time as lrck edge. note 25 . dsd data transmitting device must meet this time. note 26 . data must be held for sufficient time to bridge the 300 ns transition time of scl. note 27 . the ak4490 en can be reset by bringing the pdn pin to l . when the ak8157a is used for mclk, minimum pulse width is specified as below. parameter symbol min typ max unit master clock timing fcl k fclk fclk t clk h / tclkl 9.155 16.384 22.5792 24.576 mhz mhz mhz ns frequency 1 (cksel= [AK4490EN] 015013666 - e - 01 2015/1 2 - 22 - timing diagram clock timing 1/fclk tclkl vih tclkh mclk vil dclk =tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil twck t w ckl vih t w ckh w ck vil tb tbl vih tbh bck vil [AK4490EN] 015013666 - e - 01 2015/1 2 - 23 - audio interface timing (pcm mode) audio serial interface timing (dsd normal mode, dckb bit = 0 ) tlrb lrck vih bick vil tsds vih sdata vil tsdh vih vil tblr vih dclk vil tddd vih dsdl dsdr vil tdckh tdckl tdck tddd vih dsdl dsdr vil [AK4490EN] 015013666 - e - 01 2015/1 2 - 24 - audio serial interface timing (dsd phase modulation mode, dckb bit = 0 ) 3 wire serial mode w rite command input t iming vih dclk vil tddd vih dsdl dsdr vil tdckh tdckl tdck tddd tddd vih dsdl dsdr vil tddd tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh [AK4490EN] 015013666 - e - 01 2015/1 2 - 25 - 3 wire serial mode w rite data input timing i 2 c bus mode timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh thigh scl sda vih tlo w tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp [AK4490EN] 015013666 - e - 01 2015/1 2 - 26 - power down & reset timing external digital filter i/f mode tpd pdn vil twb wck vih bck vil tds vih dinl dinr vil tdh vih vil tbw [AK4490EN] 015013666 - e - 01 2015/1 2 - 27 - 9. functional descriptions d/a conversion mode in serial mode, the ak4490 en can perform d/a conversion for either pcm data or dsd data. the dp bit controls pcm/dsd mode. when dsd mode, dsd data can be input from dclk, dsdl and dsdr pins. when pcm mode , pcm data can be input from bick, lrck and sdata pins. when pcm/dsd mode is change d by d p bit , the ak4490 en should be reset by rstn bit. it takes about 2/fs to 3/fs to change the mode. in parallel mode, the ak4490 en performs for only pcm data. table 1 . pcm/dsd mode control dp bit interface 0 pcm 1 dsd w h en dp bit= 0 , an internal digital filter or external digital filter can be selected. when using an external digital filter ( ex df i/f mode), data is input to each mclk, bck, w ck, dinl and dinr pin. exd f bit controls the modes. when switching internal and external digital filters, the ak4490 en must be reset by rstn bit. a digital filter switching takes 2~3k/fs. table 2 . digital filter control (dp bit = 0 ) ex d f bit interface 0 pcm 1 ex df i/f system clock [1] pcm m ode the external clocks, which are required to operate the ak4490 en , are mclk, bick and lrck. mclk should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and th e delta-sigma modulator. there are two modes for mclk frequency setting: manual setting mode and auto setting mode. in manual setting mode, mclk frequency is set automatically ( table 3 , table 9 ) . in auto setting mode, s ampling speed and mclk frequency are detected automatically ( table 4 , table 10 ) and the n the initial master clock is set to the appropriate frequency ( table 5 , table 11 ). when the reset is released ( pdn pin = ? ), the ak4490 en is in auto setting mode. the ak4490 en is automatically placed in reset state when mclk and lrck are stop ped during a normal operat ion (pdn pin = h ) , and the analog output becomes hi - z state . when mclk and lrck are input again, the ak4490 en exit s reset state and starts operation. after exiting system reset (pdn pin = lh ) at power - up and other situations , the ak4490 en is in power - down mode until mclk and lrck are supplied. the mclk frequency corresponding to each sampling speed should be provided externally ( table 3 , table 4 , table 9 , table 10 ). [AK4490EN] 015013666 - e - 01 2015/1 2 - 28 - (1) parallel mode (psn pin = h ) 1. manual setting mode (acks pin = l ) the mclk frequency corresponding to each sampling speed should be provided externally ( table 3 ). dfs1 - 0 bit is fixed to 00 . in this mode, only normal speed mode are available. table 3 . system clock example (manual setti ng mode @parallel mode) (n/a: not available) lrck mclk (mhz) bick fs 128fs 192fs 256fs 384fs 512fs 768fs 1024fs 1152fs 64fs 32.0khz n/a n/a 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 2.0480mhz 44.1khz n/a n/a 11.2896 16.9344 22.5792 33.8688 n/a n/a 2.8224mhz 48.0khz n/a n/a 12.2880 18.4320 24.5760 36.8640 n/a n/a 3.0720mhz 2. auto setting mode (acks pin = h ) in auto setting mode, mclk frequency and sampling frequency are detected automatically ( table 4 ) . m clk of correspond ed frequency to each sampling speed mode should be input externally. ( table 5 ) table 4 . sampling speed (auto setting mode @parallel mode) mclk sampling speed 1152fs no rmal (fs ? 32khz) 512 /256 fs 768 /384 fs normal 256fs 384fs double 128fs 192fs quad 64fs 96fs oct 32fs 48fs hex table 5 . system clock example (auto setting mode @parallel mode) (n/a: not available) lrck mclk (mhz) sampling speed f s 32fs 48fs 64fs 96fs 128fs 192fs 256fs 384fs 512fs 768fs 1024fs 1152fs 32.0khz n/a n/a n/a n/a n/a n/a 8.192 12.288 16.384 24.576 32.768 36.864 normal 44.1khz n/a n/a n/a n/a n/a n/a 11.2896 16.9344 22.5792 33.8688 n/a n/a 48.0khz n/a n/a n/a n/a n/ a n/a 12.288 18.432 24.576 36.864 n/a n/a 88.2khz n/a n/a n/a n/a n/a n/a 22.5792 33.8688 n/a n/a n/a n/a double 96.0khz n/a n/a n/a n/a n/a n/a 24.576 36.864 n/a n/a n/a n/a 176.4khz n/a n/a n/a n/a 22.5792 33.8688 n/a n/a n/a n/a n/a n/a quad 192.0 khz n/a n/a n/a n/a 24.576 36.864 n/a n/a n/a n/a n/a n/a quad 384khz n/a n/a 24.576 36.864 n/a n/a n/a n/a n/a n/a n/a n/a oct 768khz 24.576 36.864 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a hex when mclk= 256fs/384fs, a uto s etting m ode supports sampling rate of 32khz~96khz. however , the dr and s/n performances will degrade approximately 3db as compared to when mclk= 512fs/768fs when the sampling rate is 32khz~48khz ( table 6 ) . table 6 . rel ationship of mclk frequency and dr, s/n performance (fs = 44.1khz) acks pin mclk dr,s/n l 256fs/384fs/512fs/768fs 120 db h 256fs/384fs 117 db h 512fs/768fs 12 0 db [AK4490EN] 015013666 - e - 01 2015/1 2 - 29 - 3. digital filter the ak4490 en has four kinds of digital filter selected by sslow, sd and slow pins. different sound qualities on playback can be selected by these filters. table 7 . digital f i lter setting sslow pin sd pin slow pin mode l l l sharp roll - off filter l l h slow roll - off filter l h l short delay sharp roll - off filter (default) l h h short delay slow roll - off filter h - - super slow roll - off filter the ak4490 en can be operated on a slower sampling frequency. this mode is available when the sslow pin = h . (2) serial mode (psn pin = l ) 1. manual setting mode (acks bit = 0 ) mclk frequency is detected automatically and the sampling speed is set by dfs2 - 0 bits ( table 8 ). the mclk frequency corresponding to each sampling speed should be provided externally ( table 9 ). the ak4490 en is set to manual setting mode at power - up (pdn pin = l h). when dfs 2 - 0 bits are changed, the ak4490 en should be reset by rstn bit. table 8 . sampling speed (manual setting mode @serial mode) dfs2 dfs1 dfs0 sampling rate (fs) (default) 0 0 0 normal speed mode 30khz ? ? ? [AK4490EN] 015013666 - e - 01 2015/1 2 - 30 - table 9 . system clock example (manual setting mode @serial mode) lrck mclk (mhz) sampling speed fs 16fs 32fs 48fs 64fs 96fs 128fs 192fs 256fs 32.0khz n/a n/a n/a n/a n/ a n/a n/a 8.1920 normal 44.1khz n/a n/a n/a n/a n/a n/a n/a 11.2896 48.0khz n/a n/a n/a n/a n/a n/a n/a 12.2880 88.2khz n/a n/a n/a n/a n/a n/a n/a 22.5792 double 96.0khz n/a n/a n/a n/a n/a n/a n/a 24.5760 176.4khz n/a n/a n/a n/a n/a 22.5792 33.8 688 45.1584 quad 192.0khz n/a n/a n/a n/a n/a 24.5760 36.8640 49.152 quad 384khz n/a 12.288 18.432 24.576 36.864 n/a n/a n/a oct 768khz 12.288 24.576 36.864 49.152 n/a n/a n/a n/a hex lrck mclk (mhz) sampling speed fs 384fs 512fs 768fs 1024fs 1152fs 32.0khz 12.2880 16.3840 24.5760 3 2.7680 36.8640 normal 44.1khz 16.9344 22.5792 33.8688 n/a n/a 48.0khz 18.4320 24.5760 36.8640 n/a n/a 88.2khz 33.8688 45.1584 n/a n/a n/a double 96.0khz 36.8640 49.152 n/a n/a n/a 176.4khz n/a n/a n/a n/a n/a quad 192.0khz n/a n/a n/a n/a n/a quad 384khz n/a n/a n/a n/a n/a oct 768khz n/a n/a n/a n/a n/a hex 2. auto setting mode (acks bit = 1 ) mclk frequency and the sampling speed are detected automatically ( table 10 ) and dfs 1 - 0 bits are ignored. the mclk frequency corresponding to each sampling speed should be provided externally ( table 11 ). table 10 . sampling speed (auto setting mode @serial mode) m clk sampling speed 1152fs normal (fs ? lrck mclk(mhz) sampling speed fs 32fs 48fs 64fs 96fs 1 28fs 192fs 256fs 384fs 512fs 768fs 1024fs 1152fs 32.0khz n/a n/a n/a n/a n/a n/a 8.192 12.288 16.384 24.576 3 2.7680 36.864 normal 44.1khz n/a n/a n/a n/a n/a n/a 11.2896 16.9344 22.5792 33.8688 n/a n/a 48.0khz n/a n/a n/a n/a n/a n/a 12.288 18.432 24. 576 36.864 n/a n/a 88.2khz n/a n/a n/a n/a n/a n/a 22.5792 33.8688 n/a n/a n/a n/a double 96.0khz n/a n/a n/a n/a n/a n/a 24.576 36.864 n/a n/a n/a n/a 176.4khz n/a n/a n/a n/a 22.5792 33.8688 n/a n/a n/a n/a n/a n/a quad 192.0khz n/a n/a n/a n/a 24. 576 36.864 n/a n/a n/a n/a n/a n/a quad 384khz n/a n/a 24.576 36.864 n/a n/a n/a n/a n/a n/a n/a n/a oct 768khz 24.576 36.864 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a hex [AK4490EN] 015013666 - e - 01 2015/1 2 - 31 - when mclk= 256fs/384fs, a uto s etting m ode supports sampling rate of 32khz~96khz. however , the dr and s/n performances will degrade approximately 3db as compared to when mclk= 512fs/768fs when the sampling rate is 32khz~48khz ( table 12 ) . table 12 . relationship of mclk fr equency and dr, s/n performance (fs = 44.1khz) acks bit mclk dr,s/n 0 256fs/384fs/512fs/768fs 120 db 1 256fs/384fs 117 db 1 512fs/768fs 12 0 db 3. digital filter the AK4490EN has four kinds of digital filter selected by sslow, sd and slow bits. differen t sound qualities on playback can be selected by these filters. table 13 . digital f i lter setting sslow bit sd bit slow bit mode 0 0 0 sharp roll - off filter 0 0 1 slow roll - off filter 0 1 0 short delay sharp roll - off filter ( default) 0 1 1 short delay slow roll - off filter 1 - - super slow roll - off filter the ak4490 en can be operated on a slower sampling frequency. this mode is available when the sslow bit = 1 (05h d0). [AK4490EN] 015013666 - e - 01 2015/1 2 - 32 - [2] dsd m ode the ak4490 en has a dsd playback function . the external clocks, which are required in dsd mode , are mclk and dclk . mclk should be synchronized with dclk but the phase is not critical . the frequency of mclk is set by dcks bit. the ak4490 en is automatically placed in reset state when mclk is stop ped during a normal operation (pdn pin = h ) , and the analog output becomes hi - z state . however, the external clock (dclk) should not be stopped. when dclk is not supplied, the ak4490 en may not be able to operate properly because of an over current since it has a dynamic logic circuit internally. the pdn pin should be set to l when stopping the dclk. when the reset is released (pdn pin = l h ), t he ak4490 en is in power - down state until mclk and dclk are input . table 14 . system clock (dsd mode) dcks bit mclk frequency dclk frequency 0 512fs 64fs /128fs/256fs (default) 1 768fs 64fs/128fs/256fs the ak4490 en supp orts dsd data stream of 2.8224mhz (64fs) , 5.6448mhz (128fs) and 11.2896mhz (256fs) . the data s ampling speed is selected by dsdsel 1 - 0 bit s. table 15 . dsd sampling speed control dsdsel1 dsdsel0 dsd data stream 0 0 2.8224mhz (defa ult) 0 1 5.6448mhz 1 0 11.2896mhz 1 1 reserved the ak4490 en ha s a volume by pass function for play backing dsd signal . t w o modes are selectable by dsdd bit . when setting dsdd bit = 1 , the output volume control function is not available. table 16 . dsd play back mode control d sdd mode 0 normal path (default) 1 v o lume byp ass when dsdd bit = 1 , filter characteristic can be switched between 50khz and 100khz by dsdf bit . table 17 . dsd filter sele ct dsdd bit dsdf bit cut off filter 0 0 50khz (default) 0 1 reserved 1 0 50khz 1 1 150khz [AK4490EN] 015013666 - e - 01 2015/1 2 - 33 - full scale (fs) dsd signal detection function the ak4490 en has a full scale (fs) detection function at each channel in dsd mode. when dsdl or dsdr input data is continuously 0 ( - fs) or 1 (+fs) for 2048 cycles , the ak4490 en detects full scale and enters full scale detection status and dml or dmr bit becomes 1 . the output will be muted by full scale detection if ddm bit = 1 . when dsdd bit is 0 , th e output is attenuated in soft transition . w hen dsdd bit is 1 , the soft transition is disabled. recovery method to normal operation mode from full scale detection status is controlled by dmc bit when ddm bit = 1 . when dmc bit = 0 , the ak4490 en retu rns to normal operation autom atically by a normal signal input . when dmc bit = 1 , the ak4490 en returns normal operation by writing dmre bit = 1 . table 18 . dsd mode and the device status after detection (ddm bit= 1 ) d sdd mod e status after detection 0 normal path soft mute enable (default) 1 volume bypass soft mute disable table 19 . recovery m ethod to n ormal o peration m ode from f ull s cale d etection s tatus d dm dm c dmre status after detection 0 * * when full scale is detect ed , m ute function is disable . (default) 1 0 * when full scale is detected , mute function is en able . t he AK4490EN returns normal operation automatically by a normal signal input. 1 1 0 when full scale is detected, mute function is enable. t he AK4490EN keeps mute mode, even if a normal signal is input. 1 1 1 ( note 28 ) when full scale is detected, mute function is enable. t he AK4490EN returns normal operation , when a normal signal is inp ut and dmre bit is set 1 0 automatically. figure 9 . analog output waveform on dsd fs detection (dsdd bit= 1 ) figure 10 . analog output waveform on dsd fs detection (dsdd bit= 0 ) dsd error (ddr or ddlbit ) d sd data dsd data dsd data (fs or - fs ) dsd data 2048fs aout mode dsd error (ddr or ddlbit ) d sd data dsd data dsd data (fs or - fs ) dsd data 2048fs aout mode [AK4490EN] 015013666 - e - 01 2015/1 2 - 34 - [3] external digital filter mode (ex df i/f mode) the AK4490EN has the external digital filter playback function. the external clocks, which are required in ex df i/f mode, are mclk , bck and w ck. b ck should be same frequency with m clk. the frequency of w c k is set by e cs bit. table 20 . ex df sampling speed ecs wck [khz] 0 768khz (default) 1 384khz [AK4490EN] 015013666 - e - 01 2015/1 2 - 35 - audio interface format [1] pcm m ode data is shifted in via the sdata pin using bick and lrck inputs. eight d ata formats are supported and selected by the dif2 - 0 pins (parallel control mode) or dif2 - 0 bits (serial control mode) as shown in table 21 . in all formats the serial data is msb-first, 2's compliment format and is latched on the rising edge of bick. mode 2 can be used for 20 - bit and 16 - bit msb justified formats by zeroing the unused lower bit . table 21 . audio interface format mode dif2 dif1 dif0 input format bick figure 0 0 0 0 16 - bit lsb justified ? 32fs figure 11 1 0 0 1 20 - bit lsb justified ? 48fs figure 12 2 0 1 0 24 - bit msb justified ? 48fs figure 13 (default) 3 0 1 1 24 - bit i 2 s c ompatible ? 48fs figure 14 4 1 0 0 24 - bit lsb justified ? 48fs figure 12 5 1 0 1 32 - bit lsb justified ? 64fs figure 15 6 1 1 0 32 - bit msb justified ? 64fs figure 16 7 1 1 1 32 - bit i 2 s c ompatible ? 64fs figure 17 figure 11 . mode 0 timing sdata bick lrck sdata 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3 2 1 0 15 14 (32fs) (64fs) 0 14 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don t care don t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data [AK4490EN] 015013666 - e - 01 2015/1 2 - 36 - figure 12 . mode 1 / 4 timing figure 13 . mode 2 timing figure 14 . mode 3 timing sdata lrck bick (64fs) 0 9 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don t care don t care 19:msb, 0:lsb sdata mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don t care don t care 22 21 22 21 lch data rch data 8 23 23 8 lrck bick (64fs) sdata 0 22 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don t care 23 lch data rch data 23 30 22 2 24 23 30 22 1 0 don t care 23 22 23 lrck bick (64fs) sdata 0 3 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don t care 23 lch data rch data 23 25 3 2 24 23 25 22 1 0 don t care 23 23 [AK4490EN] 015013666 - e - 01 2015/1 2 - 37 - figure 15 . mode 5 timing figure 16 . mode 6 timing figure 17 . mode 7 timing lrck bick(128fs) sdata 0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 1 0 31 1 bick(64fs) sdata 0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0 31 1 30 9 31 30 20 19 18 9 31 20 19 18 31: msb, 0:lsb 8 0 1 8 0 1 lch data rch data 0 31 1 lrck bick(128fs) sdata 0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 31 1 30 0 31 30 12 11 10 0 31 12 11 10 bick(64fs) sdata 0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0 31 1 30 9 31 30 20 19 18 9 31 20 19 18 31: msb, 0:lsb 8 0 1 8 0 1 lch data rch data lrck bick(128fs) sdata 0 1 2 20 21 22 33 34 63 0 1 2 20 21 22 33 34 63 0 1 31 0 31 13 12 11 0 13 12 11 bick(64fs) sdata 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 0 1 31 9 0 31 21 20 19 9 0 21 20 19 31: msb, 0:lsb 8 1 2 8 1 2 lch data rch data [AK4490EN] 015013666 - e - 01 2015/1 2 - 38 - [2] dsd m ode in case of dsd mode, dif2 - 0 pins and dif2 - 0 bits are ignored. the frequency of dclk is selected between 64fs, 128fs and 256fs . dckb bit can invert the polarity of dclk. phase modulation function is not available in 256fs mode. figure 18 . dsd mode timing dclk (64fs) dckb=1 dclk (64fs) dckb=0 dsdl,dsdr normal dsdl,dsdr phase modulation d1 d0 d1 d2 d0 d2 d3 d1 d2 d3 [AK4490EN] 015013666 - e - 01 2015/1 2 - 39 - [3] external digital filter mode ( ex df i/f m ode) dw i n d icates the number of bc k in one wck cycle. the audio data is input by mclk, bck and wck from the dinl and dinr pins . three formats are available ( table 23 ) by dif2 - 0 bits setting. the data is latched on the rising edge of bck. the bck an d mclk clock s must be the same frequency and must not burst. bck and mclk frequencies for each sampling speed are shown in table 22 . table 22 . system clock example (ex df i/f mode) (n/a: n ot available) sampling speed[khz] mclk&bck [mhz] wck ecs 128fs 192fs 256fs 384fs 512fs 768fs 44.1(30 ~48 ) n/a n/a n/a n/a 22.5792 33.8688 16fs 0 (default) n/a n/a n/a n/a 32 48 dw 44.1(30 ~48 ) n/a n/a 11.2896 16.9344 n/a 33.8688 8fs 1 n/a n/a 32 48 n/a 96 dw 96(54 ~96 ) n/a n/a 24.576 36.864 n/a n/a 8fs 0 n/a n/a 32 48 n/a n/a dw 96(54 ~96 ) 12.288 18.432 n/a 36.864 n/a n/a 4fs 1 32 48 n/a 96 n/a n/a dw 192(108 ~192 ) 24.576 36.864 n/a n/a n/a n/a 4fs 0 32 48 n/a n/a n/a n/a dw 1 92(108 ~192 ) n/a 36.864 n/a n/a n/a n/a 2fs 1 n/a 96 n/a n/a n/a n/a dw table 23 . audio interface format (ex df i/f mode) (n/a: not available) mode dif2 dif1 dif0 input format 0 0 0 0 16 - bit lsb justified 1 0 0 1 n/a 2 0 1 0 n/a 3 0 1 1 n/a 4 1 0 0 24 - bit lsb justified 5 1 0 1 32 - bit lsb justified (default) 6 1 1 0 n/a 7 1 1 1 n/a [AK4490EN] 015013666 - e - 01 2015/1 2 - 40 - figure 19 . ex df i/f m ode t iming d/a conversion mode switching timing figure 20 . d/a mode switching timing (pcm to dsd) figure 21 . d/a mode switching timing (dsd to pcm) note 29 . the signal range is identified as 25 % ~ 75 % duty ratio s in dsd mode. dsd signal must not go beyond this duty range at the sacd format b oo k (scarlet book). b ck (32wck) w ck dinl or di nr 23 22 bck (96wck) 0 1 8 9 10 11 16 17 26 27 28 29 30 31 0 1 21 20 17 16 0 5 1 6 7 8 47 48 49 65 92 93 94 95 0 1 31 30 3 1 0 15 14 6 5 4 3 2 1 0 don t care don t care dinl or dinr 2 31 24 don t care don t care bck (48wck) 0 13 1 14 15 16 23 24 25 44 45 46 47 0 1 3 1 0 don t care dinl or dinr 2 31 don t care don t care 1/ ( 16fs ) or 1/ ( 8fs ) or 1/ ( 4fs ) or 1/ ( 2fs ) 31: msb, 0:lsb rstn bit d/a data d/a mode ? 4/fs ? 0 pcm data dsd data pcm mode dsd mode rstn bit d/a data d/a mode ? 4/fs dsd data pcm data dsd mode pcm mode [AK4490EN] 015013666 - e - 01 2015/1 2 - 41 - de-emphasis filter a digital de-emphasis filter is available for 32 khz , 44.1 khz or 48khz sampling rates (tc = 50/15s) and is enabled or disabled with dem1 - 0 pins or dem 1 - 0 bits . in case of 256fs/384fs and 128fs/192fs , the digital de-emphasis filter is always off. when dsd mode, dem1 - 0 bits are ignored. the setting value is h eld even if pcm mode and dsd mode are switched. table 24 . de - emphasis control dem1 dem0 mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz output volume (pcm, dsd) the ak4490 en includes channel independent digital output volumes (att) with 25 6 levels at 0.5db step including mute. this volume control is in front of the dac and it can attenuate the input data from 0db to C 127 db or mute. when changing output levels, it is executed in soft transition thus no switching noise occurs during these transitions. it takes 7 395 /fs from ffh (0db) to 00h (mute). the attenuation level is initialized to ffh by setting to pdn pin = l . register setting val ues will be kept even switching the pcm and dsd modes. table 25 . att transition time sampling speed transition time 0db to mute fs=44.1khz 168 .3 ms fs= 96 khz 77.3 ms fs= 192 khz 38.6ms [AK4490EN] 015013666 - e - 01 2015/1 2 - 42 - zero detection ( pcm , dsd , ex df i/f ) the ak4490 en has a channel - independent zero s detect function. when the input data at each channel is continuously zero s for 8192 lrck cycles, the dzf pin of each channel goes to h . the dzf pin of each channel immed iately return s to l if the input data of each channel is not zero after going to h . if the rstn bit is 0 , the dzf pins of both l and r channels go to h . the dzf pin of each channel returns to l in 4 ~ 5/fs after the input data of each channel bec omes 1 when rstn bit is set to 1 . if dzfm bit is set to 1 , the dzf pins of both l and r channels go to h only when the input data for both channels are continuously zeros for 8192 lrck cycles. the z ero detect function can be disabled by setting the dzfe bit. in this case, dzf pins of both channels are always l . the dzfb bit can invert the polarity of the dzf pin. table 26 . zero detect function and dzf pin output dzfe dzfb data dzf - pin 0 0 - l 1 - h 1 0 not zero l z ero detect h 1 not zero h zero detect l mono output (pcm, dsd, ex df i/f) t he ak4490 en can select input/output for both output channels by setting the mono bit and sellr bit. this function is available for any audio format. table 27 mono mode output select mono bit se llr bit lch out rch out 0 0 lch in rch in 0 1 rch in lch in 1 0 lch in lch in 1 1 rch in rch in sound quality control (pcm, dsd, ex df i/f) sound quality of the ak4490 en can be selected by sc 1 - 0 bits. table 2 8 . sc1 - 0 bits control s c 1 s c 0 mode 0 0 sound s etting 1 (default) 0 1 sound s etting 2 1 0 sound s etting 3 1 1 reserved [AK4490EN] 015013666 - e - 01 2015/1 2 - 43 - characteristics (dsd) ( ta= 25 ? c ; a vdd= dvdd=3.3v; avss=dvss=vssl/r=0v; vrefhl/r=vddl/r=5v, vrefll/r= vssl/r=0v; input data = 24bit; r l ? 1k ? ; signal frequency = 1khz; sampling frequency = 44.1khz ; measurement bandwidth = 20hz ~ 20khz; external circuit: figure 41 ; unless otherwise specified.) dynamic characteristics thd+n dsd data stream 2.8224mhz 0dbfs - 110 db dsd data stream 5.6448mhz 0dbfs - 110 db dsd data stream 11.2896mhz 0dbfs - 110 db s/n (a - weighted, normal path) digital dc accuracy output voltage (normal pat h ) ? ? [AK4490EN] 015013666 - e - 01 2015/1 2 - 44 - soft mute operation (pcm, dsd) the s oft mute operation is performed at digital domain. when the smute pin goes to h or the smute bit set to 1 , the out put signal is attenuated by ? ? during att_data ? att transition time from the current att level . when the smute pin is returned to l or the smute bit is returned to 0 , the mute is cancelled and the output attenuation gradually changes to the att level during att_data ? att transition time . if the soft mute is cancelled before attenuating ? ? after starting the operation, the attenuation is discontinued and returned to att level by the same cycle . the soft mute is effective for changing the signal source without stopping the signal transmission. note 30 . ( 1) att_data ? att transition time. for example, this time is 7 395 lrck cyc les at att_data=255 in normal speed mode. (2) the a nalog outpu t corresponding to the digital input has group delay (gd). (3) if the soft mute is cancelled before attenuating ? ? after starting the operation, the attenuation is discontinued and returned to att level by the same cycle . (4) when the input data for each channel is contin uously zeros for 8192 lrck cycles, the dzf pin for each channel goes to h . the dzf pin immediately returns to l if input data are not zero. figure 22 . soft mute function system reset the ak4490 en should be reset once by b ringing the pdn pin = l upon power - up. it initializes registe r settings of the device. the analog block of the ak4490 en exits power - down mode by mclk input, and t he digital block exits power - down mode after the int ernal counter counts mclk for 4/fs. smute pin or smute bit attenuat ion dzf pin att_level - ? aout 8192/fs gd gd (1) (2) (3) (4) (1) (2) [AK4490EN] 015013666 - e - 01 2015/1 2 - 45 - power on/off timing the ak4490 en is placed in the power - down mode by bringing the pdn pin l and the registers are initialized. t he analog outputs are floating (hi - z). as some click noise occurs at the edge of the pdn pin signal, the analog output should be muted externally if the click noise influences system application. the dac can be reset by setting rstn bit to 0. in this case, r egisters are not initialized and the corresponding analog outputs go to vcml/r . as some click noise occurs at the edge o f rstn signal, the analog output should be muted externally if click noise aversely affect system performance. note 31 . (1) digital and analog power supply should be powered up at the same time , otherwis e power up the 1.8v base power supplies (tvdd) at first, the 3.3v base power supplies secondarily (dvdd, avdd) and 5v base power supplies finally (vddl/r, vrefhl/r). after tvdd, avdd and dvdd reach to 90%vdd , the pdn pin should be l for 150ns or more . ( 2 ) the analog output corresponding to digital input has group delay (gd). ( 3 ) analog outputs are floating (hi - z) in power-down mode. ( 4 ) click noise occurs at the edge of pdn signal. this noise is output even if 0 data is input. (5) mclk, bick and lrck c locks can be stopped in power - down mode (pdn pin= l ). ( 6 ) mute the analog output externally if click noise ( 4 ) adversely affect system performance the timing example is shown in this figure. ( 7 ) dzf l/r pins are l in the power - down mode (pdn pin = l) . ( 8 ) clocks should be input after power supplies are powered up. figure 23 . power-down/up sequence example pdn pin power reset normal operation clock in mclk,lrck,bick dac in (digital) dac out (analog) external mute mute on ( 6 ) dzfl/dzfr 0 data gd ( 2 ) ( 4 ) ( 5 ) ( 7 ) gd ( 4 ) mute on 0 data internal state ( 3 ) ( 3 ) (1) ( 8 ) ( 8 ) [AK4490EN] 015013666 - e - 01 2015/1 2 - 46 - reset function (1) reset by rstn bit = 0 when the rstn bit = 0, the ak4490 en s digital block is powered down, bu t the internal register values are not initialized. in this time, the a nalog outputs go to vcml/r voltage and dzfl/dzfr pins are h . figure 24 shows an example of reset by rstn bit. n ote 32 . ( 1) the a nalog output corresponding to digital input ha s group delay (gd). (2) analog outputs settle to vcom voltage . (3) small pop noise occurs at the edges( ? ? ) of the internal timing of rstn bit . this noise is output ev en if 0 data is input. (4) the dzf pins change to h when the rstn bit becomes 0 , and return to l at 2/fs after rstn bit becomes 1 . (5) there is a delay, 3 ~ 4/fs from rstn bit 0 to the internal rstn bit 0 , and 2 ~ 3/fs from rstn bit 1 to the in ternal rstn bit 1 . (6) mute the analog output externally if click noise (3) and hi - z (2) adversely affect system performance figure 24 . reset s equence e xample 1 internal state rstn bit digital block power - down normal operation gd gd 0 data d/a out (analog) d/a in (digital) (1) (3) dzf (3) (1) (2) normal operation 2/fs(4) internal rstn bit 2~3/fs (5) 3~4/fs (5) (6) [AK4490EN] 015013666 - e - 01 2015/1 2 - 47 - (2) reset by mclk or lrck /wck s top the ak4490 en is automaticall y placed in reset state when mclk or lrck is stop ped during pdm mode ( pdn pin = h ) , and the analog output s are floating ( hi - z ) . when mclk and lrck are input again, the ak4490 en exit s reset state and starts the operation. zero detect function is disable w hen mclk or lrck is stopped. in dsd mode the ak4490 en is in reset state when mclk is stopped, and it is in reset state when mclk or wck are stopped in external digital filter mode. note 33 . (1) after avdd a nd dvdd are powered - up , the pdn pin should be l for 150ns . (2) the analog output corresponding to digital input has group delay (gd). (3) the digital data can be stopped. click noise after mclk and lrck are input again can be reduced by inputting 0 data durin g this period . (4) click noise occurs within 3 ~ 4lrck cycles from the riding edge ( ) of the pdn pin or mclk inputs. this noise occurs even when 0 data is input. (5) clocks (mclk, bick, lrck /wck ) can be stopped in the reset state (mclk or lrck /wck is stopped). (6) m ute the analog output externally if click noise (4) and (5) influences syste m application s . the timing example is shown in this figure. (7) clocks should be input after power supplies are powered up. figure 25 . reset s equence e xample 2 normal operation internal state digital circuit power - down normal operation gd gd d/a out (analog) d/a in (digital) clock in mclk, bick, lrck , wck (2) (3) external mute (6) (5) (2) mclk , bick, lrck , wck st op pdn pin power - down power - down ( 5 ) ( 5 ) (4) hi - z (6) (5) (1) a vdd pin dv dd pin (6) (7) [AK4490EN] 015013666 - e - 01 2015/1 2 - 48 - synchronize function the ak449 0 en has a function that resets the int ernal counter to synchronize with the external clock edge (lrck) in a range of 3/256fs. clock synchronize function becomes valid if synce bit is set to 1 during operation in pcm mode or exdf mode and input data of both l and r channels are 0 f or 8129 t imes continuously or r stn bit is 1 . in pcm mode, the internal counter is synchronized with a falling edged of lrck (rising edge of lrck in i2c mode), and it is synchronized with a falling edge of wck in exdf mode. in this case, the analog output has the same voltage as vcml/r. figure 26 shows a synchronizing sequence when the input data is 0 for 8192 times continuously. figure 27 shows a synchronizing sequence by rstn bi t. (1) synchronization by continuous 0 data input for 8192 times if the input data is 0 for 8192 times continuously, or if the data becomes 0 for 8192 times continuously by attenuation, the dzfl/dzfr pin goes to h and the synchronize function be comes valid. the synchronize function is enabled only when both l and r channels data are 0 for 8192 times continuously. figure 26 shows a synchronizing sequence when the input data is 0 for 8192 times continuo usly. note 34 . (1) att_data ? att transition time. for example, this time is 7 395 lrck cycles (1020/fs) at att_data=255 in normal speed mode. (2) when both l and r channels data are 0 for 8192 times con tinuously, dzfl/r pins become h and the synchronize function is valid. (3) internal data is fixed to 0 forcibly for 4 to 5/fs when internal counter is reset. (4) a click noise may occur when the internal counter is reset. this noise is output even if a 0 data is input. mute the analog output externally if this click noise affects the system performance. (5) when the internal clock and external clock are in synchronization, the internal counter is not reset even if the synchronize function is valid. figure 26 . synchronizing sequence by continuous 0 data input for 8192 times smute atten uation dzf pin att_level - ? aout 8192/fs gd (1) (2 ) (1) d/a in (digital) gd gd 8192/fs (2 ) sync operation ( 2 ) sync operation ( 2 ) internal counter reset internal data reset 4 ~ 5 /fs ( 3 ) ( 4 ) (5 ) [AK4490EN] 015013666 - e - 01 2015/1 2 - 49 - (2) synchronization by rstn bit if rstn bit is set to 0 , the output signal of the dzfl/dzfr pin becomes h . then, the dac is reset 3 to 4/fs afte r the dzfl/dzfr pin = h and the analog output becomes the same voltage as vcml/r. the synchronize function becomes valid when both of the dzfl and dzfr pins output h . figure 27 shows a synchronizing sequence by rstn bit. note 35 . (1) dzfl/r pin becomes h by a rising edge of rstn bit, and becomes l 2/fs after a falling edge of internal signal of rstn bit. the synchronize function is valid during the dzfl/r pin = h . (2) internal data is fixed to 0 forcibly for 4 to 5/fs when the internal counter is reset. (3) since t he analog output corresponding to digital input has group delay (gd) , it is recommended to have a no - input period longer than the group del ay before writing 0 to rstn bit. (4) it takes 3 to 4/fs when falling to change the internal rstn signal of the lsi after writing to rstn bit. it also takes 3 to 4/fs when rising to change the internal rstn signal of the lsi. the synchronize function bec omes valid immediately when 0 is written to rstn bit. therefore, there is a case that the internal counter is reset before internal rstn signal of the lsi is changed. (5) a click noise occurs on the rising or falling edge of the internal rstn signal an d when the internal counter is reset. this noise is output even if a 0 data is input. mute the analog output externally if this click noise affects the system performance. figure 27 . synchronizing sequence by rstn bit internal state rstn bit digital block power - down normal operation gd gd d/a out (analog) d/a in (digital) ( 3 ) ( 5 ) dzf ( 5 ) ( 3 ) normal operation 2/fs(4) internal rstn bit 2~3/ fs (4 ) 3 ~4/fs (4 ) internal counter r eset internal data reset 4 ~ 5 /fs ( 2 ) force 0 sync operation (1) ( 2 ) [AK4490EN] 015013666 - e - 01 2015/1 2 - 50 - registe r control interface (1) 3 - wire serial control mode (i2c pin = l ) pins (parallel control mode) or registers (serial control mode) can control the functions of the ak4490 en . in parallel control mode, the register setting is ignored, and in serial control mode the pin settings are ignored. when the state of the psn pin is changed, the ak4490 en should be reset by the pdn pin. the serial control interface is enabled by the psn pin = l. internal registers may be written to through3 - wire p interface pins: cs n, cclk and cdti. the data on this interface consists of chip address (2 - bits, c 1/0 ), read/write (1 - bit; fixed to 1), register address (msb first, 5 - bits) and control data (msb first, 8 - bits). the data is output on a falling edge of cclk and the data is received on a rising edge of cclk. the writing of data is valid when csn ? . the clock speed of cclk is 5mhz (max) . table 29 . function list1 (y: available , - : not available) function parallel control mode serial control mode audi o format y y auto setting mode y y de - emphasis y y smute y y dsd mode - y ex df i/f - y zero detection - y sharp roll off filter y y slow roll off filter y y minimum delay filter y y digital attenuator - y setting the pdn pin to l resets the registers to their default values. in serial control mode, the internal timing circuit is reset by the rstn bit, but the registers are not initialized. c1 - c0: chip address (c1 bit =cad1 pin , c0 bit =cad0 pin ) r/w: read/writ e (fixed to 1 , write only) a4 - a0: register address d7 - d0: control data figure 28 . control i/f timing * the ak4490 en does not support read command s in 3 - wire serial control mode . * when the ak4490 en is in power down mode (pdn pin = l), writing into control register s is prohibited. * the control data can not be written when the cclk rising edge is 15 times or less or 17 times or more during csn is l. cdti cclk c1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 csn [AK4490EN] 015013666 - e - 01 2015/1 2 - 51 - (2) i 2 c - bus control mode (i2c pin = h) the ak4 4 9 0 en supports the fast - mode i 2 c - bus (max: 400khz , ver 1.0 ). (2) - 1. write operations figure 29 shows the data transfer sequence for the i 2 c - bus mode. all commands are preceded by a start condition. a high to low transition on the sda line wh ile scl is high indicates a start condition ( figure 35 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most signif icant five bits of the slave address are fixed as 00100. the next bit s are cad 1 and cad0 (device address bit s ). this bit identifies the specific device on the bus. the hard - wired input pin ( cad1pins, cad0 pin) sets these device address bits ( figure 30 ). if the slave address matches that of the ak4 4 9 0 en , the ak4 4 9 0 en generates an acknowledge and the operation is executed. the master must generate the acknowledge - related clock pulse and release the sda line (high) du ring the acknowledge clock pulse ( figure 36 ). a r/w bit value of 1 indicates that the read operation is to be executed, and 0 indicates that the write operation is to be executed. the second byte consists of th e control register address of the ak4 4 9 0 en and t he format is msb first . ( figure 31 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 32 ). the ak4 490 en generates an acknowledge after each byte is received. data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 35 ). the ak4 4 9 0 en can perform more than one byte write operation per sequence. after receipt of the third byte the ak4 4 9 0 en generates an acknowledge and awaits the next data. the master can transmit more than one byte inst ead of terminating the write cycle after the first data byte is transferred. after receiving each data packet the internal address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 09h p rior to generating a stop condition, the address counter will roll over to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. high or low state of the data line can only be c hanged when the clock signal on the scl line is low ( figure 37 ) except for the start and stop conditions. figure 29 . data transfer sequence at i 2 c bus mode 0 0 1 0 0 cad1 cad0 r/w (cad0 is set by the pin) figure 30 . the first byte 0 0 0 a4 a3 a2 a1 a0 figure 31 . the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 32 . the third byte and aft er the third byte sda s t a r t a c k a c k s slave address a c k sub address(n) data(n) p s t o p data( n+x) a c k data(n+1) a c k r/w= 0 a c k [AK4490EN] 015013666 - e - 01 2015/1 2 - 52 - (2) - 2. read operations set the r/w bit = 1 for the read operation of the ak449 0 en . after transmission of data, the master can read the next addresss data by generating an acknowledge instead of terminating the write cycle after the r eceipt of the first data word. after receiving each data packet the internal address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 09h prior to generating stop condition, the address counter will roll over to 00h and the data of 00h will be read out. the ak449 0 en supports two basic read operations: c urrent a ddress r ead and r andom a ddress r ead . (2) - 2 - 1. c urrent a ddress r ead the ak449 0 en has an internal address counter that ma intains the address of the last accessed word incremented by one. therefore, if the last access (either a read or write) were to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit 1, the ak449 0 en generates an acknowledge, transmits 1 - byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak449 0 en ceases the transmission. figure 33 . c urrent a ddress r ead (2) - 2 - 2. r andom a ddress r ead the random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit 1 , the master must first perform a dummy write operation. the master issues a start request, a slave address (r/w b it = 0) an d then the register address to read. after the register address is acknowledge d, the master immediately reissues the start request and the slave address with the r/w bit 1 . the ak449 0 en then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak449 0 en ceases the transmission. figure 34 . r andom address read sda s t a r t a c k a c k s slave address a c k data(n+1) p s t o p data( n+x) a c k data(n+2) a c k r/w= 1 a c k data(n) sda s t a r t a c k a c k s slave address a c k data(n) p s t o p data( n+x) a c k data(n+1) a c k r/w= 0 a c k sub address(n) s t a r t a c k s slave address r/w= 1 [AK4490EN] 015013666 - e - 01 2015/1 2 - 53 - figure 35 . start condition and stop cond ition figure 36 . acknowledge (i 2 c bus) figure 37 . bit transfer (i 2 c bus) scl sda stop condition start condition s p scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 scl sda data line stable; data valid change of data allowed [AK4490EN] 015013666 - e - 01 2015/1 2 - 54 - function list table 30 . function list (y: avail able , - : not available) function default address bit pcm dsd ex df i/f attenuation level 0db 03h 04h att7 - 0 y y - external digital filter i/f mode disable 00h exdf y - y ex df i/f mode clock setting 16fs(fs=44.1khz) 00h esc - - y audio data interface m odes 24bit msb justified 00h dif2 - 0 y - y data zero detect enable disable 01h dzfe y y - data zero detect mode separated 01h dzfm y y - minimum delay filter enable sharp roll - off filter 01h sd y - - de - emphasis response off 01h dem1 - 0 y - - soft mute enable normal operation 01h smute y y - dsd/pcm mode select pcm mode 02h dp y y - master clock frequency select at dsd mode 512fs 02h dcks - y - mono mode stereo mode select stereo 02h mono y y y inverting enable of dzf [AK4490EN] 015013666 - e - 01 2015/1 2 - 55 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks exdf ecs 0 dif2 dif1 dif0 rstn 01h control 2 dzfe dzfm sd dfs1 dfs0 dem1 dem0 smute 02h control 3 dp 0 dcks dckb mono dzfb sellr slow 03h lch att att7 att6 att5 att4 att3 att 2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 05h control4 invl invr 0 0 0 0 dfs2 sslow 06h control5 ddm dml dmr dmc dmre 0 dsdd dsdsel0 07h control6 0 0 0 0 0 0 0 synce 08h control7 0 0 0 0 0 0 sc1 sc0 09h control8 0 0 0 0 0 0 dsdf dsdsel1 note 36 . in 3 - wire serial c ontrol m ode, the ak4490 en does not support read command s . the ak4490 en supports read command in i 2 c - bus c ontrol m ode . data must not be written into addresses from 0a h to 1fh. when the pdn pin goes to l, the registers are initialized to their default values. when rstn bit is set to 0, only the internal timing is reset, and the registers are not initialized to their default values. when the state of the psn pin is changed, the ak4490 en should be reset by the pdn pin. register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks exdf ecs 0 dif2 dif1 dif0 rstn r(i2c)/w r/w r/w r/w r r/w r/w r/w r/w d efault 0 0 0 0 0 1 0 0 rstn: internal timing reset 0: reset. all registers are not initial ized. (default) 1: normal operation writing 0 to this bit resets the internal timing circuit but register values are not initialized. when the psn pin = h , the ak4490 en operates regardless of this register setting. dif2 - 0: audio data interface mo des ( table 21 ) initial value is 010 (mode 2: 24 - bit msb justified). ecs: ex df i/f mode clock setting ( table 22 ) 0: wck=768khz mode (default) 1 : wck=384khz mode exdf: external digital filter i/f mode ( serial mode only) 0: disable: internal digital filter mode (default) 1: enable: external digital filter mode acks: master clock frequency auto setting mode enable (pcm only) 0: dis able: manual setting mode (default) 1: enable: auto setting mode when acks bit = 1 , mclk frequency and the sampling frequency are detected automatically. [AK4490EN] 015013666 - e - 01 2015/1 2 - 56 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 dzfe dzfm sd dfs1 dfs0 dem1 dem0 smu te r(i2c)/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 1 0 0 0 1 0 smute: soft mute enable 0: normal operation (default) 1: dac outputs soft - muted. dem1 - 0: de - emphasis response initial value is 01 (off). dfs 2 - 0: sampling speed control ( table 31 ) initial value is 0 0 0 (normal speed). click noise occurs when dfs 2 - 0 bits are changed. (05h, d1: dfs2 bit ) table 31 . sampling speed (manual setting mode @serial mode) dfs2 dfs1 d fs0 sampling rate (fs) 0 0 0 normal speed mode 30khz ? ? ? to 1 , the dzf pins of both l and r channels go to h only when the input data at both channels are continuously zeros for 8192 lrck cycles. dzfe: data zero detect enable 0: disable (default) 1: enable zero detect function can be disabled by d zfe bit 0 . in this case, the dzf pins of both channels are always l . [AK4490EN] 015013666 - e - 01 2015/1 2 - 57 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h control 3 dp 0 dcks dckb mono dzfb sellr slow r(i2c)/w r/w r r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 slow: slow roll - of f filter enable 0: sharp roll - off filter (default) 1: slow roll - off filter table 33 . digital f i lter setting sslow bit sd bit slow bit mode 0 0 0 sharp roll - off filter 0 0 1 slow roll - off filter 0 1 0 short delay sharp roll - off filter (default) 0 1 1 short delay slow roll - off filter 1 - - super slow roll - off filter sellr: the data selection of l channel and r channel table 34 mono mode output select mono bit sellr bit lch out rch out 0 0 lch in rch in (default) 0 1 rch in lch in 1 0 lch in lch in 1 1 rch in rch in dzfb: inverting enable of dzf 0: dzf pin goes h at zero detection (default) 1: dzf pin goes l at zero detection table 35 . zero detec t function and dzf pin output dzfe dzfb data dzf - pin 0 0 - l 1 - h 1 0 not zero l zero detect h 1 not zero h zero detect l mono: mono mode stereo mode select 0: stereo mode (default) 1: mono mode when mono bit is 1 , mono mode is en abled. dckb : polarity of dclk (dsd only) 0: dsd data is output from dclk falling edge. (default) 1: dsd data is output from dclk rising edge. dcks : master clock frequency select at dsd mode (dsd only) 0: 512fs (default) 1: 768fs dp: dsd/pcm mode select 0: pcm mode (default) 1: dsd mode when d p bit is changed, the ak4490 en should be reset by rstn bit. [AK4490EN] 015013666 - e - 01 2015/1 2 - 58 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 at t0 r(i2c)/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 1 1 1 1 1 1 1 1 att7 - 0: attenuation level 25 5 levels, 0.5db step + mute data attenuation ffh 0db feh - 0.5db fdh - 1.0db : : 02h - 126.5db 01h - 127.0db 00h mute ( - ? ) the transition between set values is soft transition of 7 396 levels. it takes 7 395 /fs (168ms@fs=44.1khz) from ffh (0db) to 00h (mute). if the pdn pin goes to l , the atts are initialized to ffh. the atts are ffh when rstn bit = 0 . when rstn return to 1 , t he atts fade to their current value. this digital attenuator is independent of soft mute function. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 5 h control 4 invl invr 0 0 0 0 dfs2 sslow r(i2c)/w r/w r/w r r r r r/w r/w d efault 0 0 0 0 0 0 0 0 sslow : super slow roll - off filter enable 0: disable (default) 1: enable dfs2 - 0 : sampling speed control ( table 36 ) initial value is 000 (normal speed). click noise occurs when dfs2 - 0 bits are changed. (01h, d4, d3: dfs1 - 0 bits) table 36 . sampling speed (manual setting mode @serial mode) dfs2 dfs1 dfs0 sampling rate (fs) 0 0 0 normal speed mode 30khz ? ? ? [AK4490EN] 015013666 - e - 01 2015/1 2 - 59 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 6 h control 5 ddm dml dmr dmc dmre 0 dsdd dsdsel 0 r(i2c)/w r/w r/w r/w r/w r/w r r/w r/w d efault 0 0 0 0 0 0 0 0 dsdsel 1 - 0 : dsd sampling speed c ontrol (see also control 7 register.) table 15 . dsd sampling speed control dsdsel1 bit dsdsel 0 bit dsd data stream 0 0 2.8224mhz (default) 0 1 5.6448mhz 1 0 11.2896mhz 1 1 reserved dsdd : dsd p lay b ack path c ontrol table 16 . dsd play back mode control d sdd mode 0 normal p ath (default) 1 v o lume byp ass dmre : dsd m ute r elease 0: hold (default) 1: release mute this register is only valid when ddm bit = 1 and dmc bit = 1 . when the ak4490 en mutes ds d data by ddm and dmc bits settings, the mute is released by setting dmre bit to 1 . table 19 . recovery m ethod to n ormal o peration m ode from f ull s cale d etection s tatus d dm dm c dmre status after detection 0 * * when full sca le is detected, mute function is disable. (default) 1 0 * when full scale is detected, mute function is enable. t he AK4490EN returns normal operation automatically by a normal signal input. 1 1 0 when full scale is detected, mute function is enable. t he AK4490EN keeps mute mode, even if a normal signal is input. 1 1 1 ( note 28 ) when full scale is detected, mute function is enable. t he AK4490EN returns normal operation , when a normal signal is input and dmre bit is set 1 0 automatically. dmc : dsd m ute c ontrol 0: auto r eturn (default) 1: mute h old (manual return) this register is only val id when ddm bit = 1 . it selects the mute releasing mode of when the dsd data level becomes under full - scale after the ak4490 en mutes dsd data by ddm bit setting . dmr/dml this register outputs detection flag when a full scale signal is detected at dsdr/ l channel. ddm : dsd d ata m ute 0: disable (default) 1: enable the ak4490 en has an internal mute function that mutes the output when dsd audio data becomes all 1 or all 0 for 2048 s ample s (1/fs). ddm bit controls this function. [AK4490EN] 015013666 - e - 01 2015/1 2 - 60 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 7 h control 6 0 0 0 0 0 0 0 synce r(i2c)/w r r r r r r r r/w d efault 0 0 0 0 0 0 0 0 synce : synchroniz ation control 0: disable (default) 1: enable this register enables the function that synchronizes multiple ak4490 en s when using more than one ak4490 en s in a system. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 8 h control 7 0 0 0 0 0 0 sc1 sc0 r(i2c)/w r r r r r r r/w r/w d efault 0 0 0 0 0 0 0 0 sc1 - 0: sound control bit table 37 . sc1 - 0 bits contro l s c 1 s c 0 sound mode 0 0 sound s etting 1 (default) 0 1 sound setting 2 1 0 sound setting 3 1 1 reserved addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 9 h control 8 0 0 0 0 0 0 dsdf dsdsel 1 r(i2c)/w r r r r r r r/w r/w d efault 0 0 0 0 0 0 0 0 dsdsel1 - 0 : dsd sampling speed control (see also control 4 register.) table 15 . dsd sampling speed control dsdsel1 dsdsel0 dsd data stream 0 0 2.8224mhz (default) 0 1 5.6448mhz 1 0 11.2896mhz 1 1 reserved dsdf: dsd filter when dsdd bit= 1 , the filter characteristics can be switched between 50khz and 150khz by dsdf bit. table 17 . dsd filter sele ct dsdd bit dsdf bit cut off filter 0 0 50khz (default) 0 1 rese rved 1 0 50khz 1 1 150khz [AK4490EN] 015013666 - e - 01 2015/1 2 - 61 - 10. recommended external circuits figure 38 shows the system connection diagram. figure 40 , figure 41 an d figure 42 show the analog output circuit examples. the evaluation board (akd 449 0 ) demonstrates the optimum layout, power supply arrangements and measurement results. figure 38 . typical connection diagram (avdd=3.3v, vddl/r=5v, dvdd=3.3v, serial control mode) (tvdd=1.8v , dvdd=3.3v, avdd=3.3v, vddl/r=5.0v and v refh l/r=5.0v, serial control mode) note 37 . (1) chip address = 00 . bick = 64fs, lrc k = fs (2) power lines of avdd and dvdd should be distributed separately from the point with low impedance of regulator etc. (3) avss, dvss, vssl, vssr, vrefll and vreflr must be connected to the same analog ground plane. (4) when aout drives a capacitive load, some r esistance should be connected in series between aout and the capacitive load . (5) all input pins except pull-down/pull - up pins should not be allowed to float. (6) the exposed pad on the bottom surface of the package must be connected to the ground. analog 5.0v r ch lpf r ch mute r ch o ut analog ground digital ground d igital 3 . 3 v 0.1u 10u a nalog 3.3 v 0.1u 10u dsp micro - controller 0.1u 10u lch lpf lch mute lch out pdn dvdd 1 bick 44 2 sdata 3 lrck 4 wck 5 csn 6 cclk 7 cdti 8 dzfl 9 dzfr 10 11 psn 33 aoutln ak4490 en 13 14 15 16 17 19 20 21 22 i2c dem0 dem1 cad1 vrefhr vrefhr vreflr vreflr vcmr 32 vddl 31 vddl 30 vssl 29 vssl 28 27 vssr n 26 vssr 25 vddr vddr aoutrn dvss 43 mclk 42 avss 41 avdd 40 vrefhl 39 vrefhl 38 vrefll 37 vrefll v c ml 0.1u 1 0u 10u 0.1u 10u 10u 1 0u 0.1u nc 23 24 18 nc aoutr p aoutlp 34 35 36 48 47 46 45 nc tvdd 12 nc cad0 0.1u 10u d igital 1.8v ceramic capacitor [AK4490EN] 015013666 - e - 01 2015/1 2 - 62 - connection with ak8157a the ak8157a is recommended to use with a premium dac, the ak4490 en . circuits for a high quality premium audio solution are shown as below. in this circuit, a 9.6mhz external clock is input to the ak8157a. mclk, bclk and lrck are generated by the ak8157a. sdata for the ak4490 en is output from the external dsp in s ynchronization with bclk and lrck. figure 39 . h igh q uality p remium a udio solution of the ak4490 en with the ak8157a analog 5.0v ceramic capacitor + electrolytic capacitor r ch lpf r ch mute r ch out analog ground digital ground d igital 3 . 3 v 0.1u 10u a nalog 3.3 v 0.1u 10u + 0.1u 10u lch lpf lch mute lch out pdn dvdd 1 bick 44 2 sdata 3 lrck 4 wck 5 smute 6 scl 7 sda 8 dif0 9 dif 1 10 11 psn 33 aoutln ak4490 en 13 14 15 16 17 19 20 21 22 i2c dem0 dem1 cad1 vrefhr vrefhr vreflr vreflr vcmr 32 vddl 31 vddl 30 vssl 29 vssl 28 27 vssr n 26 vssr 25 vddr vddr aoutrn dvss 43 mclk 42 avss 41 avdd 40 vrefhl 39 vrefhl 38 vrefll 37 vrefll v c ml 0.1u 1 0u 10u 0.1u 10u + 10u 1 0u 0.1u nc 23 24 18 nc aoutr p aoutlp 34 35 36 48 47 46 45 nc tvdd 12 nc cad0 0.1u 10u d igital 1.8v mclk vdd1 cad0 clkin vss1 scl lrck vss3 vdd4 rstn sda vdd2 cad1 vdd3 vss2 bclk 4 3 2 1 d c b a digital 1.8 v digital 1.8v dsp micro - controller ak8157a 9.6mhz vdd1.8v ground digital ground analog ground 0.1u 0.1u 0.1u 0.1u 0.1u [AK4490EN] 015013666 - e - 01 2015/1 2 - 63 - 1. groundi ng and power supply decoupling to minimize coupling by digital noise, decoupling capacitors should be connected to tvdd, dvdd, avdd and vddl/r respectively. vddl/r and vrefhl/r are supplied from analog supply in system , and tvdd, d vdd and a vdd are supplie d from digital supply in system. power lines of tvdd, dvdd, avdd and vddl/r and vrefhl/r should be distributed separately from the point with low impedance of regulator etc. digital and analog power supply should be powered up at the same time, otherwise p ower up the 1.8v base power supplies (tvdd) at first, the 3.3v base power supplies secondarily (dvdd, avdd) and 5v base power supplies finally (vddl/r, vrefhl/r). dvss, a vss, vssl/r and vrefll/r must be connected to the same analog ground plane. decoupling capacitors for high frequency should be placed as near as possible to the supply pin. 2. voltage reference the differential voltage between vrefhl/r and vrefll/r sets the analog output range. the vrefhl/r pin is normally connected to avdd, and the vrefl l/r pin is normally connected to vss1/2/3. vrefhl/r and vrefll/r should be connected with a 0.1f ceramic capacitor as near as possible to the pin to eliminate the effects of high frequency noise. no load current may be drawn from vc ml/r pin. all signals, especially clocks, should be kept away from the vrefhl/r and vrefll/r pins in order to avoid unwanted noise coupling into the ak4490 en . 3. analog outputs the analog outputs are full differential outputs and 2.8 vpp (typ , vref hl/r ? vrefll/r = 5v) centere d around vddr /2 and vddl/ 2 voltages . the differential outputs are summed externally, v aout = (aout+) ? (aout ? ) between aout+ and aout ? . if the summing gain is 1, the output range is 5.6 vpp (typ , vref hl/r ? vrefll/r = 5v). the bias voltage of the external s umming circuit is supplied externally. the input data format is 2's complement. the output voltage (v aout ) is a positive full scale for 7fffff ff h (@ 32 bit) and a negative full scale for 800000 00 h (@ 32 bit). the ideal v aout is 0v for 00000 00 0h(@ 32 bit). the i nternal switched-capacitor filter s attenuate the noise generated by the delta-sigma modulator beyond the audio passband. figure 40 shows an example of external lpf circuit summing the differential outputs by an op - a mp. figure 41 shows an example of differential outputs and lpf circuit example by three op - amps. figure 40 . external lpf circuit example 1 for pcm ( fc = 99.2 khz , q=0. 704 ) 1.5 k 1.5 k 390 1.5 k 390 1.5 k 1n +vop 1n - vop aout - aout+ 2.2 n analog out ak4 49 0 en [AK4490EN] 015013666 - e - 01 2015/1 2 - 64 - table 38 . frequency response of external lpf circuit example 1 for pcm frequency response gain 20khz ? ? ? st stage 2 nd stage total cut - off frequency 182khz 284khz - q 0.637 - - gain +3.9db - 0.88db +3.02db frequency response 2 0khz - 0.025 db - 0.021 db - 0.046db 40khz - 0.106 db - 0.085 db - 0.191db 80khz - 0.517 db - 0.331 db - 0.848db 330 100 180 aoutl - 10k 3.9n 1.2k 680 3.3n 6 4 3 2 7 10 0.1 0.1 10 10 njm5534d 330 100 180 aoutl+ 10k 3.9n 1.2k 680 3.3n 6 4 3 2 7 10 0.1 0.1 10 njm5534d 0.1 + njm5534d 0.1 10 100 4 3 2 1.0n 620 620 560 7 + + + + - * + - + + + - + + 1.0n lch g - 15 +15 6 560 [AK4490EN] 015013666 - e - 01 2015/1 2 - 65 - it is recommended for sacd format book (scarlet book) that the filter response at sacd playback is an analog low pass filter with a cut - off frequency of maximum 50khz and a slope of minimum 30db/oct. the ak4490 en can achieve this filter response by combination of the internal filter ( table 40 ) and an external filter ( figure 42 ). table 40 . internal filter response at dsd mode frequency gain 20khz ? ? ? ? ? ? 1.8k 4.3k 1.0k 1.8k 1.0k 4.3k 270p +vop 270p - vop aout - aout+ + 3300p analog out 2.0k 2.0k 2200p - + 2.8vpp 6.34vpp 2.8vpp [AK4490EN] 015013666 - e - 01 2015/1 2 - 66 - 11. package outline dimensions 48 - pin qf n (unit mm) note 38 . the exposed pad on the bottom surface of the package must be connected to the ground. material & lead finish package molding compound: epoxy , halogen (bromine and chlorine) free lead frame material: cu pin surface treatment: solder (pb free) plate 0 . 40 0 . 10 4 . 1 0 0 . 10 4 . 1 0 0 . 10 0 ~ 0 . 05 0 . 20 m 0 . 07 0 . 05 24 36 37 48 c a b c 0 . 35 1 13 0 . 40 6 . 00 6 . 00 0 . 10 0 . 10 0 . 05 0 . 8 5 b 0 . 08 c a c ( 0 . 20 ) ( 0 . 5 5 ) [AK4490EN] 015013666-e- 01 2015/12 - 67 - v ma rking 1) akm logo 2) pin #1 indication 3) date code: xxxxxxx(7 digits) 4) marking code: AK4490EN 12. ordering guide v ordering guide AK4490EN 40 a +85 q c 48 -pin qfn (0.4mm pitch) akd4490 en evaluation board for AK4490EN 13. revision history date (y/m/d) revision reason page contents 1 5 / 10 / 15 00 first edition 1 5 / 1 2 / 0 8 0 1 description ad dition 7, 61, 66 the descriptions regarding the exposed pad were ak 4 490en xxxxxxx akm [AK4490EN] 015013666 - e - 01 2015/1 2 - 68 - important notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when y ou consider any use or application of akm product stipulated in this document ( product ) , please make inquiries the sales office of akm or authorized distributor s as to current status of the products. 1. all information included in this document are provi ded only to illustrate the operation and application examples of akm products . akm neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellec tual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use of such information contained in this document in your product design or applications . akm assumes no lia bility for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high leve ls of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact , including but not limited to, equipment used in nuclear facilities, equipment used in t he aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for the above use unless specifically agreed by akm in writing . 3. though akm works continually to improve the products quality and reliability, you are responsible for comp lying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, devel opment, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). when exporting the p roducts or related technology or any information contained in this document, you should com ply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. the p roducts and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sal e is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact akm sales representative for details as to environmental matters such as the rohs compatibility of the product. please use the product in compliance with all ap plicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. resale of the product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm . |
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