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electronics semiconductor division preliminary information describes products that are not in full production at the time of printing. specifications are based on design goals and limited characterization. they may change without notice. contact raytheon for current information. preliminary information features >85% ef?iency 350ua quiescent current in shutdown fast transient response soft control power-up over-voltage protection output voltage range from 2.0v to 3.6v factory trimmed low tc reference voltage adjustable oscillator frequency drives n-channel mosfets 16 pin soic package applications 3.3v power supply for pentium based cpu motherboards 3.45v power supply for amd-k5 cpu 2.5v or 3.6v power supply for powerpc description the RC5033 is a synchronous mode dc-dc controller ic dedicated to providing a 5v to 2.0v up to 3.6v conversion for various types of cpu power . it can be con?ured in both the synchronous and non-synchronous modes and with the proper applications circuitry can be used to deliver load cur- rent greater than 10 amps. the RC5033 is designed to oper- ate in a standard pwm control mode under heavy load conditions and as a pfm controller in light load conditions. its highly accurate low tc reference eliminates the need for precision external components in order to achieve tight tolerance voltage regulation. through the use of external resistors, the RC5033 can generate accurate output voltages from 2.0v up to 3.6v. an integrated over-voltage protection function constantly monitors the output voltage and shuts down the power to the cpu in the event of a out-of- tolerance voltage situation, thereby protecting the cpu. the programmable oscillator can operate from 200khz to greater than 1mhz to provide for ?xibility in choosing external components such as inductors, capacitors, and power mosfets. block diagram digital control + + i vref 65-5033-01 osc vref + + i + + i + + i vin vo RC5033 adjustable synchronous dc-dc converter rev. 0.9.5
product specification RC5033 2 pr eliminar y infor mation pin assignments pin de nitions note: 1. see voltage adjust table for function output v olta g e selection t ab le note: 1. see figure 3 for resistor connection. 2. indicated short pins together. pin name pin number pin function description on/off 1 a low level on this pin will power down; tie to vccd if not used. ifb 2 current feedback input. vfb 3 voltage feedback input. vcca 4 analog vcc. vccd 5 digital vcc. vccp 6 vcc for synchronous fet output drivers. lodrv 7 synchronous fet driver output. gndp 8 power ground for high current drivers. hidrv 9 high side fet driver output. vccqp 10 vcc for high side fet output driver adj1 11 vref adjust pin. 1 adj2 12 vref adjust pin. 1 gndd 13 digital ground. adj3 14 vref adjust pin. 1 gnda 15 analog ground. cext 16 external capacitor for setting oscillator frequency. v out adj1 adj2 adj3 3.5v n/c n/c n/c 3.35v n/c 2 2 3.3v 2 n/c 2 2.9v 1 3.9k n/c n/c 2.5v 1 2k n/c n/c 2.0v 1 39 w n/c n/c 1 2 3 4 5 6 8 7 cext gnda adj3 gndd adj2 adj1 hidrv vccqp 16 15 14 13 12 11 9 10 on/off ifb vfb vcca vccd vccp gndp lodrv 65-5033-02
RC5033 product specification 3 pr eliminar y infor mation absolute maxim um ratings (be y ond which the de vice ma y be damaged) 1 note: 1. functional operation under any of these conditions is not implied. operating conditions dc electrical characteristics (v cc = 5v , f osc = 650 khz, and t a = +25?c unless otherwise noted) notes: 1. functional operation under any of these conditions is not implied. performance is guaranteed only if operating conditions are not exceeded. 2. output voltage accuracy, tempco, load regulation, ripple, and transient performance determine the cumulative accuracy. p arameter conditions min t yp max units v ccp driver voltage 13 v v ccqp high driver supply 13 v t j junction temperature 175 c t a ambient operating temperature 0 70 c t s storage temperature -65 150 c t l lead soldering temperature (10 seconds) 300 c p arameter conditions min t yp max units v cc supply voltage 4.5 5 7 v v ccp low driver supply 4.5 5 12 v v ccqp high driver supply 9 13 v v ih input voltage, logic high 2 v v il input voltage, logic low 0.8 v p arameter conditions min t yp max units v o output voltage nominal, pin 12 conn. pin 14, t a = 0?0 c 3.135 3.3 3.465 v i o output current see figure for application 5 a vref acc voltage reference accuracy 1 % vtc output voltage tempco -40 ppm ldr load regulation 0.5 to 7a 1 %v o lir line regulation v cc = 5% 0.14 %v o v r output voltage ripple 30 mv cum acc cumulative accuracy 2 t a = 0?0 c 3 % eff efficiency synchronous mode > 1a 80 85 % iodr output driver i open loop 0.5 0.7 a pd power dissipation 0.1 0.2 w
product specification RC5033 4 pr eliminar y infor mation a c electrical characteristics 1 (t a = +25?c unless otherwise noted) note: 1. guaranteed by design, not 100% total. p arameter conditions min t yp max units tr response time il=0.5a to 5.5a 10 m s fosc oscillator range 0.2 1.2 mhz osc acc fosc accuracy 10 % dtc max duty cycle pwm mode 90 95 % dtcm min duty cycle pfm mode 100 ns imax imax threshold 30 mv iscp short circuit prot 80 mv ovp over voltage prot 20 %vo trimax response to imax 15 30 ns tssp soft start response 10 m s
RC5033 product specification 5 pr eliminar y infor mation t ypical operating characteristics 1 note: 1. data taken with circuit of figure 1. efficiency vs output current (f osc = 400 khz) efficiency (%) output current (a) 100 90 80 70 60 50 0 2 4 6 efficiency vs output current (f osc = 650 khz) efficiency (%) output current (a) 100 90 80 70 60 50 0 2 4 6 efficiency vs output current (f osc = 1 mhz) efficiency (%) output current (a) 100 90 80 70 60 50 0 2 4 6 load regulation (f osc = 1 mhz) v out output current (a) output current (a) 3.36 3.35 3.34 3.33 3.32 3.31 3.3 0 2 4 6 65-5033-03 8 load regulation (f osc = 650 khz) v out 3.37 3.36 3.35 3.34 3.33 3.32 3.31 3.3 0 2 4 6 8 output current (a) load regulation (f osc = 400 khz) v out 3.38 3.37 3.36 3.35 3.34 3.33 3.32 3.31 3.3 0 2 4 6 8
product specification RC5033 6 pr eliminar y infor mation t ypical operating characteristics (contin ued) line regulation vs. output load (f osc = 400 khz) line reg (%) output current (a) 0.3 0.25 0.2 0.15 0.1 0.05 0 0 2 4 6 8 reference tempco v ref temp 3.5 3.495 3.49 3.485 3.48 3.475 3.47 0 50 100 line regulation vs. output load (f osc = 650 khz) line reg (%) output current (a) 0.3 0.25 0.2 0.15 0.1 0.05 0 0 2 4 6 8 line regulation vs. output load (f osc = 1 mhz) line reg (%) output current (a) 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 65-5033-04 0 2 4 6 8 cext vs. oscillator frequency cext (pf) frequency (hz) 200 150 100 50 0 0 4 8 4
RC5033 product specification 7 pr eliminar y infor mation t ypical operating characteristics (contin ued) ac ripple response .2a load ac ripple response 5a load transient response .2a to 5a load transient response magnified figure 1. standard 7a application schematic time ( 1 m s/division) hidrv (5v/division) v out (50mv/division) time ( 1 m s/division) hidrv (5v/division) v out (50mv/division) time ( 200 m s/division) i out (2a/division) v out (50mv/division) time ( 20 m s/division) i out (2a/division) v out (50mv/division) vcc c5 200 f ds2 ec10qs02 RC5033 9 10 11 12 c13 4.7 f 13 14 8 7 6 5 4 3 2 1 15 16 gnd c4 0.1 f c1 47pf m1 mtd20n03hdl m2 mtd20n03hdl ds1 mbrb1545ct c9 330 f 65-5033-05 c2 1 f l1 1.5 h r1 0.012 vo
product specification RC5033 8 pr eliminar y infor mation figure 2. non-synchronous 7a application circuit figure 3. adjustable voltage dc-dc converter vcc c5 200 f ds2 ec10qs02 RC5033 9 10 11 12 c13 4.7 f 13 14 8 7 6 5 4 3 2 1 15 16 gnd c4 0.1 f c1 47pf m1 mtd20n03hdl ds1 mbrb1545ct c9 330 f 65-5033-06 c2 1 f l1 cdrh127-1r3nc r1 0.012 vo vcc c5 200 f ds2 ec10qs02 RC5033 9 r2 10 11 12 c13 4.7 f 13 14 8 7 6 5 4 3 2 1 15 16 gnd c4 0.1 f c1 47pf m1 mtd20n03hdl m2 mtd20n03hdl ds1 mbrb1545ct c9 330 f 65-5033-07 c2 1 f l1 1.5 h r1 0.012 vo
RC5033 product specification 9 pr eliminar y infor mation table 1. components for RC5033 table 2. alternate components selection RC5033 standar d application cir cuit bill of materials ref designator quantity p ar t no. man ufacturer l1 1 cdrh127-1r3nc sumida m1,m2 2 mtd20n03hdl motorola ds1 1 mbrb1545ct motorola ds2 1 ec10qs02l nihon r1 1 lrc-2512 irc c5 1 os-con 10sa220m san y o c9 1 os-con 10sa330m san y o c2 1 1uf monolithic cer amic cap c1 1 47pf smd cap c4 2 0.1uf smd cap RC5033 alternate supplier s of components ref designator quantity alter nate p ar t no . alter nate man uf acturer l1 1 pe-53680 pulse engineer ing m1,m2 2 2sk1388 fuji irlz44n inter national recti er si4410d y t emic (siliconix) ds1 1 c10t02ql nihon sr1620c rectron ds2 1 mbrs140t3 motorola r1 1 wsl-2512 d ale c5 1 c9 1
product specification RC5033 10 pr eliminar y infor mation dual p o wer suppl y application in some cpu po wer applications there may be a need for a split v oltage con v erter . the circuit in figure 4 addresses this need with only minimal component count. the basic RC5033 non-synchronous dc-dc con v erter is augmented with an op-amp, a po wer mosfet , and some 1% resistors to pro vide a dual po wer supply with one v oltage set to 3.3v and the other , sla v ed of f of the 3.3v , set to 2.9v . in this con- guration, the RC5033 con v erts the 5v to 3..3v with high ef cienc y . by using the op-amp, po wer fet , and the resis- tors, a lo w-dropout linear re gulator is realized that can be run of f of the 3.3v . the 2.9v linear re gulator has a relati v ely high ef cienc y just due to the f act that the ratio of 2.9v/3.3v is close to 88%. the po wer fet is a lo w rdson n-channel mosfet , and thus it is reasonably ine xpensi v e. the opamp can be a g arden v ariety , though the input bias current and output sle w rate need to be considered to optimize accurac y and transient response. the o v erall ef cienc y of this po wer supply system will v ery much depend upon the percentage of po wer used on each po wer output. ov erall, the ef cienc y of this system will be lo wer than if both supplies were imple- mented as switchers; ho we v er , the added sa vings of the part count reduction may more than compensate for the o v erall lo wer ef cienc y . standar d application cir cuit the circuit sho wn in figure 1 along with its components and v alues has been designed as representati v e of the typical application in v olving the RC5033 for a pentium cpu. use of the standard application circuit will deli v er the perfor - mance curv es sho wn under the t ypical operating character - istics section of the data sheet. man y users will w ant to de v elop their o wn dc-dc con v erter solution that is uniquely tailored to a speci c application requirement. in that case, the users should re vie w the detailed information in the design procedure and applications information section of the data sheet. detailed description the RC5033 is a programmable v oltage synchronous con- troller . when designed around the appropriate e xternal com- ponents, it can be con gured to deli v er more than 10a of output current. during hea vy loading conditions the RC5033 functions as a current-mode pwm step do wn re gulator . under light loading conditions, the re gulator functions in the pfm or pulse skipping mode, thereby increasing its ef - cienc y under light loads. applications discussion vccp c5 200 f ds2 ec10qs02 RC5033 9 10 11 12 c13 4.7 f 13 14 8 7 6 5 4 3 2 1 15 16 gnd c4 0.1 f +12v c1 47pf r2 12k r3 88k lm308a + + m1 mtd20n03hdl ds1 mbrb1545ct c9 330 f 65-5033-08 c2 1 f l1 1.5 h r1 0.012 vo m2 mtd20n03hdl vo2 2.9v c1 47pf
RC5033 product specification 11 pr eliminar y infor mation main control loop the main control loop of the re gulator (see block diagram) contains tw o main blocks, the analog control block and the digital control block. the analog control block consists of signal conditioning ampli ers that feed into a set of f ast comparators which pro vide the inputs to the digital control block. the signal conditioning block tak es inputs from the ifb(current feedback) and vfb(v oltage feedback) pins and then sets up tw o controlling signal paths. the v oltage control path g ains up the vfb signal and presents that signal to one of the summing ampli er inputs. the current control path tak es the dif ference between the ifb and vfb pins and pre- sents that signal to another input of the summing ampli er . these tw o signals are then summed together with the slope compensation input from the oscillator and the output is then presented to a comparator . this comparator pro vides the main pwm control signal to the digital control block. there are three other comparators in the analog control block. the rst tw o control the thresholds of where the RC5033 goes into its pulse skipping mode during light loads and the second controls the point at which the max current comparator disables the output dri v e signal to the upper po wer mosfet . the third comparator determines when the synchronous mode bottom side po wer mosfet will be enabled and disabled. the digital controller section is designed to tak e the compar - ator inputs along with the main clock signal from the oscilla- tor and pro vide the appropriate pulses to the hidr v and lodr v output pins that will in turn control the e xternal po wer mosfets. this digital section w as designed in high speed schottk y transistor logic which allo ws the RC5033 to clock up to speeds greater then 1mhz. this section is responsible for pro viding the break-before-mak e timing that ensures that both e xternal fets will not be on at the same time. high current output drivers the RC5033 contains tw o identical high current output dri v- ers. these dri v ers contain high speed bipolar transistors con- gured in a push-pull con guration. each output dri v er is capable of pumping out 1a of current in less than 100ns. each dri v er s po wer and ground are separated from the o v er - all chip po wer and ground for added switching noise immu- nity . the hidr v dri v er has a po wer supply , vccqp , which can be either deri v ed from an e xternal v oltage source or can be boot-strapped from a ying-capacitor as is sho wn in fig- ure 1. in the boot-strapped mode, c2 is alternately char ged from vcc via the schottk y diode ds2 and then boosted up when m1 is turned on. this pro vides a vccqp v oltage equal to 2*vcc - vds(ds2); or about 9.5v with vcc=5v . this v oltage is suf cient to pro vide the 9v g ate dri v e to the e xter - nal mosfet that will be needed for achie ving a lo w rdson. since the lo w side synchronous fet is referenced to ground, there is no need to boost the g ate dri v e v oltage and its vccp po wer pin can just be tied to vcc. internal reference the reference in the RC5033 is a precision band-g ap type reference. its temperature coef cient is trimmed to pro vide a near zero tc. f or applications that require a v oltage other than the v oltages pro vided by the x ed jumper connections, an e xternal resistor will change the reference v oltage from 2.0v up to 3.6v . f or a guaranteed stable operation under all loading conditions, a 0.1 m f capacitor is recommended on the vref output pin. over -voltage protection the RC5033 pro vides a constant monitor of the output v olt- age for o v er -v oltage protection. should the v oltage at the vfb pin e xceed 20% of the selected program v oltage, then an o v erv oltage condition will be assumed to e xist and the RC5033 will shut do wn the output dri v e signals to the po wer fets. oscillator the RC5033 oscillator is designed as a x ed current capaci- tor char ging oscillator . an e xternal capacitor allo ws for max- imum e xibility in choosing the associated e xternal components for the RC5033. the oscillator frequenc y con be set from less than 200khz to o v er 1mhz depending on the application requirements. design pr ocedure and applications inf ormation simple step-down converter figure 4 sho ws a step-do wn dc-to-dc con v erter with no feedback controller . the deri v ation of the basic step-do wn con v erter will serv e as a basis for the design equations for the RC5033 in figure 1. in figure 5, the basic operation be gins by closing the switch, s1. when s1 is closed the input v oltage vb is impressed across the inductor l1. the current o wing in the inductor is gi v en by the follo wing equation: il=(vb- v o)t on/l; where t on is the time duration for s1 to be closed. when s1 is open, the diode will conduct the inductor current and the output current will be deli v ered to the load according to the equation: il=v o(t ? t on)/l; where t - t on is the time duration for s1 to be of f. by solving these tw o equations we can arri v e at the basic relationship for the output v oltage of a step-do wn con v erter: v o= vb(t on/t). figure 5. simple buck dc-dc converter c1 r l vout 1 2 1 + 2 d1 vb 1 65-5033-09 2 l1 s1
product specification RC5033 12 pr eliminar y infor mation selecting the inductor the inductor is one of the most critical components to be selected in the dc-to-dc con v erter application. the critical parameters are inductance (l), max dc current (imax), and the coil resistance (rl). the inductor core material is a criti- cal f actor in determining the amount of current that the inductor will be able to handle. as with all engineering designs there are trade- of fs for v arious types of inductor core materials. in general, ferrites are popular because of their lo w cost, lo w emi, and high frequenc y (>500khz) characteristics. molypermallo y po wder (mpp) materials ha v e good saturation characteristics and lo w emi with lo w h ysteresis losses; ho we v er the y tend to be e xpensi v e and are more ef ciently utilized at frequencies belo w 400khz. dc winding resistance is another critical parameter . in general, the dc resistance should be k ept as lo w as possible. the po wer loss in the dc resistance will de grade the ef cienc y of the con v erter by the relationship: po wer loss = (io)2*rl. the v alue of the inductor is a function of the switching fre- quenc y (t on) and the maximum inductor current. the max inductor current can be calculated from the relationship: where: f o is the desired clock frequenc y t on is the max on time of the m1 fet vd is the forw ard v oltage of the schottk y diode d1 then the inductor v alue can be calculated with the relationship: where: vdson is the v oltage across the drain-source of the m1 fet when switched on. (this can be calculated by rdson * imax) current-sense resistor the current sense resistor will carry all of the peak current of the inductor . this current will be more than the designed for load current. the RC5033 will be gin to limit the output cur - rent to the load by turning of f the top-side fet dri v er when the v oltage across the current-sense resistor e xceeds 100mv . when this happens the output v oltage will temporarily go out of re gulation. as the v oltage across the resistor becomes lar ger , the top-side fet will turn of f more and more until the current limit v alue is reached and then the RC5033 will con- tinuously deli v er the limit current at a reduced output v oltage le v el. t o insure that load transient conditions do not momen- tarily cause dere gulation of the output v oltage, a 20% mar gin in the limit v oltage is advisable. thus the resistor should be set by the relationship: r = 100 mv/ ipeak where: ipeak = imax * 1.33 i m a x 2 i l f o t o n v i n v o u t v o u t v d - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ? ? ? 1 + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - = l v i n v d s o n i m a x - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - t o n ( ) = since the v alue of the sense resistor is generally in the mil- iohm re gion, care should be tak en in the layout of the pcb. t race resistance can contrib ute signi cant errors. the traces to the ifb and vfb pins of the RC5033 should be k elvin connected to the pads of the current-sense resistor as sho wn in the sample layout figure 5. t o minimize the in uence of noise the tw o traces should be run ne xt to each other and the pins should be bypassed with a .1uf to gnd as close to the de vice pins as possible. filter capacitors good ripple performance and transient response are func- tions of the lter capacitors. since the 5v input for a pc motherboard can be located se v eral inches a w ay from the dc-to-dc con v erter , input capacitance can play an impor - tant role in the load transient response of the RC5033. in general, the higher the input capacitance, the more char ge storage is a v ailable for impro ving the current transfer through the top-side fet . a good rule of thumb is that for each w att of output po wer that you wish to deli v er , there should be around 10uf of input capacitance. lo w ?sr? capacitors are best suited for this application and can ha v e an in uence on the con v erter s ef cienc y . the input capacitor should be placed as close to the drain of the top-side fet as possible to reduce the ef fect of ringing that can be caused by lar ge trace lengths. the esr rating of a capacitor is a dif cult number to pin do wn. esr or equi v alent series resistance, is de ned at the resonant impedance of that capacitor . since the capacitor is actually a comple x impedance de vice ha ving resistance, inductance and capacitance, it is quite natural for it to ha v e an associated resonant frequenc y . as a rule, the lo wer the esr, the better suited the capacitor is for use in switching po wer supply applications. man y capacitor manuf acturers do not supply esr data. a useful estimate of the esr can be obtained with the follo wing equation: esr = pd/2pfc. where pd is the capacitor s dissipation f actor and f is the fre- quenc y of measure and c is the capacitance in f arads. w ith this in mind, calculating the output capacitance cor - rectly is crucial to the performance of the dc-to-dc con- v erter . the output capacitor determines the o v erall loop stability , output v oltage ripple, and the transient load response. the calculation uses the follo wing equation: where: vr is the desired output ripple v oltage schottky diode selection the application circuit diagram sho ws tw o schottk y diodes, ds1 and ds2. ds1 is used in parallel of m2 in order to pre- v ent the lossy body diode in the fet from turning on. ds2 serv es a dual purpose. as it is con gured, it allo ws the vccqp supply pin of the RC5033 to be bootstrapped up to c m f ( ) t o n v i n v o u t ( ) i m a x v o u t - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - i l + ? ? ? v r - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =
RC5033 product specification 13 pr eliminar y infor mation 9v by using the bootstrap capacitor c2. when the lo wer fet m2 is turned on, one side of the capacitor c2 is connected to gnd while the other side of the cap is being char ged up through d2 to a v oltage that is v in - vd. when the lo wer fet turns of f and the upper one turns on, the v oltage that is supplied to the vccqp pin is 2v in - vd. the v oltage then that is applied to the g ate of the fet is vccqp - vsat, typi- cally around 9v . it is important in the selection of ds1 and ds2 that the y ha v e a lo w forw ard v oltage drop as this directly af fects the re gulator ef cienc y . the other job that ds2 performs is that of bootstrapping vccqp during star - tup. it is possible to cause the output stage to latchup if the vccqp supply is brought up before the other vcc supplies of the RC5033. it is therefore advisable that ds2 be con- nected e v en in applications that do not utilize the bootstrap- ping technique for vccqp . an alternate application could tie the vccqp supply pin to the +12v po wer supply in the pc, thus eliminating the need for c2 and forcing the rdson of m1 e v en lo wer by increasing its vgs. mosfet switches the mosfet switches in the RC5033 applications circuit are n-channel ?ogic-le v el?fets. this means that the y will be fully on with a vgs of 4v . man y manuf acturers mak e logic-le v el fets and the trick is to choose the one with the lo west rdson at the gi v en imax current le v el. the v alue of rdson directly enters into the ef cienc y equation as a po wer loss. also in uencing the ef cienc y is the g ate char ge of the fet and the clock frequenc y of the RC5033. at higher clocking rates the amount of char ge needed to be deli v ered to the fet is going to lo wer the o v erall ef cienc y . in higher current applications, the upper fet can be paralleled to pro- vide greater current capability; ho we v er , the lo wer fet doesn t necessarily ha v e to be doubled since it is on only a fraction of the time that the upper fet is on. pcb layout and grounding as is the case with most analog circuitry , good layout practices are necessary to achie v e the optimum in the o v erall performance of the dc-to-dc con v erter . in general, it is al w ays a good practice to ha v e a tight layout that attempts to minimize short lo w inductance wiring to the RC5033. the use of multilayer pcb is recommended. in particular , it is recommended to ha v e a continuos ground plane beneath the circuit, 2oz copper w ould be preferred in high current applications. as w as stated pre viously , the current-sense resistor , r1, should be located as close to the RC5033 as possible and the ifb and vfb traces should be k elvin con- nected to the pads of r1. t o minimize switching losses and noise, place m1, m2, l and ds2 as close together as possi- ble. also try to k eep the hidr v and lodr v g ate dri v e sig- nal traces as short as possible. it is recommended that the noisy switching part of the circuit be k ept a w ay from the lo w current pins on the chip such as ifb, vfb, adj3, adj1, and cext . k eep the 0.1uf bypass capacitors as close to the chip pins as possible. all of the ground pins should be connected to the ground plane directly under the chip. a sample layout is pro vided in figure 6.
product specification RC5033 14 pr eliminar y infor mation figure 6. sample pcb layout
RC5033 product specification 15 pr eliminar y infor mation mec hanical dimensions ?16-lead soic p ac ka g e a .093 .104 2.35 2.65 symbol inches min. max. min. max. millimeters notes a1 .004 .012 0.10 0.30 .020 0.51 b .013 0.33 c .009 .013 0.23 0.32 e .291 .299 7.40 7.60 e .394 .419 10.00 10.65 .010 .020 0.25 0.51 h .050 bsc 1.27 bsc h l .016 .050 0.40 1.27 0 8 0 8 3 6 5 2 2 n 16 16 a ccc .004 0.10 d .398 .413 10.10 10.50 notes: 1. 2. 3. 4. 5. 6. dimensioning and tolerancing per ansi y14.5m-1982. "d" and "e" do not include mold flash. mold flash or protrusions shall not exceed .010 inch (0.25mm). "l" is the length of terminal for soldering to a substrate. terminal numbers are shown for reference only. "c" dimension does not include solder finish thickness. symbol "n" is the maximum number of terminals. 16 9 1 8 d a a1 ?c ccc c lead coplanarity seating plane e b l h x 45 c a e h
product specification RC5033 pr eliminar y infor mation 10/95 2.5m stock#ds30005033 ?raytheon company 1995 the information contained in this data sheet has been carefully compiled; ho we v er , it shall not by implication or otherwise become part of the terms and conditions of an y subsequent sale. raytheon s liability shall be determined solely by its standard terms and conditions of sale. no representation as to application or use or that the circuits are either licensed or free from patent infringement is intende d or implied. raytheon reserv es the right to change the circuitry and an y other data at an y time without notice and assumes no liability for errors. life support policy: raytheon s products are not designed for use in life support applications, wherein a f ailure or malfunction of the component can reasonably be e xpected to result in personal injury . the user of raytheon components in life support applications assumes all risk of such use and indemni es raytheon compan y ag ainst all damages. raytheon electronics semiconductor division 350 ellis street mountain view ca 94043 650.968.9211 fax 650.966.7742 or dering inf ormation pr oduct number p ac ka g e q j a RC5033m 16 soic 85 c/w

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