may 2016 docid027160 rev 2 1 / 9 this is information on a product in full production. www.st.com esdavlc12 - 1bv2 single line bidirectional tvs diode for esd protection datasheet - production data features ? 01005 package size ? ultra small pcb area: 0.08 mm2 ? bidirectional device ? low capacitance: 7 pf ? minimum breakdown voltage: v br = 12 v ? halogen free and rohs compliant complies with the following standards ? iec 61000 - 4 - 2 level 4 ? 15 kv (air discharge) ? 8 kv (contact discharge) applications where transient overvoltage protection in esd sensitive equipment is required, such as: ? tablet pcs, netbooks and notebooks ? portable multimedia devices and accessories ? digital cameras and camcorders ? communication an d highly integrated systems ? smartphones, mobile phone and accessories description the esdavlc12 - 1bv2 is a bidirectional single line tvs diode designed to protect the data l ines or other i/o ports against esd transients. the device is ideal for applications where both reduced printed circuit board space and high esd protection levels are required. figure 1 : functional diagram s t 0 1 0 0 5
characteristics esdavlc12 - 1bv2 2 / 9 docid027160 rev 2 1 characteristics table 1: absolute ratings (t amb = 25 c) symbol parameter value unit v pp peak pu lse voltage iec 61000 - 4 - 2: contact discharge air discharge 8 15 kv i pp peak pulse current 8/20s 1.5 a t stg storage junction temperature range - 65 to +150 c t j maximum operating junction temperature - 40 to +125 t l maximum temperature for soldering during 10 s 260 c figure 2 : electrical characteristics (definiti ons) table 2: electrical characteristics (t amb = 25 c) symbol test condition min. typ. max. unit v br i r = 1 ma 12 v i rm v rm = 10.5 v 2.5 70 na r d dynamic resistance, 100 ns pulse duration 2 v cl i pp = 1 a; 8/20 s 20 v v cl 8 kv contact dis charge after 30 ns iec 61000 - 4 - 2 33 c line f = 1 mhz, v r = 0 v 7 10 pf
esdavlc12 - 1bv2 characteristics docid027160 rev 2 3 / 9 1.1 characteristics (curves) figure 3 : junction capacitance v ersus applied voltage figure 4 : variation of leakage current versus junction temperature (typical values) figure 5 : esd response to iec 61000 - 4 - 2 (+8 kv contact discharge) figure 6 : esd response to iec 61000 - 4 - 2 ( - 8 kv contact discharge) figure 7 : tlp measurements figure 8 : s21 attenuation measurement result c ( p f ) 0 2 4 6 8 1 0 1 2 7 6 5 4 3 2 1 0 v r ( v ) 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 0 1 2 3 4 5 v r = v r m = 1 0 . 5 v f o r w a r d a n d r e v e r s e i r ( n a ) t j ( c ) f o r w a r d r e v e r s e 1 0 m 3 0 m 1 0 0 m 3 0 0 m 1 g 3 g - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 0 i - o s 2 1 ( d b ) f ( h z ) i p p ( a ) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 l i n e a r ( v o l t a g e f o r w a r d ( v f ) ) l i n e a r ( b r e a k d o w n ( v b r ) ) v c l ( v )
package information esdavlc12 - 1bv2 4 / 9 docid027160 rev 2 2 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and prod uct status are available at: www.st.com . ecopack ? is an st trademark. ? epoxy meets ul 94,v0 ? lead - free package 2.1 st01005 package information figure 9 : st01005 package outline
esdavlc12 - 1bv2 package information docid027160 rev 2 5 / 9 table 3: st01005 package mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.16 0.18 0.20 0.0063 0.0071 0.00 79 b 0.094 0.104 0.114 0.0037 0.0041 0.0045 e 0.17 0.2 0.23 0.0067 0.0078 0.0091 e1 0.154 0.164 0.174 0.0061 0.0065 0.0069 d 0.37 0.40 0.43 0.0146 0.0157 0.0169 d1 0.26 0.6 0.0102 0.0236 fe 0.010 0.018 0.026 0.0004 0.0007 0.0010 fd 0.11 0.125 0.13 0.0043 0.0049 0.0051 figure 10 : footprint recommendations, dimensions in mm (inches) figure 11 : marking layout product marking may be rotated by multiples of 90 for assembly plant differentiati on. in no case should this product marking be used to orient the component for its placement on a pcb. only pin 1 mark is to be used for this purpose. figure 12 : tape and reel specifications b a r i n d i c a t e s p i n 1 u s e r d i r e c t i o n o f u n r e e l i n g a l l d i m e n s i o n s a r e i n m m 4 . 0 0 . 1 4 . 0 0 . 1 2 . 0 0 . 0 5 8 . 0 + 0 . 3 / - 0 . 1 1 . 7 5 0 . 1 3 . 5 0 . 0 5 ? 1 . 5 0 0 . 1 0 . 2 0 0 . 0 3 0 . 2 3 0 . 0 3 0 . 2 0 0 . 2 0 . 4 6 0 . 0 3 v v v v v v 1 7 0 m 1 2 0 m 4 6 0 m 1 7 0 m 7 5 m t o p s i d e s o l d e r m a s k p a d s p i n 1 p i n 2
recommendation on pcb assembly esdavlc12 - 1bv2 6 / 9 docid027160 rev 2 3 recommendation on pcb assembly 3.1 stencil opening design 1. reference design a. stencil opening thickne ss: 75 m figure 13 : stencil opening dimensions figure 14 : recommended stencil window position in mm (inches) 3.2 solder paste 1. halide - free flux qualification rol0 according to ansi/j - std - 004. 2. no clean solder paste is recommended. 3. offers a high tack force to resist component movement during high speed. 4. solder paste with fine particles: powder particle size is 20 - 38 m. l t w 1 0 0 m 1 5 0 m 2 0 0 m s t e n c i l o p e n i n g s t e n c i l t h i c k n e s s : 7 5 m ( 3 m i l s ) u s e o f s o l d e r p a s t e t y p e 4 m a n d a t o r y
esdavlc12 - 1bv2 recommendation on pcb assembly docid027160 rev 2 7 / 9 3.3 placement 1. manual positioning is not recommended. 2. it is recommended to use the lead recognition capabilities of the placement system, not the outline centering 3. standard tole rance of 0.05 mm is recommended. 4. 3.5 n placement force is recommended. too much placement force can lead to squeezed out solder paste and cause solder joints to short. too low placement force can lead to insufficient contact between package and solder pas te that could cause open solder joints or badly centered packages. 5. to improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. for assembly, a perfect supporting of the pcb (all the more on flex ible pcb) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 3.4 pcb design preference 1. to control the solder p aste amount, the closed via is recommended instead of open vias. 2. the position of tracks and open vias in the solder area should be well balanced. a symmetrical layout is recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to so lder flow away. 3.5 reflow profile figure 15 : st ecopack? recommended soldering reflow profile for pcb mounting minimize air convection current s in the reflow oven to avoid component movement. maximum soldering profile corresponds to the latest ipc/jedec j - std - 020.
ordering information esdavlc12 - 1bv2 8 / 9 docid027160 rev 2 4 ordering information figure 16 : ordering information scheme table 4: ordering information order code marking (1) package weight base qty. delivery mode esdavlc12 - 1bv2 v st01005 0.043 mg 20000 tape and reel notes: (1) the marking can be rotated by multiples of 90 to differentiate assembly location 5 revision history table 5: document revision history date revision changes 02 - dec - 2014 1 initial r elease. 23 - may - 2016 2 updated section 9: "recommendation on pcb assembly" and section 8.2: "st01005 package information" .
esdavlc12 - 1bv2 docid027160 rev 2 9 / 9 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time w ithout notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely respons ible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of s t products with provisions different from the information set forth herein shall void any warranty granted by st for such pro duct. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved
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