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this is information on a product in full production. july 2014 docid025558 rev 2 1/13 ESDAVLC8-1BT2Y automotive single-line low capacitance transil?, transient surge voltage suppressor (tvs) for esd protection datasheet ? production data features ? single-line bidirectional protection ? breakdown voltage = 8.5 v min. ? very low capacitance = 4.5 pf at 0 v ? lead-free packages ? ecopack ? 2 compliant component ? aec-q101 qualified benefits ? very low capacitance for optimized data integrity ? very low reverse current < 50 na ? low pcb space consumption: 0.6 mm 2 ? high reliability offered by monolithic integration complies with the following standards: ? iec 61000-4-2 (exceeds level 4) ? 17 kv (air discharge) ? 17 kv (contact discharge) ? iso10605: c = 330 pf, r = 330 ? ? 15 kv (air discharge) ? 8 kv (contact discharge) ? mil std 883g - method 3015-7: class 3 ? hbm (human body model) applications where transient overvoltage protection in esd sensitive equipment is required, such as: ? automotive applications ? computers ? printers ? communication systems ? cellular phone handsets and accessories ? video equipment description the ESDAVLC8-1BT2Y is a bidirectional single- line tvs diode designed to protect data lines or other i/o ports against esd transients. this device is ideal for applications where both printed circuit board space and power absorption capability are required. figure 1. functional diagram tm : transil is a trademark of stmicroelectronics sod882t ESDAVLC8-1BT2Y i/o1 i/o2 www.st.com
characteristics ESDAVLC8-1BT2Y 2/13 docid025558 rev 2 1 characteristics figure 2. electrical characteristics (definitions) table 1. absolute maximum ratings (t amb = 25 c) symbol parameter value unit v pp (1) 1. for a surge greater than the maximum values, the diode will fail in short-circuit. peak pulse voltage iec 61000-4-2 contact discharge iec 61000-4-2 air discharge iso10605 contact discharge iso10605 air discharge mil std 883g - method 3015-7: class 3 17 17 8 15 25 kv p pp (1) peak pulse power dissipation (8/20 s) t j initial = t amb 30 w i pp peak pulse current (8/20 s) 1.3 a t op operating junction temperature range - 50 to + 125 c t stg storage temperature range - 65 to + 125 c t l maximum lead temperature for soldering during 10 s 260 c table 2. electrical characteristics (values, t amb = 25 c) symbol test condition min. typ. max. unit v br from i/o 1 to i/o 2, i r = 1 ma 14.5 17 20 v from i/o 2 to i/o 1, i r = 1 ma 8.5 11 14 i rm v rm = 3 v 50 na c line f = 1 mhz, v r = 0 v 4.5 5.5 pf symbol parameter v = breakdown voltage i = leakage current @ v v = stand-off voltage i = peak pulse current i = breakdown current br rm rm rm pp r v = clamping voltage v triggering voltage = c = input capacitance per line r dynamic resistance = cl trig line d v cl v br v rm i r i pp v i v trig i rm r d
docid025558 rev 2 3/13 ESDAVLC8-1BT2Y characteristics 13 figure 3. peak pulse power versus initial junction temperature (maximum values) figure 4. junction capacitance versus reverse voltage applied (typical values) p pp (w) 0 10 20 30 40 50 0 25 50 75 100 125 150 8/20s t (c) j 0,0 1,0 2,0 3,0 4,0 5,0 6,0 0123 c(pf) f = 1 mhz v = 30 mv osc t = 25 c j v(v) line figure 5. peak pulse power versus exponential pulse duration (maximum values) figure 6. peak pulse power versus exponential pulse duration (maximum values) p pp (w) 1 10 100 1000 1 10 100 1000 t j initial = 25 c t (s) p i/o 1 to i/o 2 p pp (w) 1 10 100 1000 1 10 100 1000 t(s) p t j initial = 25 c i/o 2 to i/o 1 figure 7. clamping voltage versus peak pulse current (maximum values) figure 8. clamping voltage versus peak pulse current (maximum values) 0,1 1 10 19 20 21 22 23 24 v(v) cl i(a) pp 8/20 s t j initial = 25 c i/o 1 to i/o 2 0,1 1 10 13 14 15 16 17 18 19 20 21 22 23 24 i (a) pp 8/20 s t j initial = 25 c i/o 2 to i/o 1 v(v) cl
characteristics ESDAVLC8-1BT2Y 4/13 docid025558 rev 2 figure 9. leakage current versus junction temperature (typical values) figure 10. leakage current versus junction temperature (typical values) 0,01 0,1 1 10 100 25 35 45 55 65 75 85 95 105 115 125 v r =v rm = 3 v i (na) r t (c) j i/o 1 to i/o 2 i (na) r 0,01 0,1 1 10 100 25 35 45 55 65 75 85 95 105 115 125 v r =v rm = 3 v t (c) j i/o 2 to i/o 1 figure 11. s21 attenuation measurement result figure 12. tlp measurements 100k 1m 100m 1g -3 0 -2 5 -2 0 -1 5 -1 0 -5 0 , 100k 1m 100m 1g -3 0 -2 5 -2 0 -1 5 -1 0 -5 0 , f (hz) 10m db i pp (a) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 10 15 20 25 30 35 40 v cl (v) i/o2 to i/o1 i/o1 to i/o2 figure 13. esd response to iso 10605 - c = 150 pf, r = 330 ? (+8 kv contact) figure 14. esd response to iso 10605 - c = 150 pf, r = 330 ? (-8 kv contact) 20 ns/div 10 v/div 20 ns/div 10 v/div
docid025558 rev 2 5/13 ESDAVLC8-1BT2Y characteristics 13 figure 15. response to iso 7637-3 pulse 3a (us = -150 v) figure 16. response to iso 7637-3 pulse 3b (us = +100 v) 50 ns/div 5 v/div 500 ma/div 50 ns/div 500 ma/div 10 v/div
package information ESDAVLC8-1BT2Y 6/13 docid025558 rev 2 2 package information ? epoxy meets ul94, v0 ? lead-free packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 17. sod882t dimension definitions pin # 1 id e d a1 a l1 e l2 b2 b1
docid025558 rev 2 7/13 ESDAVLC8-1BT2Y package information 13 note: product marking may be rotated by multiples of 90 for assembly plant differentiation. in no case should this product marking be used to orient the component for its placement on a pcb. only pin 1 mark is to be used for this purpose. table 3. sod882t dimension values ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.30 0.40 0.012 0.016 a1 0.00 0.05 0.000 0.002 b1 0.45 0.50 0.55 0.018 0.020 0.022 b2 0.45 0.50 0.55 0.018 0.020 0.022 d 0.55 0.60 0.65 0.022 0.024 0.026 e 0.95 1.00 1.05 0.037 0.039 0.041 e 0.60 0.65 0.70 0.024 0.026 0.028 l1 0.20 0.25 0.30 0.008 0.010 0.012 l2 0.20 0.25 0.30 0.008 0.010 0.012 figure 18. sod882t footprint in mm (inches) figure 19. sod882t marking 0.55 (0.022) 0.40 (0.016) 0.50 () 0.020 0.55 (0.022) i/o 1 i/o 2 l
package information ESDAVLC8-1BT2Y 8/13 docid025558 rev 2 figure 20. sod882t tape and reel specifications user direction of unreeling all dimensions in mm 4.0 2.0 8.0 2.0 1.75 3.5 1.50 0.70 0.20 1.15 x x x x x x x 0.47 bar indicates pin 1
docid025558 rev 2 9/13 ESDAVLC8-1BT2Y recommendation on pcb assembly 13 3 recommendation on pcb assembly 3.1 stencil opening design 1. general recommendation on stencil opening design a) stencil opening dimensions: l (length), w (width), t (thickness). figure 21. stencil opening dimensions b) general design rule stencil thickness (t) = 75 ~ 125 m 2. reference design a) stencil opening thickness: 100 m b) stencil opening for central exposed pad: opening to footprint ratio is 50%. c) stencil opening for leads: opening to footprint ratio is 90%. figure 22. recommended stencil window position in mm (inches) l t w aspect ratio w t ----- 1.5 = aspect area lw 2t l w + () --------------------------- - 0.66 = lead footprint on pcb stencil window opening 0.55 (0.022) 0.50 (0.020) 0.40 (0.016) 0.522 (0.021) 0.474 (0.019) 0.014 (0.00055) 0.014 (0.00055) 0.013 (0.00051) 0.013 (0.00051)
recommendation on pcb assembly ESDAVLC8-1BT2Y 10/13 docid025558 rev 2 3.2 solder paste 1. halide-free flux qualification rol0 according to ansi/j-std-004. 2. ?no clean? solder paste is recommended. 3. offers a high tack force to resist component movement during high speed. 4. solder paste with fine particles: powder particle size is 20-45 m. 3.3 placement 1. manual positioning is not recommended. 2. it is recommended to use the lead rec ognition capabilities of th e placement system, not the outline centering. 3. standard tolerance of 0.05 mm is recommended. 4. 3.5 n placement force is recommended. too much placement force can lead to squeezed out solder paste and cause solder joints to short. too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. to improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. for assembly, a perfect supporting of the pcb (all the more on flexible pcb) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 3.4 pcb design preference 1. to control the solder paste amount, the closed via is recommended instead of open vias. 2. the position of tracks a nd open vias in the solder area should be well balanced. the symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
docid025558 rev 2 11/13 ESDAVLC8-1BT2Y recommendation on pcb assembly 13 3.5 reflow profile figure 23. st ecopack ? recommended soldering reflow profile for pcb mounting note: minimize air convection currents in the reflow oven to avoid component movement. 250 0 50 100 150 200 240 210 180 150 120 90 60 30 300 270 - 6c/s 240-245 c 2 - 3 c/s temperature (c) -2 c/s -3 c/s time (s) 0.9 c/s 60 sec (90 max)
ordering information ESDAVLC8-1BT2Y 12/13 docid025558 rev 2 4 ordering information figure 24. ordering information scheme 5 revision history table 4. ordering information order code marking (1) 1. the marking can be rotated by multiples of 90 to differentiate assembly location package weight base qty delivery mode ESDAVLC8-1BT2Y l sod882t 0.81 mg 12000 tape and reel esda vlc 8 - 1 b t2 y esd array very low capacitance breakdown voltage 8 = 8.5 volts min number of lines directional b = bidirectional package t2 = thin sod882 automotive table 5. document revision history date revision changes 09-dec-2013 1 initial release. 15-jul-2014 2 added figure 13 , figure 14 , figure 15 and figure 16 .
docid025558 rev 2 13/13 ESDAVLC8-1BT2Y 13 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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