IRFB9N60A, sihfb9n60a www.vishay.com vishay siliconix s16-0763-rev. d, 02-may-16 1 document number: 91103 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 power mosfet features ? low gate charge q g results in simple drive requirement ? improved gate, avalanche and dynamic dv/dt ruggedness ? fully characterized capacitance and avalanche voltage and current ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 applications ? switch mode power supply (smps) ? uninterruptible power supply ? high speed power switching applicable off line smps topologies ? active clamped forward ?main switch notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. starting t j = 25 c, l = 6.8 mh, r g = 25 ? , i as = 9.2 a (see fig. 12). c. i sd ? 9.2 a, di/dt ? 50 a/s, v dd ? v ds , t j ? 150 c. d. 1.6 mm from case. product summary v ds (v) 600 r ds(on) ( ? )v gs = 10 v 0.75 q g max. (nc) 49 q gs (nc) 13 q gd (nc) 20 configuration single n-channel mo s fet g d s to-220ab g d s available available ordering information package to-220ab lead (pb)-free IRFB9N60Apbf sihfb9n60a-e3 snpb IRFB9N60A sihfb9n60a absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 600 v gate-source voltage v gs 30 continuous drain current v gs at 10 v t c = 25 c i d 9.2 a t c = 100 c 5.8 pulsed drain current a i dm 37 linear derating factor 1.3 w/c single pulse avalanche energy b e as 290 mj repetitive avalanche current a i ar 9.2 a repetitive avalanche energy a e ar 17 mj maximum power dissipation t c = 25 c p d 170 w peak diode recovery dv/dt c dv/dt 5.0 v/ns operating junction and storage temperature range t j , t stg -55 to +150 c soldering recommendations (peak temperature) d for 10 s 300 mounting torque 6-32 or m3 screw 10 lbf in 1.1 n m
IRFB9N60A, sihfb9n60a www.vishay.com vishay siliconix s16-0763-rev. d, 02-may-16 2 document number: 91103 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. pulse width ? 300 s; duty cycle ? 2 %. c. c oss effective is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 % to 80 % v ds . thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -62 c/w case-to-sink, flat, greased surface r thcs 0.50 - maximum junction-to-case (drain) r thjc -0.75 specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 600 - - v v ds temperature coefficient ? v ds /t j reference to 25 c, i d = 1 ma - 660 - mv/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 30 v - - 100 na zero gate voltage drain current i dss v ds = 600 v, v gs = 0 v - - 25 a v ds = 480 v, v gs = 0 v, t j = 125 c - - 250 drain-source on-sta te resistance r ds(on) v gs = 10 v i d = 5.5 a b - - 0.75 ? forward transconductance g fs v ds = 50 v, i d = 5.5 a 5.5 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 1400 - pf output capacitance c oss - 180 - reverse transfer capacitance c rss -7.1- output capacitance c oss v gs = 0 v v ds = 1.0 v, f = 1.0 mhz - 1957 - v ds = 480 v, f = 1.0 mhz - 49 - effective output capacitance c oss eff. v ds = 0 v to 480 v - 96 - total gate charge q g v gs = 10 v i d = 9.2 a, v ds = 400 v see fig. 6 and 13 b --49 nc gate-source charge q gs --13 gate-drain charge q gd --20 turn-on delay time t d(on) v dd = 300 v, i d = 9.2 a r g = 9.1 ? , r d = 35.5 ? , see fig. 10 b -13- ns rise time t r -25- turn-off delay time t d(off) -30- fall time t f -22- gate input resistance r g f = 1 mhz, open drain 0.5 - 3.2 ? drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the ? integral reverse ? p - n junction diode --9.2 a pulsed diode forward current a i sm --37 body diode voltage v sd t j = 25 c, i s = 9.2 a, v gs = 0 v b --1.5v body diode reverse recovery time t rr t j = 25 c, i f = 9.2 a, di/dt = 100 a/s b - 530 800 ns body diode reverse recovery charge q rr -3.04.4c forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) s d g
IRFB9N60A, sihfb9n60a www.vishay.com vishay siliconix s16-0763-rev. d, 02-may-16 3 document number: 91103 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-r esistance vs. temperature 0.1 1 10 100 0.1 1 10 100 20s pulse width t = 25 c j top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.7v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.7v 1 10 100 1 10 100 20s pulse width t = 150 c j top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.7v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.7v 0.1 1 10 100 4.0 5.0 6.0 7.0 8.0 9.0 10.0 v = 50v 20s pulse width ds v , gate-to-source voltage (v) i , drain-to-source current (a) gs d t = 25 c j t = 150 c j -60 -40 -20 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 3.0 t , junction temperature ( c) r , drain-to-source on resistance (normalized) j ds(on) v = i = gs d 10v 9.2a
IRFB9N60A, sihfb9n60a www.vishay.com vishay siliconix s16-0763-rev. d, 02-may-16 4 document number: 91103 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area 1 10 100 1000 10000 100000 1 10 100 1000 c, capacitance (pf) ds v , drain-to-source voltage (v) a v = 0v, f = 1mhz c = c + c , c shorted c = c c = c + c gs iss gs gd ds rss gd oss ds gd c iss c oss c rss 0 10 20 30 40 50 0 4 8 12 16 20 q , total gate charge (nc) v , gate-to-source voltage (v) g gs for test circuit see figure i = d 13 9.2a v = 120v ds v = 300v ds v = 480v ds 400v 0.1 1 10 100 0.2 0.5 0.7 1.0 1.2 v ,source-to-drain voltage (v) i , reverse drain current (a) sd sd v = 0 v gs t = 25 c j t = 150 c j 0.1 1 10 100 1000 10 100 1000 10000 operation in this area limited by r ds(on) single pulse t t = 150 c = 25 c j c v , drain-to-source voltage (v) i , drain current (a) i , drain current (a) ds d 10us 100us 1ms 10ms
IRFB9N60A, sihfb9n60a www.vishay.com vishay siliconix s16-0763-rev. d, 02-may-16 5 document number: 91103 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 9 - maximum drain curre nt vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case 25 50 75 100 125 150 0.0 2.0 4.0 6.0 8.0 10.0 t , case temperature ( c) i , drain current (a) c d v ds pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10v + - v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (s) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response)
IRFB9N60A, sihfb9n60a www.vishay.com vishay siliconix s16-0763-rev. d, 02-may-16 6 document number: 91103 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate ch arge test circuit r g i as 0.01 w t p d.u.t. l v ds + - v dd driver a 15 v 20 v t p v ds i as 25 50 75 100 125 150 0 100 200 300 400 500 600 starting t , junction temperature ( c) e , single pulse avalanche energy (mj) j as i d top bottom 4.1a 5.8a 9.2a q g q gs q gd v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
IRFB9N60A, sihfb9n60a www.vishay.com vishay siliconix s16-0763-rev. d, 02-may-16 7 document number: 91103 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 14 - for n-channel ? ? ? ? ? ? ? ? ? vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91103 . p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd
package information www.vishay.com vishay siliconix revison: 14-dec-15 1 document number: 66542 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 to-220-1 note ? m* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for hvm m * 3 2 1 l l(1) d h(1) q ? p a f j(1) b(1) e(1) e e b c dim. millimeters inches min. max. min. max. a 4.24 4.65 0.167 0.183 b 0.69 1.02 0.027 0.040 b(1) 1.14 1.78 0.045 0.070 c 0.36 0.61 0.014 0.024 d 14.33 15.85 0.564 0.624 e 9.96 10.52 0.392 0.414 e 2.41 2.67 0.095 0.105 e(1) 4.88 5.28 0.192 0.208 f 1.14 1.40 0.045 0.055 h(1) 6.10 6.71 0.240 0.264 j(1) 2.41 2.92 0.095 0.115 l 13.36 14.40 0.526 0.567 l(1) 3.33 4.04 0.131 0.159 ? p 3.53 3.94 0.139 0.155 q 2.54 3.00 0.100 0.118 ecn: x15-0364-rev. c, 14-dec-15 dwg: 6031 package picture a s e xian
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