ds06-20208-3e fujitsu semiconductor data sheet copyright?2002-2006 fujitsu limited all rights reserved semicustom cmos standard cell array CS91 series description the CS91 series 0.11 m cmos standard cell is a line of highly integrated cmos asics featuring high speed and low power consumption. this series incorporates up to 48 million gates which have a gate delay time of 16 ps, resulting in both integration and speed about three times higher than conventional products. features ? technology : 0.11 m silicon-gate cmos, 5- to 8-layer wiring (copper is used as wire material.) , low-k (2.7) inter-layer material (inter-lay er material that has low permittivity) support for high speed, high integrati on, low leak internal cell set. capabl e of incorporating on the same chip. supply voltage : + 1.2 v 0.1 v (standard specification) junction temperature range : ? 40 c to + 125 c gate delay time : t pd = 16 ps (1.2 v, inverter, f/o = 1) gate power consumption : pd = 6.6 nw/mhz/bc (1.2 v, inverter, f/o = 1) support for ultra high speed (622 mbps to 780 mbps, 2.5 gbps to 3.125 gbps, 10 gbps) interface macros for transmission special interfaces* : p-cml, lvds, pci, sstl, hstl, t-lvttl, and others. buffer cell dedicated to crystal oscillator ip macros* : cpu (arm9, arm7tdmi) , dsp, pci, ieee1394, usb, irda, pll, adc, dac, and others. compiled cells (ram/rom/multiplier, and others.) uses industry standard tools and supports the optimum tools for the application short-term development usi ng a physical prototyping tool hierarchical design environment for supporting large-scale circuits support for signal integrity, emi noise reduction support for high resolution rc extrac tion base delay calculation environment support for optimization environment of power supply wire (continued)
CS91 series 2 (continued) support for static timing sign off support for memory (ram/rom) bist support for boundary scan support for logic bist a variety of package options* : fcbga ( 2116 pin max) , ebga, fbga, and others. * : including items under development. macro library (including macros being prepared) 1. logic cells (about 400 types) 2. ip macros 3. special i/o interface macros adder decoder and-or inverter non-scan flip flop clock buffer inverter latch buffer nand or-and inverter and or nor selector scan flip flop eor enor others and-or cpu/dsp arm9, arm7tdmi, communications dsp, dsp for av ultra high speed i/f macros 622 mbps to 780 mbps, 2.5 gbps to 3.125 gbps, 10 gbps interface macros pci, ieee1394, usb, irda, etc. multimedia processing macros jpeg, mpeg, etc. mixed signal macros adc, dac, opamp, etc. compiled macros ram, rom, multiplier, adder, multiplier-accumulator, etc. pll analog pll, digital pll t-lvttl sstl hstl p-cml lvds pci usb
CS91 series 3 compiled cells compiled cells are macro cells which are automatically gener ated with the bit/word co nfiguration specified. the CS91 series has the following types of compiled cells. (note that each macro is different in word/bit range depending on the column type.) 1. clock synchronous single-port ram (1 address : 1 rw) 2. clock synchronous dual-port ram (2 addresses : 2 rw) 3. clock synchronous rom 4. high-capacity memory type of clock synchronous single port ram ( 1 address : 1 rw ) column type memory capacity word range bit range unit 4 32 to 128 k 16 to 1 k 2 to 128 bit 16 2176 to 288 k 1088 to 8 k 2 to 36 bit column type memory capacity word range bit range unit 4 32 to 288 k 16 to 2 k 2 to 144 bit 16 128 to 288 k 64 to 8 k 2 to 36 bit column type memory capacity word range bit range unit 16 256 to 1 m 128 to 8 k 2 to 128 bit 64 1024 to 1 m 512 to 32 k 2 to 32 bit column type memory capacity word range bit range unit 32 16 k to 4 m 8 k to 32 k 2 to 128 bit
CS91 series 4 absolute maximum ratings *1 : values are determined separately for lvds, etc. *2 : maximum output current wh ich can be supplied constantly. warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. (v ss = 0 v) parameter symbol application rating unit min max power supply voltage v dd v ddi (internal) ? 0.5 + 1.8 v v dde (external 2.5 v) ? 0.5 + 3.6 v v dde (external 3.3 v) ? 0.5 + 4.0 v input voltage *1 v i 1.2 v ? 0.5 v ddi + 0.5 ( 1.8 v) v 2.5 v ? 0.5 v dde + 0.5 ( 3.6 v) v 3.3 v ? 0.5 v dde + 0.5 ( 4.0 v) v output voltage v o 1.2 v ? 0.5 v ddi + 0.5 ( 1.8 v) v 2.5 v ? 0.5 v dde + 0.5 ( 3.6 v) v 3.3 v ? 0.5 v dde + 0.5 ( 4.0 v) v storage temperature t st plastic package ? 55 + 125 c output current *2 i o l type simultaneous switching noise : minimum, delay : long ? 25 ma m type simultaneous switching noise : small, delay : middle ? 25 ma h type simultaneous switching noise : middle, delay : short ? 25 ma
CS91 series 5 recommended operating conditions single power supply ( v dd = 1.2 v 0.1 v ) dual power supply ( v dde = 3.3 v 0.3 v, v ddi = 1.2 v 0.1 v ) dual power supply ( v dde = 2.5 v 0.2 v, v ddi = 1.2 v 0.1 v ) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electr ical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. (v ss = 0 v) parameter symbol value unit min typ max power supply voltage v dd 1.1 1.2 1.3 v ?h? level input voltage v ih v dd 0.7 ? v dd + 0.3 v ?l? level input voltage v il ? 0.3 ? v dd 0.3 v junction temperature t j ? 40 ?+ 125 c (v ss = 0 v) parameter symbol value unit min typ max power supply voltage 3.3 v supply voltage v dde 3.0 3.3 3.6 v 1.2 v supply voltage v ddi 1.1 1.2 1.3 v ?h? level input voltage 3.3 v cmos level v ih 2.0 ? v dde + 0.3 v 1.2 v cmos level v ddi 0.7 ? v ddi + 0.3 v ?l? level input voltage 3.3 v cmos level v il ? 0.3 ?+ 0.8 v 1.2 v cmos level ? 0.3 ? v ddi 0.3 v junction temperature t j ? 40 ?+ 125 c (v ss = 0 v) parameter symbol value unit min typ max power supply voltage 2.5 v supply voltage v dde 2.3 2.5 2.7 v 1.2 v supply voltage v ddi 1.1 1.2 1.3 v ?h? level input voltage 2.5 v cmos level v ih 1.7 ? v dde + 0.3 v 1.2 v cmos level v ddi 0.7 ? v ddi + 0.3 v ?l? level input voltage 2.5 v cmos level v il ? 0.3 ?+ 0.7 v 1.2 v cmos level ? 0.3 ? v ddi 0.3 v junction temperature t j ? 40 ?+ 125 c
CS91 series 6 electrical characteristics single power supply : v dd = 1.2 v (v dd = 1.2 v 0.1 v, v ss = 0 v, t j = ? 40 c to + 125 c) * : the input leakage current may exceed the above value when the input buffer with pull-up/pull-down resistor is used. dual power supply : v dde = 3.3 v, v ddi = 1.2 v (v dde = 3.3 v 0.3 v, v ddi = 1.2 v 0.1 v, v ss = 0 v, t j = ? 40 c to + 125 c) * : the input leakage current may exceed the above value when the input buffer with pull-up/pull-down resistor is used. parameter symbol condition value unit min typ max ?h? level output voltage v oh i oh = ? 100 av dd ? 0.2 ? v dd v ?l? level output voltage v ol i ol = 100 a0 ? 0.2 v input leakage current* i l ??? 10 a pull-up/pull-down resistance r p pull-up : v il = 0 pull-down : v ih = v dd ? 12 ? k ? parameter symbol condition value unit min typ max ?h? level output voltage v oh4 i oh = ? 100 av dde ? 0.2 ? v dde v v oh2 i oh = ? 100 av ddi ? 0.2 ? v ddi v ?l? level output voltage v ol4 i ol = 100 a0 ? 0.2 v v ol2 i ol = 100 a0 ? 0.2 v input leakage current* i l ??? 10 a pull-up/pull-down resistance r p 3.3 v pull-up : v i = 0 pull-down : v i = v dde 15 33 70 k ? 1.2 v pull-up : v i = 0 pull-down : v i = v ddi ? 12 ? k ?
CS91 series 7 dual power supply : v dde = + 2.5 v, v ddi = + 1.2 v (v dde = 2.5 v 0.2 v, v ddi = 1.2 v 0.1 v, v ss = 0 v, t j = ? 40 c to + 125 c) * : the input leakage current may exceed the above value when the input buffer with pull-up/pull-down resistor is used. ac characteristics *1 : delay time = propagation delay time, enable time, disable time *2 : ?typ? is calculated fr om the cell specification. *3 : measurement conditions note : reference values. the va lues according to the cell. parameter symbol condition value unit min typ max ?h? level output voltage v oh3 i oh = ? 100 a v dde ? 0.2 ? v dde v v oh2 i oh = ? 100 av ddi ? 0.2 ? v ddi v ?l? level output voltage v ol3 i ol = 100 a0 ? 0.2 v v ol2 i ol = 100 a0 ? 0.2 v input leakage current* i l ??? 10 a pull-up/pull-down resistance r p 2.5 v pull-up : v i = 0 pull-down : v i = v dde ? 25 ? k ? 1.2 v pull-up : v i = 0 pull-down : v i = v ddi ? 12 ? k ? parameter symbol rating unit min typ max delay time t pd * 1 typ* 2 tmin* 3 typ* 2 ttyp* 3 typ* 2 tmax* 3 ns measurement condition t min t typ t max v dd = 1.2 v 0.1 v, v ss = 0 v, t j = ? 40 c to + 125 c0.651.001.66
CS91 series 8 input/output pin capacitance (f = 1 mhz, v dd = v di = 0 v, t j = + 25 c) note : capacitance values according to the package and the location of the pin. design method fujitsu?s reference design flow provides the following functions that shorten the development time of large scale and high quality lsis. high reliability design estimation in the early stage of physical design realized by physical prototyping. layout synthesis with optimized timing realized by physical synthesis tools. high accuracy design environment considering drop in power supply voltage, signal noise, delay penalty, and crosstalk. i/o design environment (power line design, assignment and selection of i/os, pack age selection) considering noise. packages a variety of package types development of chips with narrow-pitch solder bump technology and high-pin co unt packages enables users to respond to the high-pin count, high -speed requirements of the network market. a variety of packages from existing series are also available for smoot h transition from previously developed models. contact your fujitsu represent ative for availability dates. fcbga package : maximum 2116 pins ebga package : maximum 672 pins fbga package : maximum 304 pins qfp package : maximum 304 pins parameter symbol value unit input pin c in 16 max pf output pin c out 16 max pf input/output pin c i/o 16 max pf
CS91 series f0609 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. edited business promotion dept.
|
