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| technical note single-chip built-in fet type switching regulator series simple step-down switching regulator with integrated compensation bd9322efj, BD9323EFJ, bd9324efj z description the bd9322efj, BD9323EFJ and bd9324efj are step-down regulators that integrate a low resistance high side n-channel mosfet. it achieves 2a / 3a / 4a continuous output current over a wide input supply range. current mode operation provides fast transie nt response and easy phase compensation. z features 1) wide operating input range 4.75v 18v 2) selectable 2a / 3a / 4a output current 3) selectable 0.1 / 0.15 internal mosfet switch 4) low esr output ceramic capacitors are available 5) low stanby current during shutdown mode 6) 380khz operating frequency 7) feedback voltage 0.9v 1.5% accuracy 8) protection circuit: undervoltage lockout protection circuit thermal shutdown circuit overcurrent protection circuit 9) htsop-j8 package (with exposed thermal pad) z applications distributed power system pre-regulator for linear regulator z absolute maximum ratings (ta = 25 c ) parameter symbol rating unit supply voltage v in 20 v switch voltage v sw 20 v power dissipation for htsop-j8 pd 3760* mw operating temperature range topr -40 +85 storage temperature range ts t g - 5 5 +150 junction temperature tjmax 150 bst voltage v bst v sw +7 v all other pins v oth 7 v * derating in done 30.08 mw/ for operating above ta R 25 (mount on 4-layer 70.0mm 70.0mm 1.6mm board) apr.2008
2/13 operation range(ta= -40 85 ) parameter symbol min typ max unit supply voltage v in 4.75 12 18 v output current for bd9322efj i sw2 2** a output current for BD9323EFJ i sw3 3** a output current for bd9324efj i sw4 4** a ** pd, aso should not be exceeded electrical characteristics (unle ss otherwise specified vin=12v ta=25 ) parameter symbol limits unit conditions min typ max error amplifier block fb input bias current i fb - 0.1 2 a feedback voltage v fb 0.886 0.900 0.914 v voltage follower sw block ? sw hi-side fet on-resistance for bd9322efj r on2 - 0.15 - i sw = -0.8a *** hi-side fet on-resistance for BD9323EFJ r on3 - 0.10 - i sw = -0.8a *** hi-side fet on-resistance for bd9324efj r on4 - 0.10 - i sw = -0.8a *** lo-side fet on-resistance r onl - 10 - i sw = 0.1a leak current n-channel i leakn - 0 10 a v in = 18v , v sw = 0v switch current limit for bd9322efj i limit2 2.5 - - a *** switch current limit for BD9323EFJ i limit3 3.5 - - a *** switch current limit for bd9324efj i limit4 4.5 - - a *** maximum duty cycle m duty - 90 - % v fb = 0v general enable pull-up current i en 12 23 34 a v en = 0v enable threshold voltage v en 0.4 0.63 0.9 v under voltage lockout threshold v uvlo 4.05 4.40 4.75 v v in rising under voltage lockout hysteresis v hys - 0.1 - v soft start current i ss 23 41 62 ua v ss = 0.1 v soft start time t ss - 1.6 - ms c ss = 0.1 uf operating frequency f osc 300 380 460 khz circuit current i cc - 2.1 4.3 ma v fb = 1.5v, v en = open quiescent current i qui - 100 190 a v en = 0v *** see the series line-up table below. series line-up table line-up bd9322efj BD9323EFJ bd9324efj fet on-resistance 0.15 0.10 0.10 output current 2.0 a 3.0a 4.0 a 3/13 block diagram typical application circuit open automatic startup en fb vref tsd uvlo ibias err softstart slope pwm vreg osc 5v lvs gnd sw vin bst ss vin s drv logic r comp lvs ocp output 12v r_pc 15k en vin bst sw ss comp fb gnd fb r_dw r_up 10 h c_vc1 10 f sw d vin 12v c_pc1 3300pf 10 k 27k vout 3.33v c_ss 0.1 f l c_co1 20 f c_bs 0.1 f thermal pad 4/13 z block operation ? vreg a block to generate constant-voltage for dc/dc boosting. ? vref a block that generates internal reference voltage of 2.9 v (typ.). ? tsd/uvlo tsd (thermal shutdown)/uvlo (under voltage lockout) prot ection block. the tsd circuit shuts down ic at 175 (typ.) the uvlo circuit shuts down the ic when the vcc is low voltage. ? error amp block (err) this is the circuit to compare the reference voltage and the f eedback voltage of output voltage. the comp pin voltage resulting from this comparison determines the switching duty. at the time of startup, since the soft start is operated by the ss pin volt age, the comp pin voltage is limited to the ss pin voltage. ? oscillator block (osc) this block generates the oscillating frequency. ? slope block this block generates the triangular waveform from the clock cr eated by osc. generated triangular waveform is sent to the pwm comparator. ? pwm block the comp pin voltage output by the error amp is compared to the slope block's triangul ar waveform to determine the switching duty. since the switching duty is limited by the maximum duty ratio which is determined internally, it does not becom e 100%. ? drv block a dc/dc driver block. a signal from the pwm is input to drive the power fets. ? current sense current flowing to the power fet is detected by voltage at the current sense and the overcu rrent protection operates at 2.5/3.5/4.5a (min.). w hen the overcurrent protection operates, switchi ng is turned off and the ss pin capacitance is discharged. ? delay start a start delay circuit for positive/negative charge pump and boost converter. ? soft start circuit since the output voltage rises gradually while restricting the curr ent at the time of startup, it is possible to prevent the ou tput voltage overshoot or the rush current. 5/13 z physical dimension z pin assignment and pin function pin no. pin name function 1 ss soft start control input 2 bst high-side gate drive boost input 3 vin power input 4 sw power switching output 5 gnd ground 6 fb feed back input 7 comp compensation node 8 en enable input fig htsop-j8 package (unit:mm) +0.05 -0.03 4.9 0.1 (max5.25 include.burr) (3.2) (2.4) 6.0 0.2 3.9 0.1 0.545 1pin mark 8 7 6 5 4 3 2 1 1.05 0.2 0.17 1.27 0.42 -0.04 +0.05 0.85 0.05 1.0max -4 +6 s 0.08 0.08 s m +0.05 -0.03 0.65 0.15 0.08 0.08 4 6/13 z typical performance characteristics (unle ss otherwise specified, vin= 12v ta = 25 ) fig. circuit current 0.85 0.86 0.87 0.88 0.89 0.9 0.91 0.92 0.93 0.94 0.95 -40-20 0 20406080 temperature : [c] feedback voltage [v] fig. quiescent current fig. input bias current fig. feedback voltage fig. hi-side on-resistance 0 0.05 0.1 0.15 0.2 0.25 -40 -20 0 20 40 60 80 ta [ ] ron [ ] 330 340 350 360 370 380 390 -40 -20 0 20 40 60 80 temperature : [c] operating frequency [khz] fig. operating frequency 50 55 60 65 70 75 80 85 90 95 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 iout [a] efficiency [%] fig. step down efficiency (vin= 12v v out = 3.3v l= 22uh) v out v sw v ss i out fig. overcurrent protection (v out is shorted to gnd) 0.01 0.1 1 10 100 0.001 0.01 0.1 1 c ss [uf] softstart time [ms] fig. soft start time bd9322efj bd9323/24efj v out = 5.0v v out = 3.3v 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 4 6 8 1012141618 vin : [v] icc [ma] 0 20 40 60 80 100 120 140 160 180 200 4 6 8 10 12 14 16 18 vin : [v] icc [ua] -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0 0.5 1 1.5 2 v fb [v] ifb [ua] 7/13 fig. transient response (vin= 12v v out = 3.3v l= 10uh cout =22uf iout= 0.2-1.0a ) fig. output ripple voltage (vin= 12v v out = 3.3v l= 10uh cout =22uf i out= 1.0a ) fig. transient response (vin= 12v v out = 3.3v l= 10uh cout =22uf iout= 0.2-3.0a) fig. output ripple voltage (vin= 12v v out = 3.v l= 10uh cout =22uf io=3.0a ) i out v out v out v out i out en v out : 200 mv / div i out : 1.0 a / div v out : 10.0 mv / div i out : 1.0 a / div i out v out : 10.0 mv / div i out : 1.0 a / div :29.8 mv : 20.8 mv v out - max : +520mv v out - min : -240mv v out i out i out : 1.0 a / div v out - max : +120mv v out - min : -100m v fig. start up waveform (vin= 12v v out = 3.3v l= 22uh c ss = 0.1uf iout= 0a) v out : 100 mv / div v out : 1.0v / div i out : 1.0a / div i out v out 8/13 z selecting application components (1) output lc constant (buck converter) the inductance l to use for output is decided by the rated current i lr and input current maximum value i omax of the inductance. fig. fig. adjust so that i omax + ? i l does not reach the rated current value i lr . at this time, ? i l can be obtained by the following equation. ? i l = 1 (vcc - vo) vo 1 l vcc f set with sufficient margin because the induct ance l value may have the dispersion of 30%. for the capacitor c to use for the output, select the capa citor which has the larger value in the ripple voltage v pp permissible value and the drop voltage permissible value at the time of sudden load change. output ripple voltage is decid ed by the following equation. perform setting so that the voltage is within the permissible ripple voltage range. for the drop voltage v dr during sudden load change, please perform the rough calculation by the following equation. v dr = ? i 10 sec [v] co however, 10 sec is the rough calculation val ue of the dc/dc response speed. make co settings so that these two va lues will be within the limit values. ? v pp = ? i l r esr + ? i l vo 1 [v] 2co vcc f [a] il t ilr i omax + vo l vcc i l co 9/13 (2)loop compensation choosing compensation capacitor c 1 and resistor r 3 the example of dc/dc converter application bode plot is shown below. the compensation resistor r 3 will set the cross over frequency f c that decides the stability and response speed of dc/dc converter. so compensation resistor r 3 has to be adjusted to adequate value for good stability and response speed. the cross over frequency f c can be adjusted by changing the compensation resistor r 3 connected to comp terminal. the higher cross over frequency achieves good response speed, bu t less stability. and the lower cross over frequency shows good stability, but worse response speed. usually, the 1/10 of dc/dc converter operating frequency is used for cross over frequency f c . so please decide the compensation resistor and capacitor using the following formula on setting f c to 1/10 of operating frequency at first. after that, please measure and adjust the cross over frequency on your set (on the actual application) to meet the enough respo nse speed and phase-margin. ( i ) choosing phase compensation resistor r 3 please decide the compensation resistor r 3 on following formula. where c out output capacitor connected to dc/dc output v out output voltage f c desired cross over frequency (38khz) ( ii ) choosing phase compensation capacitor c 1 the stability of dc/dc converter needs to cancel the phase delay that is from output lc filter by inserting the phase advance. the phase advance can be added by the zero on compensation resistor and capacitor. the lc resonant frequency f lc and the zero on compensation resistor and capacitor are expressed below. please choose c1 to make f z to 1 / 3 of f lc . ( iii ) the condition of the loop compensation stability the stability of dc/dc converter is important. to secure the operating stability, please check the loop compensation has the en ough phase-margin. for the condition of loop compensation stability, the phase-delay must be less than 150 degree where gain is 0 db . namely over 30 degree phase-margin is needed. lastly after the calculation above, please measure and adjust the phase-margin to secure over 30 degree. compensation resistor r 3 = 5800 c out f c v out [ohm] lc resonant frequency f lc = 1 [hz] 2 lc out zero by c 1 and r 3 f z = 1 [hz] 2 c 1 r 3 compensation capacitor c 1 = 3 [f] 2 f lc r 3 phase margin 180 90 180 90 0 0 a (a) gbw(b) f f gain [db] phase f c v out r1 r2 c1 comp r3 fb 10/13 (3) design of feedback resistance constant set the feedback resistance as shown below. z soft start function the buck converter has an adjustable s oftstart function to prevent high inrush current during start up. the soft-start time is set by the extern al capacitor connected to ss pin. the soft start time is given by; please confirm the overshoot of the output voltage and inrush current when deciding the ss capacitor value. z en function the en terminal controls ic?s shut down. leaving en terminal open, makes ic start up automatically. to shut down the ic, the external component has to pull the current from en terminal and make the en voltage low. the en threshold voltage is 0.63v (typ.). the equivalent internal circuit. ex) the example of en driving circuit. v out = r1+r2 0.900 [v] r2 t ss = 16200 c ss [s] v out r 1 r2 err feedback volta g e 0.900v fb c ss ss 2.9v(typ) + - comp 70k (typ) erramp en vin vin 11/13 z layout pattern consideration two high pulsing current flowing loops exist in the buck regulator system. the first loop, when fet is on, starts from the input capacito rs, to the vin terminal, to the sw terminal, to the inductor, to the output capacitors, and then returns to the input capacitor through gnd. the second loop, when fet is off, starts from the shotkey diod e, to the inductor, to the output capacitor, and then returns to the shotkey diode through gnd. to reduce the noise and improve the efficiency, please minimize these two loop area. especially input capacitor, output capacitor and s hotkey diode should be connected to gnd plain. pcb layout may affect the thermal perfo rmance, noise and efficiency greatly. so please take extra care when designing pcb layout patterns. ? the thermal pad on the back side of ic has the great thermal conduction to the chip. so using the gnd plain as broad and wide as possible can help thermal dissipation. and a lot of thermal via for helping the spread of heat to the different layer is also effective. ? the input capacitors should be connected as close as possible to the vin terminal. ? keep sensitive signal traces such as trace connected fb and comp away from sw pin. ? the inductor, the shot key diode and the output capacitors should be placed close to sw pin as much as possible. c in fet di c out l v out vin 2 current loop in buck regulator system the example of pcb layout pattern ss bst vin sw gnd fb comp en c in c out l di fet vin sw v out 12/13 z operation notes 1) absolute maximum ratings use of the ic in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in ic damage. assumptions should not be made regarding the state of the ic (s hort mode or open mode) when such damage is suffered. a physical safety measure such as a fuse should be implemented when use of the ic in a special mode where the absolute maximum ratings may be exc eeded is anticipated. 2) gnd potential ensure a minimum gnd pin potenti al in all operating conditions. 3) setting of heat use a thermal design that allows for a sufficient margin in li ght of the power dissipation (pd) in actual operating conditions. 4) pin short and mistake fitting use caution when orienting and positioning the ic for mounting on printed circuit boards. improper mounting may result in damag e to the ic. shorts between output pins or between output pins and the power supply a nd gnd pins caused by the presenc e of a foreign object may res ult in damage to the ic. 5) actions in strong magnetic field use caution when using the ic in the presence of a strong magnetic field as doi ng so may cause the ic to malfunction. 6) testing on application boards when testing the ic on an application board, connecting a capacitor to a pin with low impedance subjects the ic to stress. alwa ys discharge capacitors after each process or step. ground the ic during a ssembly steps as an antistatic measure, and use similar caution wh en transporting or storing the ic. always turn the ic's power supply off before connec ting it to or removing it from a jig or fixture during the i nspection process. 7) ground wiring patterns when using both small signal and large current gnd patterns, it is recommended to isolate the two ground patterns, placing a si ngle ground point at the application's reference point so that the pattern wiri ng resistance and voltage variations caused by large currents do n ot cause variations in the small signal ground voltage. be careful not to change the gnd wiring patterns of any external components. 8) regarding input pin of the ic this monolithic ic contains p+ isolation and p substrate layers between adjacent element s in order to keep them isolated. p/n j unctions are formed at the intersection of these p layers with the n layers of other elements to create a variety of parasitic elements. for example, when the resistors and transisto rs are connected to the pins as shown in fig. , a parasitic diode or a transistor operates by inverting the pin voltage and gnd voltage. the formation of parasitic elements as a result of the relationshi ps of the potentials of different pins is an inevitable resul t of the ic's architecture. the operation of parasitic elements can caus e interference with circuit operation as we ll as ic malfunction and damage. for the se reasons, it is necessary to use caution so that the ic is not used in a way t hat will trigger the operation of parasitic elements such as by t he application of voltages lower than the gnd (p substrate) voltage to input and output pins. fig. example of a simple monolithic ic architecture 9) overcurrent protection circuits an overcurrent protection circui t designed according to the output current is incorporated for the prevention of ic damage that may result in the event of load shorting. this protection circuit is effective in preventing damage due to sudden and unexpected accidents. howev er, the ic should not be used in applications char acterized by the continuous operation or transiti oning of the protection circuits. at the time of thermal designing, keep in mind that the current capacity has negative characteristics to temperatures. 10) thermal shutdown circuit (tsd) this ic incorporates a built-in tsd circui t for the protection from thermal destructi on. the ic should be used within the speci fied power dissipation range. however, in the event that the ic continues to be oper ated in excess of its power dissipation limits, the attendant rise in the chip's junction temperature tj will trigger the tsd circuit to turn off all output power elements. operation of t he tsd circuit presumes that t he ic's absolute maximum ratings have been exceeded. application designs should never make use of the tsd circuit. (pin a) gnd n p n n p+ p+ resistor parasitic elements p parasitic elements ( pin b ) gnd c b e parasitic elements gnd ( pin a ) gnd n p n n p+ p+ parasitic elements p substrate ( pin b ) c b e transistor (npn) n gnd 13/13 z i/o equivalent circuit diagram fig. 1.ss 2.bst 4.sw 6.fb 7.comp 8.en z power dissipation vin vin sw reg vin vin vin vin vin on 70 70 1.6 mm glass epoxy pcb (1) 1-layer board (backside copper foil area 0 mm 0 mm) (2) 2-layer board (backside copper foil area 15 mm 15 mm) (3) 2-layer board (backside copper foil area 70 mm 70 mm) (4) 4-layer board (backside copper foil area 70 mm 70 mm) 150 0 50 75 100 125 2000 4000 1000 3000 25 power dissipation: pd [mw] ambient temperature: ta [c] (1)820mw (2)1100mw (3)2110mw (4)3760mw 0 notes no technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of rohm co.,ltd. the contents described herein are subject to change without notice. the specifications for the product described in this document are for reference only. upon actual use, therefore, please request that specifications to be separately delivered. application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. rohm co.,ltd. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by rohm co., ltd. is granted to any such buyer. products listed in this document are no antiradiation design. appendix1-rev2.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / europe / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2008 rohm co.,ltd. the products listed in this document are designed to be used with ordinary electronic equipment or de vices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. it is our top priority to supply products with the utmost quality and reliability. however, there is always a chance of failure due to unexpected factors. therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. rohm cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the notes specified in this catalog. 21 saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix |
Price & Availability of BD9323EFJ
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