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tw2 809c multichannel h.264 audio/video codec fn7875 rev. 1.00 page 1 of 130 february 27, 2014 fn7875 rev. 1.00 february 27, 2014 datasheet features tw2809c is a high performance and cost effective multi - channel h.264 codec solution design ed for security surveillance market. it is capable of encoding and decoding maximum 8 channels standard definition (sd) video in real time. it can do high d efinition (hd) 1080x60i encode or decode at real time too. each video channel can be independently controlled in terms of encode / decode mode, frame rate, bit rate, and resolution. tw2809c is a n ideal h.264 codec candidate for different dvr p latforms such as 16ch sd or 16ch cif . video feature s ? real time full - duplex video codec compliant to h.264 main profile standard ? support s real time full duplex 9 channel sd encode and /or decode ? support s cif jpeg or h.264 network stream en code ? supports cbr and vbr ? four video input por ts compliant to bt.656 up to 108mhz ? four video output ports compliant to bt.656 up to 108mhz ? two video input ports compliant to bt.1120 at 74.25mhz ? two video output ports compliant to bt.1120 at 74.25mhz audio feature s ? real time 16 channel e ncode and 1 channel decode compliant to adpcm standard. ? independent digital audio input and output i/f compliant to standard ? audio sample rate from 8 khz to 48 k hz peripheral i/f ? external 16 - bit ddr2 sdram @ 400mhz ? 32 - bit pci target fo r host communications @ 33 / 66mhz operating voltage ? 1.2v for core ? 3.3v for i/o pad ? 1.8v for ddr2 dram i/o physical ? pbga - 320, 27mmx 27mm, 1.27mm lead pitch ? 1. 2 w power consumption not recommended for new designs contact our technical support center at 1 - 888 - intersil or www.intersil.com/tsc s i 2
tw2809c fn7875 rev. 1.00 page 2 of 130 february 27, 2014 table of contents tw2809 register definition overview ................................ ................................ ................................ ................... 18 tw2809 memory map ................................ ................................ ................................ ................................ .............. 18 interrupt scheme ................................ ................................ ................................ ................................ ....................... 19 interrupt register ................................ ................................ ................................ ................................ ............... 19 interrupt protocol ................................ ................................ ................................ ................................ .............. 19 pci register definitions ................................ ................................ ................................ ................................ ................. 20 pci register 00 ................................ ................................ ................................ ................................ .......................... 21 pci register 04 ................................ ................................ ................................ ................................ .......................... 21 pci register 08 ................................ ................................ ................................ ................................ .......................... 22 pci register 0c ................................ ................................ ................................ ................................ .......................... 22 pci register 10 - 24 ................................ ................................ ................................ ................................ .................... 23 pci register 28 ................................ ................................ ................................ ................................ .......................... 23 pci register 2c ................................ ................................ ................................ ................................ .......................... 24 pci register 30 ................................ ................................ ................................ ................................ .......................... 24 pci register 34 ................................ ................................ ................................ ................................ .......................... 25 pci register 38 ................................ ................................ ................................ ................................ .......................... 25 pci register 3c ................................ ................................ ................................ ................................ .......................... 26 pin mux register definitions ................................ ................................ ................................ ................................ ......... 27 uart pin mux configuration ................................ ................................ ................................ ................................ .... 27 descriptions ................................ ................................ ................................ ................................ ....................... 27 gpio[7:0] pin mux configuration ................................ ................................ ................................ ........................... 28 descriptions ................................ ................................ ................................ ................................ ....................... 28 gpio[15:8] pin mux configuration ................................ ................................ ................................ ......................... 29 descriptions ................................ ................................ ................................ ................................ ....................... 29 gpio[23:16] pin mux configuration ................................ ................................ ................................ ...................... 30 descriptions ................................ ................................ ................................ ................................ ....................... 30 gpio[31:24] pin mux configuration ................................ ................................ ................................ ...................... 31 gpio[39:32] pin mux configuration ................................ ................................ ................................ ...................... 32 descriptions ................................ ................................ ................................ ................................ ....................... 32 gpio[47:4 0] pin mux configuration ................................ ................................ ................................ ...................... 33 descriptions ................................ ................................ ................................ ................................ ....................... 33 gpio[55:48] pin mux configuration ................................ ................................ ................................ ...................... 34 descriptions ................................ ................................ ................................ ................................ ....................... 34 pdma register definitions ................................ ................................ ................................ ................................ ............ 35 master mode ................................ ................................ ................................ ................................ .............................. 35 pdma interrupt status register for fw ................................ ................................ ................................ ........ 35 descriptions ................................ ................................ ................................ ................................ ....................... 36 pdma master tx and rx interrupt status register (optiona l) ................................ ................................ .. 36 descriptions ................................ ................................ ................................ ................................ ....................... 36 pdma master tx and rx endian control register ................................ ................................ ...................... 37 descriptions ................................ ................................ ................................ ................................ ....................... 37 pdma master tx control register ................................ ................................ ................................ ................. 38 descriptions ................................ ................................ ................................ ................................ ....................... 38 pdma master tx buffer id register ................................ ................................ ................................ .............. 38 descriptions ................................ ................................ ................................ ................................ ....................... 38 pdma master tx target start address register ................................ ................................ ......................... 39 descriptions ................................ ................................ ................................ ................................ ....................... 39 pdma master tx total length register ................................ ................................ ................................ ........ 39 pdma master tx 2d xy star t register ................................ ................................ ................................ ......... 39 pdma master rx control register ................................ ................................ ................................ ................ 40 descriptions ................................ ................................ ................................ ................................ ....................... 40 pdma master rx buffer id register ................................ ................................ ................................ ............. 40 descriptions ................................ ................................ ................................ ................................ ....................... 40
tw2809c fn7875 rev. 1.00 page 3 of 130 february 27, 2014 pdma master rx source start address register ................................ ................................ ........................ 41 descriptions ................................ ................................ ................................ ................................ ....................... 41 pdma master rx total length register ................................ ................................ ................................ ....... 41 pdma master rx 2d xy start registe r ................................ ................................ ................................ ......... 41 slave mode ................................ ................................ ................................ ................................ ................................ . 42 pdma slave tx control register ................................ ................................ ................................ .................... 42 description s ................................ ................................ ................................ ................................ ....................... 42 pdma slave tx buffer id register ................................ ................................ ................................ ................. 43 descriptions ................................ ................................ ................................ ................................ ....................... 43 pdma sl ave tx total length register ................................ ................................ ................................ .......... 43 descriptions ................................ ................................ ................................ ................................ ....................... 43 pdma slave tx 2d xy start register ................................ ................................ ................................ ............ 44 pdma slave rx control register ................................ ................................ ................................ ................... 44 descriptions ................................ ................................ ................................ ................................ ....................... 44 pdma slave rx buffer id register ................................ ................................ ................................ ................ 45 descriptions ................................ ................................ ................................ ................................ ....................... 45 pdma slave rx total length register ................................ ................................ ................................ .......... 45 descriptions ................................ ................................ ................................ ................................ ....................... 45 pdma slave rx 2d xy start register ................................ ................................ ................................ ........... 45 pdma slave interrupt status register ................................ ................................ ................................ .......... 46 descriptions ................................ ................................ ................................ ................................ ....................... 46 communication between fw and host ................................ ................................ ................................ ................. 47 the communication command register from host driver ................................ ................................ ....... 47 descriptions ................................ ................................ ................................ ................................ ....................... 47 the first extra communication register from host driver ................................ ................................ ........ 47 descript ions ................................ ................................ ................................ ................................ ....................... 47 the second extra communication register from host driver ................................ ................................ .. 48 the communication command register from fw ................................ ................................ ..................... 48 descriptions ................................ ................................ ................................ ................................ ....................... 48 the first extra communication register from fw ................................ ................................ ...................... 49 descriptions ................................ ................................ ................................ ................................ ....................... 49 the second extra communication register from fw ................................ ................................ ................ 49 descriptions ................................ ................................ ................................ ................................ ....................... 49 interrupt status for pci host driver ................................ ................................ ................................ ........................ 50 pdma interrupt status register for pci channel ................................ ................................ ........................ 50 descriptions ................................ ................................ ................................ ................................ ....................... 51 global control register definitions ................................ ................................ ................................ .............................. 51 normal interrupt ................................ ................................ ................................ ................................ ........................ 51 descriptions ................................ ................................ ................................ ................................ ....................... 51 codec video channel ................................ ................................ ................................ ................................ ................ 52 descriptions ................................ ................................ ................................ ................................ ....................... 52 software reset ................................ ................................ ................................ ................................ .......................... 53 description ................................ ................................ ................................ ................................ ........................ 54 timer period register ................................ ................................ ................................ ................................ ............... 55 descriptions ................................ ................................ ................................ ................................ ....................... 55 encode mode register ................................ ................................ ................................ ................................ .............. 55 fast interrupt ................................ ................................ ................................ ................................ .............................. 56 descriptions ................................ ................................ ................................ ................................ ....................... 56 encoder parameter register 0 ................................ ................................ ................................ ................................ 57 encoding parameter register 1 ................................ ................................ ................................ .............................. 57 encoder parameter regist er 2 ................................ ................................ ................................ ................................ 58 encoder parameter register 3 ................................ ................................ ................................ ................................ 58 timer 0 count ................................ ................................ ................................ ................................ ............................ 59 timer 1 count ................................ ................................ ................................ ................................ ............................ 59 timer 2 count ................................ ................................ ................................ ................................ ............................ 59 timer 3 count ................................ ................................ ................................ ................................ ............................ 59
tw2809c fn7875 rev. 1.00 page 4 of 130 february 27, 2014 encoder parameter re gister 4 ................................ ................................ ................................ ................................ 60 encoder parameter register 5 ................................ ................................ ................................ ................................ 60 encoder parameter register 6 ................................ ................................ ................................ ................................ 61 encoder parameter register 7 ................................ ................................ ................................ ................................ 61 encoder parameter register 8 ................................ ................................ ................................ ................................ 61 encoder parameter register 9 ................................ ................................ ................................ ................................ 62 encoder parameter register 10 ................................ ................................ ................................ ............................. 62 encoder parameter register 11 ................................ ................................ ................................ ............................. 63 encoder parameter register 12 ................................ ................................ ................................ ............................. 63 watch dog limit ................................ ................................ ................................ ................................ ........................ 63 timer control register ................................ ................................ ................................ ................................ .............. 64 desc riptions ................................ ................................ ................................ ................................ ....................... 64 timer 1 control register ................................ ................................ ................................ ................................ .......... 65 timer 2 control register ................................ ................................ ................................ ................................ .......... 65 timer 3 control register ................................ ................................ ................................ ................................ .......... 66 host interface register definitions ................................ ................................ ................................ .............................. 67 hif interrupt ................................ ................................ ................................ ................................ ............................... 67 descriptions ................................ ................................ ................................ ................................ ....................... 67 device id 68 pci class code ................................ ................................ ................................ ................................ ........................... 68 pci sub - system id ................................ ................................ ................................ ................................ ..................... 69 pci header info ................................ ................................ ................................ ................................ .......................... 69 ddr mode register ................................ ................................ ................................ ................................ ................... 70 ddr timing control register 0 ................................ ................................ ................................ ............................... 72 descriptions ................................ ................................ ................................ ................................ ....................... 72 ddr timing control register 1 ................................ ................................ ................................ ............................... 72 descriptions ................................ ................................ ................................ ................................ ....................... 72 fw pdma control register ................................ ................................ ................................ ................................ ...... 73 fw pdma command register ................................ ................................ ................................ ................................ 73 i2 c register definitions ................................ ................................ ................................ ................................ .................. 74 i2c interrupt register ................................ ................................ ................................ ................................ ............... 74 descriptions ................................ ................................ ................................ ................................ ....................... 74 i2c mode select register ................................ ................................ ................................ ................................ ......... 75 descriptions ................................ ................................ ................................ ................................ ....................... 75 i2c write register0, register1, register2, regis ter3 ................................ ................................ ......................... 75 descriptions ................................ ................................ ................................ ................................ ....................... 75 i2c write register4, register5, register6, register7 ................................ ................................ ......................... 76 descriptions ................................ ................................ ................................ ................................ ....................... 76 i2c write register8, register9, register10, register11 ................................ ................................ .................... 76 descriptions ................................ ................................ ................................ ................................ ....................... 76 i2c write register12, register13, register14, register15 ................................ ................................ ............... 77 descriptions ................................ ................................ ................................ ................................ ....................... 77 i2c write register16, register17, register18, register19 ................................ ................................ ............... 77 descriptions ................................ ................................ ................................ ................................ ....................... 77 i2c write register20, register21, register22, register23 ................................ ................................ ............... 78 descriptions ................................ ................................ ................................ ................................ ....................... 78 i2c write register24, register25, register26, register27 ................................ ................................ ............... 78 descriptions ................................ ................................ ................................ ................................ ....................... 78 i2c write register28, register29, register30, register31 ................................ ................................ ............... 79 descriptions ................................ ................................ ................................ ................................ ....................... 79 i2c read register0, register1, register2, register3 ................................ ................................ ......................... 79 descriptions ................................ ................................ ................................ ................................ ....................... 79 i2c read register4, register5, register6, register7 ................................ ................................ ......................... 80 descriptions ................................ ................................ ................................ ................................ ....................... 80 i2c read register8, register9, register10, register11 ................................ ................................ .................... 80 descriptions ................................ ................................ ................................ ................................ ....................... 80
tw2809c fn7875 rev. 1.00 page 5 of 130 february 27, 2014 i2c read register12, register13, register14, register15 ................................ ................................ ............... 81 descript ions ................................ ................................ ................................ ................................ ....................... 81 i2c read register16, register17, register18, register19 ................................ ................................ ............... 81 descriptions ................................ ................................ ................................ ................................ ....................... 81 i2c read register20,register21,register22,register23 ................................ ................................ .................. 82 descriptions ................................ ................................ ................................ ................................ ....................... 82 i2c read register24,register25,regist er26,register27 ................................ ................................ .................. 82 descriptions ................................ ................................ ................................ ................................ ....................... 82 i2c read register28, register29, register30, register31 ................................ ................................ ............... 83 descriptions ................................ ................................ ................................ ................................ ....................... 83 i2c master mode protocol ................................ ................................ ................................ ................................ ....... 84 write cbus 32 bit registers: ................................ ................................ ................................ ........................... 84 read cbus 32 bit registers: ................................ ................................ ................................ ........................... 84 uart register definitions ................................ ................................ ................................ ................................ .............. 86 uart interrupt enable regi ster ................................ ................................ ................................ .............................. 86 descriptions ................................ ................................ ................................ ................................ ....................... 86 uart interrupt status register ................................ ................................ ................................ ............................... 86 descri ptions ................................ ................................ ................................ ................................ ....................... 86 uart line control register(lcr) ................................ ................................ ................................ ............................ 87 descriptions ................................ ................................ ................................ ................................ ....................... 87 uar t divisor latch byte 1 register(lsb) ................................ ................................ ................................ .............. 88 descriptions ................................ ................................ ................................ ................................ ....................... 88 uart divisor latch byte 2 register (msb) ................................ ................................ ................................ ............ 89 descriptions ................................ ................................ ................................ ................................ ....................... 89 uart internal interrupt enable register(ier) ................................ ................................ ................................ ....... 90 descriptions ................................ ................................ ................................ ................................ ....................... 90 uart interrupt identification register(iir) ................................ ................................ ................................ ........... 91 descriptions ................................ ................................ ................................ ................................ ....................... 91 uart fifo co ntrol register(fcr) ................................ ................................ ................................ ............................ 92 descriptions ................................ ................................ ................................ ................................ ....................... 92 uart modem control register(mcr) ................................ ................................ ................................ ..................... 93 descriptions ................................ ................................ ................................ ................................ ....................... 93 uart line status register(lsr) ................................ ................................ ................................ ............................. 94 descriptions ................................ ................................ ................................ ................................ ....................... 95 uart modem status register(msr) ................................ ................................ ................................ ...................... 96 descriptions ................................ ................................ ................................ ................................ ....................... 96 uart receiver buffer ................................ ................................ ................................ ................................ ................ 97 descriptions ................................ ................................ ................................ ................................ ....................... 97 uart transmitter holding register ................................ ................................ ................................ ........................ 97 descriptions ................................ ................................ ................................ ................................ ....................... 97 gpio register definitions ................................ ................................ ................................ ................................ ............... 98 gpio interrupt enable register ................................ ................................ ................................ ............................... 98 descriptions ................................ ................................ ................................ ................................ ....................... 98 gpio interrupt status register ................................ ................................ ................................ ................................ 99 descriptions ................................ ................................ ................................ ................................ ....................... 99 gpio line driving register0 ................................ ................................ ................................ ................................ .... 99 descriptions ................................ ................................ ................................ ................................ ....................... 99 gpio line driving register1 ................................ ................................ ................................ ................................ . 100 descriptions ................................ ................................ ................................ ................................ .................... 100 gpio line control register0 ................................ ................................ ................................ ................................ . 100 descriptions ................................ ................................ ................................ ................................ .................... 100 gpio line control register1 ................................ ................................ ................................ ................................ . 101 descriptions ................................ ................................ ................................ ................................ .................... 101 gpio line load register0 ................................ ................................ ................................ ................................ ..... 101 des criptions ................................ ................................ ................................ ................................ .................... 101 gpio line load register1 ................................ ................................ ................................ ................................ ..... 102
tw2809c fn7875 rev. 1.00 page 6 of 130 february 27, 2014 descriptions ................................ ................................ ................................ ................................ .................... 102 peri pheral timing ................................ ................................ ................................ ................................ ......................... 103 uart interface ................................ ................................ ................................ ................................ ........................ 113 ddr2 timing ................................ ................................ ................................ ................................ ........................... 114 power up se quence ................................ ................................ ................................ ................................ ............... 118 power off sequence ................................ ................................ ................................ ................................ .............. 118 electrical specifications ................................ ................................ ................................ ................................ ........ 119 absolute maximum ratings ................................ ................................ ................................ ........................ 119 recommended operating conditions ................................ ................................ ................................ ........ 119 supply current and power dissipation ................................ ................................ ................................ ....... 119 dc characteristics ................................ ................................ ................................ ................................ ......... 120 input / output capacitance ................................ ................................ ................................ ......................... 120 package description ................................ ................................ ................................ ................................ .................... 121 ball assignment ................................ ................................ ................................ ................................ ...................... 121 pin definitions ................................ ................................ ................................ ................................ ......................... 122 mechanical specifications ................................ ................................ ................................ ................................ .... 130
tw2809c fn787 5 rev. 1.00 page 7 of 130 february 27, 2014 ordering information part number part marking package (pb - free) tw2809 - bc1 - gr (note 1 ) tw2809 pkbc1 - gr 320 ld 27mm x 27mm pbga note: 1. these intersil pb - free wlcsp and bga packaged products empl oy special pb - free material sets; molding compounds/die attach materials and snagcu - e1 solder ball terminals, which are rohs compliant and compatible with both snpb and pb - free soldering operations. intersil pb - free wlcsp and bga packaged products are ms l classified at pb - free peak reflow temperatures that meet or exceed the pb - free requirements of ipc/jedec j std - 020 .
tw2809c fn787 5 rev. 1.00 page 8 of 130 february 27, 2014 general d escription tw2809c is a highly integrated multi - channel h.264 codec targeting security surveillance market . the video codec i s designed to work in full duplex mode so it is capable of doing digital video compress ing and de - compress ing simul taneously. tw2809c uses a tightly pipelined hardware sol ution to guarantee its performance benchmark . th e e mbedded arm926 microprocessor enab les tw2809c to tailor various customized sets of functions such as various bit rate s , different frame rate s , and different resolutions for each channel. customers can change tw2809c configuration parameters to meet their own needs. these parameters include s video channel number, bit rate, frame rate, ntsc/pal, progressive / interleave mode, encode / decode mode, etc. peripheral interface tw2809c implements a few peripheral interfaces: video capture, video display , audio i/f, memory i/f, and pci i/f. these inter faces are described in more details in this section. video input i/f sd video input i/f there are four independent sd video input ports with their own clock . the video input format is compliant to bt.656. each port can tak e frame interleaved video input @ 27mhz, 54mhz, or 108mhz. video input port 0 is a special port . in addition to frame interleaved video input, i t also take s 108mhz or 54mhz byte - interleaved video input. it can directly connect to tw2866 - a like video decoder and receive 4 channel sd video i nputs. video input port 2 is also a special port . it can take 54mhz byte - interleaved video input. it can be used together with input port 0 to take 4 channel sd video inputs from tw2866 - a like video decoder with two 54mhz input clocks . hd video input i/f there are two independent hd video input ports with their own clock. the video input format is compliant to bt.1120. each port can take one hd video input @ 74.25mhz. video output i/f sd video output i/f there are four video output ports. port 0 and port 1 share the same video outpu t clock. port 2 and port 3 share the same video output clock. each port can output frame interleaved video @27mhz, 54mhz, or 108mhz. hd video output i/f there are two independent hd video output ports with their own clock. the video output format is compliant to bt.1120. each port can send one hd video input @ 74.25mhz. audio i/f the codec has two sets of digital audio interface. one is the audio input interface operating as slave mode. the other is the audio output interface operating as master mode. ddr i/f the external ddr2 sdram is used as memory for storing video and audio information during encoding and decoding process es. the codec supports 1 gb ddr2 sdr am with 16 - bit data bus. pci i/f tw2809c use s pci bus to communicate with the host. the bitstream from encoder output is stored to the h ard disk via the pci bus. the encoded bitstream is transferred to tw2809c decoder via pci bus in the playback mode. the pci clock can be either 33mhz or 66mhz. top level block diagram figure 1 shows the top level codec block diagram. the arm 926 handles bot h a/v synchronization and slice - layer - above video processing. the major video codec task is done by the tightly coupled macroblock v ideo pipeline. there is an internal 64 - bit memory data bus connecting most of the codec modules with the external ddr2 memory. the arm processor h as ahb bus interface. t he codec implements its own internal 32 - bit control bus for global on - chip register ac cess. there is an interface bridge to convert ahb protocol to the internal co ntrol bus. the external memory interface needs to operate at 4 00mhz in order to provide enough bandwidth. s i 2
tw2809c fn787 5 rev. 1.00 page 9 of 130 february 27, 2014 32 8 8 8 8 8 8 8 8 pci video if audio if ddr if arm h.264 codec jpeg enc audio codec 16 64 figure 1 . tw2809c block d iagram
tw2809c fn787 5 rev. 1.00 page 10 of 130 february 27, 2014 encoding block diagr am tw2809c hardwired video encoder is designed to compress a sequence of yuv 4:2:0 pictures to a single compressed video bitstream. it sup ports various resolutions from cif (352x240 ) to hd (1920x108 0 ). the motion vector is in ? pixel accuracy. all intra - prediction modes are supported. the firmware in the embedded microprocessor is responsible for rate control scheme , such as cbr and vbr. in the cbr mode, the qp value can be adjusted at each macroblock. the visual subjective video quality is improved by implementing programmable in - loop filter. the vid eo encoding is divided into a series of processing steps for each 16x16 macroblock for each video frame. the initial step is to generate the prediction for the current macroblock. there are two kinds of prediction s: intra prediction (spatial prediction us ing encoded current pix) and inter prediction (temporal prediction using previously encoded pictures). the residual difference between current block and the predicated block goes through transformation and then quantized. the results will be coded into h.2 64 bitstream using content adaptive variable length coding ( cavlc ) method . meanwhile, the reconstructed macroblock is calculated by applying inverse quantization and transform ed to the quantized coefficients. an in - loop de - blocking filter is applied to the reconstructed macroblock before it is stored in the reference frame buffer. the h.264 encoding requires many of its operation in sequence , which impose s a computation challenge for asic design. in order to meet this challenge, the codec simplifies certai n part s of sequence operation into parallel operation without introducing noticeable artifact s . a macroblock level pipelin e is implemented in tw2809c to break down one macroblock proces sing it into smaller tasks and making it easier for hardware implementa tion. as shown in figure 2 , the macroblock pipeline consists of 4 stages: the motion estimation unit ( meu ), the fractional motion estimation ( fme ), macroblock type decision ( mtd ), and macroblock coding ( mbc ). each stage has to com plete all assigned tasks within one macrobl ock processing period . each macroblock pipeline can be further partitioned into several sub - bocks . during the encoding process, all four macroblock pipelines are concurrently proc essing 4 consecutive macroblock d ata in raster - scan order . figure 3 illustrates encoding macroblock pipeline schedule in the time domain. figure 2 . encoder hw p ipeline two pixel me ? pixel me ? pixel me chroma inter pred ip estimate edge filter meu f m e mbus integer me m t d intra pred code entropy encoding dq idq mbc
tw2809c fn787 5 rev. 1.00 page 11 of 130 february 27, 2014 figure 3 . encoder macroblock p ipeline schedule for each of these processes, the arm must set up parameters and monit or events communicated by interrupts. the microprocessor involvement is limited, in the norm al operation mode, to the slice - layer - above processing with the exception of video bit rate control. the rate control adjusts the quantization value at macroblock l evel. decoding block diagr am the major video decompression task is done by the tightly coupled macroblock pipeline that consists of variable length decoding ( vld ), block transform unit for idct/iq ( btu ), intra/inter prediction ( ipd ), and edge filter ( egf ) . the decoding macroblock pipeline is able to decode in its entirety a video bitstream from slice layer downwards. the arm must decode the higher layers in order to extract the information needed for decoding and appropriately set up the registers. the codec implements a start code detector that is a few slices in advance of macroblock decoding pipeline. this start code detector parses the bitstream and locates start codes corresponding to slice layer and above. when one of these start - code s is found, t he start code detectors stops and raise s an interrupt to the arm. the arm is then able to read the header data following the start code. the decoded header parameters will be programmed into hardware shared parameter data structure that will be discussed i n detail later in this document. figure 4 . decode r b lock d iagram meu fme mtd mbc mb _ ( n - 1 ) mb _ 1 mb _ 2 mb _ 3 mb _ 4 mb _ n mb _ ( n - 2 ) mb _ ( n - 3 ) mb _ ( n - 1 ) mb _ 1 mb _ 2 mb _ 3 mb _ 4 mb _ n mb _ ( n - 2 ) mb _ ( n - 3 ) mb _ ( n - 1 ) mb _ 1 mb _ 2 mb _ 3 mb _ 4 mb _ n mb _ ( n - 2 ) mb _ ( n - 3 ) mb _ ( n - 1 ) mb _ 1 mb _ 2 mb _ 3 mb _ 4 mb _ n mb _ ( n - 2 ) mb _ ( n - 3 ) time line vld v l d b t u i p d e g f mbus iq idct pixel reconstruct edge filter boundary strength half - pixel motion compensate quart - pixel motion compensate chroma motion compensate intra predicaiton
tw2809c fn787 5 rev. 1.00 page 12 of 130 february 27, 2014 figure 5 . decoder macroblock p ipeline schedule video configuration and interfaces tw2809c can be configured differently for it video codec operation. customers can set resolution and frame rate differently for primary and secondary video channels. this section provides guideline s for the customer to configure tw2809c video correctly. primary video stream there are some limitations for tw2809c primary video processing. customers should be c areful not to violate any of these limitations. tw2809c maximum video proces sing power tw2809c can do real time 8 channel sd codec (4 enc + 4 dec). it can also do real time 32 channel cif codec (16enc + 16dec). in other words, tw2809c can process up to 240 sd frames in a second. customers can assign any 240 frames to any video channel for either encode or decode. for example, the user can use all 240 frames for encoding tasks so that tw2809c operates as 8 sd encoding mode. the u ser can also use all 240 f rames for decoding tasks so that tw2809c operates as 8 sd decoding mode. the u ser can use 120 frames for encoding tasks and remaining 120 frames for decoding tasks. then tw2809c works as 4 sd encode and 4 sd decode. customers can use a single sd computation p ower for roughly four cif picture processing. it is not exactly four cif picture considering firmware overhead to handle four cif pictures instead of one sd picture. tw2809c maximum video channe l number the maximum primary video channel number is 32. this is an internal architecture limit for tw2809c . thus it is impossible for tw2809c to support 64 cif codec @15fps, even though the computation power is almost the same as 32 cif codec @30fps. tw2809c maximum external fra me buffer number the u ser should be aware that external frame buffer size is decided by the resolution of the video channel. it has nothing to do with the frame rate. for example, the frame buffer size for two sd @15fps is two times larger than one sd @30fps, even though the computation powe r remains rou ghly the same. with 1gb ddr as external memory, there is a limitation of maximum frame buffer number. network secondary video stream tw2809c supports network stream encoding. the performance benchmark for network stream is different for sd an d cif case. for 8 ch sd dvr (4 enc + 4 dec) , tw2809c is capable of encoding 4 real time cif secondary video stream . however there is not much computation power reserved for secondary video stream for 32 ch cif dvr (16 enc + 16 dec). if the user needs to e ncode 16 real - time qcif secondary video stream, the decoding channel number has to be reduced from 16 to 8 in order provide sufficient computer power. video input description tw2809c implements 4 physical input ports. these four input ports can be configu red to take sd video inputs. tw2809c takes either frame or byte interleave video input format. but users cannot assign some video input ports to frame interleave format and the remaining video input ports to byte interleave format. video input port 0 and 1 or port 2 and 3 can be configured to receive hd video input. it is possible for tw2809c to take mixed hd and sd input format. for example, tw2809c can receive sd vld btu ipd egf mb _ ( n - 1 ) mb _ 1 mb _ 2 mb _ 3 mb _ 4 mb _ n mb _ ( n - 2 ) mb _ ( n - 3 ) mb _ ( n - 1 ) mb _ 1 mb _ 2 mb _ 3 mb _ 4 mb _ n mb _ ( n - 2 ) mb _ ( n - 3 ) mb _ ( n - 1 ) mb _ 1 mb _ 2 mb _ 3 mb _ 4 mb _ n mb _ ( n - 2 ) mb _ ( n - 3 ) mb _ ( n - 1 ) mb _ 1 mb _ 2 mb _ 3 mb _ 4 mb _ n mb _ ( n - 2 ) mb _ ( n - 3 ) time line
tw2809c fn787 5 rev. 1.00 page 13 of 130 february 27, 2014 video input on port 2 and 3. at the same time, tw2809c can receive hd video input on port 0 a nd 1 . video input logic po rts there are some limitations on how to use tw2809c physical ports for sd or hd video inputs. 1) f our input ports at frame interleaved mode: @ 27 / 54 / 108mhz . use port 0 - 3 port - 0: { vi 0_ data [7:0]} clk_vi 0 @ 27 / 54 / 108mhz port - 1: { vi 1_ data [7:0] } clk_vi 1 @ 27 / 54 / 108mhz port - 2: { vi 2_ data [7:0]} clk_vi 2 @ 27 / 54 / 108mhz port - 3: { vi 3_ data [7:0]} clk_vi 4 @ 27 / 54 / 108mhz 1) 2) t wo input ports at byt e interleaved mode @ 54mh z . use port - 0 and port - 2 port - 0: { vi0_data [7:0]} clk_vi 0 @ 54mhz port - 2: { vi2_data [7:0]} clk_vi 2 @ 54mhz 3) on e input port at byte interleaved mode @ 108mhz . use port - 0 port - 0: { vi0_data [7:0]} clk_vi 0 @ 108mhz bt.656 f rame interleave d video input the frame interleave d case is rather simple. each tw2809c video input port can operate up to 1 08mhz. the clocks of four ports are independent from each other. for example, the user can feed two channel video inputs to port 0 at 54mhz. at the same, the user can also feed one channel video input to port 1 at 27mhz. for 8 sd encoding only case, tw2809 c accepts up to 8 sd video inputs. bt.656 b yte interleave d 54mh z video input v ideo input port 0 and port 2 can take 54mhz byte interleaved video input. when port 0 is used fo r 54mhz video input, port 1 can not connect to any video input. figure 6 . b yte - interleave 54mh z video input top level diagram when port 2 is used for 54mhz video input, port 3 c an not connect to any video input. bt.656 b yte interleaved 108mh z video input video port 0 is the only p ort that accepts 108mhz byte interleaved video input. when port 0 is used for 108mhz video input, all other three video input port s cannot connect to any video input. figure 7 . 108mh z byte - interleave video input top level diagram bt.1120 hd video inp ut tw2809c is designed to take two channel hd video inputs. as shown in the following figure, video physical input ports 0 and 1 can be grouped together to receive one hd video input. the hd video input cl ock is connected to pin clk_vi0 . it is noted that video input port 0 and 1 should be connected to hd luma and chroma ports respectively . physical video input ports 2 and 3 can be used to receive another hd video input similar as video input port 0 and 1. v i 0 _ d a t a [ 7 : 0 ] 2 c h v i d e o i n p u t c l k _ v i 0 5 4 m h z t w 2 8 0 9 v i 2 _ d a t a [ 7 : 0 ] 2 c h v i d e o i n p u t c l k _ v i 2 5 4 m h z v i 0 _ d a t a [ 7 : 0 ] 4 c h v i d e o i n p u t c l k _ v i 0 1 0 8 m h z t w 2 8 0 9
tw2809c fn787 5 rev. 1.00 page 14 of 130 february 27, 2014 tw2809c is capable of encoding one channel 1080x60i in real time. it can encode two channel 1080x60i in half of real time frame rate. figure 8 . bt.1120 hd input dia gram sd/hd mixed video in put tw280 9c can take hd and sd video input at the same time. the max encode performance benchmark is 1ch hd plus 2ch sd video encode at real time. picture 9 shows one configuration to use video input port vi2 (@54mhz) to take 2ch sd in frame - interleaved format. ano ther configuration is to use two video input port vi2 and vi3 (@27mhz) to take 2ch sd video. figure 9 . hd/sd mixed video in put mode video output description there are four video output ports and two clocks for the four ports. vi deo output port 0 and port 1 share vo_clk_0. video output port 2 and port 3 share vo_clk_1. video output logic p orts f our output ports at frame interleaved mode: @ 27 / 5 4/ 108mhz. use port 0 - 3 port - 0: { vo0_data [7:0]} clk_vo_out_0 @ 27 / 54 / 108mhz port - 1: { vo1 _data [7:0]} clk_vo_out_0 @ 27 / 54 / 108mhz port - 2: { vo2_data [7:0]} clk_vo_out_1 @ 27/54 / 108mhz port - 3: { vo3_data [7:0]} clk_vo_out_1 @ 27/54/ 108mhz bt. 656 f rame interleaved vid eo output tw2809c output port only supports frame interleave video format. it does not support byte - interleave video format. video output port 0 and port 1 shares same output clock vo_clk_0 . video output port 2 and port 3 shares same output clock vo_clk_1 . the two video o utput clocks are independent of each other . bt.1120 video output tw2809c physical video output port 0 and 1 can be grouped together to send one channel hd video data out. it is noted that video output port 0 and 1 is designed to output hd luma and chroma data respectively. the other two video output port s 2 and 3 can be grouped together to send another channel hd video data out similar to port 0 and 1. figure 10 . hd video output tw2809c is capable of decoding one channel 1080x60i in real time. it can also encode and decode one channel hd video (full duplex ) in about 4/5 of real time frame rate. channel muxed video output tw2809c has limited video mux function and can assemble 4cif video into 1 sd format and send it v i 0 _ d a t a [ 7 : 0 ] h d 0 _ l u m a c l k _ v i 0 7 4 . 2 5 m h z v i 1 _ d a t a [ 7 : 0 ] h d 0 _ c h r o m a v i 2 _ d a t a [ 7 : 0 ] h d 1 _ l u m a c l k _ v i 2 7 4 . 2 5 m h z v i 3 _ d a t a [ 7 : 0 ] h d 1 _ c h r o m a t w 2 8 0 9 v i 0 _ d a t a [ 7 : 0 ] h d 0 _ l u m a c l k _ v i 0 7 4 . 2 5 m h z v i 1 _ d a t a [ 7 : 0 ] h d 0 _ c h r o m a v i 2 _ d a t a [ 7 : 0 ] 2 c h v i d e o i n p u t c l k _ v i 2 5 4 m h z t w 2 8 0 9 v o 0 _ d a t a [ 7 : 0 ] h d 0 _ l u m a c l k _ v o _ o u t 0 7 4 . 2 5 m h z v o 1 _ d a t a [ 7 : 0 ] h d 0 _ c h r o m a v o 2 _ d a t a [ 7 : 0 ] h d 1 _ l u m a 7 4 . 2 5 m h z v o 3 _ d a t a [ 7 : 0 ] h d 1 _ c h r o m a t w 2 8 0 9 c l k _ v o _ o u t 1
tw2809c fn787 5 rev. 1.00 page 15 of 130 february 27, 2014 to the video display. it can also assemble 6 sd video into 1hd format and send it to tw2880 hd playback port. each video output port has up - scalar function to take decoded cif video and display it in sd format. four cif video output mux tw2809c is capable of decoding multiple compressed cif videos and assembl e them into a single sd format to display. figure 11 . cif video output ass embler as shown in the above figure, four channels of the cif video are put together and sent to display in a single sd frame. where the top field of t he sd frame consists of video from channel 0 and channel 1, and bottom field of the sd frame consists of video from channel 2 and channel 3. if there are less than 4 channels of cif video decoded, tw2809c will fill the unused channel with a pre - programmed color. mixed resolution video output mux vout is flexible to assemble different video resolutions from different channel s . as shown in the following figure, two cif video and one half sd video are put together and sent to display in a single sd frame. figure 12 . cif / half sd video output assembl er vout implements on - the - fly up - scalar function to upsize a cif video into a sd format and send to display. the horizontal direction is a bi - linear up - scalar. the bottom field is just a d uplication of the top field. figure 13 . vout up - scalar in the time domain, different resolutions of video from different channels can be assembled together and sent to the display. the following figure illustrates on possibili ty for the vout case. it assembles 12 channels video with different resolutions and composes a single bt 656 video display stream. the vout assembler is limited by its though - put upper limit, i.e. , 8 sd video. if each cif video channel needs to be upsized to sd resolution for the output, then only 8 cif video can be displayed. figure 14 . example of tw2809c d isplay o rder ch_0 ch_1 ch_2 ch_3 ch_0 ch_2 ch_1 cif cif (horizontal x2) cif (horizontal x2) ch_0 ch_1 ch_2 ch_3 ch_6 ch_7 ch_8 ch_9 ch_10 ch_11 ch_4 ch_5
tw2809c fn787 5 rev. 1.00 page 16 of 130 february 27, 2014 audio processing the audio processing unit ( apu ) handles audio compression and de - compression. for simple speech codec, there is no need to support multi - format audio compression; instead a single adpcm format codec is implemented using hardware approach. adpcm is a variant of dpcm that varies the size of the quantization step, to allow further reduction of the required bandwidth for a given signal to noise ratio. it is used to m ap a series of 8 - bit - law (or a - law) pcm samples into a series of 4 bit adpcm samples (the adpcm compression ratio is 4:1, but tw2809c will take each 8 bit sample and extend it to 16 - bit before compression). the audio compressed bitstream is packed into packets. the size of each packet is 188 byte s with an embedded 28 - bit packet header. the actual audio compressed bitstream size is 1476 - bit or 369 audio samples. i2s protocol the bus is a serial bus consisting of three lines: serial clock, word select ion , and serial data. the digital audio input interface is working as slave mode. the digital audio output interface is working as master mode. the codec shall generate both serial clock and word select when it operates as master mode. it receives both serial clock and word select when it operates as slave mode. the codec uses two set pins to transmit or receive multi - channel digital audio data. multi - channel audio protocol the serial clock ( sck ) depends on audi o sample rate, audio sample bit width, and how many audio channels are occupied for current configuration. different audio channel may have different sample rate and sample bit width. in order to simplify the audio codec design, the following equation is u sed to calculate the audio serial clock. sck = 256 x sample _ rate max (eq. 1) equation 1 audio serial clock while is the maxima audio sample rate among all. for example, the serial clock should be 2,048khz if max audio sample rate is 8khz . in the above equation, it is assumed that each word select cycle covers 64 - bits. the codec audios are all mono channel. there is no need for the codec to support stereo audio. the audio channels are evenly divided to fit into le ft and right channel space. figure 16 . multi - channel digital audi o interface figure 15 . i2s p rotocol s i 2 max rate sample _ sck ws edge detection msb lsb msb lsb sd edge detection sample 0 sample 1
tw2809c fn787 5 rev. 1.00 page 17 of 130 february 27, 2014 figure 16 shows an example of multi - channels digital audio input protocol. it is noted that only firs t 4 bits after word select transition are valid. the remaining bits in the word select are not used .
tw2809c fn787 5 rev. 1.00 page 18 of 130 february 27, 2014 tw2809 register definition overview tw2809 memory map tw2809 memory map is partitioned into two distinct seg ments: one for the external ddr memory and th e other for on - chip global control registers. table 1 . soc memory map the external ddr access supports both single cycle and burst type. arm926ejs burst length is always 32 bytes. the cbus supports up to 20 clients with each clie nt takes 256 byte space. the following table shows current cbus memory map. table 2 . cbus memory map module name start address end address dbg 32'h8000_0000 32'h8000_00ff spr 32'h8000_0100 32'h8000_01ff vld 32'h8000_0200 32'h800 0_02ff ipd 32'h8000_0300 32'h8000_03ff it 32'h8000_0400 32'h8000_04ff egf 32'h8000_0500 32'h8000_05ff vif 32'h8000_0600 32'h8000_06ff tsm 32'h8000_0700 32'h8000_07ff tme 32'h8000_0800 32'h8000_08ff rtb 32'h8000_0900 32'h8000_09ff hpm 32'h8000_0a00 32'h8000_0aff mbc 32'h8000_0b00 32'h8000_0bff vlc 32'h8000_0c00 32'h8000_0cff dcm 32'h8000_0d00 32'h8000_0dff hif 32'h8000_0e00 32'h8000_0eff ctr 32'h8000_0f00 32'h8000_0fff gpio 32h8000_1c00 32h8000_1cff uart0 32h8000_1d00 32h8000_1dff uart1 3 2h8000_1e00 32h8000_1eff i2c 32h8000_1f00 32h8000_1fff start_address end_address mbus 32'h0000_0000 32'h3fff_ffff cbus 32'h8000_0000 32'h8000_1fff
tw2809c fn787 5 rev. 1.00 page 19 of 130 february 27, 2014 interrupt scheme the interrupt protocol is outlined in this section. by default, the first register of each hardware module should be the register that defines the interrupt enable and status f or the module. interrupt register address module base address + 0x00 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 status 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 enable [31:17] reserved [16] status C interrupt status. hw set this bit to high to initiate interrupt. fw wirte hight to clear interrupt [15:1] reserved [0] enable C interrupt enable. 0: interrupt disable. 1: interrupt enable. default is 1. interrupt protocol hw generates an interrupt signal to fw when the interrupt source e xist and the interrupt is enabled by the fw. when fw detects the interrupt, it gets into interrupt service routine. when it is done, fw writes high to the status bit to clear the interrupt. when hw detects that fw is writing 1 to status bit, it shall clear the interrupt source.
tw2809c fn787 5 rev. 1.00 page 20 of 130 february 27, 2014 pci register definitions this section describes pci module registers. normally, any pci core suppo rts the following registers. tw2809 defines some value in the registers such as device id, vendor id, class code, and so on. if custom ers want to know more detail information, they can check the configuration space section in pci local bus specification document.
tw2809c fn787 5 rev. 1.00 page 21 of 130 february 27, 2014 pci register 00 address pci base address + 0x00 type read only 31 3 0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 device id 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vendor id [31:16] device id C it specifies tw2809 pci device id default value: 0x2809 [15:0] vendor id C it specifies tw2809 pci vendor id default value: 0x1 719 pci register 04 address pci base address + 0x04 type read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 status 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 command [31:16] status C it specifies tw2809 pci status: 66mhz capable, devsel timing is medium default value: 0x02a0 [15:0] command C it specifies tw2809 pci command: tw2809 use memory space only, but no i/o space. default value: 0x0007
tw2809c fn787 5 rev. 1.00 page 22 of 130 february 27, 2014 pci register 08 address pci base address + 0x08 type read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 class code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 class code revision id [31:8] class code C it specifies tw2809 pci class code default value: 0x048000 [7:0] revision id C it specifies tw2809 pci revision id 0: tw2809a1 1: tw2809 b1 2: tw2809c1 pci register 0c address pci base address + 0x0c type read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bist header type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 latency timer cache line size [31:24] bist C it specifies tw280 9 pci bist default value: 0x00 [23:16] header type C it specifies tw2809 pci header type default value: 0x00 [15:8] latency timer C it specifies tw2809 pci latency timer default value: 0x00 [7:0] cache line size C it specifies tw2809 pci cache line size default value: 0x00
tw2809c fn787 5 rev. 1.00 page 23 of 130 february 27, 2014 pci register 10 - 24 address pci base address + 0x10 C 0x24 type read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 base address registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register 10 (bart #0) C tw2809 has 64k byte memory space register 14 (bart #1) C reserved register 18 (bart #2) C reserved register 1c (bart #3) C reserved register 20 (bart #4) C reserved register 24 (bart #5) C reserved pci register 28 address pci base address + 0x28 type read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cardbus cis pointer 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] cardbus cis pointer C it specifies tw2809 pci cardbus cis pointer default value: 0x00
tw2809c fn787 5 rev. 1.00 page 24 of 130 february 27, 2014 pci register 2c address pci base address + 0x2 c type read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 subsystem id 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 subsystem vendor id [31:16] subsystem id C it specifies tw2809 pci subsystem id default value: 0x2809 [15:0] subsystem vendor id C it specifies tw2809 pci subsystem vendor id default value: 0x1719 pci register 30 address pci base address + 0x30 type read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 expansion rom base address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [ 31:0] expansion rom base address C it specifies tw2809 pci expansion rom base address default value: 0x00
tw2809c fn787 5 rev. 1.00 page 25 of 130 february 27, 2014 pci register 34 address pci base address + 0x34 type read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved capabilities pointers [31:8] reserved [7:0] capabilities pointer C it specifies tw2809 pci capabilities pointer default value: 0x00 pci register 38 address pci base address + 0x38 type read only 31 30 29 2 8 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] reserved
tw2809c fn787 5 rev. 1.00 page 26 of 130 february 27, 2014 pci register 3c address pci base address + 0x3c type read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 max_lat min grant 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 interrupt pin interrupt line [31:24] max_lat C it specifies tw2809 pci max_lat default value: 0x 48 [23:16] min_gnt C it specifies tw2809 pci min_gnt default value: 0x 20 [15:8] interrupt pin C it specifies tw2809 pci interrupt pin default value: 0x 01 [7:0] interrupt line C it specifies tw2809 pci interrupt line default value: 0x 00
tw2809c fn787 5 rev. 1.00 page 27 of 130 february 27, 2014 pin mux register definitions this section describestw2809 pin mux regsiter definitions. these regsiters shall be directly programmed by external host during power up. uart pin mux configuration address 0x8000_1404 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dbg 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [ 3 1] reserved [ 30 ] dbg C it specifies chip debug mode. to enable uart , this bit shall be set to low. [29:0] reserved address 0x8000_1408 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 uart1_e n uart0_e n mux_vo 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [ 3 1:20] reserved [19] uart1_en C it specifies pin mux control. to make pin h18 and h19 to be uart1, this bit shall be set to high. [18] uart0_en C it specifies pin mux control. to make pin h20 and g17 to be uart0, this bit shall be set to high. [17] mux_vo C it specifies pin mux control. to enable uart0/uart1, this bit shall be set to low. [16:0] reserved descriptions pin h20 and g17 is muxed by video input port 3 data bus [1:0] and uart0 . in order to m ake these two pins to be uart0 . pin h18 and h19 is muxed by video input port3 data bus[3:2]. in order to make these two pins to be uart 1 , both register 0x8000_1404 and 0x8000_1408 need to be programmed. ball num symbol pin mux mux condition tw2809 c uart1 h18 vi3_data[3] uart1_tx 8000_1404[30] = 1'b0 8000_1408[17] = 1'b0 8000_1408[19] = 1'b1 h19 vi3_data[2] uart1_rx 8000_1408[19] = 1'b1 tw2809 c uart0 h20 vi3_data[1] uart0_tx 8000_1404[30] = 1'b0 8000_1408[17] = 1'b0 8000_1408[18] = 1'b1 g17 vi3 _data[0] uart0_rx 8000_1408[18] = 1'b1
tw2809c fn787 5 rev. 1.00 page 28 of 130 february 27, 2014 gpio[7:0] pin mux configuration address 0x8000_1404 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dbg 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [ 3 1] reserved [ 30 ] dbg C it specifies chip debug mode. to enable gpio[7:0] , this bit shall be set to low. [29:0] reserved address 0x8000_1408 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gpio_e n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [ 3 1:21] reserved [20] gpio_en C it specifies pin mux control. to enable gpio[7:0] , this bit shall be set to high. [19:0] reserved descriptions gpio[7:0] is muxed with video output port 2. in order to enable gpio [7:0 ] , both register 0x8000_1404 and 0x8000_1408 need to be programmed. ball num symbol pin mux mux condition w4 vo2_data[7] gpio[7] 8000_1404[30] = 1'b0 8000_1408[20] = 1'b1 8000_1c40[7:0] controls gpio direction output: 1'b1 inpu t: 1'b0 y3 vo2_data[6] gpio[6] y4 vo2_data[5] gpio[5] y5 vo2_data[4] gpio[4] w5 vo2_data[3] gpio[3] v5 vo2_data[2] gpio[2] u5 vo2_data[1] gpio[1] y6 vo2_data[0] gpio[0]
tw2809c fn787 5 rev. 1.00 page 29 of 130 february 27, 2014 gpio[15:8] pin mux configuration address 0x8000_1400 type r /w 31 3 0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mux_vi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [ 3 1] mux_vi C it specifies vi/vo mux mode. to enable gpio[15 :8] and gipio[23:16] , this bit shall be set to low. [30:0] reserved address 0x8000_1408 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gpio_e n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31] gpio_en C it specifies pin mux control. to enable gpio[15:8 ] , this bit shall be set to high. [30:0] reserved descriptions gpio[15:8 ] is muxed with video output port 1. in order to enable gpio[15:8] , both register 0x8000_1400 and 0x8000_1408 need to be programmed. ball num symbol pin mux tw2809b mux condition d18 v o 1_data [7] gpio[15] 8000_1400[31] = 1'b1 8000_1408[31] = 1'b1 8000_1c40[15:8] controls gpio direction output: 1'b1 input: 1'b0 d19 vo1_data [6] gpio[14] d20 vo 1_data [5] gpio[13] c1 8 vo 1 _data[4] gpio[12] c19 vo 1_data [3] gpio[11] c20 vo 1_data [2] gpio[10] b19 vo 1_data [1] gpio[9] b20 vo 1_data [0] gpio[8]
tw2809c fn787 5 rev. 1.00 page 30 of 130 february 27, 2014 gpio[23:16] pin mux configuration address 0x8000_1400 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mux_vi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [ 3 1] mux_vi C it specifies vi/vo mux mode. to enable gpio[15:8] and gipio[23:16], this bit shall be set to low. [30:0] re served address 0x8000_1408 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gpio_e n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31] reserved [30] gpio_en C it specifies pin mux contr ol. to enable gipio[23:16], this bit shall be set to high. [29:0] reserved descriptions gpio[23:16 ] is muxed with video output port 0. in order to enable gpio[23:16] , both register 0x8000_1400 and 0x8000_1408 need to be programmed. ball num symbol pin m ux tw2809b mux condition g19 vo 0_data [7] gpio[23] 8000_1400[31] = 1'b1 8000_1408[30] = 1'b1 8000_1c40[23:16] controls gpio direction output: 1'b1 input: 1'b0 f17 vo 0_data [6] gpio[22] f18 vo 0_data [5] gpio[21] f19 vo 0_data [4] gpio[20] e18 vo 0 _data [3] gpio[19] e19 vo 0_data [2] gpio[18] e20 vo 0_data [1] gpio[17] d17 vo 0_data [0] gpio[16]
tw2809c fn787 5 rev. 1.00 page 31 of 130 february 27, 2014 gpio[31:24] pin mux configuration address 0x8000_1404 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dbg 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [ 3 1] reserved [ 30 ] dbg C it specifies chip debug mode. to enable gpio[31:24], this bit shall be set to low. [29:0] reserved address 0x8000_1408 type r /w 31 30 29 28 27 26 25 24 23 2 2 21 20 19 18 17 16 uart1_e n uart0_e n mux_vo 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [ 3 1:20] reserved [19] uart1_en C it specifies pin mux control. to enable gpio[31:24], this bit shall be set t o low. [18] uart0_en C it specifies pin mux control. to enable gpio[31:24], , this bit shall be set to low.. [17] mux_vo C it specifies pin mux control to enable gpio[31:24], , this bit shall be set to low. [16:0] reserved descriptions gpio[31:24 ] is muxed with video input port 3. in order to enable gpio[31:24] , both register 0x8000_1404 and 0x8000_1408 need to be programmed. ball num symbol pin mux tw2809b mux condition k20 vi 3_data [7] gpio[31] 8000_1404[30] = 1'b0 8000_1408[19:17] = 3'b000 8000_1 c40[31:24] controls gpio direction output: 1'b1 input: 1'b0 j18 vi 3_data [6] gpio[30] j19 vi 3_data [5] gpio[29] h17 vi 3_data [4] gpio[28] h18 vi 3_data [3] gpio[27] h19 vi 3_data [2] gpio[26] h20 vi 3_data [1] gpio[25] g17 vi 3_data [0] gpio[24]
tw2809c fn787 5 rev. 1.00 page 32 of 130 february 27, 2014 gpio[39:32] pin mux configuration address 0x8000_1404 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dbg 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [ 3 1] reserved [ 30 ] dbg C it spec ifies chip debug mode. to enable gpio[39:32 ], this bit shall be set to low. [29:0] reserved address 0x8000_1408 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mux_vo 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [ 3 1:17] reserved [16] mux_vo C it specifies pin mux control to enable gpio [39:32 ], this bit shall be set to low. [15:0] reserved descriptions gpio[39:32 ] is muxed with video input port 2. in order to enable gpio[39:32] , b oth register 0x8000_1404 and 0x8000_1408 need to be programmed. ball num symbol pin mux tw2809b mux condition m18 vi 2_data [7] gpio[39] 8000_1404[30] = 1'b0 8000_1408[16] = 1'b0 8000_1c4 4 [ 7 : 0 ] controls gpio direction output: 1'b1 input: 1'b0 m19 v i 2_data [6] gpio[38] l17 vi 2_data [5] gpio[37] l18 vi 2_data [4] gpio[36] l19 vi 2_data [3] gpio[35] k17 vi 2_data [2] gpio[34] k18 vi 2_data [1] gpio[33] k19 vi 2_data [0] gpio[32]
tw2809c fn787 5 rev. 1.00 page 33 of 130 february 27, 2014 gpio[47:40] pin mux configuration address 0x8000_1404 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dbg 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [ 3 1] reserved [ 30 ] dbg C it specifies chip debug mode. to enable gpio[47:40 ], this bit shall be set to low. [29:0] reserved descriptions gpio[47:40 ] is muxed with video input port 1. in order to enable gpio[47:40] , register 0x8000_1404 needs to be programmed. ball num symbol pin mux tw2809b mux condition r19 vi 1_data [7] gpio[47] 8000_1404[30] = 1'b0 8000_1c4 4 [ 15 : 8 ] controls gpio direction output: 1'b1 input: 1'b0 p17 vi 1_data [6] gpio[46] p18 vi 1_data [5] gpio[45] p19 vi 1_data [4] gpio[44] n18 vi 1_data [3] gpio[43] n19 vi 1_data [2] gpio[42] n20 vi 1_data [1] gpio[41] m17 vi 1_data [0] gpio[4 0]
tw2809c fn787 5 rev. 1.00 page 34 of 130 february 27, 2014 gpio[55:48] pin mux configuration address 0x8000_1408 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 spi_e uart1_e gpio_e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [ 3 1:24] rese rved [23] spi_e C it specifies spi enable. to enable gpio[55:48 ], this bit shall be set to low. [22] uart1_e C it specifies uart1 enable. to enable gpio[55:48 ], this bit shall be set to low. [21] gpio_e C it specifies gpio enable. to enable gpio[55:48 ], this bit shall be set to high. [20:0] reserved descriptions gpio[55:48 ] is muxed with video output port 3. in order to enable gpio[55:48] , register 0x8000_1408 needs to be programmed. ball num symbol pin mux tw2809b mux condition u9 vo3_data[7] gpio[55] 8000_1408[23:21] = 3'b001 8000_1c4 4 [ 23 : 16 ] controls gpio direction output: 1'b1 input: 1'b0 v8 vo3_data[6] gpio[54] u18 vo3_data[5] gpio[53] v18 vo3_data[4] gpio[52] u17 vo3_data[3] gpio[51] v19 vo3_data[2] gpio[50] w19 vo3_data[1] gpi o[49] w20 vo3_data[0] gpio[48]
tw2809c fn787 5 rev. 1.00 page 35 of 130 february 27, 2014 pdma register definitions this section describes pdma control module registers. pdma has t hree kind of operation and is explained seperately in this chapter. master mode pdma interrupt statu s register for fw address hif base address + 0x 48 type r /w 31 30 29 28 27 26 25 24 debug _en smbus err_int_st mmbus err_int_st 23 22 21 20 19 18 17 16 slv int_st perr int_st fatal int_st rx int_st tx int_st cfg int_st com int_st 15 14 13 12 11 10 9 8 - smbus err_int_en mm bus err_int_en 7 6 5 4 3 2 1 0 slv int_en perr int_en fatal int_en m_rx int_en m_tx int_en cfg int_en com int_en [ 31 ] debug_en C it specifies the debugging enable [ 30 : 26 ] reserved [ 25 ] smbus_err_int_st C it specifies the error of mbus for slave mode [ 2 4 ] mmbus_err_int_st C it specfies the error of mbus for master mode [ 23 ] reserved [ 22 ] slv_int_st C it specifies the information of slave interrupt [ 21 ] perr_int_st C it specifies the information of pci parity error interrupt. [ 20 ] fatal_int_st C it specifies the information of pci fatal error interrupt. [ 19 ] rx_int_st C it specifies the information of end of rx tranfer interrupt. [ 18 ] tx_int_st C it specifies the information of end of tx transfer interrupt. [ 17 ] cfg_int_st C it specifies the in formation of configuration interrupt. [ 16 ] com_int_st C it specifies the information of communcation interrupt. [ 15 : 10 ] reserved [ 09 ] smbus_err_int_en C it specifies the mbus error interrupt enable for slave mode [ 08 ] mmbus_err_int_en C it specifies the mbu s error interrupt enable for master mode [ 07 ] reserved [ 06 ] slv_int_en C it specifies the slave interrupt enable. [ 05 ] perr_int_en C it specifies parity error interrupt enable. [ 04 ] fatal_int_en C it specifies fatal error interrupt enable. [ 03 ] m_rx_int_en C it specifies the end of rx transfer interrupt enable. [ 02 ] m_tx_int_en C it specifies the end of tx transfer interrupt enable. [ 01 ] cfg_int_en C it specifies the configuration interrupt enable. [ 00 ] com_int_en C it specifies the command interrupt enable.
tw2809c fn787 5 rev. 1.00 page 36 of 130 february 27, 2014 descriptions pdma supports to manage the interrupt sperately between fw and host driver. s o t he interrupt register is only used by fw, not the host driver. even if these interrupts are enable d and the host driver interrupts , which addres s 0x4c are disable in the same bit, pci interrupt doesn t generate to host driver, but it is sent to fw. for example , fw enables tx transfer. then, it means the end of tx transfer interrupt to be sent into fw, not host driver. in initial time, fw shoul d enable pci interrupt enable bits. if pci interrupt enable bits are disable d , all of interrupt except com_int_en don t generate the interrupt. otherwise, pdma can keep the interrupt when pdma generate s the interrupt during com_in_en to be disable d . then p dma will send the interrupt after com_in_en to be enable d . pdma master tx and rx interrupt status register ( optional) address hif base address + 0x 60 type r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rx end tx end [31: 02 ] reserved [ 01 ] rx_end C it specifies end of rx transfer. [ 00 ] tx_end C it specifies end of tx transfer descriptions this register isn t used the normal operation. b ut s ometimes fw or host driver doesn t receive pdma interrupt after fi nishing the reading and writing data. in that time, fw or host driver could just check the end of transfer using polling.
tw2809c fn787 5 rev. 1.00 page 37 of 130 february 27, 2014 pdma master tx and r x endian control reg ister address hif base address + 0x 58 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 1 8 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m_r_endian [02:00] m_w_endian [02:00] s_r_endian [02:00] s_w_endian [02:00] [ 31 : 15] reserved [ 14:12 ] m_r_endian C it specifies the endian control of read data for master mode. [ 11] reserved [ 10:08 ] m_w_endian C it specifies the endian control of write data for master mode. [ 07] reserved [ 06:04 ] s_r_endian C it specifies the endian control of read data for slave mode. [ 03] reserved [ 02:00 ] s_w_endian C it specifies the endian control of write data f or slave mode. descriptions intel processor uses little endian , but tw2809 uses big endian . in the case host driver wants to change little endian to big endian or big endian to little endian. so our pdma is able to support it. the following table base s on the 8 byte which our bus width is. m_endian or s_endian data format 0 d ata[63:00] 1 d ata[39:32],data[47:40] ,data[55:48],data[63:56] , d ata[ 07 : 00 ],data[ 15 : 08 ] ,data[23:16],data[31:24] 2 d ata[ 47 : 40 ],data[ 39 : 32 ] ,data[63:56],data[55:48] , d ata[ 15 : 08 ],data[ 0 7 : 00 ] ,data[31:24],data[23:16] 3 data[31:24],data[23:16], data[ 15 : 08 ] ,d ata[ 07 : 00] , data[63:56],data[55:48], data[47:40] ,d ata[39:32 ] 4 data[55:48],data[63:56],d ata[39:32],data[47:40] , data[23:16],data[31:24],d ata[ 07 : 00 ],data[ 15 : 08 ] 5 d ata[ 07 : 00 ],data[ 15 : 08 ] ,d ata[23:16],data[31:24] , d ata[39:32],data[47:40] ,data[55:48],data[63:56] 6 d ata[ 15 : 08 ],data[ 07 : 00 ] ,data[31:24],data[23:16] , d ata[ 47 : 40 ],data[ 39 : 32 ] ,data[63:56],data[55:48] 7 data[23:16],data[31:24],d ata[ 07 : 00 ],data[ 15 : 08 ] , data[55:48],data[63:56],d ata[39:32] ,data[47:40]
tw2809c fn787 5 rev. 1.00 page 38 of 130 february 27, 2014 pdma master tx contr ol register address hif base address + 0x 64 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - m_tx 2d_formt[02:00] m_tx 2d_en 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m_tx start [ 31 : 19 ] reserved [ 18:17 ] m _tx_2d_format C it specifies the data format while tx 2d access. [ 16 ] m_tx_2d_en C it specifies tx 2d access enable. [ 15 : 01 ] reserved [ 00 ] m_tx_start C it specifies pci dma tx start request for master mode. descriptions host driver or fw should enable m _tx_start bit after writing pdma parameter registers such as tx start address, total length and tx buffer id. also m_tx_start bit is disabled automatically when tx transfer is finished. however, tx transfer means fw transfers some data into pci host or host driver reads some data from our external memory. pdma master tx buffe r id register address hif base address + 0x 68 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 m_tx_frame_id[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m_tx_frame_i d[15:00] [31: 00 ] m_tx_frame_id C it specifies the buffer id which fw defines in our frame memory. descriptions the m_tx_buf_id , which is indicated a position in our external memory, is decided by fw at initicial time, not host driver. if host driver wants to know a value of this register, host driver should get the value from fw using communication protocol.
tw2809c fn787 5 rev. 1.00 page 39 of 130 february 27, 2014 pdma master tx targe t start address regi ster address hif base address + 0x 6c type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 m_t x_tar_addr[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m_tx_tar_addr[15:00] [31: 00 ] m_x_tar_addr C it specifies the target address which is in host driver. descriptions when fw transfers some data or host driver receives data , fw should know the ta rget address which is the internal buffer in host driver. fw can know the target address using the communication protocol with host driver. pdma master tx total length register address hif base address + 0x 70 type r/w 31 30 29 28 27 26 25 24 23 22 21 2 0 19 18 17 16 m_tx_total_length[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m_tx_total_length[15:00] [31: 00 ] m_tx_total_length C it species the tx total length. pdma master tx 2d xy start register address hif base address + 0x a4 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 m_tx_2d_x_start[07:00] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m_tx_2d_y_start[10:00] [31: 24 ] reserved [ 23 : 16 ] m_tx_2d_x_start C it speifies the start of x coordinate for tx 2d transfer [ 15 : 11 ] reserved [ 10 : 0 0] m_tx_2d_y_start C it speifies the start of y coordinate for tx 2d transfer
tw2809c fn787 5 rev. 1.00 page 40 of 130 february 27, 2014 pdma master rx contr ol register address hif base address + 0x 78 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 m_rx_2d format[02:00] m_rx 2d_en 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m_rx start [3 1 : 19 ] reserved [ 18:17 ] m_rx_2d_format C it specifies the data format for rx 2d transfer [ 16 ] m_rx_2d_en C it specifies rx 2d transfer enable. [ 15 : 01 ] reserved [ 00 ] m_rx_start C it specifies rx dma start request. d escriptions host driver or fw can enable the bit, m_rx_start , after setting pdma rx parameter registers such as tx start address and total length. also m_rx_start bit is disabled automatically by pdma when tx transfer is finished. however, rx transfer means host driver writes some data into our external memory. pdma master rx buffe r id register address hif base address + 0x 7c type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 m_rx_frame_id[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m_rx_ frame_id[15:00] [31: 00 ] m_rx_frame_id C it specifies the rx frame id which fw defines in our frame memory. descriptions the m_rx_buf_id , which is indicated a buffer in our external memory, is decided by fw, not host driver at initicial time. if host driver wants to know the value of m_rx_buf_id , host driver should get the value from fw using commulation protocol.
tw2809c fn787 5 rev. 1.00 page 41 of 130 february 27, 2014 pdma master rx sourc e start address regi ster address hif base address + 0x 80 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 m_rx_s_addr[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m_rx_s_addr[15:00] [31: 00 ] m_rx_s_addr C it specifies the source address which is the start address of internal buffer in host driver. descriptions if host driver wants to send some data i nto our buffer or fw wants to read some data from host driver s buffer, fw or host driver set up m_rx_s_addr which is in host driver s start buffer address. so fw should gets the information from host driver using communication register. pdma master rx total length registe r address hif base address + 0x 84 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 m_rx_total_length[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m_rx_total_length[15:00] [31: 00 ] m_rx_total_length C it species the rx t otal length. pdma master rx 2d xy start register address hif base address + 0x a8 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 m_rx_2d_x_start[07:00] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m_rx_2d_y_start[10:00] [31: 24 ] reserved [ 23 : 16 ] m_2d_rx_x_start C it speifies the start of x coordinate for rx 2d transfer [ 10 : 0 0] m_2d_rx_y_start C it speifies the start of y coordinate for rx 2d transfer
tw2809c fn787 5 rev. 1.00 page 42 of 130 february 27, 2014 slave mode host pci driver should control registers for reading and writing. pdma slave tx control register address hif base address + 0x 24 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 s_tx_2d format[0 1 : 00] s_tx 2d_en 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s _tx_ strn s_tx start [3 1 : 19 ] reserved [ 18:17 ] s_tx_2d_format C it specifies the data format while tx 2d access [ 16 ] s_tx_2d_en C it specifies tx 2d access enable [ 15:05 ] reserved [ 04 ] s_tx_strn C it specifies the single tranfer enable [ 03:01 ] reserved [ 00 ] s_tx_start C it specifies dma start request descriptions c urrently, our host driver only supports the single tranfer, not burst transfer for slave mode. if host driver uses the single transfer, pci should enable s_tx_strn bit. host driver or fw enables s_tx_start bit after finishing to write other tx setting registers such as tx start address and length. in addition, the performace is so slowly. b ecause pci host driver is waiting to write data until receving pci interrupt after each 128 word transfer. this means pdma internal buffer to be limited, 128 word.
tw2809c fn787 5 rev. 1.00 page 43 of 130 february 27, 2014 pdma slave tx buffer id register address hif base address + 0x 28 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s_tx_buf_id[05:00] [31: 06 ] reserved [ 05 : 0 0] s_tx_buf_id C it specifies tx buffer id descriptions the s_tx_buf_id, which is indicated a buffer id in our external memory, is decided by fw, not pci host driver. so pci host driver should get the buffer id from fw using commulation protocol. pdma slave tx total length register address hif base address + 0x 2c type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 s_tx_total_length[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s_tx_total_length[15:00] [31: 00 ] s_tx_total_length C it specifies the tx total length descriptions when pci driver transfers some data into our external memory, pci driver writes the total length, which is word count, into the register.
tw2809c fn787 5 rev. 1.00 page 44 of 130 february 27, 2014 pdma slave tx 2d xy start register address hif base address + 0x ac type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 s_tx_2d_x_start[07:00] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s_tx_2d_y_start[10:00] [31: 24 ] reserved [ 23 : 16 ] s_tx_2d_x_start C it specifies the start of x for tx 2d accessing for slave mode [15:11] reserved [ 10 : 0 0] s_tx_2d_y_start C it spec ifies the start of y for tx 2d accessing for slave mode pdma slave rx contro l register address hif base address + 0x 34 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 s_rx_2d foramt[0 1 :00] s _rx_2d _en 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s_rx start [3 1 : 19 ] reserved [ 18:17 ] s_rx_2d_format C it specifies the data format while rx 2d access [ 16 ] s_rx_2d_en C it specifies rx 2d access enable [ 15 : 01 ] reserved [ 00:00 ] s_rx_start C it specifies the starting of rx dma descriptions pci host d river or fw enables s_rx_start bit after finishing to write other rx setting registers such as rx start address and length. if pci host driver write some data using 2d access, pci host driver decides the written format. the information is decides by fw.
tw2809c fn787 5 rev. 1.00 page 45 of 130 february 27, 2014 pdma slave rx buffer id register address hif base address + 0x 38 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s_r_buf_id[05:00] [31: 06 ] reserved [ 05 : 0 0] s_r_buf_id C it specifies the extern al rx buffer id descriptions the s_r_buf_id , which is one of buffer id in our external memory, is decided by fw, not pci host driver. so pci host driver should get the s_r_buf_id from fw using commulation protocol. pdma slave rx total length regist er address hif base address + 0x 3c type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 s_rx_total_length[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s_rx_total_length[15:00] [31: 00 ] s_rx_total_length C it specifies the rx total length descri ptions when pci driver transfers some data into our external memory or fw receives some data from internal buffer of pci host driver, pci driver writes the total length, which is word count, into the register. pdma slave rx 2d xy start register address hif base address + 0x 88 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 s_rx_2d_x_start[07:00] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s_rx_2d_y_start[10:00] [31: 24 ] reserved [ 23 : 16 ] s_rx_2d_x_start C it specifies the start of x for rx 2d accessing for slave mode [ 15 : 11 ] reserved [ 10 : 0 0] s_rx_2d_y_start C it specifies the start of y for rx 2d accessing for slave mode
tw2809c fn787 5 rev. 1.00 page 46 of 130 february 27, 2014 pdma slave interrupt status register address hif base address + 0x 44 type r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rx _ end rx _ emt tx _ end tx _ full [31: 04 ] reserved [ 03 ] rx_end C it specifies the end of rx transfer [ 02 ] rx_emt C it specifies the empty of rx fifo [ 01 ] tx_end C it specifies the end of tx transfer [ 00 ] tx_full C it specifies the full of tx fifo descriptions host driver or fw has to check pci interrupt status register when host driver or fw receives pci interrupt. if slv_st bit in pci interrupt status is asserted, host driver or fw should check data in this register. then pci host or fw can know what kind of the interrupt for slave mode.
tw2809c fn787 5 rev. 1.00 page 47 of 130 february 27, 2014 communication between fw and host these registers are used to communicate between fw and host driver. in the further , fw and host driver will be decided some comm ands for proper processing. the communication co mmand register from host driver address hif base address + 0x 8c type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cmd_from_host[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cmd_from_host[15:00] [ 31:00 ] cmd_from_host C it specifies a communication command which host driver sends into fw. descriptions pdma generates the interrupt to fw when host driver writes a command in this register. f w will operate the proper task after reading data in the pci interrupt serive rountine of fw. for example, host driver sends a command which is ready the decoding bitstream after sending the decoding bitstream into a external vld buffer of tw2809. in that time, host driver uses this register. the first extra comm unication register from host driver address hif base address + 0x 54 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cmd_extra1_from_host[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cmd_ extra1_from_host[15:00] [ 31:00 ] cmd_ extra1_from_host C it specifies the first extra communication data descriptions sometime s , host driver needs to have the first extra data with a command. in that time, host driver uses the register. h o st driver has to write the register before writing the communication register, communication register from host . for example, host driver wants to send the command, which is the bitstream size, after sending the bitstream for decoding. in that time, host driver writes the bitstream size into this register. t hen fw can know the bitstream size after reading this register.
tw2809c fn787 5 rev. 1.00 page 48 of 130 february 27, 2014 the second extra com munication register from host driver address hif base address + 0x 58 type r /w 31 30 29 28 27 26 25 24 23 22 21 2 0 19 18 17 16 cmd_extra2_from_host[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cmd_extra2_from_host[15:00] [ 31:00 ] cmd_ extra2_from_host C it specifies the second extra communication data the communication co mmand register from fw add ress hif base address + 0x 90 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cmd_from_fw[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cmd_from_fw[15:00] [ 31:00 ] cmd_from_fw C it specifies a communication command which fw sends into host. descriptions pdma s able to generate the the interrupt to host driver when fw writes this register. after that, host driver will operate the proper task after reading the command. for example, fw wants to recevice a bitstream of slice for decoding. in tha t time, fw writes a command into the register. a nd host driver recevices the command. then, host driver will download the bitstream into external vld buffer of tw2809. in the futher, fw and host driver will define the value of command.
tw2809c fn787 5 rev. 1.00 page 49 of 130 february 27, 2014 the first extra com munication register from fw address hif base address + 0x 94 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 extra1_com_from_fw[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 extra1_com_from_fw[15:00] [ 31:00 ] extra1_com_ from_fw C it specifies the first extra communication data. descriptions sometime s , fw needs to have extra data with a command. in that time, fw uses current register. fw has to write the register before writing the commnication register, communication register from fw . for example, fw sends the command, which is the request bitstream, to host driver. in that time, fw also send a buffer id which is defined the external vld buffer. t hen fw writes the buffer id into the register. therefore host driver can know buffer id after r eading this register. the second extra com munication register from fw address hif base address + 0x 98 type r /w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 extra2_com_from_fw[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 extra2_com_from_fw[15:00] [ 31:00 ] extra2_com_from_fw C it specifies the second extra communication data descriptions sometime s , fw needs to have extra data with a communication command. in that time, fw uses the register. fw has to write the register before writin g the communication register, communication command register from fw . for example, fw wants to send the command, which is the end of encoding, to host driver. in that time, fw also send the buffer id which is defined in external vlc buffer, and a total length which is the bitstream size of current slice. t hen fw uses extra #1 and #2 register. fw write the buffer id into the register, the first communication extra register from fw . a lso current register is written the total length.
tw2809c fn787 5 rev. 1.00 page 50 of 130 february 27, 2014 interrupt status fo r pci host driver pci host should read this registers when it receives pci interrupt from tw2809. pdma interrupt statu s register for pci channel address hif base address + 0x 4c type r /w 31 30 29 28 27 26 25 24 int_ edge_en smbus _ err_int_st mmbus _ err _int_st 23 22 21 20 19 18 17 16 wdog _ int_st slv _ int_st perr _ int_st fatal _ int_st rx _ int_st tx _ int_st cfg _ int_st com _ int_st 15 14 13 12 11 10 9 8 smbus _ err_ int_en mmbus _ err_ int_en 7 6 5 4 3 2 1 0 wdog _ int_en slv _ int_en perr _ int_en fatal _ int_en rx _ int_en tx _ int_en cfg _ int_en com _ int_en [ 31 ] int_edge_en C it specfies the edge trigger interrupt. [ 30 : 26 ] reserved [ 25 ] smbus_err_int_st C it specfies the error of mbus for slave mode [ 24 ] mmbus_err_int_st C it specfies the error of mbus f or master mode [ 23 ] wdog_int_st C it specfies the information of watch dog. [ 22 ] slv_int_st C it specfies the interrupt for slave mode (debug mode) [ 21 ] perr_int_st C it specifies the information of parity error interrupt. [ 20 ] fatal_int_st C i t specfies the information of fatal error interrupt. [ 19 ] rx_int_st C it specifies the information of end of rx transfer. [ 18 ] tx_int_st C it specifies the information of end of tx transfer. [ 17 ] cfg_int_st C it specifies the information of config interrupt. [ 16 ] com_int_st C it specifies the information of command interrupt. [ 15 : 10 ] reserved [ 09 ] smbus_err_int_en C it specfies the mbus error interrupt enable for slave mode [ 08 ] mmbus_err_int_en C it specfies the mbus error interrupt enable for ma ster mode [ 07 ] wdog_int_en C it specifies watch dog interrupt enable. [ 06 ] slv_int_en C it specifies slave mode interrupt enable. [ 05 ] perr_int_en C it specifies pci parity error interrupt enable. [ 04 ] fatal_int_en C it specifies pci fatal error interrup t enable. [ 03 ] rx_int_en C it specifies rx end interrupt enable. [ 02 ] tx_int_en C it specifies tx end interrupt enable. [ 01 ] cfg_int_en C it specifies configuration interrupt enable. [ 00 ] com_int_en C it specifies command interrupt enable.
tw2809c fn787 5 rev. 1.00 page 51 of 130 february 27, 2014 descriptions o ur pci interrupt supports the level trigger or edge trigger. default is the level trigger interrupt. so if host driver wants to change the edge trigger, host driver enables int_edge_en bit. global control register definitions this section describes ctr module registers. normal interrupt address ctr base address + 0x00 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 jpeg gpio uart1 uart0 i2c dsm pci aud tme tsmd tsme vlc vld egf hpm 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 jen gpen urt1e n urt0en i2cen dsmen pcien auden tmeen tsmde tsmeen vlcen vlden egfen hpmen [31] reserved [30] jpeg C it specifie s the normal interrupt from jpeg module [29] gpio C it specifi es the normal interrupt from gpio module [28] uart1 C it specifies the normal interrupt from uart1 module [27] uart0 C it specifies the normal interrupt from uart0 module [26] i2c C it specifies the normal interrupt from i2c module [25] dsm C it specifies the normal interrupt from dsm module [24] pci C it specifies the normal inte rrupt from pci module [23] aud C it specifies the normal interrupt from aud module [22] tme C it specifies the normal interrupt from tme module [21] tsmd C it specifies the normal interrupt from tsm decode module [20] tsme C it specifies the normal interru pt from tsm encode module [19] vlc C it specifies the normal interrupt from vlc module [18] vld C it specifies the normal interrupt from vld module [17] egf C it specifies the normal interrupt from egf module [16] hpm C it specifies the normal interrupt fr om hpm module [15] reserved [ 14 :0] enables C it specifies the normal interrupt enable for each corresponding module {30:16} descriptions dcm shall follow the interrupt protocol described in interrupt scheme section.
tw2809c fn787 5 rev. 1.00 page 52 of 130 february 27, 2014 codec video channel address ctr base address + 0x04 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cur_dec_ch 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cur_enc_ch [31:21] reserved [2 0 :16] cur_dec_ch C it specifies current decode video channel [15:5] reserved [4:0] cur_enc_ch C it specifies current encode video channel descriptions dcm shall follow the interrupt protocol described in interrupt scheme section.
tw2809c fn787 5 rev. 1.00 page 53 of 130 february 27, 2014 software r eset address ctr base address + 0x08 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 audd di nt uart1 uart0 i2c it vld hpm tme mbc vlc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 jpg egf spr tsm rtb ipd dec enc aud dsm vof vif pci hif ddr mpu [31 : 27 ] reserved [26 ] audd - reset the audio decoding block [25 ] dint - reset the de - interlace block [2 4 ] uart1 - reset the uart1 block [23 ] uart0 - reset the uart0 block [22] i2c - reset the i2c block [ 21 ] it - reset the it block for decoding [ 20 ] vld - reset the vld block for decoding [ 19 ] hpm - reset the hpm block for decoding [ 18 ] tme - reset the tme block for encoding [ 17 ] mbc - reset the mbc block for encoding [ 16 ] vlc - reset the vlc block for encoding [ 15 ] jpg - reset jpeg [ 14 ] egf - reset the egf block for encoding or decoding [ 13 ] spr - reset the spr block for encoding or decoding [ 12 ] tsm - reset the tsm block for encoding or decoding [ 11 ] rtb - reset the rtb block for encoding or decoding [ 10 ] ipd - reset the ipd block for encoding or decoding [ 09 ] dec - reset the all of decoder block [ 08 ] enc - reset the all of encoder block [ 07 ] aud - reset the audio encoding block [ 06 ] dsm - reset the sub sample block [ 05 ] vof - reset the vof block [ 04 ] vif : reset the vif block [ 03 ] pci : reset the pci block [ 02 ] hif : reset the hif bloc k [ 01 ] ddr : reset the ddr controller [ 00 ] mpu : reset the arm and amba
tw2809c fn787 5 rev. 1.00 page 54 of 130 february 27, 2014 description this register is used to control the tw2809 reset. host or fw write low to assert tw2809 blocks reset. host or fw write high to release the reset. if you want to ass ert reset to all of encoder block, you write low into enc bit. t hen, all of encoder blocks will be asserted the reset. a lso you write low into dec bit, all of decoder blocks will be asserted the reset.
tw2809c fn787 5 rev. 1.00 page 55 of 130 february 27, 2014 timer period register address ctr base address + 0x0c type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 timer3_period timer2_period 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 timer1_period timer0_period [31:24] timer3_period C it specifies timer 3 period. [23:16] timer2_period C it specifies t imer 2 period. [15:8] timer1_period C it specifies timer 1 period. [7:0] timer0_period C it specifies timer 0 period. descriptions the timer period specifies the timer unit in terms of system cycle. if timer_period equals 0, then timer counter increments every cycle. if timer_period equals 1, then timer counter increments every 2 cycles. encode mode register address ctr base address + 0x10 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e nc _mode [31:1] reserved [0] enc_mode C it specifies the operation mode for the video pipeline.
tw2809c fn787 5 rev. 1.00 page 56 of 130 february 27, 2014 fast interrupt address ctr base address + 0x14 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 timer0 timer1 timer2 timer3 vout vin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t0en t1en t2en t3en voen vien [31] timer0 C it specifies the fast interrupt from timer0 [30] timer1 C it specifies the fast interrupt from timer1 [29] timer2 C it specifies the fast interrupt from timer2 [28] timer3 C it specifies the fast interrupt from timer 3 [27:18] reserved [17] vout C it specifies the fast interrupt from vout module [16] vin C it specifies the fast interrupt from vin module [12:2] reserved C it specifies the fast interrupt source. [15] t0en C it specifies t he fast interrupt enable for timer0 [14] t1en C it specifies the fast interrupt enable for timer1 [13] t2en C it specifies the fast interrupt enable for timer2 [12] t3en C it specifies the fast interrupt enable for timer3 [11:2] reserved [1] voen C it s pecifies the fast interrupt enable for vout module [0] vien C it specifies the fast interrupt enable for vin module descriptions dcm shall follow the interrupt protocol described in interrupt scheme section.
tw2809c fn787 5 rev. 1.00 page 57 of 130 february 27, 2014 encoder parameter register 0 address ctr base address + 0x20 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vertical_size 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 horizontal_size [31:27] reserved [26:16] vertical_size C it specifies video vertical size in pixel. [15:11] reserved [10:0] horizontal_size C it specifies video horizontal size in pixel. encoding parameter register 1 address ctr base address + 0x24 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rc_type bframe_num prog initial_qp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 frame_rate idrperiod [31:30] rc_type C video rate control type: 00 C cqp, 01 - cbr, 10 - vbr, 11 - hbr [29:28] b f rame _num C it specifies how many b frames between two reference frame [27] prog C it specifies if curren video sequence is progre ssive video. 1 - progressive video 0 C interleaved video [26:16] initial_qp C it specifies initial qp for the video encoding [15:8] frame_rate C it specifies encoding frame rate [7:0] idrperiod C it specifies idr distance in terms of frame count
tw2809c fn787 5 rev. 1.00 page 58 of 130 february 27, 2014 encoder parameter register 2 address ctr base address + 0x28 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 v ideo _ bit _ rate [31:16] reserved [15:0] video_bit_rate C it specifies current video sequence en coding bit rate in terms of kbps encoder parameter register 3 address ctr base address + 0x2c type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lp_flag lp_dis loopfilter_alphaoffset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 loopfilter_beltaof fset [31] lp_flag [30] lp_dis C it specifies loop filter disable [29:24] reserved [23:16] loopfilter_alphaoffset [15:8] reserved [7:0] loopfilter_beltaoffset
tw2809c fn787 5 rev. 1.00 page 59 of 130 february 27, 2014 timer 0 count address ctr base address + 0x30 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 timer_count 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] timer_coun t C it specifies timer value timer 1 count address ctr base address + 0x34 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 timer_count 15 1 4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] timer_coun t C it specifies timer value timer 2 count address ctr base address + 0x38 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 timer_count 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31 :0] timer_coun t C it specifies timer value timer 3 count address ctr base address + 0x3c type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 timer_count 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] timer_coun t C it specifies timer val ue
tw2809c fn787 5 rev. 1.00 page 60 of 130 february 27, 2014 encoder parameter register 4 address ctr base address + 0x40 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lp_flag 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] lp_flag descriptions: please refer to tw2809 sw user manual for more details on how to set encoder paramters. encoder parameter register 5 address ctr base address + 0x44 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lp_flag 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] lp_flag - descriptions: pleas e refer to tw2809 sw user manual for more details on how to set encoder paramters.
tw2809c fn787 5 rev. 1.00 page 61 of 130 february 27, 2014 encoder parameter register 6 address ctr base address + 0x48 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lp_flag 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] lp_flag descriptions: please refer to tw2809 sw user manual for more details on how to set encoder paramters. encoder parameter register 7 address ctr base address + 0x4c type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lp _flag 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] lp_flag descriptions: please refer to tw2809 sw user manual for more details on how to set encoder paramters. encoder parameter register 8 address ctr base address + 0x50 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lp_flag 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] lp_flag descriptions: please refer to tw2809 sw user manual for more details on how to set encoder paramters.
tw2809c fn787 5 rev. 1.00 page 62 of 130 february 27, 2014 encoder parameter register 9 address ctr bas e address + 0x54 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lp_flag 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] lp_flag - descriptions: please refer to tw2809 sw user manual for more details on how to set encoder paramters. en coder parameter register 10 address ctr base address + 0x58 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lp_flag 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] lp_flag descriptions: please refer to tw2809 sw user manual for more de tails on how to set encoder paramters.
tw2809c fn787 5 rev. 1.00 page 63 of 130 february 27, 2014 encoder parameter register 11 address ctr base address + 0x5c type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lp_flag 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] lp_flag descriptions: pleas e refer to tw2809 sw user manual for more details on how to set encoder paramters. encoder parameter register 12 address ctr base address + 0x60 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lp_flag 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] lp_flag descriptions: please refer to tw2809 sw user manual for more details on how to set encoder paramters. watch dog limit address ctr base address + 0x64 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 watch_dog_limit 1 5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] watch_dog_limit C it species the watch dog interrupt counter value. if watch dog counter reaches this value, it will raise interrupt to host.
tw2809c fn787 5 rev. 1.00 page 64 of 130 february 27, 2014 timer control register address ctr base address + 0x68 typ e r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wd g _en go3 go2 go1 go0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hold3 hold2 hold1 hold0 [31] wdg_en C it species watch dog enable [30:20] reserved [19] go3 C it species timer3 control go s ignal [18] go2 C it species timer2 control go signal [17] go1 C it species timer1 control go signal [16] go0 C it species timer0 control go signal [15:4] reserved [3] hold3 C it species timer3 control hold signal [2] hold2 C it species timer 2 control hold signal [1] hold1 C it species timer1 control hold signal [0] hold0 C it species timer0 control hold signal descriptions hold C it species timer hold control. this is a level control signal 0 : counter is disabled and held in the cur rent state 1: counter is allowed to count go C it resets and starts the timer counter. this is a pulse control register 0 : no effets on the timers 1: if hold is hight, the counter register is zeroed and begins counting on the next clock.
tw2809c fn787 5 rev. 1.00 page 65 of 130 february 27, 2014 timer 1 c ontrol register address ctr base address + 0x44 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hold go [31:2] reserved [1] hold C it species timer hold control. this is a level control signal 0 : counter is disabled and held in the current state 1: counter is allowed to count [0] go C it resets and starts the timer counter. this is a pulse control register 0 : no effets on the timers 1: if hold is hight, the counter register is zeroed and begins counting on the next clock. timer 2 control register address ctr base address + 0x48 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hold go [31:2] reserved [1] hold C it species ti mer hold control. this is a level control signal 0 : counter is disabled and held in the current state 1: counter is allowed to count [0] go C it resets and starts the timer counter. this is a pulse control register 0 : no effets on the timers 1: if hold is hight, the counter register is zeroed and begins counting on the next clock.
tw2809c fn787 5 rev. 1.00 page 66 of 130 february 27, 2014 timer 3 control register address ctr base address + 0x4c type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ho ld go [31:2] reserved [1] hold C it species timer hold control. this is a level control signal 0 : counter is disabled and held in the current state 1: counter is allowed to count [0] go C it resets and starts the timer counter. this is a puls e control register 0 : no effets on the timers 1: if hold is hight, the counter register is zeroed and begins counting on the next clock.
tw2809c fn787 5 rev. 1.00 page 67 of 130 february 27, 2014 host interface register definitions this section descrips host interface module registers. the hif register spa ce is partitioned into thre sections: 1. normal hif register space 2. pdma slave register space 3. pdma master register space the pdma register space is defined in the next chapter. hif interrupt address hif_baseaddress + 0x00 type ro 31 30 29 28 27 2 6 25 24 23 22 21 20 19 18 17 16 tx_f mx_f tr_e tx_e mr_e mx_e c_busy int 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 int_e [31:24] reserved [23] tx_f C it specifies target transmit buffer fullness. 1 : the buffer is full. 0 : the buffer is not full [2 2] mx_f C it specifies master transmit buffer fullness. 1 : the buffer is full. 0 : the buffer is not full [21] tr_e C it specifies target receving buffer emptyness. 1 : the buffer is empty. 0 : the buffer is not empty [20] tx _e C it specifies target t ransmit buffer emptyness. 1 : the buffer is empty. 0 : the buffer is not empty [19] mr_e C it specifies master receving buffer emptyness. 1 : the buffer is empty. 0 : the buffer is not empty [18] mx_e C it specifies master transmit buffer emptyness. 1 : the buffer is empty. 0 : the buffer is not empty [17] c_busy C cbus masters can only read this bit. if this bit is high, cbus master can not issue next serial flash command. [16] int C it specifies hif interrupt [15:1] reserved [0] int_e C it specifi es hif interrupt enable. 0: interrupt disable. 1: interrupt enable. default is 1. descriptions hif shall follow the interrupt protocol described in interrupt scheme section.
tw2809c fn787 5 rev. 1.00 page 68 of 130 february 27, 2014 device id address hif_baseaddress + 0x04 type ro 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 device_id 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vendor_id [31:16] device_id C it specifies device id. default is 0x2809 [15:0] vendor_id C it specifies vendor id. default is 0x1797 pci class code address hif_baseaddress + 0x08 type ro 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 class_code [31:24] reserved [23:0] class code C it specifies pci class code. the default value is 0x48000
tw2809c fn787 5 rev. 1.00 page 69 of 130 february 27, 2014 pci sub - system id address hi f_baseaddress + 0x0c type ro 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 subsys_id 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 subsys_ vendor_id [31:16] subsys_id C it specifies pci subsystem id. default is 0x2809 [15:0] subsys_vendor_id C it specifie s pci subsystem vendor id. default is 0x1797 pci header info address hif_baseaddress + 0x10 type ro 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 header rev_id 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 max_lat min_gnt [31:24] header C it specifies pci header [23:16] rev _id C it specifies revision id [15:8] max_lat C it specifies pci max latency [23:16] min_gnt C it specifies pci min grant timing
tw2809c fn787 5 rev. 1.00 page 70 of 130 february 27, 2014 ddr mode register address hif base address + 0x14 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 1 8 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mr pd wr dll tm cl bt bl [31:16] reserved [15:14] mr C it specifies mode register definition [13] reserved [12] pd C it specifies pd mode. 0: fast exit, 1: slow exit [11:9] wr C it specifies the writ e recovery [8] dll C it specifies the dll reset. 0: no, 1: yes [7] tm C it specifies test mode. 0: normal operation, 1: test [6:4] cl C it specifies the cas latency [3] bt C it specifies burst type. 0: sequenential, 1: interleaved [2:0] bl C it specif ies the burst length mode register definition 0 0 mode regisger (mr) 0 1 extended mode register (emr) 1 0 extended mode register (emr2) 1 1 extended mode register (emr3) mr write recovery 0 0 0 reserved 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 reserved 1 1 1 reserved mr cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 reserved cl
tw2809c fn787 5 rev. 1.00 page 71 of 130 february 27, 2014 burst length 0 0 0 reserved 0 0 1 reserved 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved bl
tw2809c fn787 5 rev. 1.00 page 72 of 130 february 27, 2014 ddr timing control register 0 address hif base address + 0x18 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wtr wl rfc rc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rp rcd ras rrd half_cl [31:30] wtr C write recovery time [29:26] wl C write latency [25:20] rfc - refresh interval [19:16] rc C activate to activate delay (same bank) [15:12] rp C precharge period [11:8] rcd C activate to read or write delay [7:4] ras C activate to precharge delay [3:2] rrd C activate to activate delay (different bank) [1:0] half_cl C half cas latency descriptions fw programs ddr timing control register based on ddr speed grade. all timing parameters need to be converted into cycle count in the current core frequency. these parameters are ddr vendor dependent and please refer to tw2809 application not e for more details. ddr timing control register 1 address hif base address + 0x1c type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mrd 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 power_up_delay [31:2 0 ] reserved [ 19 : 16 ] m rd - load mode cycle time [1 5 : 0 ] power_up_delay - ddr power up delay cycle descriptions fw programs ddr timing control register based on ddr speed grade. all timing parameters need to be converted into cycle count in the current core frequency. these parameters are ddr vendor dependent and please refer to tw2809 application note for more details.
tw2809c fn787 5 rev. 1.00 page 73 of 130 february 27, 2014 fw pdma control register address hif base address + 0x24 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 int_en - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - t_type r/w go [ 31 ] int_en C interrupt enable bit. when f/w want to finish pdma access and go bit is disables, interrupt is assert to arm after the last transfer. [3 0 : 3 ] reserved [ 2 ] t_ type C power pc interfac e type. 00 : interrupt is assert to power pc when pdma s fifo is prepared data. 01 : interrupt is only assert to power pc when pdma prepare the first 64 words. [ 1 ] r/w C read or write select bit. when this bit is set, data in external memo ry is transferred to the power pc. [ 0 ] go C dma request. user should enable the bit after pdma command register is written. when this bit is diables, pdma transfer is disabled. fw pdma command register address hif base address + 0x28 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 buf_id [31: 6 ] reserved [ 5 : 0 ] buf_id C linear buffer id ( up to 64 linear buffer )
tw2809c fn787 5 rev. 1.00 page 74 of 130 february 27, 2014 i2 c register definitions i 2 c interrupt register address i2c_baseaddr ess + 0x00 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 i2c rd interrupt status (clear) i2c wr interrupt status(clea r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i2c rd interrupt enable i2c wr interrupt enable [17] i2c read interrupt sta tus (clear) - C fw wirte high to clear 1 : happened i2c read interrupt ( the status bit can be cleared by writing bit 17 1. ) [16] i2c write interrupt status(clear) - C fw wirte high to clear 1 : happened i2c write interrupt ( the status bit can be cleared by writing bit 16 1. ) [1] i2c read interrupt enable C fw wirte high to enable [0] i2c write interrupt enable C fw wirte high to enable descriptions i 2 c read/write interrupt status bits can be cleared by arm
tw2809c fn787 5 rev. 1.00 page 75 of 130 february 27, 2014 i 2 c mode select register address i2c_baseaddress + 0x04 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 master/slave mode select [ 0 0] master/slave mode select descriptions 1 is master mode, 0 is slave mode. default is 1. i2c slave address slave address r/w 0 1 1 1 1 0 0 1 = read 0 = write i2c write register0, register1, register2, register3 address i2c_baseaddress + 0x20 type i2c write/arm read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 write reg3 write reg2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write reg1 write reg 0 [31:24 ] write reg31 C i2 c write data byte 3 [23 : 16] write reg30 C i2 c write data byte 2 [15 : 8] write reg 29 C i2 c write data byte 1 [7 : 0] write reg28 C i2 c writ e data byte 0 descriptions i2c writes to this register and fw read from this register.
tw2809c fn787 5 rev. 1.00 page 76 of 130 february 27, 2014 i2c write register4, register5, register6, register7 address i2c_baseaddress + 0x24 type i2c write/arm read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 w rite reg7 write reg6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write reg5 write reg 4 [31:24 ] write reg31 C i2 c write data byte 7 [23 : 16] write reg30 C i2 c write data byte 6 [15 : 8] write reg 29 C i2 c write data byte 5 [7 : 0] write reg28 C i2 c write data byte 4 descriptions i2c writes to this register and fw read from this register. i2c write register8, register9, register10, register11 address i2c_baseaddress + 0x28 type i2c write/arm read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 write reg11 wri te reg10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write reg9 write reg 8 [31:24 ] write reg31 C i2 c write data byte 11 [23 : 16] write reg30 C i2 c write data byte 10 [15 : 8] write reg 29 C i2 c write data byte 9 [7 : 0] write reg28 C i2 c write data byte 8 descript ions i2c writes to this register and fw read from this register.
tw2809c fn787 5 rev. 1.00 page 77 of 130 february 27, 2014 i2c write register12, register13, register14, register15 address i2c_baseaddress + 0x2c type i2c write/arm read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 write reg 15 write r eg 14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write reg 13 write reg 12 [31:24 ] write reg31 C i2 c write data byte 15 [23 : 16] write reg30 C i2 c write data byte 14 [15 : 8] write reg 29 C i2 c write data byte 13 [7 : 0] write reg28 C i2 c write data byte 12 descripti ons i2c writes to this register and fw read from this register. i2c write register16, register17, register18, register19 address i2c_baseaddress + 0x30 type i2c write/arm read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 write reg19 write reg18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write reg17 write reg16 [31:24 ] write reg31 C i2 c write data byte 19 [23 : 16] write reg30 C i2 c write data byte 18 [15 : 8] write reg 29 C i2 c write data byte 17 [7 : 0] write reg28 C i2 c write data byte 16 descriptions i2c writes to this register and fw read from this register.
tw2809c fn787 5 rev. 1.00 page 78 of 130 february 27, 2014 i2c write register20, register21, register22, register23 address i2c_baseaddress + 0x34 type i2c write/arm read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 write reg23 write reg22 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write reg21 write reg20 [31:24 ] write reg31 C i2 c write data byte 23 [23 : 16] write reg30 C i2 c write data byte 22 [15 : 8] write reg 29 C i2 c write data byte 21 [7 : 0] write reg28 C i2 c write data byte 20 descriptions i2 c writes to this register and fw read from this register. i2c write register24, register25, register26, register27 address i2c_baseaddress + 0x38 type i2c write/arm read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 write reg27 write reg26 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write reg25 write reg24 [31:24 ] write reg31 C i2 c write data byte 27 [23 : 16] write reg30 C i2 c write data byte 26 [15 : 8] write reg 29 C i2 c write data byte 25 [7 : 0] write reg28 C i2 c write data byte 24 descriptions i2c writ es to this register and fw read from this register.
tw2809c fn787 5 rev. 1.00 page 79 of 130 february 27, 2014 i2c write register28, register29, register30, register31 address i2c_baseaddress + 0x3c type i2c write/arm read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 write reg31 write reg30 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write reg29 write reg28 [31:24 ] write reg31 C i2 c write data byte 31 [23 : 16] write reg30 C i2 c write data byte 30 [15 : 8] write reg 29 C i2 c write data byte 29 [7 : 0] write reg28 C i2 c write data byte 28 descriptions i2c wri tes to this register and fw read from this register. i2c read register0, register1, register2, register3 address i2c_baseaddress + 0x80 type i2c read/arm write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 read reg3 read reg2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read reg1 read reg0 [31:24] read reg3 C i2c read data byte 3 [23 : 16] read reg2 C i2c read data byte 2 [15 : 8] read reg1 C i2c read data byte 1 [7 : 0] read reg0 C i2c read data byte 0 descriptions arm writes this register and i2c reads f rom this register
tw2809c fn787 5 rev. 1.00 page 80 of 130 february 27, 2014 i2c read register4, register5, register6, register7 address i2c_baseaddress + 0x84 type i2c read/arm write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 read reg7 read reg6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read reg5 r ead reg4 [31:24] read reg3 C i2c read data byte 7 [23 : 16] read reg2 C i2c read data byte 6 [15 : 8] read reg1 C i2c read data byte 5 [7 : 0] read reg0 C i2c read data byte 4 descriptions arm writes this register and i2c reads from this register i2c read r egister8, register9, register10, register11 address i2c_baseaddress + 0x88 type i2c read/arm write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 read reg11 read reg10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read reg9 read reg8 [31:24] read reg3 C i2c read data byte 11 [23 : 16] read reg2 C i2c read data byte 10 [15 : 8] read reg1 C i2c read data byte 9 [7 : 0] read reg0 C i2c read data byte 8 descriptions arm writes this register and i2c reads from this register
tw2809c fn787 5 rev. 1.00 page 81 of 130 february 27, 2014 i2c read register12, register13, register14, register15 address i2c_baseaddress + 0x8c type i2c read/arm write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 read reg 15 read reg 14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read reg 13 read reg 12 [31:24] read reg3 C i2c read data byte 15 [23 : 16] read reg2 C i2c read data byte 14 [15 : 8] read reg1 C i2c read data byte 13 [7 : 0] read reg0 C i2c read data byte 12 descriptions arm writes this register and i2c reads from this register i2c read register16, register17, register18, register19 address i2c_baseaddress + 0x90 type i2c read/arm write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 read reg19 read reg18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read reg17 read reg16 [31:24] read reg3 C i2c read data byte 19 [23 : 16] read reg2 C i2c read data byte 18 [15 : 8] read reg1 C i2c read data byte 17 [7 : 0] read reg0 C i2c read data byte 16 descriptions arm writes this register and i2c reads from this register
tw2809c fn787 5 rev. 1.00 page 82 of 130 february 27, 2014 i2c read register20,register21,register22,register23 address i2c_baseadd ress + 0x94 type i2c read/arm write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 read reg23 read reg22 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read reg21 read reg20 [31:24] read reg3 C i2c read data byte 23 [23 : 16] read reg2 C i2c read data byte 2 2 [15 : 8] read reg1 C i2c read data byte 21 [7 : 0] read reg0 C i2c read data byte 20 descriptions arm writes this register and i2c reads from this register i2c read register24,register25,register26,register27 address i2c_baseaddress + 0x98 type i2c re ad/arm write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 read reg27 read reg26 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read reg25 read reg 24 [31:24] read reg3 C i2c read data byte 27 [23 : 16] read reg2 C i2c read data byte 26 [15 : 8] read reg1 C i2c read data byte 25 [7 : 0] read reg0 C i2c read data byte 24 descriptions arm writes this register and i2c reads from this register
tw2809c fn787 5 rev. 1.00 page 83 of 130 february 27, 2014 i2c read register28, register29, register30, register31 address i2c_baseaddress + 0x9c type i2c read/arm write 3 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 read reg31 read reg30 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read reg29 read reg28 [31:24] read reg3 C i2c read data byte 31 [23 : 16] read reg2 C i2c read data byte 30 [15 : 8] read reg1 C i2c read data byte 29 [7 : 0] read reg0 C i2c read data byte 28 descriptions arm writes this register and i2c reads from this register
tw2809c fn787 5 rev. 1.00 page 84 of 130 february 27, 2014 i2c master mode protocol i2c master mode protocol is for i2c read/write soc internal registers. from the i2c int erface waveform, it should be the following protocol to finish read/write operations. write cbus 32 bit re gisters: i2c start byte 0: i2c device id (7b0111100) + 1b0 byte1 : 8h00 byte 2: cbus_addr[7:0] byte 3: cbus_addr[15:8] byte 4: cbus_addr[23:16] byt e 5: cbus_addr[31:24] byte 6: cbus_wdata[7:0] byte 7: cbus_wdata[15:8] byte 8: cbus_wdata[23:16] byte 9: cbus_wdata[31:24] byte a: 8h01 ( this is write command ) i2c stop read cbus 32 bit reg isters: i2c start byte 0: i2c device id (7b0111100) + 1b0 byt e 1: 8h00 byte 2: cbus_addr[7:0] byte 3: cbus_addr[15:8] byte 4: cbus_addr[23:16] byte 5: cbus_addr[31:24] i2c stop i2c start byte 0: i2 c device id (7b0111100) + 1b0 byte 1 : 8h08 byte 2 : 8h00 ( this is read command ) i2c stop i2c start byte 0: i2c d evice id (7b0111100) + 1b0 byte 1: 8h00 i2c stop
tw2809c fn787 5 rev. 1.00 page 85 of 130 february 27, 2014 i2c start byte 0: i2c device id (7bit) + 1b1 byte 1: read cbus_rdata[7:0] byte 2: read cbus_rdata[15:8] byte 3: read cbus_rdata[23:16] byte 4: read cbus_rdata[31:24] i2c stop
tw2809c fn787 5 rev. 1.00 page 86 of 130 february 27, 2014 uart register definitions uart interrupt enable register address uart_baseaddress + 0x00 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 uart i nterrupt e nable [0] uart interrupt enable descriptions uar t interrupt can be enabled by writing bit 0 1. uart interrupt status register address uart_baseaddress + 0x04 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 uart interrupt status [0] uart inte rrupt status descriptions uart interrupt status bit can be cleared by writing bit 0 1.
tw2809c fn787 5 rev. 1.00 page 87 of 130 february 27, 2014 uart line control register(lcr) address uart_baseaddress + 0x2c type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1 0 9 8 7 6 5 4 3 2 1 0 divisor latch access bit break control bit stick parity bit. even parity select parity enable specify the number of generated stop bits select number of bits in each character [7] divisor latch access bit. 1 C the divisor latches can be accessed 0 C the normal registers are accessed [6] break control bit 1 C the serial out is forced into logic 0 (break state). 0 C break is disabled [5] stick parity bit. 0 C stick parity disabled 1 - if bits 3 an d 4 are logic 1, the parity bit is transmitted and checked as logic 0. if bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1. [4] even parity select 0 C odd number of 1 is transmitted and checked in each word (data and parity combined). in other words, if the data has an even number of 1 in it, then the parity bit is 1. 1 C even number of 1 is transmitted in each word. [3] parity enable 0 C no parity 1 C parity bit is generated on each outgoing character and is checked on each incoming one. [2] specify the number of generated stop bits 0 C 1 stop bit 1 C 1.5 stop bits when 5 - bit character length selected and 2 bits otherwise note that the receiver always checks the first s top bit only. [ 1:0 ] select number of bits in each character 00 C 5 bits 01 C 6 bits 10 C 7 bits 11 C 8 bits descriptions the line control register allows the specification of the format of the asynchronous data communication used. a bit in the re gister also allows access to the divisor latches, which define the baud rate. reading from the register is allowed to check the current settings of the communication. reset value: 00000011b
tw2809c fn787 5 rev. 1.00 page 88 of 130 february 27, 2014 uart divisor latch byte 1 register(lsb) address uart_baseaddres s + 0x20 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 the lsb of the divisor latch [7:0] the lsb of the divisor latch C see descriptions below descriptions there are 2 clock divisor registers that together form one 16 - bit. the registers can be accessed when the 7th (dlab) bit of the line control register is set to 1. at this time the above registers at addresses 0 - 1 cant be accessed. the divisor latches can be accessed by setting the 7th bi t of lcr to 1. you should restore this bit to 0 after setting the divisor latches in order to restore access to the other registers that occupy the same addresses. the 2 bytes form one 16 - bit register, which is internally accessed as a single number. y ou should therefore set all 2 bytes of the register to ensure normal operation. the register is set to the default value of 0 on reset, which disables all serial i/o operations in order to ensure explicit setup of the register in the software. the value se t should be equal to (system clock speed) / (16 x desired baud rate). the internal counter starts to work when the lsb of dl is written, so when setting the divisor, write the msb first and the lsb last.
tw2809c fn787 5 rev. 1.00 page 89 of 130 february 27, 2014 uart divisor latch byte 2 register (msb) address u art_baseaddress + 0x24 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 the m sb of the divisor latch [7:0] the msb of the divisor latch C see descriptions below descriptions there are 2 clock di visor registers that together form one 16 - bit. the registers can be accessed when the 7th (dlab) bit of the line control register is set to 1. at this time the above registers at addresses 0 - 1 cant be accessed. the divisor latches can be accessed by set ting the 7th bit of lcr to 1. you should restore this bit to 0 after setting the divisor latches in order to restore access to the other registers that occupy the same addresses. the 2 bytes form one 16 - bit register, which is internally accessed as a s ingle number. you should therefore set all 2 bytes of the register to ensure normal operation. the register is set to the default value of 0 on reset, which disables all serial i/o operations in order to ensure explicit setup of the register in the softwar e. the value set should be equal to (system clock speed) / (16 x desired baud rate). the internal counter starts to work when the lsb of dl is written, so when setting the divisor, write the msb first and the lsb last.
tw2809c fn787 5 rev. 1.00 page 90 of 130 february 27, 2014 uart internal interrupt ena ble register(ier) address uart_baseaddress + 0x24 type r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved. should be logic 0. modem status interrupt receiver line status interrupt transmitter holdin g register empty interrupt received data available interrupt [7: 4] reserved. should be logic 0. [3] modem status interrupt 0 C disabled 1 C enabled [ 2 ] receiver line status interrupt 0 C disabled 1 C enabled [ 1 ] transmitter holding r egister empty interrupt 0 C disabled 1 C enabled [ 0 ] received data available interrupt 0 C disabled 1 C enabled descriptions reset value: 00h
tw2809c fn787 5 rev. 1.00 page 91 of 130 february 27, 2014 uart interrupt identification register(iir) address uart_baseaddress + 0x28 type r/w 3 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved. should be logic 1 for compatibility reserved. should be logic 0. bit 3 bit 2 bit 1 bit 0 [7:6] reserved C should be logic 1 for comp atibility [5:4] reserved C should be logic 0 [3 :1 ] bit 3 /2/1 - the following table displays the list of possible interrupts along with the bits they ena ble, priority, and their source and reset control. [0] bit 0 - it indicates that an interrupt is pending when its logic 0. when its 1 C no interrupt is pending. bit 3 bit 2 bit 1 priority i nterrupt type interrupt source interrupt reset 0 1 1 1st receiver line status parity, overrun or framing errors or break interrupt reading the line status register 0 1 0 2nd receiver data available fifo trigger level reached fifo drops below trigger l evel 1 1 0 2nd timeout indication theres at least 1 character in the fifo but no character has been input to the fifo or read from it for the last 4 char times. reading from the fifo (receiver buffer register) 0 0 1 3rd transmitter holding register emp ty transmitter holding register empty writing to the transmitter holding register or reading iir. 0 0 0 4th modem status cts, dsr, ri or dcd. reading the modem status register. descriptions the iir enables the programmer to retrieve what is the c urr ent highest priority pending interrupt. reset value: c1h
tw2809c fn787 5 rev. 1.00 page 92 of 130 february 27, 2014 uart fifo control register(fcr) address uart_baseaddress + 0x28 type write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 define the receiver fifo interrupt trigger level ignored clr_tx_ fifo clr_rx_ fifo ignored [7:6] define the receiver fifo interrupt trigger level 00 C 1 byte 01 C 4 bytes 10 C 8 bytes 11 C 14 bytes [5:3] ignored [2] clr_tx_fifo - writing a 1 to bit 2 clears the transmitter fifo and resets its logic. the shift register is not cleared, i.e. transmitting of the current character continues. [1] clr_rx_fifo - writing a 1 to bit 1 clears the receiver fifo and resets its logic. but it doesnt clear the shift register, i.e. receiving of the current character continues. [0] ignored - (used to enable fifos in ns16550d). since this uart only supports fifo mode, this bit is ignored. descriptions reset value : 11000000b
tw2809c fn787 5 rev. 1.00 page 93 of 130 february 27, 2014 uart modem control register(mcr) address uart_baseaddress + 0x30 type write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ignored loopback out2 out1 rts_ctrl dtr_ctrl [7:5] ignored [ 4 ] loop back - loop back mode. 0 C normal operation , 1 C loopback mode. when in loopback mode, the serial output signal (stx_pad_o) is set to logic 1. the signal of the transmitter shift register is internally connected to the input of the receiver shift register. the following connections are made: dtr ? dsr }, { rts ? cts }, { out1 ? ri }, { out2 ? dcd } [ 3 ] out2 - in loopback mode, connected to data carrier detect (dcd) input. [ 2 ] o ut1 - in loopback mode, connected ring indicator (ri) signal input [ 1 ] rts_ctrl - request to send (rts) signal control . 0 C rts is 1 , 1 C rts is 0 [0] dtr_ctrl - data terminal ready (dtr) signal control . 0 C d tr is 1 , 1 C dtr is 0 descriptions reset value: 0
tw2809c fn787 5 rev. 1.00 page 94 of 130 february 27, 2014 uart line status register(lsr) address uart_baseaddress + 0x34 type read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 all error indicat or transmitter empty indicator transmit fifo is empty break interrupt (bi) indicator framing error (fe) indicator parity error (pe) indicator overrun error (oe) indicator data ready (dr) indicator [7] all error indicator 1 C at least one parity error, framing error or break indications have been received and are inside the fifo. the bit is cleared upon reading from the register. 0 C otherwise. [6] transmitter empty indicator 1 C both the transmitter fifo and transmitter shift register are empty. the bit is cleared when data i s being been written to the transmitter fifo. 0 C otherwise [5] transmit fifo is empty. 1 C the transmitter fifo is empty. generates transmitter holding register empty interrupt. the bit is cleared when data is being been written to the transmitter fifo. 0 C otherwise [4] break interrupt (bi) indicator 1 C a break condition has been reached in the current character. the break occurs when the line is held in logic 0 for a time of one character (start bit + data + parity + stop bit). in that c ase, one zero character enters the fifo and the uart waits for a valid start bit to rec eive next character. the bit is cleared upon reading from the register. generates receiver line status interrupt. 0 C no break condition in the current character [3] framing error (fe) indicator 1 C the received character at the top of the fifo did not have a valid stop bit. of course, generally, it might be that all the following data is corrupt. the bit is cleared upon reading from the register. generates receiver line status interrupt. 0 C no framing error in the current character [2] parity error (pe) indicator 1 C the character that is currently at the top of the fifo has been received wi th parity error. the bit is cleared upon reading from the register. generates receiver line status interrupt. 0 C no parity error in the current character [1] overrun error (oe) indica tor 1 C if the fifo is full and another character has been received in the receiver shift register. if another character is starting to arrive, it will overwrite the data in the shift register but the f ifo will remain intact. the bit is cleared upon reading from the register. generates receiver line status interrupt. 0 C no overrun state
tw2809c fn787 5 rev. 1.00 page 95 of 130 february 27, 2014 [0] data ready (dr) indicator. 1 C at least one cha racter has been received and is in the fifo. 0 C no characters in the fifo descriptions the register displays the current state of uart line.
tw2809c fn787 5 rev. 1.00 page 96 of 130 february 27, 2014 uart modem status register(msr) address uart_baseaddress + 0x38 type read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 comp_ dcd comp_ ri comp_ dsr comp_ cts ddcd i ndicator teri detector ddsr i ndicator dcts i ndicator [7] comp_dcd - complement of the dcd input or equals to out2 in loopback mode. [6] comp_ri - complement of the ri input or equals to out1 in loopback mode. [5] comp_dsr - complement of the dsr input or equals to dtr in loopback mode. [4] comp_cts - complement of the cts input or equ als to rts in loopback mode. [3] ddcd indicator - delta data carrier detect (ddcd) indicator 1 C the dcd line has changed its state. [2] teri detector - trailing edge of ring indicator (teri) detector. the ri line has changed its state from low to high state. [1] ddsr indicator - delta data set ready (ddsr) indicator 1 C the dsr line has changed its state. [0] dcts indicator - delta clear to send (dcts) indicator 1 C the cts line has changed its state. descriptions the register displays the current state of the modem control lines. also, four bits also provide an indication in the state of one of the modem status lines. these bits are set to 1 when a change in corresponding line has been detected and they are reset when the re gister is being read.
tw2809c fn787 5 rev. 1.00 page 9 7 of 130 february 27, 2014 uart receiver buffer address uart_baseaddress + 0x20 type read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rx_buf 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] rx_buf C receiver buffer descriptions receiver fi fo output uart transmitter holding register address uart_baseaddress + 0x20 type write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 tx_buf 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [31:0] tx_buf C transmitter buffer descriptions transmit fi fo input
tw2809c fn787 5 rev. 1.00 page 98 of 130 february 27, 2014 gpio register definitions gpio interrupt enable register address gpio_baseaddress + 0x00 type write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gpio interrupt status clear 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gp io interrupt enable [16] gpio interrupt status clear - fw can clear gpio interrupt by writing high to this bit. [00] gpio interrupt enable - gpio interrupt can b e enabled by writing high to this bit. descriptions gpio interrupt status clear bi t can clear the interrupt status bi t by writing bit 16 1.
tw2809c fn787 5 rev. 1.00 page 99 of 130 february 27, 2014 gpio interrupt status register address gpio_baseaddress + 0x00 type read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gpio interrupt status [00] gpio interrupt status - gpio set this bit to high to interrupt fw. descriptions gpio line driving register0 address gpio_baseaddress + 0x30 type write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gpio line d river 31:24 gpio line driver 23:16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gpio line driver 15:8 gpio line driver 7:0 [31: 24 ] gpio line driver 31: 24 C output data from gpio 31 to 24 [ 23 : 16 ] gpio line driver 23 : 16 C output data from gpio 23 to 16 [ 15 : 8 ] g pio line driver 15 : 8 C output data from gpio 15 to 8 [ 7 : 0 ] gpio line driver 7 : 0 C output data from gpio 7 to 0 descriptions gpio line driver 31 : 0
tw2809c fn787 5 rev. 1.00 page 100 of 130 february 27, 2014 gpio line driving register1 address gpio_baseaddress + 0x34 type write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gpio line driver 5 5 : 48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gpio line driver 47:40 gpio line driver 39:32 [ 23 : 16 ] gpio line driver 55 : 48 C output data from gpio 55 to 48 [ 15 : 8 ] g p io line driver 47 : 40 C output data from gpio 47 to 40 [ 7 : 0 ] gpio line driver 39 : 32 C output data from gpio 39 to 32 descriptions gpio line driver 55 : 32 gpio line control register0 address gpio_baseaddress + 0x40 type write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gpio direction control 31:24 gpio direction control 23:16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gpio direction control 15:8 gpio direction control 7:0 [31:24] gpio direction control 31:24 C input and output pin directi on control from gpio 31 to 24 1 : output, 0: input [23:16] gpio direction control 23:16 C input and output pin direction control from gpio 23 to 16 1 : output, 0: input [15:8] gpio direction control 15:8 C input and output pin dir ection control from gpio 15 to 8 1 : output, 0: input [7:0] gpio direction control 7:0 C input and output pin direction control from gpio 7 to 0 1 : output, 0: input descriptions gpio line control register0 : input/output control 31 : 0
tw2809c fn787 5 rev. 1.00 page 101 of 130 february 27, 2014 gpio line control register1 address gpio_baseaddress + 0x44 type write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gpio direction control 55:48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gpio direction control 47:40 gpio direction contr ol 39:32 [ 23 : 16 ] gpio direction control 55 : 48 C input and output pin direction control from gpio 55 to 48 1 : output, 0: input [ 15 : 8 ] gpio direction control 47 : 40 C input and output pin direction control from gpio 47 to 40 1 : output, 0: input [ 7 : 0 ] gpio direction control 39 : 32 C input and output pin direction control from gpio 39 to 32 1 : ou tput, 0: input descriptions gpio line control register1 : input/output control 55 : 32 gpio line load register0 address gpio_baseaddress + 0x20 type read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gpio line load 31:24 gpio line load 23:16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gpio line load 15:8 gpio line load 7:0 [31: 24 ] gpio line load 31: 24 C input pin from gpio 31 to 24 [ 23 : 16 ] gpio line load 23 : 16 C input pin from gpio 23 to 16 [ 15 : 8 ] g pio line load 15 : 8 C inp ut pin from gpio 15 to 8 [ 7 : 0 ] gpio line load 7 : 0 C input pin from gpio 7 to 0 descriptions gpio line load 31 : 0
tw2809c fn787 5 rev. 1.00 page 102 of 130 february 27, 2014 gpio line load register1 address gpio_baseaddress + 0x24 type read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gpio lin e load 55:48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gpio line load 47:40 gpio line load 39:32 [ 23 : 16 ] gpio line load 55 : 48 C input data from gpio 55 to 48 [ 15 : 8 ] g pio line load 47 : 40 C input data from gpio 47 to 40 [ 7 : 0 ] gpio line load 39 : 32 C input data from gpio 39 to 32 descriptions gpio line load 55 : 32
tw2809c fn787 5 rev. 1.00 page 103 of 130 february 27, 2014 peripheral timing this section describ es timing restrictions tw2809 p eripheral interface ports such as video interface interfac e, audio interface, and i2c. timings for other industry standard p eripheral such as pci and ddr2 are not corvered in this data sheet. customers can refer to related document for details timing information. video interface tw2809 supports 4 video input ports and four video output ports. thei r timing information are covered here. figure 17 . video input port t iming diagram note: 1. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. parameter symbol min (note 1) typ max (note 1) units 4.62 (108mhz) 6.76 (74mhz) 9.26 (54mhz) 18.52 (27mhz) 9.25 (108mhz) 13.51 (74mhz) 18.51 (54mhz) 37.03 (27mhz) input data setup time t 3 3 ns input data hold time t 4 1.5 ns input clock period t 2 8.78 38.8 ns input clock half period t1 4.39 19.45 ns table 3 . video input port ac timing
tw2809c fn787 5 rev. 1.00 page 104 of 130 february 27, 2014 figure 18 . video output port ti ming diagram parameter symbol min (note1) typ max (note1) units output clock half pe riod t1 4.39 4.62 (108m h z ) 19.45 ns 6.76 ( 74mhz ) 9.26 (54m hz ) 18.52 (27m hz ) output clock period t2 8.78 9.25 ( 108m hz ) 38.8 ns 13.51 (74m hz ) 18.51 (54m hz ) 37.03 (27m hz ) output data delay t3 2.6 5.2 ns table 4 . video output port ac timing note: 1. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
tw2809c fn787 5 rev. 1.00 page 105 of 130 february 27, 2014 audio interface this section describs audio interface port timing. tw2809 audio interfaces follows industry standard i2s protocal with modifications to support multi - channel au dio. figure 19 . audio input port tim ing diagram figure 20 - 1 . audio output port timing diagram parameter symbol min typ max units asynr,adatr,adatm propagation delay ta_pd 0.6 2 ns aclk p high pulse duration ta_hw 37 ns aclkp low pulse duration ta_lw 74 ns asynp, adatp setup time ta_su 36 ns asynp, adatp hold time ta_h 35 ns table 5 . audio input port ac timing note: 1. t a_lw min value and t a_su min value are f s=48khz mode only. if fs < 48khz, these min values are more bigger. high period of aclkr/aclkp is 27mhz one clock period.
tw2809c fn787 5 rev. 1.00 page 106 of 130 february 27, 2014 i2c interface this section describs i2c interface timing for t w2809. figure 21 . i2c port timing di agram table 6 . i2c input port ac ti ming note: 1. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
tw2809c fn787 5 rev. 1.00 page 107 of 130 february 27, 2014 pci interface this section describs pci interface timing for tw2 809. the pci of the tw2809 is designed to be satisfied with the protocol and electrical features of the pci local bus specification, revision 2.2 32bit/33mhz (66mhz). the pci interface requires a minimum of 47 pins for a target - only device to handle dat a and addressing, interface control, arbitration, and system functions. figure 22 . pci pin list
tw2809c fn787 5 rev. 1.00 page 108 of 130 february 27, 2014 system pins clk in clock provides timing for all transactions on pci and is an input to every pci device. all other pci signals, except nrst , and nintd , are sampled on the rising edge of clk and all other timing parameters are defined with respect to this edge. pci operates up to 33 mhz and, in general, the minimum frequency is dc (0 hz). nrst in reset is used to bring pci - specific registers, sequencers, and signals to a consistent state. what effect nrst has on a device beyond the pci sequencer is beyond the scope of this specification, except for reset states of required pci configuration registers. a device that can wake the system while in a powered down bus state has additional requirements related to nrst . refer to the pci power management interface specification for details. anytime nrst is asserted, all pci output signals must be driven to their benign state. in gene ral, this means they must be asynchronously tri - stated. nreq and ngnt must both be tristated (they cannot be driven low or high during reset). to prevent ad , nc/be , and par signals from floating during reset, the central resource may drive these lines duri ng reset (bus parking) but only to a logic low level; they may not be driven high. nrst may be asynchronous to clk when asserted or deasserted. although asynchronous, deassertion is guaranteed to be a clean, bounce - free edge. except for configuration acces ses, only devices that are required to boot the system will respond after reset. address and data pins ad[31:0] t/s address and data are multiplexed on the same pci pins. a bus transaction consists of an address2 phase followed by one or more data phas es. pci supports both read and write bursts. the address phase is the first clock cycle in which nframe is asserted. during the address phase, ad[31:0] contain a physical address (32 bits). for i/o, this is a byte address; for configuration and memory, it is a dword address. during data phases, ad[07:0] contain the least significant byte (lsb) and ad[31:24] contain the most significant byte (msb). write data is stable and valid when nirdy is asserted; read data is stable and valid when ntrdy is asserted. da ta is transferred during those clocks where both nirdy and ntrdy are asserted. nc/be[3:0] t/s bus command and byte enables are multiplexed on the same pci pins. during the address phase of a transaction, nc/be[3:0] define the bus command. during the data phase, nc/be[3:0] are used as byte enables. the byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. nc/be[0] applies to byte 0 (lsb) and nc/be[3] applies to byte 3 (msb). par t/s parity is even3 parity ac ross ad[31:0] and nc/be[3:0] . parity generation is required by all pci agents. par is stable and valid one clock after each address phase. for data phases, par is stable and valid one clock after either nirdy is asserted on a write transaction or ntrdy is asserted on a read transaction. once par is valid, it remains valid until one clock after the completion of the current data phase. ( par has the same timing as ad[31:0] , but it is delayed by one clock.) the master drives par for address and write data phas es; the target drives par for read data phases. interface control pins nframe s/t/s cycle frame is driven by the current master to indicate the beginning and duration of an access. nframe is asserted to indicate a bus transaction is beginning. while nfra me is asserted, data transfers continue. when nframe is deasserted, the transaction is in the final data phase or has completed. nirdy s/t/s cycle frame is driven by the current master to indicate the beginning and duration of an access. nframe is asserte d to indicate a bus transaction is beginning. while nframe is asserted, data transfers continue. when nframe is deasserted, the transaction is in the final data phase or has completed. ntrdy s/t/s target ready indicates the target agents (selected device s) ability to complete the current data phase of the transaction. ntrdy is used in conjunction with nirdy . a data phase is completed on any clock both ntrdy and nirdy are asserted. during a read, ntrdy indicates that valid data is present on ad[31:0] . dur ing a write, it indicates the target is prepared to accept data. wait cycles are inserted until both nirdy and ntrdy are asserted together. nstop s/t/s stop indicates the current target is requesting the master to stop the current transaction.
tw2809c fn787 5 rev. 1.00 page 109 of 130 february 27, 2014 nlock s/t/ s lock indicates an atomic operation to a bridge that may require multiple transactions to complete. when nlock is asserted, non - exclusive transactions may proceed to a bridge that is not currently locked. a grant to start a transaction on pci does not gua rantee control of nlock . control of nlock is obtained under its own protocol in conjunction with ngnt . it is possible for different agents to use pci while a single master retains ownership of nlock . locked transactions may be initiated only by host bridge s, pci - to - pci bridges, and expansion bus bridges. refer to appendix f for details on the requirements of nlock .. idsel in initialization device select is used as a chip select during configuration read and write transactions. ndevsel s/t/s device select , when actively driven, indicates the driving device has decoded its address as the target of the current access. as an input, ndevsel indicates whether any device on the bus has been selected. arbitration pins (bus masters only) nreq t/s request indicat es to the arbiter that this agent desires use of the bus. this is a point - to - point signal. every master has its own nreq which must be tri - stated while nrst is asserted. ngnt t/s grant indicates to the agent that access to the bus has been granted. this i s a point - to - point signal. every master has its own ngnt which must be ignored while nrst is asserted. error reporting pins nperr s/t/s parity error is only for the reporting of data parity errors during all pci transactions except a special cycle. the n perr pin is sustained tri - state and must be driven active by the agent receiving data (when enabled) two clocks following the data when a data parity error is detected. the minimum duration of nperr is one clock for each data phase that a data parity error is detected. (if sequential data phases each have a data parity error, the nperr signal will be asserted for more than a single clock.) nperr must be driven high for one clock before being tri - stated as with all sustained tri - state signals. nserr o/d sys tem error is for reporting address parity errors, data parity errors on the special cycle command, or any other system error where the result will be catastrophic. if an agent does not want a non - maskable interrupt (nmi) to be generated, a different report ing mechanism is required. nserr is pure open drain and is actively driven for a single pci clock by the agent reporting the error. the assertion of nserr is synchronous to the clock and meets the setup and hold times of all bused signals. however, the res toring of nserr to the deasserted state is accomplished by a weak pullup (same value as used for s/t/s) which is provided by the central resource not by the signaling agent. this pullup may take two to three clock periods to fully restore nserr . the agent that reports nserr to the operating system does so anytime nserr is asserted. interrupt pins (optional) nint o/d interrupt is used to request an interrupt. exactly how the idsel pin is driven is left to the discretion of the host/memory bridge or syste m designer. this signal has been designed to allow its connection to one of the upper 21 address lines, which are not otherwise used in a configuration access. however, there is no specified way of determining idsel from the upper 21 address bits. therefor e, the idsel pin must be supported by all targets. devices must not make an internal connection between an ad line and an internal idsel signal in order to save a pin. the only exception is the host bridge, since it defines how idsel s are mapped. idsel gen eration behind a pci - to - pci bridge is specified in the pci - to - pci bridge architecture specification. how a system generates idsel is system specific; however, if no other mapping is required, the following example may be used. the idsel signal associated w ith device number 0 is connected to ad[16] , idsel of device number 1 is connected to ad[17] , and so forth until idsel of device number 15 is connected to ad[31] . for device number 17 - 31, the host bridge should execute the transaction but not assert any of the ad[31:16] lines but allow the access to be terminated with master - abort. twenty - one different devices can be uniquely selected for configuration accesses by connecting a different address line to each device an asserting one of the ad[31:11] lines at a time. the issue with connecting one
tw2809c fn787 5 rev. 1.00 page 110 of 130 february 27, 2014 of the upper 21 ad lines to idsel to the appropriate ad line. this does, however, create a very slow slew rate on idsel , causing it to be in an invalid logic state most of the time, as shown in figure 23 with xxxx marks. figure 23 . configuration read figure 24 illustrates a real transaction and starts with an address phase which occurs when nframe is asserted for the first time and occurs on clock2. during the address phase, ad[31:0] contain a valid address and nc/be[3:0] contain a valid bus command. figure 24 . basic read operation the first clock of the first data phase is clock3. during the data phase, nc/be indicate which byte lanes are involved in the current data phase. a data phase may consist of wait cycles and a data transfer. the nc/be output buffers must remain enabled (for both read and writes) form the fist clock of the data phase throu gh the end of the transaction. this ensures nc/be are not left floating for long intervals. the nc/be lines contain valid byte enable information during the entire data phase independent of the state of nirdy . the nc/be
tw2809c fn787 5 rev. 1.00 page 111 of 130 february 27, 2014 lines contain the byte enable inform ation for data phase n+1 on the clock following the completion of the data phase n. this is not shown in figure 24 because a burst read transaction typically has all byte enables asserted; however, it is shown in figure 25 . notice on clock 5 in figure 25 , the master inserted a wait state by deasserting nirdy . however, the byte enables for data phase 3 are valid on clock 5 and remain valid until the data phase completes on clock 8. the fist data ph ase on a read transaction requir es a turnaround - cycle (enforced by the target via ntrdy ). in this case, the address is valid on clock2 and then the master stops driving ad . the earliest the target can provide valid data is clock 4. the target must drive the ad lines following the turnaround cycle when ndevsel is asserted. once enabled, the output buffers must stay enabled through the end of the transaction. (this ensures that the ad lines are not left floating for lone intervals.) one way for a data phase to complete is when data is transferred, which occurs when both nirdy and ntrdy are asserted on the same rising clock edge. there are other conditions that complete a data phase. ( ntrdy cann ot be driven until ndevsel is asserted.) when either nirdy or ntrdy is deasseted, a wait cycle is inserted and no d ata is transferred. data is successfully transferred on clocks 4, 6, and 8 and wait cycles are inserted on clock 3, 5, and 7. the first data phase completes in the minimum time for a read transaction. the second data phase is extended on clock 5 because ntrdy is deasserted. the last data phase is extended because nirdy was deasserted on clock 7. the master knows at clock 7 that the next data p hase is the last. however, because the master is not ready to complete the last transfer ( nirdy is deasserted on clock 7), nframe stays asserted. only when nirdy is asserted can nframe be deasserted as occurs on clock 8, indicating to the target that this is the last data phase of the transaction. figure 25 illustrates a write transaction. the transaction starts when nframe is asserted for the first time which occurs on clock 2. a write transaction is similar to a read transaction except no turnaround cycle is required following the address phase because the master provides both address and data. data phases work the same for both read and write transactions. figure 25 . basic write opera tion in figure 25 , the first and second data phases complete with zero wait cycles. however, the third data phase has three wait cycles inserted by the target. notice both agents insert a wait cycle on clock 5. nir dy must be asserted when nframe is deasserted indicating the last data phase.
tw2809c fn787 5 rev. 1.00 page 112 of 130 february 27, 2014 the date transfer was delayed by the master on clock 5 because nirdy was deasserted. the last data phase is signaled by the master on clock 6, but it does not complete until clo ck 8 . table 7 shows pci configuration registers, which is listed up initial values. device id, vendor id, subsys id, subsys vendor id, class code, rev id, header type, max lat, min gnt and int pin of pci configura tion registers can be update by only pci configuration eeprom. command, status, latency timer, cache line size, memory base address, interrupt line, retry timeout and trdy timeout of pci configuration registers can be update by pci configuration write as s hown as figure 23 . in this case, pci command needs to be change as pci configuration write instead of pci configuration read. in addition, pci configuration read is used to read pci configuration registers for chec king initial value and updated value. table 7 . pci configuration re gisters 31 16 15 0 offset initial value device id vendor id 00h 2809 _ 1797 h status command 04h 02a0_000 7 h class code revision id 08h 04 8 000_0 2 h bist header type latency timer cache line size 0ch 00_00_ 0 0_00h memory base address 10h 00_00000_8h (?) reserved 14h reserved 18h reserved 1ch reserved 20h reserved 24h card bus cis pointer 28h 0000_0000h subsystem id subsystem vendor id 2ch 2809 _ 1719h expansion rom base address 30h 0000_0000h reserved capabilities pointers 34h 000000_ 00h reserved 38h max_lat min_gnt interrupt pin interrupt line 3ch 48_20 _ 01_ 00 h reserved retry timeout trdy timeout 40h 0000_80 _ 80 h table 8 . contents of pci conf iguration eeprom address contents 00h vendor id 04h device id 58h subsystem vendor id 5ch subsystem id 78h interrupt pin 7ch max_lat min _gnt
tw2809c fn787 5 rev. 1.00 page 113 of 130 february 27, 2014 uart interface the uart serial communication parameters comply with eia - rs - 232 - c interface standard. the frame properties are specified in figure 26 . every frame starts with the start bit (which is always 0 ), followed by the least significant data bit (indicated with d0). then the next data bits are succeeding, ending with the most significant bit (indicated with d7). figure 26 . frame structure (st= start bit, dn=data b its, p=pari tbit, sp=stop bit) the parity bit is inserted after the data bits, before the stop bit (which is always 1 ). when a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. eac h frame corresponds to a single byte of information . each command or query can consist of one or several successive rxd frames . the lamp driver will answer accordingly with one or several successive txd frames . figure 27 shows the communication flow and defines the timing limit for receiving and transmitting tmax command and tmax response . following timing limits in the communication flow have to be kept: ? if after the time tmax command = 15 ms a whole command is not transmitted completely to the lamp driver, the command queue is cleared (this is necessary to synchronize the command decoding algorithm with the projector electronics) and the error byte abh is returned; ? the response will start earliest after having r eceived the first frame of a command and latest after having received the last frame of a command plus a processing time, which can vary between zero and 5 ms. the whole response time is guaranteed to be finished after tmax response = 10 ms . figure 27 . communication flow c hart table 9 . uart parameter frame parameter value tolerance baud rate 128000 (max.) 1% number of start bits 1 n/a number of data bits 8 n/a number of stop bits 1 /2 n/a parity bit o dd/ even /none n/a
tw2809c fn787 5 rev. 1.00 page 114 of 130 february 27, 2014 ddr2 timing figure 28 . ddr2 timing table figure 29 . cmd - ck timing
tw2809c fn787 5 rev. 1.00 page 115 of 130 february 27, 2014 figure 30 . txdqs - ck timng for tdqss figure 31 . txdqs - ck timin g for tdss/tdsh
tw2809c fn787 5 rev. 1.00 page 116 of 130 february 27, 2014 figure 32 . txdq - dqs timing figure 33 . rxdq - dqs timing
tw2809c fn787 5 rev. 1.00 page 117 of 130 february 27, 2014 figure 34 . round trip path timi ng
tw2809c fn787 5 rev. 1.00 page 118 of 130 february 27, 2014 power up sequence the tw2809 has to follow certain power up sequ ence to guarantee working. it shows in the diagram below. figure 35 . tw2809 power up sequ ence power off sequence the tw2809 has to follow certain power off sequence to guarantee working. it shows in the diagram below. figure 36 . tw2809 power off sequence document or the summary of an interesting point. you can position the t ext box anywhere in the document. use the text box tools tab to change the formatting of the pull quote text box.] 1.8v ddr i/o power supply 3.3v i/o power supply hw_rst_n ref_clk regulator power up time to chip power stable time delay dont care min. 740us 1.8v ddr i/o power supply 1.2v core power supply 0us( min. ) internal clock s pll lock time ( 240 us ) pll reset time : 5us( min. ) 740us + t_cfg + 245 us = 985us + t_cfg us 1.2v core power supply dont care 3.3v i/o power supply 1.8v ddr i/o power supply 0us( min. ) pci_config_done config time ( t_cfg us ) pci_rst_in_n pci_rst_in_n hw_rst_n 0us( min. )
tw2809c fn787 5 rev. 1.00 page 119 of 130 february 27, 2014 electrical specifications absolute maximum rat ings parameter symbol min typ max units vref dvdi - 0.5 1.2 1.8 v p ll avd avdd - 0.5 1.2 1.8 v ddr avd 1.8v sstl_vde - 0.5 1.8 2.5 v vdd 3.3v dvde - 0.5 3.3 4.6 v voltage on a ny dig ital data p in ( see caution statement ) - - 0.5 - 3.8 v voltage on osc related analog p in - - 0.5 - 3.8 v storage temperature t s - 5 5 - 1 25 c junction temperature t j - 4 0 - 125 c reflow soldering ( 1 0 seconds) t peak - - 2 4 0 - 250 c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may a dversely impact product reliability and result in failures not covered by warranty. recommen ded operating condit ions parameter symbol min typ max units vref dvdi 1.10 1.2 1.25 v pll avd avdd 1.1 5 1.2 1. 25 v ddr avd sstl_vde 1.7 1.8 1.9 v vdd 3.3v dvde 3.0 3.3 3.6 v ambient operating temperature t a 0 25 70 c supply current and p ower dissip ation parameter symbol mi n typ max units pll supply current (1. 2 v nom ) i dd p 18.2 ma sstl 1.8v supply current ( 1.8 v nom ) i dd h 215 ma digital internal supply current (1. 2 v nom ) i ddi 580 ma digital i/o supply current (3.3v nom ) i ddo 18.87 ma tot al power dissipation pd 1.16 w
tw2809c fn787 5 rev. 1.00 page 120 of 130 february 27, 2014 dc characteristics parameter symbol min (note 1 ) typ max (note 1 ) units digital inputs input high voltage (ttl) v ih 2.0 --- v dde + 0.3 v input low vo ltage (ttl) v il ? 0.3 --- 0.8 v input leakage current (@v i = 3.3 v or 0v) i l --- --- 4 a input capacitance c in --- --- 16 pf digital outputs output high voltage v oh v dde ? 0.2 --- v dde v output low voltage v ol 0 --- 0.2 v high level output curren t (@v oh = 2. 8 v) i oh *1 ma low level output current (@v ol = 0. 2 v) i ol ma tri - state output leakage current (@v o = 2.5v or 0v) i oz --- --- 4 a output capacitance c o --- --- 16 pf input / output capac i tance parameter symbol requirements units input pin cin max 16 pf output pin cout max 16 pf i/o pin ci/o max 16 pf notes: 1. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
tw2809c fn787 5 rev. 1.00 page 121 of 130 february 27, 2014 packa ge description ball assignment figure 37 . tw2809c pin assign ment (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a dvss dvss pci_ad[0] pci_ad[1] pci_ad[3] pci_ad[6] dvss pci_ad[12] pci_serr_n pci_perr_ n dvss pci_ad[16] pci_ad[20] pci_ad[23] dvss pci_ad[28] pci_clk_in pci_inta_n dvss dvss a b dvss sstl_vde ddr_ cke pci_ad[2] pci_ad[4] pci_ad[7] pci_ad[9] pci_ad[13] pci_cbe_n [1] pci_stop_ n pci_irdy_n pci_ad[17] pci_ad[21] pci_ad[24] pic_ad[25] pci_ad[29] pci_req_n pci_gnt_n vo1_data[1 ] vo1_data[0 ] b c ddr_ addr[7] ddr_ addr[10] ddr_ we_n dvss pci_ad[5] pci_cbe_n [0] pci_ad[10] pci_ad[14] pci_par pci_trdy_n pci_cbe_n [2] pci_ad[18] pci_ad[22] pci_cbe_n [3] pci_ad[26] pci_ad[30] pci_rst_in _n vo1_data[4 ] vo1_data[3 ] vo1_data[2 ] c d ddr_ addr[12] ddr_ addr[1] ddr_ ba[2] dvss dvde pci_ad[8] pci_ad[11] pci_ad[15] dvde pci_devsel _n pci_frame _n pci_ad[19] dvde pci_idsel pci_ad[27] pci_ad[31] vo0_data[0 ] vo1_data[7 ] vo1_data[6 ] vo1_data[5 ] d e dvss ddr_ addr[3] ddr_ ba[0] sstl_vde dvde vo0_data[3 ] vo0_data[2 ] vo0_data[1 ] e f ddr_ addr[9] ddr_ addr[5] ddr_ ba[1] sstl_vde vo0_data[6 ] vo0_data[5 ] vo0_data[4 ] clk_vo_ou t_0 f g ddr_ dq[1] ddr_ dq[0] ddr_ ras_n dvss dvss dvdi dvde dvdi dvdi dvde dvdi dvss vi3_data[0] clk_vo vo0_data[7 ] dvss g h dvss ddr_ dq[3] ddr_ dq[2] dvss dvdi dvss dvss dvss dvss dvss dvss dvdi vi3_data[4] vi3_data[3] vi3_data[2] vi3_data[1] h j ddr_ dqs[0] ddr_ dm[0] ddr_ dq[4] sstl_vde sstl_vde dvss dvdi dvss dvss dvdi dvss dvde dvde vi3_data[6] vi3_data[5] clk_vi3 j k ddr_ dqs_n[0] ddr_ dq[6] ddr_ dq[5] sstl_vde dvdi dvss dvss dvss dvss dvss dvss dvdi vi2_data[2] vi2_data[1] vi2_data[0] vi3_data[7] k l dvss ddr_ dq[7] ddr_ dq[8] ddr_ref sstl_vde dvss dvss dvss dvss dvss dvss dvdi vi2_data[5] vi2_data[4] vi2_data[3] dvss l m ddr_ dqs[1] ddr_ dq[9] ddr_ dq[10] dvss dvdi dvss dvdi dvss dvss dvdi dvss dvde vi1_data[0] vi2_data[7] vi2_data[6] clk_vi2 m n ddr_ dqs_n[1] ddr_ dq[11] ddr_ dm[1] dvss dvdi dvss dvss dvss dvss dvss dvss dvdi dvde vi1_data[3] vi1_data[2] vi1_data[1] n p dvss ddr_ dq[12] ddr_ dq[13] docdres dvss dvdi dvdi dvde dvdi dvde dvdi dvss vi1_data[6] vi1_data[5] vi1_data[4] clk_vi1 p r ddr_clk ddr_ dq[14] ddr_ dq[15] sstl_vde vi0_data[1] vi0_data[0] vi1_data[7] dvss r t ddr_ clk_n ddr_ addr[11] ddr_ cas_n sstl_vde vi0_data[4] vi0_data[3] vi0_data[2] clk_vi0 t u dvss ddr_ addr[6] ddr_ addr[2] dvss vo2_data[1 ] iddrtest[0] jtag_sel dvde vo3_data[7 ] test_mode [4] jtag_rtck test_mode [0] dvde test_mode [2] arm_sdi_c hip arm_se_c hip vo3_data[3 ] vo3_data[5 ] vi0_data[6] vi0_data[5] u v ddr_ addr[8] ddr_ addr[4] ddr_ addr[0] ddr_ odt vo2_data[2 ] iddrtest[1] nc vo3_data[6 ] test_mode [5] test_mode [3] jtag_tdo jtag_tck test_mode [1] slave_mo de arm_sdo_ chip arm_bu_cl k adatm vo3_data[4 ] vo3_data[2 ] vi0_data[7] v w dvss sstl_vde ddr_ cs_n vo2_data[7 ] vo2_data[3 ] iddrtest[2] clk_vo_ou t_1 i2c_sda arm_testm ode avss avss jtag_tms vpd arm_tm1 arm_trst_t arm_boot _mode adatr aclkp vo3_data[1 ] vo3_data[0 ] w y dvss dvss vo2_data[6 ] vo2_data[5 ] vo2_data[4 ] vo2_data[0 ] dvss i2c_scl jtag_trstn avdd avdd jtag_tdi ref_clk hw_rst_n arm_tm2 adatp0 asynp aclkr asynr dvss y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
tw2809c fn787 5 rev. 1.00 page 122 of 130 february 27, 2014 pin definitions table 10 . pin definitions ball no. symbol attribute descriptions y13 ref_clk input c hip reference clock input (54mhz) y14 hw_rst_n input c hip reset input (active low) v14 slave_m ode input tw2809c operation mode (tied to 1) r1 ddr_clk output ddr differential clocks t1 ddr_clk_n v3 ddr_addr[0] output ddr address bus d2 ddr_addr[1] u3 ddr_addr[2] e2 ddr_addr[3] v2 ddr_addr[4] f2 ddr_addr[5] u2 ddr_addr[6] c1 ddr_addr[7] v1 ddr_addr[8] f1 ddr_addr[9] c2 ddr_addr[10] t2 ddr_addr[11] d1 ddr_addr[12] e3 ddr_ba[0] output ddr control signals f3 ddr_ba[1] d3 ddr_ba[2] b3 ddr_cke w3 ddr_cs_n g3 ddr_ras_n t3 ddr_cas_n c3 ddr_we_n v4 ddr_odt g2 ddr_dq[0] i/o ddr data bus g1 ddr_dq[1] h3 ddr_dq[2] h2 ddr_dq[3] j3 ddr_dq[4]
tw2809c fn787 5 rev. 1.00 page 123 of 130 february 27, 2014 ball no. symbol attribute descriptions k3 ddr_dq[5] k2 ddr_dq[6] l2 ddr_dq[7] l3 ddr_dq[8] m2 ddr_dq[9] m3 ddr_dq[10] n2 ddr_dq[11] p2 ddr_dq[12] p3 ddr_dq[13] r2 ddr_dq[14] r3 ddr_dq[15] j1 ddr_dqs[0] i/o ddr differential data strobe k1 ddr_dqs_n[0] m1 ddr_dqs[1] n1 ddr_dqs_n[1] j2 ddr_dm[0] output ddr data write mask n3 ddr_dm[1] p4 docdres output ddr sstl_18 special purpose output signal (1.8v) l4 ddr_ref input ddr sstl_18 reference voltage (1.8v) a17 pci_clk_in input pci input clock (33/66 mhz) a3 pci_ad[0] i/o pci address and data bus a4 pci_ad[1] b4 pci_ad[2] a5 pci_ad[3] b5 pci_ad[4] c5 pci_ad[5] a6 pci_ad[6] b6 pci_ad[7] d6 pci_ad[8] b7 pci_ad[9] c7 pci_ad[10] d7 pci_ad[11] a8 pci_ad[12] b8 pci_ad[13]
tw2809c fn787 5 rev. 1.00 page 124 of 130 february 27, 2014 ball no. symbol attribute descriptions c8 pci_ad[14] d8 pci_ad[15] a12 pci_ad[16] b12 pci_ad[17] c12 pci_ad[18] d1 2 pci_ad[19] a13 pci_ad[20] b13 pci_ad[21] c 13 pci_ad[22] a14 pci_ad[23] b14 pci_ad[24] b15 pci_ad[25] c15 pci_ad[26] d1 5 pci_ad[27] a16 pci_ad[28] b16 pci_ad[29] c16 pci_ad[30] d1 6 pci_ad[31] c6 pci_cbe_n[0] i/o pci bus command and byte enable b9 pci_cbe_n[1] c11 p ci_cbe_n[2] c14 pci_cbe_n[3] c17 pci_rst_in_n input pci control signals c9 pci_par i/o d1 1 pci_frame_n i/o b11 pci_irdy_n i/o c10 pci_trdy_n i/o b10 pci_stop_n i/o d1 4 pci_idsel input d1 0 pci_devsel_n i/o b17 pci_req_n i/o b18 pci_gn t_n input a10 pci_perr_n i/o a9 pci_serr_n i/o
tw2809c fn787 5 rev. 1.00 page 125 of 130 february 27, 2014 ball no. symbol attribute descriptions a18 pci_inta_n output g18 clk_vo input vo clock input to generate internal four video output ports clocks f20 clk_vo_out_0 output vo clock output for video output ports 0 and 1 d1 7 vo0_data[0] i/o vo video output port 0 data buas e20 vo0_data[1] e19 vo0_data[2] note: vo0_data[7:0] is pin muxed with gpio[23:16] e18 vo0_data[3] f19 vo0_data[4] f18 vo0_data[5] f17 vo0_data[6] g19 vo0_data[7] b20 vo1_data[0] i/o vo video output port 1 data buas b19 vo1_data[1] c20 vo1_data[2] note 1 : vo1_data[7:0] is pin muxed with gpio[15:8] c19 vo1_data[3] c18 vo1_data[4] d20 vo1_data[5] d1 9 vo1_data[6] d1 8 vo1_data[7] w7 clk_vo_out_1 output vo clock output for video outp ut ports 2 and 3 y6 vo2_data[0] i/o vo video output port 2 data buas u5 vo2_data[1] v5 vo2_data[2] note: vo2_data[7:0] is pin muxed with gpio[7:0] w5 vo2_data[3] y5 vo2_data[4] y4 vo2_data[5] y3 vo2_data[6] w4 vo2_data[7] w20 vo 3_data[0] i/o vo video output port 3 data buas w19 vo3_data[1] v19 vo3_data[2] note 1 : vo3_data[7:0] is pin muxed with
tw2809c fn787 5 rev. 1.00 page 126 of 130 february 27, 2014 ball no. symbol attribute descriptions u17 vo3_data[3] gpio[55:48] v18 vo3_data[4] u18 vo3_data[5] v8 vo3_data[6] u9 vo3_data[7] t20 clk_vi0 input vi v ideo input port 0 clock input r18 vi0_data[0] input vi video input port 0 data bus r17 vi0_data[1] t19 vi0_data[2] t18 vi0_data[3] t17 vi0_data[4] u20 vi0_data[5] u19 vi0_data[6] v20 vi0_data[7] p20 clk_vi1 input vi video input port 1 clock input m17 vi1_data[0] i/o vi video input port 2 data bus n20 vi1_data[1] n19 vi1_data[2] note: vi1_data[7:0] is pin muxed with gpio[47:40] n18 vi1_data[3] p19 vi1_data[4] p18 vi1_data[5] p17 vi1_data[6] r19 vi1_data[7] m 20 clk_vi2 input vi video input port 2 clock input k19 vi2_data[0] i/o vi video input port 2 data bus k18 vi2_data[1] k17 vi2_data[2] note: vi2_data[7:0] is pin muxed with gpio[39:32] l19 vi2_data[3] l18 vi2_data[4] l17 vi2_data[5] m19 vi2_data[6] m18 vi2_data[7] j20 clk_vi3 input vi video input port 3 clock input
tw2809c fn787 5 rev. 1.00 page 127 of 130 february 27, 2014 ball no. symbol attribute descriptions g17 vi3_data[0] i/o vi video input port 3 data bus h20 vi3_data[1] h19 vi3_data[2] note 1 : vi3_data[7:0] is pin muxed with gpio[31:24] h18 vi3_data[3] note2: vi 3_data[0 ] is pin muxed with uart 0 _rx h17 vi3_data[4] note3: vi3_data[1 ] is pin muxed with uart 0 _tx j19 vi3_data[5] note4: vi3_data[2] is pin muxed with uart1_rx j18 vi3_data[6] note5: vi3_data[3] is pin muxed with uart1_tx k20 vi3_data[7] w18 ac lkp i/o audio playback port bit clock, word select, and serial data y17 asynp y16 adatp0 y18 aclkr input audio record port bit clock, word select, and serial data y19 asynr w17 adatr v17 adatm input pll test pin (tied to ground "0") v7 nc not connected w16 arm_boot_mode input arm926 ip test pins ( tied to ground 0) w9 arm_tstmode w14 arm_tm1 y15 arm_tm2 w15 arm_trst_t v16 arm_bu_clk u16 arm_ se_chip u15 arm_ sdi_chip v15 arm_ sdo_chip output w13 vpd input all ddr phy ip test pins (tied to ground 0) u6 iddrt e st[0] v6 iddrt e st[1] w6 iddrt e st[2] u12 test_mode[0] input all g lobal test mode pins (tied to ground 0) v13 test_mode[1]
tw2809c fn787 5 rev. 1.00 page 128 of 130 february 27, 2014 ball no. symbol attribute descriptions u14 test_mode[2] v10 test_mode[3] u10 test_mode[4] v9 test_mode[5] v12 jtag_tck input jtag test pins . all 5 input pins should be tied to low for normal operation. y9 jtag_trstn input y12 jtag_tdi input u7 jtag_sel input w12 jtag_tms input v11 jtag_tdo output u11 jtag_rtck output y8 i2c_scl i/o i 2 c interf ace w8 i2c_sda i/o y10,y11 avdd 1.2 v po we r of analog pll w10,w11 avss - ground of analog pll g8,g10,g11,g13,h7, h14,j9,j12,k7,k14, l14,m7,m9,m12,n7, n14,p8,p9,p11,p13 dvdi 1.2v power of core logic b2,e4,f4,j4,j7, k4,l7,r4,t4,w2 sstl_vde 1.8v pow er of the ddr i/o d5,d9, d 1 3,e17,g9, g12,j14,j17,m14, n17,p10,p12,u8,u13 dvde 3.3v power of the external i/o a1,a2,a7,a11,a15, a19,a20,b1,c4,d4, e1,g4,g7,g14,g20, h1,h4,h8,h9,h10, h11,h12,h13,j8, j10,j11,j13,k8,k9, k10,k11,k12,k13, dvss - ground
tw2809c fn787 5 rev. 1.00 page 129 of 130 february 27, 2014 ball no. symbol attribute descriptions l1,l8,l9,l10,l11, l12,l13,l20,m4, m8,m10,m11,m13, n4,n8,n9,n10,n11, n12,n13,p1,p7,p14, r20,u1,u4,w1,y1, y2,y7,y20 dvss about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. t he company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high - end consumer markets. for the most updated datasheet, application notes, related documentation and related parts, please see the r espective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also available from our website at www.intersil.com/support
tw2809c for additional products, see www.intersil.com/product_tree inters il products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at http://www.intersil.com/en/support/qualandreliabi lity.html intersil products are sold by description only. intersil may modify the circuit design and/or specifications of products at a ny time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or f unction of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information furnished by intersil is believed to be ac curate and reliable. however, no responsibility is assumed by intersil or its su bsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersi l or its subsidiaries. for informati on regarding intersil corporation and its products, see http://www.intersil.com fn7875 rev.1.00 page 130 of 130 february 27, 2014 mechanical specifications figure 38 . mechanical specifica tions (bottom view) ? copyright intersil americas llc 20 11 - 201 4 . all rights reserved. all trademarks and registered trademarks are the property of their respective owners.

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