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1 for more information www.linear.com/LTC7150S typical application features description 20v, 20a synchronous step-down regulator the lt c ? 7150s is a high efficiency monolithic synchronous buck regulator capable of delivering 20a to the load. it uses a phase lockable controlled on-time constant frequency, current mode architecture. polyphase operation allows multiple ltc7150 s regulators to run out-of-phase, which reduces the amount of input and output capacitors required. the operating supply voltage range is from 3.1v to 20v . the operating frequency is programmable from 400khz to 3mhz with an external resistor. the high frequency ca - pability allows the use of physically smaller inductor and capacitor sizes. for switching noise sensitive applications, the lt c7150s can be externally synchronized from 400khz to 3mhz . the phmode pin allows the user control of the phase of the outgoing clock signal. the unique constant frequency/controlled on-time architecture is ideal for high step-down ratio applications that operate at high frequencies while demanding fast transient response. the ltc7150 s uses second generation silent switcher technology including integrated bypass capacitors to deliver a highly efficient solution at high frequencies with excellent emi performance. 12v in to 1.2v out application applications n silent switcher ? 2 architecture for low emi n v in range: 3.1v to 20v n v out range: 0.6v to 5.5v n differential v out remote sense n adjustable frequency: 400khz to 3mhz n polyphase ? operation: up to 12 phases n output tracking and soft-start n reference accuracy: 0.6v 1% over temperature n current mode operation for excellent line and load transient response n accurate 1.2v run pin threshold n supports forced continuous/discontinuous modes n 42-lead 6mm 5mm 1.3mm bga package n server power applications n distributed power systems n point of load supply for asic, fpga, dsp, p, etc. all registered trademarks and trademarks are the property of their respective owners. efficiency and power loss 7150 01a 7150 1 0 05 7 1 10 1 10 10 100 0 10 lt c7150s 7150sfa 8 12 16 20 70 75 80 85 90 95 sv 100 0 2 4 6 8 10 12 efficiency (%) power loss (w) in 7150s ta01b = 5v i out (a) 0 4
2 for more information www.linear.com/LTC7150S absolute maximum ratings pv in , sv in ................................................. C 0.3v to 22v run voltage ............................................. C 0.3v to sv in mode/sync, track/ss voltage ......... C 0.3v to intv cc ith, rt, pgood voltage ........................... C 0. 3v to 3.6v phmode, clk voltage .............................. C 0.3v to 3.6v v out C voltage ........................................... C 0.3v to 0.3v fb voltage ................................................. C 0.3v to 3.6v operating junction temperature range ................ 125 c storage temperature range .................. C 65 c to 150 c maximum internal temperature ............................ 125 c peak reflow solder body temperature ................. 26 0 c (note 1) order information 5 1 5 10 t jmax = 125c, ja = 21c/w pin configuration part number pad or ball finish part marking* package type msl rating tempera ture range (see note 2) device finish code LTC7150Sey#pbf sac305 (rohs) 7150s e1 bga 3 C40c to 125c LTC7150Siy#pbf sac305 (rohs) 7150s e1 bga 3 C40c to 125c ? device temperature grade is indicated by a label on the shipping container . ? pad or ball finish code is per ipc/jedec j-std-609. ? t erminal finish part marking: www.linear.com/leadfree ? this product is not recommended for second side reflow . for more information, go to www.linear.com/bga-assy ? recommended bga pcb assembly and manufacturing procedures : www.linear.com/bga-assy ? bga package and t ray drawings: www.linear.com/packaging ? this product is moisture sensitive. for more information, go to : www.linear.com/bga-assy http://www.linear.com/product/LTC7150S#orderinfo lt c7150s 7150sfa
3 for more information www.linear.com/LTC7150S electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, unless otherwise noted. symbol parameter conditions min typ max units sv in sv in operating voltage l 3.1 20 v pv in pv in operating voltage 20 v v out v out operating voltage 0.6 5.5 v i q input quiescent current (note 3) active mode shutdown mode; v run = 0v 2 20 4 40 ma a v fb feedback reference voltage (note 4) ith = 1.0v ith = 1.0v, C40c to 125c l 0.598 0.594 0.600 0.600 0.602 0.606 v v ? v fb(line+load) feedback voltage line and load regulation (note 4) l 0.2 0.5 % i fb feedback pin input current 50 na g m (ea) error amplifier transconductance ith = 1.0v 1.0 1.3 1.6 ms t on(min) minimum on-time l 20 25 ns t off(min) minimum off-time 50 ns i lim positive inductor valley current limit fb = 0.58v l 21 24 27 a i lim-ith current limit at different ith voltage ith = 1.4v ith = 1v ith = 0.6v ith = 0.2v l l l l 9.5 C2.5 C14.5 C27 12 0 C12 C24 14.5 2.5 C9.5 C21 a a a a r top top power nmos on-resistance intv cc = 3.3v 6 m r bot bottom power nmos on-resistance intv cc = 3.3v 2.5 m i sw (note 5) t op switch leakage bottom switch leakage v in = 20v, v sw = 0v v in = 20v, v sw = 20v 0.1 1 1 50 a a v uvlo intv cc undervoltage lockout threshold intv cc falling intv cc hysteresis (rising) 2.45 2.6 250 2.75 v mv v run run rising run falling hysteresis 1.15 1.20 100 1.25 v mv i run run leakage current 100 na v intvcc internal v cc voltage 3.2 3.3 3.4 v ov output overvoltage pgood upper threshold v fb rising v fb falling hysteresis 6 8 10 10 % mv uv output under voltage pgood lower threshold v fb falling v fb rising hysteresis C6 C8 10 C 10 % mv r pgood pgood pull-down resistance v pgood = 100mv 8 15 i pgood pgood leakage v fb = 0.6v 2 a t pgood pgood delay pgood low to high pgood high to low 6 25 cycles cycles i track/ss track pull-up current v track/ss = 0v 6 10 a f osc oscillator frequency rt = 162k l 0.9 1 1.1 mhz f sync sync capture range % of programmed frequency 70 130 % mode/sync mode/sync threshold input high mode/sync threshold input low 0.3 1 v v lt c7150s 7150sfa
4 for more information www.linear.com/LTC7150S symbol parameter conditions min typ max units i mode/sync mode/sync current mode/sync = 0v 6 14 a v clkout clock output high voltage clock output low voltage v intvcc C 0.2 v intvcc 0 0.2 v v phmode phmode threshold 180 (2-phase) 90 (4-phase) 120 (3-phase) v intvcc C 0.1 1.0 v intvcc C 1 0.1 v v v v inov v in overvoltage threshold v in rising v in falling 22.5 20 24.5 21.5 26.5 23 v v electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC7150S is tested under pulsed load conditions such that t j t a . the LTC7150Se is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC7150Si is guaranteed over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ), where ja (in c/w) is the package thermal impedance. note 3: the quiescent current in forced continuous mode does not include switching loss of the power fets. note 4: the LTC7150S is tested in a feedback loop that servos v ith to a specified voltage and measures the resultant v fb . note 5: there is additional switch current due to internal resistor to ground. lt c7150s 7150sfa
5 for more information www.linear.com/LTC7150S transient response, dcm transient response, ccm load regulation vs load current t a = 25c, v in = 12v, v out = 1.2v, unless otherwise noted. rds on vs temperature output tracking typical performance characteristics shutdown current vs v in efficiency vs load current 500khz efficiency vs load current 1mhz efficiency vs load current 2mhz pv in = 12v, sv in = 5v l = 0.25h (dcr = 0.37m) pv in = 12v, sv in = 5v l = 0.15h (dcr = 0.37m) pv in = 12v, sv in = 5v l = 0.33h (dcr = 0.37m) lt c7150s 7150sfa 75 4 5 6 7 8 9 10 rds on (m ) 7150s g07 v in = 12v, r out = 0.1 80 r fb1 = 10k, r fb2 = 10k v track = 0v to 1v 200s/div v out 1v/div v track/ss 500mv/div i l 10a/div 7150s g08 v in (v) 85 0 5 10 15 20 0 10 20 30 40 90 i q (ua) 7150s g09 v out = 1.0v v out = 1.2v v out = 1.5v i out (a) 0 4 8 12 95 16 20 70 75 80 85 90 95 100 efficiency (%) 100 7150s g01 efficiency (%) 7150s g02 v out = 1.0v v out = 1.2v i out (a) v out = 1.5v i out (a) 0 4 8 12 16 20 70 75 0 80 85 90 95 100 efficiency (%) 7150s g03 v out = 1.0v v out = 1.2v v out = 1.5v 4 v in = 12v, v out = 1.2v i out = 1.5a to 15a, l = 0.15h, f sw = 1mhz r ith = 10k, c ith = 1.0nf, c ithp = 100pf r fb1 = 10k, r fb2 = 10k c out = 2 100uf + 2 330f 20s/div v out ac?coupled 50mv/div i l 8 10a/div 7150s g04 v in = 12v, v out = 1.2v i out = 1.5a to 15a, l = 0.15h, f sw = 1mhz r ith = 20k, c ith = 220pf, c ithp = 22pf r fb1 = 10k, r fb2 = 10k c out = 2 100f + 2 330f 20s/div v out ac?coupled 12 50mv/div i l 10a/div 7150s g05 i out (a) 0 4 8 12 16 16 20 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 20 normalized (%) 7150s g06 v out = 1.2v bot fet top fet temperature ( c) ?55 ?35 ?15 5 70 25 45 65 85 105 125 0 1 2 3
6 for more information www.linear.com/LTC7150S t a = 25c, v in = 12v, v out = 1.2v, unless otherwise noted. typical performance characteristics efficiency vs frequency efficiency vs pv in die temperature vs load switching frequency vs v out run rising threshold vs temperature frequency vs temperature sv in current vs frequency, ccm switching frequency vs r t regulated fb voltage vs temperature lt c7150s 7150sfa 25 v out (v) 0 2 4 6 8 10 0.9 1.0 1.1 50 1.2 1.3 1.4 frequency (mhz) 7150s g15 temperature ( c) ?55 ?35 ?15 5 75 25 45 65 85 105 125 595 597 599 601 100 603 605 regulated fb voltage (mv) 7150s g16 temperature ( c) ?55 ?35 ?15 5 25 125 45 65 85 105 125 1.190 1.195 1.200 1.205 1.210 i svin (ma) 1.215 1.220 run rising threshold (v) 7150s g17 r t = 162k temperature ( c) ?55 ?35 ?15 5 7150s g10 25 45 65 85 105 125 0.90 0.95 1.00 1.05 r t (k ) 1.10 frequency (mhz) 7150s g18 0 50 sv in = 5v fc mode 100 150 200 250 300 350 400 0 0.5 1.0 frequency (mhz) 1.5 2.0 2.5 3.0 3.5 switching frequency (mhz) 7150s g11 frequency (mhz) 0.4 0.9 0.4 1.4 2.0 2.5 3 70 75 80 85 90 95 0.9 100 l = 0.25h i out = 10a i out = 20a efficiency (%) 7150s g12 i out = 10a i out = 20a pv in (v) 4 1.5 8 12 16 20 70 75 80 85 90 95 2.0 100 sv in = 5v f sw = 1mhz l = 0.25h efficiency (%) 7150s g13 pv in = 12v sv in = 5v v out = 1.2v f sw = 1mhz demoboard on still air, t a = 25c i out (a) 2.5 0 2 4 6 8 10 12 14 16 18 0 20 25 40 55 70 85 100 die temperature ( c) 7150s g14 r t = 162k
7 for more information www.linear.com/LTC7150S t a = 25c, v in = 12v, v out = 1.2v, unless otherwise noted. typical performance characteristics active current vs sv in , dcm no load start-up waveform valley current limit vs v ith valley current limit vs temperature discontinuous conduction mode operation continuous conduction mode operation period jitter vs t on start-up with pre-biased output period jitter vs i p-p lt c7150s 7150sfa v in = 12v, v out = 1.2v 1.8 ?24 ?16 ?8 0 8 16 24 valley current limit (a) 7150s g26 i out = 0a, l = 0.15h, f sw = 1mhz temperature ( c) ?55 ?35 ?15 5 25 45 65 85 105 500ns/div 125 22 23 24 25 26 valley current limit (a) 7150s g27 sw 10v/div clkout 5v/div i l 10a/div 7150s g20 v in = 12v, v out = 1.2v f sw = 1mhz i p-p = 6a t on (ns) 0 100 200 300 400 500 3.00 3.40 i out = 1.5a, l = 0.15h, f sw = 1mhz 3.80 4.20 4.60 5.00 period jitter 1 (ns) 7150s g21 i pk?pk (a) 0 2 4 1s/div 6 8 10 12 0 1 2 3 4 5 sw 6 v in = 12v v out = 1.2v f sw = 1mhz period jitter 1 (ns) 7150s g22 v track = 0v sv in (v) 0 5 10 15 5v/div 20 0 0.5 1.0 1.5 2.0 2.5 3.0 i q (ma) 7150s g23 i l v in = 12v, c track/ss = 0.1f r out = 0.1, l = 0.15h, f sw = 1mhz r fb1 = 10k, r fb2 = 10k c out = 2 100f + 2 330f 2ms/div v out 1v/div v run 2v/div v pgood 5v/div i l 10a/div 5a/div 7150s g24 2ms/div v out 1v/div v run 2v/div v pgood 5v/div i l 10a/div 7150s g25 7150s g19 v in = 12v, c track/ss = 0.1f r out = 0.1, l = 0.15h, f sw = 1mhz r fb1 = 10k, r fb2 = 10k c out = 2 100f + 2 330f v ith (v) 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
8 for more information www.linear.com/LTC7150S pin functions phmode (pin a1 ): control input to phase selector. determines the phase relationship between internal oscillator and clkout. tie it to intv cc for 2-phase operation, tie it to sgnd for 3-phase operation, and tie it to intv cc /2 (or float the pin) for 4-phase operation. pgood (pin a2): output power good with open-drain logic. pgood is pulled to ground when the voltage of the fb pin is not within 7.5% of the internal 0.6v reference. rt (pin a3): switching frequency programming pin. connect an external resistor (between 405k to 54k) from this pin to gnd to program the frequency from 400khz to 3mhz. ith (pin a4 ): error amplifier output and switching regulator compensation point. the current comparators trip threshold is linearly proportional to this voltage, whose normal range is from 0.3v to 1.8v. fb (pin a5): feedback input to the error amplifier of the step-down regulator. connect resistor divider tap to this pin. the output voltage can be adjusted from 0.6v to v in by: v out = 0.6v ? [1 + (r1/r2)]. v out C (pin a6): negative return of output rail. connect this pin directly to the bottom of the remote output capacitor near the load in order to minimize error incurred by voltage drop across the metal trace of the board. clkout (pin b1): output clock signal for polyphase operation. the phase of clkout with respect to clkin is determined by the state of the phmode pin. clkouts peak-to-peak amplitude is intv cc to gnd. run (pin b2 ): logic controlled run input. do not leave this pin floating. logic high activates the step-down regulator. mode/sync (pin b3 ): discontinuous mode select and oscillator synchronization pin. tie mode/sync to gnd for discontinuous mode of operation. floating mode/sync or tying it to a voltage above 1v will select for ced continuous mode. furthermore, connecting mode/ sync to an external clock will synchronize the system clock to the external clock and puts the part in forced continuous mode. track/ss (pin b4): output tracking and soft-start pin. allows the user to control the rise time of the output voltage. putting a voltage between 0.6v on this pin relative to v out C bypasses the internal reference input to the error amplifier, instead it servos the fb pin relative to v out C to that voltage. theres an internal 5a pull-up current from intv cc to this pin, so putting a capacitor from this pin to v out C provides a soft-start function. sgnd (pin b5): signal gnd. intv cc (pin b6): internal 3.3v regulator output. the internal power drivers and control circuits are powered from this voltage. decouple this pin to power ground with a minimum of 4.7f low esr ceramic capacitor. sv in (pin c1): signal v in . filtered input voltage to the on-chip 3.3v regulator. bypass signal into the sv in pin with a 0.1f ceramic capacitor. pv in (pins c2, c5, c6, d1, d2, d5, d6): power v in . input voltage to the on chip power mosfets. sw (pins c3, c4, d3, d4, e3, e4, f3, f4, g3, g4): switch node connection of external inductor. voltage swing of sw is from a diode voltage drop below ground to a diode voltage above pv in . pgnd (pins e1, e2, e5, e6, f1, f2, f5, f6, g1, g2, g5, g6 ): ground for power and signal ground. lt c7150s 7150sfa
9 for more information www.linear.com/LTC7150S block diagram LTC7150S 7150s bd sw intv cc boost mtop gatedrive reverse current comparator logic + ? + ? current comparator + ? + + ? track amplifier error amplifier 0.6v ? + ldo oscillator on time calculator pv in sw power good status fb pgood clk_int clkout phmode mode/sync rt sgnd ith fb track/ss run svin pgnd pvin v out ? intv cc mbot intv cc 0.22f 0.2f lt c7150s 7150sfa
10 for more information www.linear.com/LTC7150S operation main control loop the ltc7150 s is a current mode monolithic 20a step- down regulator. in normal operation, the internal top power mosfet is turned on for a fixed interval determined by a one-shot timer, ost. when the top power mosfet turns off, the bottom power mosfet turns on until the current comparator, i cmp , trips, restarting the one-shot timer and initiating the next cycle. inductor current is determined by sensing the voltage drop across the bottom power mosfet when it is on. the voltage on the ith pin sets the comparator threshold corresponding to the inductor valley current. the error amplifier, ea, adjusts this ith voltage by comparing the feedback signal, v fb , with an internal 0.6v reference. if the load current increases, it causes a drop in the feedback voltage relative to the internal reference, the ith voltage then rises until the average inductor current matches that of the load current. at low load currents, the inductor current can drop to zero and become negative. in discontinuous mode (dcm), this is detected by the current reversal comparator, i rev , which then shuts off the bottom power mosfet. both power mosfets will remain off with the output capacitor supplying the load current until the i th voltage rises above zero current level to initiate the next cycle. if continuous mode of operation is desired, simply float the mode/sync pin or tie it to intv cc . the operating frequency is determined by the value of the rt resistor, which programs the current for the internal oscillator. an internal phase-lock loop servos the oscillator frequency to an external clock signal if one is present on the mode/sync pin. another internal phase-lock loop servos the switching regulator on-time to track the internal oscillator to force a constant switching frequency. overvoltage and undervoltage comparators ov and uv pull the pgood output low if the output feedback volt- age, v fb , exits a 7.5% window around the regulation point. continuous operation is forced during ov and uv conditions except during start-up when the track pin is ramping up to 0.6v. the s in ltc7150 s refers to the second generation silent switcher technology. the ic has integrated ceramic capacitors for v in and boost to keep all the fast ac cur - rent loops small, thus improving the emi performance. furthermore, it allows for faster switching edges which greatly improves efficiency at high switching frequencies. run threshold pulling the run pin to ground for ces the LTC7150S into its shutdown state. bringing the run pin to above 0.6v will turn on the internal reference only, while keeping the power mosfets off. further increasing the run voltage above the run rising threshold (nominally 1.2v) turns on the entire chip. the accurate 1.2v run threshold allows the user to program the sv in under voltage lockout threshold by placing a resistor divider from sv in . intv cc regulator an internal low dropout (ldo) regulator produces the 3.3v supply that powers the drivers and internal bias circuitry. the intv cc must be bypassed to ground with a minimum of a 4.7f ceramic capacitor. good bypassing is neces - sary to supply the high transient currents required by the power mosfet gate drivers. applications with high input voltage and high switching frequency will experience an increase in die temperature due to the higher power dis - sipation across the ldo. in such cases, if theres another 5v or 3.3v supply rail available, consider using that to drive the sv in pin to lower the power dissipation across the internal ldo. v in overvoltage protection in order to protect the internal power mosfet devices against transient voltage spikes, the LTC7150S constantly monitors the pv in pin for an overvoltage condition. when the pv in rises above 24.5v, the regulator suspends opera- tion by shutting off both power mosfets. once pv in drops below 21.5v, the regulator immediately resumes normal operation. during an overvoltage event, the internal soft- start voltage is clamped to a voltage slightly higher than the feedback voltage, thus the soft-start feature will be present upon exiting an overvoltage condition. lt c7150s 7150sfa
11 for more information www.linear.com/LTC7150S operation output voltage programming the output voltage is set by an external resistive divider according to the following equation: v out = 0.6v ? 1 + r1 r2 ? ? ? ? ? ? the resistive divider allows the v fb pin to sense a frac - tion of the output voltage as shown in figure?1. since the lt c7150s will often be used in high power applications, there can be significant voltage drop due to board layout between the part and the point of load (pol). thus, it is imperative to have r2 and r1 kelvin directly to the positive and negative terminals of the point of load. the negative terminal should then be connected directly to the v out C pin of the LTC7150S for differential v out sensing. a feed forward compensation capacitor, c ff , can also be placed between v out and fb to improve transient performance. in applications where the pol is far from the ic, it is a good idea to place a 0.1f capacitor from v out C to gnd close to the ic to filter any noise that might be injected onto the v out C trace. the internal pll has a synchronization range of 30% around its programmed frequency. therefore, during external clock synchronization be sure that the external clock frequency is within this 30% range of the rt pro - grammed frequency. see plot of switching frequency vs r t value in the typical performance section. output voltage tracking and soft-start the ltc7150 s allows the user to program its output voltage ramp rate by means of the track/ss pin. an internal 6a current pulls up the track/ss pin to intv cc . putting an external capacitor on track/ss enables soft starting the output to prevent current surge on the input supply. for output tracking applications, track/ss can be externally driven by another voltage source. from 0v to 0.6v, the track/ss voltage will override the internal 0.6v reference input to the error amplifier, thus regulating the feedback voltage to that of the track/ss pin. during this start-up time, the ltc7150 s will operate in discontinuous mode. when track/ss is above 0.6v, tracking is disabled and the feedback voltage will regulate to the internal reference voltage. the relationship between output rise time and track/ss capacitance is given by: t ss = 120000 ? c track/ss multiphase operation for output loads that demand more than 20a of current, multiple ltc7150 ss can be paralleled to run out-of-phase to provide more output current. the mode/sync pin allows the ltc7150 s to synchronize to an external clock and the internal phase-locked-loop allows the LTC7150S to lock onto mode/syncs phase as well. the clkout signal can be connected to the mode/sync pin of the following LTC7150S to line up both the frequency and the phase of the entire system. tying the phmode pin to intv cc , sgnd or floating the pin generates a phase difference between the clock applied on the mode/sync pin and clkout of 180 degrees, 120 degrees, or 90 degrees respectively, which corresponds to 2-phase, 3- phase, or 4-phase operation. a total of 12 phases can be paralleled to run simultaneously out-of-phase with respect to each other by programming the phmode pin of each LTC7150S to different voltage levels. figure?1. setting the output voltage differentially 7150s f01 fb v out ? LTC7150S kelvin to point of load gnd r 1 r 2 c ff v out programming switching frequency connecting a resistor from the rt pin to sgnd programs the switching frequency from 400khz to 3mhz according to the following formula: frequency = 1.67 ? 10 11 r t ( ) lt c7150s 7150sfa
12 for more information www.linear.com/LTC7150S operation external i th compensation external compensation is mandatory for proper opera - tion of the LTC7150S. proper i th components should be selected for opti-loop ? optimization. the compensation network is shown in figure?2. figure?2. external compensation network 7150s f02 r ith c ith i th c ithp table 1 provides a basic guideline for the compensation values that should be used given the frequency of the part. slight tweaks to those values may be required depending on the amount of output capacitance used in the application. table 1. compensation values frequency r ith c ith c ithp 500khz 4.99k 1.5nf 47pf 1mhz 10k 1nf 22pf 2mhz 15k 0.68nf 15pf 3mhz 20k 0.47nf 10pf minimum off-time and minimum on-time considerations the minimum off-time, t off(min) , is the smallest amount of time that the LTC7150S is capable of turning on the bot - tom power mosfet, tripping the current comparator and turning the power mosfet back off. this time is generally about 50ns . the minimum off-time limit imposes a maxi - mum duty cycle of t on /(t on + t off(min) ). if the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. the minimum input voltage to avoid dropout is: v in(min) = v out ? t on + t off(min) t on conversely, the minimum on-time is the smallest dura - tion of time in which the top power mosfet can be in its on state. this time is typically 20ns. in continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of dc min = f ? t on(min) where t on(min) is the minimum on-time. reducing the operating frequency will alleviate the minimum duty cycle constraint. in the rare cases where the minimum duty cycle is sur- passed, the output voltage will still remain in regulation, and the switching frequency will decrease from its programmed value. this is an acceptable result in many applications, so this constraint may not be of critical importance in most cases. high switching frequencies may be used in the design without any fear of output overvoltage. as the sections on inductors and capacitor selection show, high switching frequencies allow the use of smaller board com - ponents, thus reducing the size of the application circuit. input capacitor (c in ) selection the input capacitance, c in , is needed to filter the square wave current at the drain of the top power mosfet. to prevent large voltage transients from occurring, a low esr input capacitor sized for the maximum rms current should be used. the maximum rms current is given by: i rms ? i out(max) v out v in v in v out ? 1 this formula has a maximum at v in = 2v out , where i rms ? i out 2 this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. lt c7150s 7150sfa
13 for more information www.linear.com/LTC7150S operation output capacitor (c out ) selection the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. the output ripple, ? v out , is determined by: v out < i l 1 8 ? f ? c out + esr ? ? ? ? ? ? the output ripple is highest at maximum input volt-age since ? i l increases with input voltage. multiple capaci - tors placed in parallel may be needed to meet the esr and rms current handling requirements. dr y tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. special polymer capacitors are very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have excellent low esr characteristics and small footprints. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the v in input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden in-rush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r and x7r dielectric formulations. these dielectrics have the best temperature and voltage char - acteristics of all the ceramics for a given value and size. since the esr of a ceramic capacitor is so low , the input and output capacitor must instead fulfill a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. typically, 5 cycles are required to respond to a load step, but only in the first cycle does the output voltage drop linearly. the output droop, v droop , is usually about 3 times the linear drop of the first cycle. thus, a good place to start with the output capacitor value is approximately: c out = 3 i out f o ? v droop more capacitance may be required depending on the duty cycle and load step requirements. in most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. a 47f ceramic capacitor is usually enough for these conditions. place this input capacitor as close to the pv in pin as possible. inductor selection given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: i l = v out f ? l 1 v out v in lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a trade-off between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 50% of i out(max) . to guarantee that ripple lt c7150s 7150sfa
14 for more information www.linear.com/LTC7150S operation current does not exceed a specified maximum, the induc - tance should be chosen according to: l = v out f ? i l(max) 1 v out v in(max) once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. as the inductance or frequency in - creases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have ver y low core losses and are pre - ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard," which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and don t radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/emi requirements. new designs for surface mount inductors are available from toko, vishay, nec/tokin, cooper, tdk and wrth elektronik. refer to table 2 for more details. checking transient response the opti-loop compensation allows the transient re - sponse to be optimized for a wide range of loads and output capacitors. the availability of the ith pin not only allows for optimization of the control loop behavior but also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time and settling at this test point truly reflects these close loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the ith external component shown in the table 1 circuit will provide an adequate starting point for most applica - tions. the rc filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested value) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because their various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out im - mediately shifts by an amount equal to the ? i load ? esr, where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generat- ing a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. table 2. inductor selection table (examples) vendor p/n inductance (nh) max current (a) dc resistance (m) dimensions (mm) height (mm) wurth 744308015 150 25 0.37 10 7 6.8 744308033 330 25 0.37 10 7 6.8 coilcraft xal7030-161me 160 32.5 1.15 7.5 7.5 3.1 xal7070-301me 300 33.4 1.06 7.5 7.2 7.0 pulse pa0511.850nlt 85 31 0.39 10.2 7 4.96 pa0512.151nlt 150 24 0.32 7 7 4.96 lt c7150s 7150sfa
15 for more information www.linear.com/LTC7150S operation the initial output voltage step may not be within the band - width of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine phase margin. the gain of the loop increases with the r ith and the bandwidth of the loop increases with decreasing c ith . if r ith is increased by the same factor that c ith is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in most critical frequency ranges of the feedback loop. the output voltage settling behavior is related to the sta - bility of the closed-loop system and will demonstrate the actual overall supply per formance. for detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to analog devices application note 76. in some applications, a more severe transient can be caused by switching in loads with large (>47f ) input capacitors. the discharge input capacitors are effectively put in paral - lel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap ? controller is designed specifically for this purpose and usually incorporates cur - rent limiting, short-circuit protection, and soft-starting. efficiency considerations the per cent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 +) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the cir cuit produce losses, three main sources usually ac - count for most of the losses in ltc7150 s circuits: 1) i 2 r losses, 2) switching and biasing losses, 3) other losses. 1. i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current flows through inductor l but is chopped between the internal top and bottom power mosfets. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1-dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance char - acteristics curves. thus to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) 2. the switching current is the sum of the mosfet driver and control currents. the power mosfet driver cur - rent results from switching the gate capacitance of the power mosfet s. each time a power mosfet gate is switched from low to high to low again, a packet of charge dq moves from in to ground. the resulting dq/ dt is a current out of in that is typically much larger than the dc control bias current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the internal top and bottom power mosfets and f is the switching frequency. the power loss is thus: switching loss = i gatechg ? v in the gate charge loss shows up as current through the intv cc ldo and becomes larger as frequency increases. thus, their effects will be more pronounced in applica - tions with higher input voltage and higher frequency. 3. other hidden losses such as transition loss and cop - per trace and internal load resistances can account for additional efficiency degradations in the overall power system. it is ver y important to include these system level losses in the design of a system. transition loss arises from the brief amount of time the top power mosfet spends in the saturated region during switch node transitions. the LTC7150S internal power de - vices switch quickly enough that these losses are not significant compared to other sour ces. other losses including diode conduction losses during dead-time and inductor core losses which generally account for less than 2% total additional loss. lt c7150s 7150sfa
16 for more information www.linear.com/LTC7150S operation thermal considerations in some applications where the ltc7150 s is operated at a combination of high ambient temperature, high switching frequency, high v in , and high output load, the required power dissipation might push the part to exceed its maxi - mum junction temperature. t o avoid the LTC7150S from exceeding the maximum junc - tion temperature, maximum current rating shall be derated depending on the operating conditions. the temperature rise of the part will var y depending on the thickness of v svin = 5v v pvin = 12v figure?3. current derating at 500khz, 5v svin v svin = 12v v pvin = 12v v svin = 5v v pvin = 12v v svin = 12v v pvin = 12v copper on the pcb board, the number of layers of the board, and the shape of copper trace. in general, a thick continuous piece of copper on the top layer of the pcb for sw and gnd pins will greatly improve the thermal performance of the part. figure?3 to figure?8 shows typical derating curves of the LTC7150S on a standard 6-layer, 2oz copper per layer pcb board (LTC7150S standard demo board). v out is set to 1.2v in all curves. figure?4. current derating at 500khz, 12v svin figure?5. current derating at 1mhz, 5v svin figure?6. current derating at 1mhz, 12v svin v svin = 5v v pvin = 12v figure?7. current derating at 2mhz, 5v svin figure?8. current derating at 2mhz, 12v svin lt c7150s 7150sfa 100 75 100 125 0 5 10 15 20 25 maximum load current (a) 125 7150s f08 0 5 10 15 20 25 maximum load current (a) 7150s f03 0lfm 0lfm 200lfm 400lfm 0 25 50 75 100 125 0 200lfm 5 10 15 20 25 maximum load current (a) 7150s f04 ambient temperature (c) 0lfm 200lfm 400lfm 400lfm 0 25 50 75 100 125 0 5 10 ambient temperature (c) 15 20 25 maximum load current (a) 7150s f05 ambient temperature (c) 0lfm 200lfm 400lfm 0 0 25 50 75 100 125 0 5 10 15 20 25 25 maximum load current (a) 7150s f06 ambient temperature (c) 0lfm 200lfm 400lfm 0 25 50 50 75 100 125 0 5 10 15 20 25 maximum load current (a) 75 7150s f07 ambient temperature (c) v svin = 12v v pvin = 12v 0lfm 200lfm 400lfm temperature ( c) 0 25 50
17 for more information www.linear.com/LTC7150S operation silent switcher architecture the ltc7150 s has integrated capacitors that allow it to operate at high switching frequencies efficiently. the internal v in bypass capacitors allow the sw edges to transition extremely fast, effectively reducing transition loss. the capacitors also greatly reduces sw overshoot during top fet turn-on which improves the robustness of the device over time. board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc7150 s (refer to figure?9). check the following in your layout: 1. are there pairs of capacitors (c in ) between v in and gnd as close as possible on both sides of the package? these capacitors provide the ac current to the internal power mosfet s and their drivers as well as minimize eui/emc emissions. 2. are c out and l closely connected? the (C) plate of c out returns current to gnd and the (C) plate of c in . 3. place the fb dividers close to the part with kelvin connections to v out and v out C at the point of load, for differential v out sensing. 4. keep sensitive components away from the sw pin. the fb resistors, r t resistor, the compensation component, and the intv cc bypass caps should be routed away from the sw trace and the inductor. 5. a ground plane is preferred. 6. flood all unused areas on all layers with copper , which reduces the temperature rise of power components. these copper areas should be connected to gnd. figure?9. example of top layer pcb design c in c in lt c7150s 7150sfa
18 for more information www.linear.com/LTC7150S operation design example as a design example, consider the LTC7150S in an ap - plication with the following specifications: v in = 12v to 15v v out = 1.2v i out(max) = 20a i out(min) = 1a f sw = 1mhz first, r fb1 and r fb2 should be the same value in order to program the output to 1.2v. a typical value that can be used here for both resistors is 10k . for best accuracy, a 0.1% resistor should be used. for a typical soft start time of 2ms (0% to 100% of final v out value), the c track/ss should be: 6a = c track /ss ? 0.6v 2ms c track/ss = 20nf a typical 22nf capacitor can be used for c track/ss . because efficiency is important at both high and low load current, discontinuous mode operation will be utilized. select from the characteristic curves the correct r t resistor for the 1mhz switching frequency. based on that, r t should be 162k . then calculate the inductor value to achieve a current ripple that is about 40% of the maximum output current (20a) at maximum v in : l = 1.2v 1mhz ? 8a ? ? ? ? ? ? 1 ? 1.2v 15v ? ? ? ? ? ? = 0.138h the closest standard value inductor higher would be 0.15h. c out will be selected based on the esr that is required to satisfy the output ripple requirement and the bulk ca - pacitance needed for loop stability. for this design, two 100f ceramic capacitors will be used. c in should be sized for a maximum current rating of: i rms = 20a 1.2v 15v ? ? ? ? ? ? 15v 1.2v ? 1 ? ? ? ? ? ? 1/2 = 5.4a decoupling v in with two 22f ceramic capacitors, as shown in figure?9, is adequate for most applications. lt c7150s 7150sfa
19 for more information www.linear.com/LTC7150S typical applications high efficiency, dual phase 1.2v/40a step-down supply package photo lt c7150s 7150sfa 4.7f 22pf 7150s ta02 0.15h 22f 2 22f 2 162k 4.7f 100f 4 0.1f 10k sv in LTC7150S run pv in track/ss clkout intv cc mode/sync pgood v out ? 2.2nf v out ? fb sw v in 3.1v to 20v v out 1.2v 40a rt gnd ith sv in LTC7150S 5k phmode run pv in track/ss clkout intv cc mode/sync pgood fb sw 22pf rt gnd ith phmode 330f 2 0.15h 10k 162k
20 for more information www.linear.com/LTC7150S package description bga package 42-lead (6mm 5mm 1.30mm) (reference adi dwg # 05-08-1515 rev c) please refer to http://www.linear.com/product/LTC7150S#packaging for the most recent package drawings. notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view pin ?a1? corner x y package bottom view 3 see notes suggested pcb layout top view bga 42 0417 rev c tray pin 1 bevel package in tray loading orientation detail a pin 1 0.000 1.2 0.4 2.0 0.4 1.2 2.0 2.4 1.6 0.8 0.8 1.6 2.4 0.000 detail a ?b (42 places) f g e a b c d 2 1 4 3 56 d detail b package side view m x yzddd m zeee 0.40 0.025 ? 42x e b e e b a2 f g bga package 42-lead (6mm 5mm 1.30mm) (reference ltc dwg # 05-08-1515 rev c) 6 see notes 4 aaa z 2 aaa z 2 5. primary datum -z- is seating plane 6 package row and column labeling may vary among products. review each package layout carefully ! symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 1.10 0.30 0.80 0.45 0.37 nom 1.30 0.40 0.90 0.50 0.40 6.00 5.00 0.80 4.80 4.00 0.20 0.70 max 1.50 0.50 1.00 0.55 0.43 0.15 0.20 0.20 0.15 0.08 total number of balls: 42 dimensions notes ball ht ball dimension pad dimension substrate thk mold cap ht a detail b substrate a1 ccc z z // bbb z h2 h1 mold cap b1 component pin ?a1? lt c7150s 7150sfa
21 for more information www.linear.com/LTC7150S information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. revision history rev date description page number a 12/17 clarified conditions on top row of graphs clarified pgnd clarified block diagram clarified minimum off-time paragraph clarified design example inductor formula 5 8 9 12 18 lt c7150s 7150sfa
22 for more information www.linear.com/LTC7150S lt 1217 rev a ? printed in usa www.linear.com/LTC7150S ? analog devices, inc. 2017 related parts typical application part number description comments ltc3605/ ltc3605a 20v, 5a synchronous step-down regulator 4v < v in < 20v, 0.6v < v out < 20v, 96% maximum efficiency, 4mm 4mm qfn-24 package lt c3613 24v, 15a monolithic step-down regulator with differential output sensing 4.5v < v in < 24v, 0.6v < v out < 5.5v, 0.67% output voltage accuracy, valley current mode, programmable from 200khz to 1mhz, current sensing, 7mm 9mm qfn-56 package lt c3622 17v, dual 1a synchronous step-down regulator with ultralow quiescent current 2.7v < v in < 17v, 0.6v < v out < v in , 95% maximum efficiency, 3mm 4mm dfn-14 and msop-16 package lt c3623 15v, 5a rail-to-rail synchronous buck regulator 4v v in 15v, 96% maximum efficiency, 3mm 5mm qfn package ltc3624 17v, 2a synchronous step-down regulator with 3.5a quiescent current 2.7v < v in < 17v, 0.6v < v out < v in , 95% maximum efficiency, 3.5a i q , zero-current shutdown, 3mm 3mm dfn-8 package lt c3633a/ ltc3633a-1 dual channel 3a, 20v monolithic synchronous step-down regulator 3.6v < v in < 20v, 0.6v < v out < v in , 95% maximum efficiency, 4mm 5mm qfn-28 and tssop-28 package lt m4639 low v in 20a dc/dc module step-down regulator complete 20a switch mode power supply, 2.375v < v in < 7v, 0.6v < v out < 5.5v, 1.5% maximum total dc output voltage error, differential remote sense amp, 15mm 15mm bga package ltm4637 20a dc/dc module step-down regulator complete 20a switch mode power supply, 4.5v < v in < 20v, 0.6v < v out < 5.5v, 1.5% maximum total dc output voltage error, differential remote sense amp, 15mm 15mm bga or lga package ltc7130 20v, 20a monolithic buck converter with ultralow dcr sensing 4.5v < v in < 20v, 95% maximum efficiency, optimized for low duty cycle applications, 6.25mm 7.5mm bga package 3.3v/20a step-down converter 12v in to C3.3v out 14a step-down converter lt c7150s 7150sfa 4.7f 0.1f 7150s ta03a 22f 2 47f 2 sv in LTC7150S run pv in track/ss 45.3k clkout intv cc mode/sync pgood fb v out ? sw v in 4v to 20v v out 3.3v 20a rt 1nf gnd ith phmode 45.3k 1nf 10k 22pf 100f 2 ?3.3v out 14a 0.33h 10k 10k 162k 4.7f 0.1f 7150s ta03b 22f 2 47f 2 sv in LTC7150S run 22pf pv in track/ss clkout intv cc mode/sync pgood fb sw 12v in rt 100f 2 gnd ith phmode 0.1f v out ? 0.33h 10k 162k

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