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| to learn more about on semiconductor, please visit our website at www.onsemi.com please note: as part of the fairchild semiconductor integration, some of the fairchild orderable part numbers will need to change in order to meet on semiconductors system requirements. since the on semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the fairchild part numbers will be changed to a dash (-). this document may contain device numbers with an underscore (_). please check the on semiconductor website to verify the updated device numbers. the most current and up-to-date ordering information can be found at www.onsemi.com . please email any questions regarding the system integration to fairchild_questions@onsemi.com . is now part of on semiconductor and the on semiconductor logo are trademarks of semico nductor components industries, llc dba on semiconductor or its subsid iaries in the united states and/or other countries. on semiconductor ow ns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellec tual property. a listing of on semiconductor?s product/patent cover age may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semicon ductor makes no warranty, representation or guarantee regarding the s uitability of its products for any particular purpose, nor does on semico nductor assume any liability arising out of the application or use of any product or circuit, and speci?ca lly disclaims any and all liability, including without limitation spe cial, consequential or incidental damages. buyer is responsible for i ts products and applications using on semiconductor products, including compliance with all laws, regul ations and safety requirements or standards, regardless of any suppor t or applications information provided by on semiconductor. ?typica l? parameters which may be provided in on semiconductor data sheets and/or speci?cations can and do vary in diffe rent applications and actual performance may vary over time. all operat ing parameters, including ?typicals? must be validated for each custo mer application by customer?s technical experts. on semiconductor does not convey any license und er its patent rights nor the rights of others. on semiconductor products a re not designed, intended, or authorized for use as a critical compone nt in life support systems or any fda class 3 medical devices or medical devices with a same or similar classi?ca tion in a foreign jurisdiction or any devices intended for implantation i n the human body. should buyer purchase or use on semiconductor products fo r any such unintended or unauthorized application, buyer shall indemnify and hold on semico nductor and its of?cers, employees, subsidiaries, af?liates, and di stributors harmless against all claims, costs, damages, and expense s, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associa ted with such unintended or unauthorized use, even if such claim alleges th at on semiconductor was negligent regarding the design or manufacture o f the part. on semiconductor is an equal opportunity/af?rmative action employer. this literatu re is subject to all applicable copyright laws and is not for resale in any manne r.
september 2014 ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FTL11639 ? rev. 1. 0.5 ftl7 116 39 configurable load switch and reset timer ftl 11639 configurable load switch and reset timer features ? factory customized turn-on time : 38 ms ? factory customized turn-off delay: 900 ms ? factory programmed reset delay : 11 .5 s ? factory programmed reset pulse: 400 ms ? adjustable reset delay option with external resistor ? low < 0.2 a typical shutdown current ? off pin turns off load switch to maintain battery charge during shipment and inventory (ready to u se right out of the box) ? typical r on : 21 m (typ .) at v bat =4.5 v ? 3.8 a / 4.5 a m ax imum continuous current (jedec 2s2p, no via / with thermal via) ? low i cct saves power interfacing to l ow -voltage chips ? input voltage operating range: 1.2 v to 5.5 v ? over-voltage protection: allow input pins > v bat ? slew rate / inrush control with t r : 2.7 ms (t yp ical) ? output capacitor discharge function ? zero-second test-mode enable ? iec61000-4-2, level 4 compliant sys_wake pin ? esd protected: - 8 kv hbm esd (per jesd22-a114) - 10 kv hbm esd (pin to pin, v bat & v out ) - 2 kv cdm (per jesd22-c101) applications ? smart phones, tablet pcs ? storage, dslr, and portable devices description the ftl 11639 is both a timer for resetting a mobile device and an advanced load management device for applicatio ns requiring a highly integrated solution. if the mobile device is off, holding /sr0 low (by pressing power-on key) for 38 ms 20% turns on the pmic. as a reset timer, it has one input and one fixed delay output. it generates a fixed delay of 11 .5 s 20% by disconnecting the pmic from the battery power supply. ftl 11639 does not accept a new input signal for 400 ms 20% to give the pmic enough time to turn off. the reset delay can be customized by connecting an external resistor to the delay_adj pin. refer to table 5 . as an advanced load management switch, the FTL11639 disconnects loads powered from the dc power rail (<6 v) with stringent off-state current targets and high load capacitances (up to 2 00 f). the ftl 11639 consists of a slew-rate controlled low-impedance mosfet switch ( 21 m t yp ical at 4.5 v) that has exceptionally low off-state curren t drain (<0.2 a typical ) to facilitate compliance with standby power requirements . the s lew -rate-controlled turn- on characteristic prevents inrush current and the resulting excessive voltage drop on power rails. the low i cct enables direct interface to lower-voltage chipsets without external translation, while maintaining low power consumption. the device is packaged in advanced , fully g reen, 1. 31 mm x 1. 62 mm, wafer-level chip-scale packaging (wlcsp) with backside laminate; providing excellent thermal conductivity, small footprint, and low electrical resista nce for a wide application range. related resources for additional information, please contact: http://www.fairchildsemi.com/cf/#regional-sales ordering information part number top mark operating temperature range package packing method ftl 11639 ucx uc -40 to +85c 12 -ball wlcsp (with backside laminate) , 3x4 array, 0.4 mm pitch, 250 m ball, nominal: 1.31 mm x 1. 62 mm 3000 units on tape and reel ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FTL11639 ? rev. 1. 0.5 2 ftl 116 39 configurable load switch and reset timer application diagram v bat delay_adj off /sr0 v out dsr sys_wake gnd FTL11639 pmic baseband power key phone_on_n v out system reset gpio or wake_1 wake_2 charger_in gpio or v bat switching charger ic e.g. fan540x r sense battery v bat sw v bus r pu v bus figure 1. typical application with stand alone switching charger ic v bat 1 off 23 /sr0 4 dsr v out delay_adj sys_wake gnd 56 7 8 FTL11639 switch-mode battery charger battery monitoring system or gpio r pd gpio or v bat charger in event 1 event 2 battery pmic with integrated charger power key over voltage protection usb connector vph_pwr opv fets over voltage protection 2 dc jack r pu power_on v bat figure 2. typical application pmic with integrated charger ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FTL11639 ? rev. 1. 0.5 3 ftl 116 39 configurable load switch and reset timer functional block diagram oscillator digital logic & counter voltage reference /sr0 v bat dsr v out turn-on slew rate controlled driver gnd delay_adj output discharge off sys_wake v bat figure 3. block diagram pin configuration b1 c1 d1 d3 d2 c2 b2 a2 c3 a1 b3 a3 b3 a3 c3 d3 b1 d2 c2 b2 a2 a1 c1 d1 figure 4. top view figure 5. bottom view pin definitions pin # name description normal operation 0-second factory-test mode (1) a1 , a2 , a3 v out switch output switch output b1, b2, b3 v bat supply input supply input c1 gnd ground ground c2 dsr delay selection input; connected to gpio with a 100 k pull - up resistor or to v bat directly without pull-up resistor logic low c3 /sr0 power-on or reset input; active low logic low d1 delay_adj reset delay adjustment; must tie to v bat directly if not used. to adjust the reset delay, a resistor (r adj ) is connected between this pin and ground. connected to v bat or gnd d2 off load switch disable; falling edge triggered; changes load switch from on state to off state dont care d3 sys_wake system wake-up input; changes load switch from off state to on state dont care note: 1. zero-second factory test mode is for t von and t phl1 only . ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FTL11639 ? rev. 1. 0.5 4 ftl 116 39 configurable load switch and reset timer absolute maximum ratings stresses exceeding the absolute maximum ratings may damag e the device. the device may not function or be operable above the recommended operating conditions and stressing th e parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operat ing conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameters condition min. max. unit v bat v bat to gnd -0.3 6.5 v v out v out to gnd i sw maximum continuous switch current 2s2p jedec std. pcb 3.8 a 2s2p + thermal via jedec std. pcb 4. 7 p d power dissipation i out =4.5 a , r on = 20 m? ( m ax .) 0.41 w v in dc input voltage /sr0, dsr, off, delay_adj -0.5 6.5 v sys_wake (2) v bat +0.3 i ik dc input diode current v bat < 0 v - 50 ma i cc dc v cc or ground current per supply pin ? 100 ma t stg storage temperature range - 65 +150 ? c t j junction temperature under bias +150 ? c t l junction lead temperature, soldering 10 seconds +260 ? c ? ja thermal resistance, junction- to -ambient 2s2p jedec std. pcb 86 c/w 2s2p + thermal via jedec std. pcb 48 ? jc ? thermal resistance, junction- to -case (3) 10.9 c/w esd human body model, jedec: jesd22-a114 all pins 8 kv human body model, pin to pin (4) v bat , v out 10 iec 61000-2-4, level 4, for sys_wake (5) air 15 contact 8 charged device model, jesd22-c101 2 notes: 2. sys_wake operates up to 28 v if an external resistor is attached. a valu e of 100 k ? is typically recommended. 3. uniform temperature at bottom solder. 4. test conditions: v bat vs. gnd and v out vs. gnd. 5. a 100 k ? resistor is required. recommended operating conditions the recommended operating conditions table defines the condi tions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameters condition min. max. unit v bat input voltage (6) v bat 1.2 5.5 v v in /sr0, dsr, off 0 sys_wake 0 v bat v out output voltage 0 5 .5 v i sw maximum continuous switch current 2s2p jedec std. pcb 3.8 a 2s2p + thermal via jedec std. pcb 4.5 t rfc v bat recovery time after power down v bat =0 v after power down, rising to 0.5 v 5 ms t a free-air operating temperature - 40 +85 ? c note: 6. v bat should never be allowed to float while input pins are driven . ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FTL11639 ? rev. 1. 0.5 5 ftl 116 39 configurable load switch and reset timer electrical characteristics unless otherwise noted, v bat = 1. 2 to 5.5 v and t a =-40 to +85c; typical values are at v bat =4.5 v and t a =25c. symbol parameters conditions min. typ. max. unit basic operation i off off supply current v bat =4 .5 v , v out =open, load switch=off 5.5 a i sd shutdown current v bat =4.5 v , v out =gnd , load switch=off 0. 2 5.5 a v bat =3.8 v , v out =gnd , load switch=off 0. 1 4.5 r on on resistance v bat =5.5 v, i out =1 a (7) 20 24 m v bat =4.5 v, i out =1 a , t a =25c (7) 21 25 v bat =3.3 v, i out =500 ma (7 ) 24 29 v bat =2.5 v, i out =500 ma (7 ) 28 35 v bat =1.8 v, i out =250 ma (7 ) 37 45 v bat =1.2 v, i out =250 ma , t a =25c (7) 75 100 r pd output discharge r pull down v bat =4.5 v, v out =off , i force =20 ma , t a =25c 65 85 v ih input high voltage (8) 1.8 v ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FTL11639 ? rev. 1. 0.5 7 ftl 116 39 configurable load switch and reset timer typical characteristics figure 6. shutdown current vs. temperature figure 7. shutdown current vs. supply voltage figure 8. off supply current vs. temperature (v out =0 v) figure 9. off supply current vs. supply voltage (v out =0 v) figure 10. quiescent current vs. temperature figure 11. quiescent current vs. supply voltage figure 12. quiescent current vs. on voltage (v bat =4.5 v) figure 13. quiescent current vs. on voltage (v bat =5.5 v) ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FTL11639 ? rev. 1. 0.5 8 ftl 116 39 configurable load switch and reset timer typical characteristics figure 14. output discharge resistor r pd vs. temperature figure 15. output discharge resistor r pd vs. supply voltage figure 16. r on vs. temperature figure 17. r on vs. supply voltage figure 18. t r /t f vs. temperature figure 19. i sw vs. (v ibat -v out ) soa figure 20. t r /t don vs. temperature figure 21. t r vs. supply voltage 0.01 0.1 1 10 100 0.01 0.1 1 10 i d , drain current (a) v ds , drain-source voltage (v) dc 10s 1s 100ms r ds(on) limit single pulse r q ja = 238 o c/w t a = 25 o c 10ms 1ms ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FTL11639 ? rev. 1. 0.5 9 ftl 116 39 configurable load switch and reset timer typical characteristics figure 22. t r vs. supply voltage figure 23. turn-off response (v bat =4.5 v, c in =10 f, c l =100 f, without external r l ) figure 24. turn-on response (v bat =4.5 v, c in =10 f, c l =1 f, r l =50 ? ) figure 25. turn-on response (v bat =4.5 v, c in =10 f, c l =100 f, r l =5 ? ) figure 26. fall time as a function of external resistive load (c l =1 f, 10 f, and 100 f) figure 27. fall time as a function of external capacitive load (r l =5 ? , 50 ? , and 500 ? ) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 10 15 20 25 30 35 voltage (v) time (ms) v on +25c 0.001 0.010 0.100 1.000 10.000 1 10 100 1000 10000 t fall (ms) r load ( ? ) 100 m f 10 m f 1 m f 0.001 0.01 0.1 1 10 100 0.1 1 10 100 1000 t fall (ms) c load ( m f) 500 ? 50 ? 5 ? ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FTL11639 ? rev. 1. 0.5 10 ftl 116 39 configurable load switch and reset timer application information reset timer and advanced load management the FTL11639 is both a reset ic and an advanced load management device. a typical application is shown in figure 1. disconnect pmic from battery with off pin (turn off) after holding the dsr pin high, the off pin chang es from high to low ( fa lling e dge trigger ed ) and remains low for at least 1 ms. the FTL11639 triggers an internal counter to allow a factory-customized 900 ms delay before turning of f internal load switch. the delay allows the pmic to complete a power-down s eq uence before safely disconnecting from the power supply . however, the turn-off sequence is terminated if a higher priority input is detected in t sd period (see resolving input conflicts) . alternatively, after holding dsr pin low, the off pin changes from high to low (falling edge triggered) and remains low for at least 1 ms . the ftl 11639 triggers the zero-second turn-o ff . delay t sd is significantly reduced to 0.6 ms to avoid the default delay to turn-off load switch (t sd ). with its stringent shutdown current flow, the FTL11639 significantly reduces the current drain on a battery when th e pmic is turned off , preserv ing battery power for a long er period when a mobile device is in shutdown m ode . power on there are two methods to turn on the load switch to wake up the pmic. when a high is inserted to the sys_wake p in or when /sr0 is held low for > 38 ms (see figure 30) ; ftl 11639 turns on its load switch to allow the pmic to connect to the battery. the reset feature is disabled whe n v out is toggled from off to on . continuously holding /sr0 low does not trigger a reset event. to enable the reset feature, /sr0 must return to high such that FTL11639 resets its internal counter. reset timer and power off with /sr0 p in during normal operation of a mobile device, if a reset operation or a power-off event is needed; holding the power switch, to which /sr0 is connected and is forced low, for at least 11.5 s causes the FTL11639 to cut off the supply power to pmic. FTL11639 does not accept any ne w input signal for 400 ms 20% to give the pmic enough time to turn off. after reset, the load switch remains in off state and the /sr0 must return to high before any new input signal i s accepted. however, when load switch is in on state and /sr0 is forced to low, in event of /sr0 returning to high within 11.5 s, the FTL11639 resets its counter and v out remains in on state; there is no change on v out and a reset does not occur. power-on reset when the ft l11639 is connected to a battery (v bat 1.2 v), the part goes into power-on reset (por) mode. all internal registers are reset and v out is on at the end of por sequence (see table 2) . zero-second factory test mode FTL11639 includes a zero-second factory test mode to shorten the turn-on time for v out (t von ) and timer delay before reset (t phl1 ) for factory testing. when v out is off, the default turn-on time (t von ) is 38 ms. if the dsr pin is low prior to /sr0 going low, the FTL11639 bypasses the 38 ms delay and v out is changed from off to on immediately. similarly, default reset delay (t phl1 ) is 11 .5 s. if v out is on and the dsr pin is low prior to /sr0 going low, the FTL11639 enters zero-second factory test mode and bypasses the default reset delay of 11 .5 s; v out is pulled from on to off immediately. the reset pulse (t rec1 ) remains at 400 ms in zero-second factory test mode. the dsr pin should never be left floating during normal operation. table 1. v out and input conditions function initial conditions (t=0 second) associated delay (typ ical ) v out /sr0 sys_wake off dsr before after power- on low x ( 12 ) x low t von < 4 ms off on low x x high t von = 38 ms off on high high x x t on =4.4 ms off on reset function (power-off) low x x low t phl1 < 1 ms t rec1 =400 ms on off low x x high t phl1 =11 .5 s ( 13 ) t rec1 =400 ms on off turn off high low ( 12 ) low t sd < 1 ms on off high low high t sd= 900 ms on off notes: 12. x= dont care, = f alling e dg e. 13. reset de lay (t phl1 ) is adjustable (see table 5) . ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FTL11639 ? rev. 1. 0.5 11 ftl 116 39 configurable load switch and reset timer table 2. pin condition after por pin name /sr0 dsr sys_wake off v out default state (after por) 1 1 0 1 on note: 14. 1=input logic high; 0=input logic low; on =load switch is in on state. timing diagrams ` 90% 50% off v out 10% t f t sd t off 10% sys_wake t don 50% v out 90% t on t r figure 28. ti ming diagram (off vs. v out ) figure 29. timing diagram (sys_wake vs. v out ) /sr0 v out t von 50% 50% /sr0 v out t phl1 t rec1 50% 50% 50% figure 30. power on with /sr0 figure 31. reset timing ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FTL11639 ? rev. 1. 0.5 12 ftl 116 39 configurable load switch and reset timer resolving input conflict ftl 11639 allows multiple inputs at the same time and c an resolve conflicts based on the priority level (see table 3) . when two input pins are triggered at the same time, only th e higher priority input is served and the lower priority input is be ing ignored. to have the lower-priority signal serviced, it must be repeated. table 3. input priority input priority (1=highest) /sr0 1 sys_wake 2 off 3 special note on off p in in the t sd period (dsr=high only , see figure 28 ); if /sr0 or sys_wake is triggered when 0 < t < t sd , the FTL11639 exits the turn-off sequence and v out remains in on state . the higher priority input is served regardless of the con dition of the off pin. to re-initiate the turn-off sequence, the off pins must return to high, then toggle from high to low again. the same input priority applies ( table 3 ) if dsr = high. application-specific note on off pin it is a common to place FTL11639 between the battery and the pmic. in this configuration, the input to the off pin is logic low after the FTL11639 completes the por. this is because the off pin is commonly tied to the i/o of the pmic or baseband, which has no power. per table 2 , the internal register of the off pin is set to high after por. therefore, a high- to -low transition (a falling edge) is triggered when FTL11639 completes por. FTL11639 immediately starts the delay to turn o ff l oad switch (t sd ). the vout pin changes from on state to off state unless t sd is interrupted (see special note on off pin) . similiarly, if the input to the off pin is logic high when FTL11639 completes its por, the vout pin remains on. table 4. off pin behavior vout (after por) immedate input to off after por associated delay vout on high n/a on on low t sd = 900 ms off special note on sys_wake pin the sys_wake pin is designed and characterized to handle high-voltage input for at least 20 v. therefore, in application, a current-limiting resistor (i.e 100 k ?) is required between the sys_wake pin and the input signal regardless of input voltage. adjustable reset delay with an external resistor and dsr the reset delay is adjustable by connecting a common ly available, low-power, 5%, rohs-compliant resistor between the delay_adj pin and the gnd pin (see table 5) . to disable the adjustable delay feature, delay_adj should be tied to v bat directly. the reset delay is factory programmed at 7.5 s. the additional power consumption caused by using an external resistor is negligible. the external resistor is normally disconnected and is enabled for milliseconds when /sr0 is pulled low. this external adjustment provides an alternati ve for delay time for engineering and production at customer locations . fairchild can also factory program a wide range of turn- on times for v out (t von ), timer delay before reset (t phl1 ), reset timeout delay for v out (t rec1 ), and load switch turn-off time (t off ) to match customer applications . the external resistor (r adj ) c an be eliminated by factory programming, if desired. for details, contact an authorized sales representative: http://www.fairchildsemi.com/cf/#regional-sales . table 5. delay adjustment vs. external resistor external resistor r adj (k?) delay multiplier adjusted reset delay t phl1 _adj , (seconds) 20% tie to gnd (no resistor) 0.50 x t phl1 5.8 3.9 0.75 x t phl1 8.6 10 1.25 x t phl1 14.4 22 1.50 x t phl1 17.3 47 1.75 x t phl1 20.1 120 2.00 x t phl1 23 .0 tie to v bat (no resistor) 1.00 x t phl1 11 .5 ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FTL11639 ? rev. 1. 0.5 13 ftl 116 39 configurable load switch and reset timer i ntellimax? switch inside the ftl 11639 input capacitor th e intellimax ? switch inside the reset timer doesnt require an input capacitor. to reduce device inrush curre nt, a 0.1 f ceramic capacitor, c in , is recommended close to the v bat pin. a higher value of c in can be used to reduce the voltage drop experienced as the switch is turned on into a large capacitive load. output capacitor while the load switch works without an output capacitor; if parasitic board inductance forces v out below gnd when switching off, a 0.1 f capacitor, c out , should be placed between v out and gnd. fall time device output fall time can be calculated based on the r c constant of the external components, as follows: 2.2 ? ? ? l l f c r t (1) where t f is 90% to 10% fall time; r l is output load; and c l is output capacitor. the same equation works for a device with a pull-do wn output resistor. r l is replaced by a parallel connected pull-down and an external output resistor combination, calculated as : 2.2 ? ? ? ? ? l pd l pd l f c r r r r t (2) where t f is 90% to 10% fall time; r l is output load; r pd =65 ? is output pull-down resistor; and c l is the output capacitor. resistive output load if resistive output load is missing, the intellimax switch without a pull-down output resistor does not discharge the output voltage. output voltage drop depends, in that case, mainly on external device leak s. application specifics at maximum operational voltage (v bat =5.5 v) , device inrush current might be higher than expected. spike current should be taken into account if v bat >5 v and the output capacitor is much larger than the input capacitor. input current i bat can be calculated as: dt t dv c c r t v t i out in load load out bat )( ) ( )( )( ? ? ? (3) where switch and wire resistances are neglected and capacitors are assumed ideal. estimating v out (t)=v bat /10 and using experimental formula for slew rate (dv out (t)/dt), spike current can be written as: ? ? ? ? ? ? 255 .0 05 .0 10 max ? ? ? ? bat in load load bat bat v c c r v i (4) where supply voltage v bat is in volts; capacitances are in micro farads; and resistance is in ohms. example: if v bat =5.5 v, c load =100 f, c in =10 f, and r load =50 ? ; calculate the spike current by: a a i bat 8.1 ) 255 .0 5.5 05 .0 )( 10 100 ( 50 10 5.5 ) max( ? ? ? ? ? ? ? maximum spike current is 1.8 a, while average ramp-up current is: a dt t dv c c r t v t i bat in load load out bat 275 .0 0022 .0 100 50 / 75 .2 )( ) ( )( )( ? ? ? ? ? ? ? output discharge the device contains a r pd = 65 on -chip pull-down resistor for quick output discharge. the resistor is activated when the switch is turned off. ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FTL11639 ? rev. 1. 0.5 14 ftl 116 39 configurable load switch and reset timer recommended layout for best thermal performance and minimal inductance and parasitic effects, keeping the input and output traces short and capacitors as close to the device as poss ible is recommended. additional recommended layout considerations include: ? a1, a2, and a3 are interconnected at pcb, as close to the landing pad as possible. ? b1, b2, and b3 are interconnected at pcb, as close to the landing pad as possible. ? c1 (gnd) is connected to gnd plane o f pcb. ? reserve a pad for capacitor connection (c1) between v bat and gnd, if no input capacitor is planned. ? reserve a pad for capacitor connection (c2) between v out and gnd, if no output capacitor is planned. ? use a dedicated v out or v bat plane to improve thermal dissipation. figure 32. sample layout product specific package dimensions d e x y 1.615 0.030 1.310 0.030 0.255 0.208 www. onsemi.com 1 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductors product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. typical parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including typic als must be validated for each customer application by customers technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 www.onsemi.com literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your localsales representative ? semiconductor components industries, llc |
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