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1 BSZ070N08LS5 rev.2.2,2016-08-18 final data sheet tsdson-8fl mosfet optimos a 5power-transistor ,80v features ?idealforhighfrequencyswitchingandsync.rec. ?optimizedtechnologyfordc/dcconverters ?excellentgatechargex r ds(on) product(fom) ?verylowon-resistancer ds(on) ?n-channel,logiclevel ?100%avalanchetested ?pb-freeplating;rohscompliant ?qualifiedaccordingtojedec 1) fortargetapplications ?halogen-freeaccordingtoiec61249-2-21 ?highersolderjointreliabilitywithenlargedsourceinterconnection table1keyperformanceparameters parameter value unit v ds 80 v r ds(on),max 7.0 m w i d 40 a q oss 29 nc q g (0v..4.5v) 14 nc type/orderingcode package marking relatedlinks BSZ070N08LS5 pg-tsdson-8 fl 070n08l - 1) j-std20 and jesd22 (enlarged source interconnection) 8 d 7 d 6 d 5 d s 1 s 2 s 3 g 4
2 optimos a 5power-transistor ,80v BSZ070N08LS5 rev.2.2,2016-08-18 final data sheet tableofcontents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 (enlarged source interconnection) 8 d 7 d 6 d 5 d s 1 s 2 s 3 g 4
3 optimos a 5power-transistor ,80v BSZ070N08LS5 rev.2.2,2016-08-18 final data sheet 1maximumratings at t a =25c,unlessotherwisespecified table2maximumratings values min. typ. max. parameter symbol unit note/testcondition continuous drain current i d - - - - - - 40 40 13 a t c =25c t c =100c t a =25c, r thja =60k/w 1) pulsed drain current 2) i d,pulse - - 160 a t c =25c avalanche energy, single pulse 3) e as - - 104 mj i d =20a, r gs =25 w gate source voltage v gs -20 - 20 v - power dissipation p tot - - 69 w t c =25c operating and storage temperature t j , t stg -55 - 150 c iec climatic category; din iec 68-1: 55/150/56 2thermalcharacteristics table3thermalcharacteristics values min. typ. max. parameter symbol unit note/testcondition thermal resistance, junction - case, bottom r thjc - 1.1 1.8 k/w - device on pcb, minimal footprint r thja - - 62 k/w - device on pcb, 6 cm 2 cooling area 1) r thja - - 60 k/w - 1) device on 40 mm x 40 mm x 1.5 mm epoxy pcb fr4 with 6 cm 2 (one layer, 70 m thick) copper area for drain connection. pcb is vertical in still air. 2) see diagram 3 for more detailed information 3) see diagram 13 for more detailed information (enlarged source interconnection) 8 d 7 d 6 d 5 d s 1 s 2 s 3 g 4
4 optimos a 5power-transistor ,80v BSZ070N08LS5 rev.2.2,2016-08-18 final data sheet 3electricalcharacteristics table4staticcharacteristics values min. typ. max. parameter symbol unit note/testcondition drain-source breakdown voltage v (br)dss 80 - - v v gs =0v, i d =1ma gate threshold voltage v gs(th) 1.1 1.7 2.3 v v ds = v gs , i d =36a zero gate voltage drain current i dss - - 0.1 10 1 100 a v ds =80v, v gs =0v, t j =25c v ds =80v, v gs =0v, t j =125c gate-source leakage current i gss - 1 100 na v gs =20v, v ds =0v drain-source on-state resistance r ds(on) - - 7.4 5.9 9.4 7.0 m w v gs =4.5v, i d =10a v gs =10v, i d =20a gate resistance 1) r g - 1.3 2 w - transconductance g fs 26 52 - s | v ds |>2| i d | r ds(on)max , i d =20a table5dynamiccharacteristics values min. typ. max. parameter symbol unit note/testcondition input capacitance 1) c iss - 1800 2340 pf v gs =0v, v ds =40v, f =1mhz output capacitance 1) c oss - 280 364 pf v gs =0v, v ds =40v, f =1mhz reverse transfer capacitance 1) c rss - 12 21 pf v gs =0v, v ds =40v, f =1mhz turn-on delay time t d(on) - 6.1 - ns v dd =40v, v gs =10v, i d =20a, r g,ext =3 w rise time t r - 4.8 - ns v dd =40v, v gs =10v, i d =20a, r g,ext =3 w turn-off delay time t d(off) - 24.6 - ns v dd =40v, v gs =10v, i d =20a, r g,ext =3 w fall time t f - 5.8 - ns v dd =40v, v gs =10v, i d =20a, r g,ext =3 w table6gatechargecharacteristics 2) values min. typ. max. parameter symbol unit note/testcondition gate to source charge q gs - 5 - nc v dd =40v, i d =20a, v gs =0to4.5v gate to drain charge 1) q gd - 5 7 nc v dd =40v, i d =20a, v gs =0to4.5v switching charge q sw - 6.9 - nc v dd =40v, i d =20a, v gs =0to4.5v gate charge total 1) q g - 14.1 18 nc v dd =40v, i d =20a, v gs =0to4.5v gate plateau voltage v plateau - 2.9 - v v dd =40v, i d =20a, v gs =0to4.5v gate charge total, sync. fet q g(sync) - 25 - nc v ds =0.1v, v gs =0to10v output charge 1) q oss - 29 39 nc v dd =40v, v gs =0v 1) defined by design. not subject to production test 2) see 2 gate charge waveforms 2 for parameter definition (enlarged source interconnection) 8 d 7 d 6 d 5 d s 1 s 2 s 3 g 4
5 optimos a 5power-transistor ,80v BSZ070N08LS5 rev.2.2,2016-08-18 final data sheet table7reversediode values min. typ. max. parameter symbol unit note/testcondition diode continous forward current i s - - 40 a t c =25c diode pulse current i s,pulse - - 160 a t c =25c diode forward voltage v sd - 0.85 1.2 v v gs =0v, i f =20a, t j =25c reverse recovery time 1) t rr - 32 64 ns v r =40v, i f =20a,d i f /d t =100a/s reverse recovery charge 1) q rr - 27 54 nc v r =40v, i f =20a,d i f /d t =100a/s 1) defined by design. not subject to production test (enlarged source interconnection) 8 d 7 d 6 d 5 d s 1 s 2 s 3 g 4
6 optimos a 5power-transistor ,80v BSZ070N08LS5 rev.2.2,2016-08-18 final data sheet 4electricalcharacteristicsdiagrams diagram1:powerdissipation t c [c] p tot [w] 0 25 50 75 100 125 150 175 0 20 40 60 80 p tot =f( t c ) diagram2:draincurrent t c [c] i d [a] 0 25 50 75 100 125 150 175 0 10 20 30 40 50 i d =f( t c ); v gs 3 10v diagram3:safeoperatingarea v ds [v] i d [a] 10 -1 10 0 10 1 10 2 10 -1 10 0 10 1 10 2 10 3 1 s 10 s 100 s 1 ms 10 ms dc i d =f( v ds ); t c =25c; d =0;parameter: t p diagram4:max.transientthermalimpedance t p [s] z thjc [k/w] 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 -2 10 -1 10 0 10 1 0.5 0.2 0.1 0.05 0.02 0.01 single pulse z thjc =f( t p );parameter: d = t p / t (enlarged source interconnection) 8 d 7 d 6 d 5 d s 1 s 2 s 3 g 4
7 optimos a 5power-transistor ,80v BSZ070N08LS5 rev.2.2,2016-08-18 final data sheet diagram5:typ.outputcharacteristics v ds [v] i d [a] 0 1 2 3 4 5 0 40 80 120 160 4.5 v 6 v 10 v 4 v 3.5 v 3 v i d =f( v ds ); t j =25c;parameter: v gs diagram6:typ.drain-sourceonresistance i d [a] r ds(on) [m w ] 0 20 40 60 80 100 0 3 6 9 12 15 4 v 4.5 v 5 v 5.5 v 6 v 10 v r ds(on) =f( i d ); t j =25c;parameter: v gs diagram7:typ.transfercharacteristics v gs [v] i d [a] 0 2 4 6 8 0 40 80 120 160 25 c 150 c i d =f( v gs );| v ds |>2| i d | r ds(on)max ;parameter: t j diagram8:typ.forwardtransconductance i d [a] g fs [s] 0 20 40 60 80 100 0 20 40 60 80 100 120 g fs =f( i d ); t j =25c (enlarged source interconnection) 8 d 7 d 6 d 5 d s 1 s 2 s 3 g 4
8 optimos a 5power-transistor ,80v BSZ070N08LS5 rev.2.2,2016-08-18 final data sheet diagram9:drain-sourceon-stateresistance t j [c] r ds(on) [m w ] -60 -20 20 60 100 140 180 0 3 6 9 12 15 max typ r ds(on) =f( t j ); i d =20a; v gs =10v diagram10:typ.gatethresholdvoltage t j [c] v gs(th) [v] -60 -20 20 60 100 140 180 0.0 0.5 1.0 1.5 2.0 2.5 360 a 36 a v gs(th) =f( t j ); v gs = v ds ;parameter: i d diagram11:typ.capacitances v ds [v] c [pf] 0 20 40 60 80 10 1 10 2 10 3 10 4 ciss coss crss c =f( v ds ); v gs =0v; f =1mhz diagram12:forwardcharacteristicsofreversediode v sd [v] i f [a] 0.0 0.5 1.0 1.5 2.0 2.5 10 0 10 1 10 2 10 3 25 c 150 c 25 c, max 150 c, max i f =f( v sd );parameter: t j (enlarged source interconnection) 8 d 7 d 6 d 5 d s 1 s 2 s 3 g 4
9 optimos a 5power-transistor ,80v BSZ070N08LS5 rev.2.2,2016-08-18 final data sheet diagram13:avalanchecharacteristics t av [s] i av [a] 10 0 10 1 10 2 10 3 10 0 10 1 10 2 25 c 100 c 125 c i as =f( t av ); r gs =25 w ;parameter: t j(start) diagram14:typ.gatecharge q gate [nc] v gs [v] 0 5 10 15 20 25 30 0 2 4 6 8 10 16 v 64 v 40 v v gs =f( q gate ); i d =20apulsed;parameter: v dd diagram15:drain-sourcebreakdownvoltage t j [c] v br(dss) [v] -60 -20 20 60 100 140 180 70 75 80 85 90 v br(dss) =f( t j ); i d =1ma (enlarged source interconnection) 8 d 7 d 6 d 5 d s 1 s 2 s 3 g 4 gate charge waveforms
10 optimos a 5power-transistor ,80v BSZ070N08LS5 rev.2.2,2016-08-18 final data sheet 5packageoutlines figure1outlinepg-tsdson-8fl,dimensionsinmm/inches (enlarged source interconnection) 8 d 7 d 6 d 5 d s 1 s 2 s 3 g 4 gate charge waveforms
11 optimos a 5power-transistor ,80v BSZ070N08LS5 rev.2.2,2016-08-18 final data sheet revisionhistory BSZ070N08LS5 revision:2016-08-18,rev.2.2 previous revision revision date subjects (major changes since last revision) 2.0 2016-03-23 release of final version 2.1 2016-04-21 update "gate threshold voltage" 2.2 2016-08-18 update qsw trademarksofinfineontechnologiesag aurix?,c166?,canpak?,cipos?,coolgan?,coolmos?,coolset?,coolsic?,corecontrol?,crossave?,dave?,di-pol?,drblade?, easypim?,econobridge?,econodual?,econopack?,econopim?,eicedriver?,eupec?,fcos?,hitfet?,hybridpack?,infineon?, isoface?,isopack?,i-wafer?,mipaq?,modstack?,my-d?,novalithic?,omnitune?,optiga?,optimos?,origa?,powercode?, primarion?,primepack?,primestack?,profet?,pro-sil?,rasic?,real3?,reversave?,satric?,sieget?,sipmos?,smartlewis?, solidflash?,spoc?,tempfet?,thinq?,trenchstop?,tricore?. trademarksupdatedaugust2015 othertrademarks allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. welistentoyourcomments anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.pleasesendyourproposal(includingareferencetothisdocument)to: erratum@infineon.com publishedby infineontechnologiesag 81726mnchen,germany ?2016infineontechnologiesag allrightsreserved. legaldisclaimer theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics.with respecttoanyexamplesorhintsgivenherein,anytypicalvaluesstatedhereinand/oranyinformationregardingtheapplication ofthedevice,infineontechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithout limitation,warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty. information forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestinfineon technologiesoffice( www.infineon.com ). warnings duetotechnicalrequirements,componentsmaycontaindangeroussubstances.forinformationonthetypesinquestion, pleasecontactthenearestinfineontechnologiesoffice. theinfineontechnologiescomponentdescribedinthisdatasheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofinfineontechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. (enlarged source interconnection) 8 d 7 d 6 d 5 d s 1 s 2 s 3 g 4 gate charge waveforms

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