vishay siliconix SI4324DY document number: 73340 s09-0226-rev. c, 09-feb-09 www.vishay.com 1 n-channel 30-v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 available ? trenchfet ? power mosfet ? 100 % r g tested applications ? synchronous buck-low side - notebook - server - workstation ? synchronous rectifier-pol product summary v ds (v) r ds(on) ( ) i d (a) a q g (typ.) 30 0.0032 at v gs = 10 v 36 25.5 nc 0.0042 at v gs = 4.5 v 29 so-8 sd sd sd gd 5 6 7 8 top v ie w 2 3 4 1 orderin g information: SI4324DY-t1-e3 (lead (p b )-free) SI4324DY-t 1-ge3 (lead (p b )-free and halogen-free) n -channel mosfet g d s notes: a. based on t c = 25 c. b. surface mounted on 1" x 1" fr4 board. c. t = 10 s. d. maximum under steady state conditions is 8 0 c/w. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 30 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t c = 25 c i d 36 a t c = 70 c 29 t a = 25 c 24 b, c t a = 70 c 19 b, c pulsed drain current i dm 70 continuous source-drain diode current t c = 25 c i s 7.0 t a = 25 c 3.0 b, c single pulse avalanche current l = 0.1 mh i as 40 avalanche energy e as 8 0 mj maximum power dissipation t c = 25 c p d 7. 8 w t c = 70 c 5.0 t a = 25 c 3.5 b, c t a = 70 c 2.2 b, c operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient b, d t 10 s r thja 29 35 c/w maximum junction-to-foot (drain) steady state r thjf 13 16
www.vishay.com 2 document number: 73340 s09-0226-rev. c, 09-feb-09 vishay siliconix SI4324DY notes: a. pulse test; pulse width 300 s, duty cycle 2 % b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 30 v v ds temperature coefficient v ds /t j i d = 250 a 34 mv/c v gs(th) temperature coefficient v gs(th) /t j - 6.4 gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.4 2.5 v gate-source leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 30 v, v gs = 0 v 1 a v ds = 30 v, v gs = 0 v, t j = 55 c 10 on-state drain current a i d(on) v ds 5 v, v gs = 10 v 30 a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 20 a 0.0025 0.0032 v gs = 4.5 v, i d = 15 a 0.0034 0.0042 forward transconductance a g fs v ds = 15 v, i d = 20 a 8 0s dynamic b input capacitance c iss v ds = 15 v, v gs = 0 v, f = 1 mhz 3510 pf output capacitance c oss 795 reverse transfer capacitance c rss 265 total gate charge q g v ds = 15 v, v gs = 10 v, i d = 20 a 55.5 8 5 nc v ds = 15 v, v gs = 4.5 v, i d = 20 a 25.5 40 gate-source charge q gs 11.6 gate-drain charge q gd 6.6 gate resistance r g f = 1 mhz 0.6 1.25 1.9 turn-on delay time t d(on) v dd = 15 v, r l = 1.5 i d ? 10 a, v gen = 4.5 v, r g = 1 30 45 ns rise time t r 1 8 52 8 0 turn-off delay time t d(off) 30 45 fall time t f 13 20 turn-on delay time t d(on) v dd = 15 v, r l = 1.5 i d ? 10 a, v gen = 10 v, r g = 1 17 26 rise time t r 90 140 turn-off delay time t d(off) 37 56 fall time t f 10 16 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c 7 a pulse diode forward current a i sm 70 body diode voltage v sd i s = 3 a 0.72 1.1 v body diode reverse recovery time t rr i f = 13 a, di/dt = 100 a/s, t j = 25 c 40 60 ns body diode reverse recovery charge q rr 40 60 nc reverse recovery fall time t a 21 ns reverse recovery rise time t b 19
document number: 73340 s09-0226-rev. c, 09-feb-09 www.vishay.com 3 vishay siliconix SI4324DY typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current and gate voltage gate charge 0 10 20 30 40 50 60 70 0.0 0.3 0.6 0.9 1.2 1.5 v gs = 10 v thr u 4 v 3 v v ds - drain-to-so u rce v oltage ( v ) -) a ( t n e r r u c n i a r d i d 0.001 0.002 0.003 0.004 0.005 0 102030405060 v gs = 10 v i d - drain c u rrent (a) v gs = 4.5 v r ) n o ( s d - m ) ( e c n a t s i s e r - n o 0 2 4 6 8 10 0 102030405060 i d = 20 a -) v ( e g a t l o v e c r u o s - o t - e t a g q g - total gate charge (nc) v s g v ds = 10 v v ds = 20 v v ds = 15 v transfer characteristics capacitance on-resistance vs. junction temperature 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.0 1.4 1.8 2.2 2.6 3.0 25 c t c = 125 c - 55 c v gs - gate-to-so u rce v oltage ( v ) -) a ( t n e r r u c n i a r d i d 0 500 1000 1500 2000 2500 3000 3500 4000 0 6 12 18 24 30 c rss c oss c iss v ds - drain-to-so u rce v oltage ( v ) c- ) f p ( e c n a t i c a p a c 0.6 0.8 1.0 1.2 1.4 1.6 1.8 - 50 - 25 0 25 50 75 100 125 150 v gs = 10 v t j - j u nction temperat u re (c) r ) n o ( s d -e c n a t s i s e r - n o ) d e z i l a m r o n ( v gs = 4.5 v i d = 20 a
www.vishay.com 4 document number: 73340 s09-0226-rev. c, 09-feb-09 vishay siliconix SI4324DY typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 1.0 1.2 0.001 10 50 0.00 0.2 0.4 0.6 0.8 t j = 25 c t j = 150 c v sd - so u rce-to-drain v oltage ( v ) -) a ( t n e r r u c e c r u o s i s 1 0.1 0.01 - 1.0 - 0.7 - 0.4 - 0.1 0.2 0.5 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a t j - temperat u re (c) v ) h t ( s g ) v ( i d = 5 ma on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0.000 0.003 0.006 0.009 0.012 0.015 0246810 i d = 20 a v gs - gate-to-so u rce v oltage ( v ) r ) n o ( s d ( ) e c n a t s i s e r - n o e c r u o s - o t - n i a r - d t j = 25 c t j = 125 c 0 120 200 40 80 ) w ( r e w o p time (s) 160 1 10 0.1 0.01 0.001 safe operating area, junction-to-ambient 100 1 0.1 1 10 100 0.01 10 -) a ( t n e r r u c n i a r d i d 0.1 1 ms t a = 25 c single p u lse v ds - drain-to-so u rce v oltage ( v ) * v gs minim u m v gs at w hich r ds(on) is specified 1 s 10 s 100 ms 10 ms dc limited b y r ds(on) *
document number: 73340 s09-0226-rev. c, 09-feb-09 www.vishay.com 5 vishay siliconix SI4324DY typical characteristics 25 c, unless otherwise noted * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resi stance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determ ine the current rating, when this rating falls below the package limit. current derating* 0 5 10 15 20 25 30 35 40 45 0 25 50 75 100 125 150 i d ) a ( t n e r r u c n i a r - d t c - case temperat u re (c) package limited power, junction-to-foot 0 2 4 6 8 10 0 25 50 75 100 125 150 t c - case temperat u re (c) r ( w ) e w o p power, junction-to-ambient 0.0 0.4 0.8 1.2 1.6 2.0 0 25 50 75 100 125 150 t a -am b ient temperat u re (c) r ( w ) e w o p
www.vishay.com 6 document number: 73340 s09-0226-rev. c, 09-feb-09 vishay siliconix SI4324DY typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73340 . normalized thermal transient im pedance, junction-to-ambient 10 -2 1 10 600 10 -1 10 -3 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) i t c e f f e d e z i l a m r o n t n e i s n a r t e v e c n a d e p m i l a m r e h t 1. d u ty cycle, d = 2. per unit base = r thja = 80 c/ w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm normalized thermal transient impedance, junction-to-case 10 -3 10 -2 1 10 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) v i t c e f f e d e z i l a m r o n t n e i s n a r t e e c n a d e p m i l a m r e h t
vishay siliconix package information document number: 71192 11-sep-06 www.vishay.com 1 dim millimeters inches min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.35 0.51 0.014 0.020 c 0.19 0.25 0.0075 0.010 d 4.80 5.00 0.189 0.196 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.50 0.93 0.020 0.037 q0808 s 0.44 0.64 0.018 0.026 ecn: c-06527-rev. i, 11-sep-06 dwg: 5498 4 3 1 2 5 6 8 7 h e h x 45 c all le a d s q 0.101 mm 0.004" l ba 1 a e d 0.25 mm (g a ge pl a ne) s oic (narrow): 8-lead jedec p a rt n u m b er: m s -012 s
vishay siliconix trenchfet ? power mosfets application note 808 mounting little foot ? , so-8 power mosfets application note document number: 70740 www.vishay.com revision: 18-jun-07 1 wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footpr int of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawin g access for vishay siliconix mosfets, ( http://www.vishay.com/ppg?72286 ), for the basis of the pad design for a little foot so-8 power mosfet. in converting this recommended minimum pad to the pad set for a power mosfet, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. in the case of the so-8 p ackage, the thermal connections are very simple. pins 5, 6, 7, and 8 are the drain of the mosfet for a single mosfet package and are connected together. in a dual package, pi ns 5 and 6 are one drain, and pins 7 and 8 are the other drain. for a small-signal device or integrated circuit, typical co nnections would be made with traces that are 0.020 inches wi de. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. the total cross section of the copp er may be adequate to carry the current required for the a pplication, but it presents a large thermal impedance. also , heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources wh en looking at heat spread on the pc board. figure 1. single mosfet so-8 pad pattern with copper spreading figure 2. dual mosfet so-8 pad pattern with copper spreading the minimum recommended pad patterns for the single-mosfet so-8 with copp er spreading (figure 1) and dual-mosfet so-8 with copper spreading (figure 2) show the starting point for utilizing th e board area available for the heat-spreading copper. to creat e this pattern, a plane of copper overlies the drain pins . the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat fr om the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. these patterns use all the available area underneath the body for this purpose. since surface-mounted packag es are small, and reflow soldering is the most comm on way in which these are affixed to the pc board, ?t hermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint wi th the copper plane on the drain pins, the solder mask ge neration occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum pow er trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.196 5.0 0.2 88 7.3 0.050 1.27 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.0 88 2.25 0.2 88 7.3 0.050 1.27 0.0 88 2.25
application note 826 vishay siliconix www.vishay.com document number: 72606 22 revision: 21-jan-08 application note recommended minimum pads for so-8 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.172 (4.369) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) return to index return to index
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