p p j s68 3 3 january 22,2015 - rev.01 page 1 3 0 v p - c hannel enhancement mode mosfet C esd protected voltage - 3 0 v current - 1. 1 a sot - 23 6l unit: inch(mm) f eatures ? rds(on) , vgs@ - 4,5 v , id@ - 1. 1 a< 37 0 m ? ? rds(on) , vgs@ - 2.5 v, id@ - 0.5 a< 54 0 m ? ? rds(on) , vgs@ - 1.8 v, i d@ - 0. 1 a< 9 7 0m ? ? advanced trench process technology ? specially designed for switch load, pwm application, etc. ? esd protected 2kv hbm ? lead free in compliance with eu rohs 2011/65/eu directive . ? green molding compound as per iec61249 std. (halogen free) mechanical data ? case: sot - 2 3 6l package ? terminals : solderable per mil - std - 750, method 2026 ? approx. weight: 0.000 5 ounces, 0.0 141 grams ? marking: s g 3 parameter symbol limit units drain - source voltage v ds - 3 0 v gate - source volta ge v gs + 8 v continuous drain current i d - 1. 1 a pulsed drain current (note 4 ) i dm - 4 .4 a power dissipation t a =25 o c p d 1.25 w derate above 25 o c 10 m w/ o c operatin g junction an d storage temperature range t j ,t stg - 55~150 o c typical thermal resistanc e - j unction to ambient (note 3 ) r ja 10 0 o c /w maximum ratings and thermal characteristics (t a =25 o c unless otherwise noted)
p p j s68 3 3 january 22,2015 - rev.01 page 2 e lectrical c haracteristics (t a =25 o c unless otherwise noted) parameter symbol test condition min. typ. max. units static drain - source breakdown voltage bv dss v gs = 0 v, i d = - 25 0ua - 3 0 - - v gate threshold voltage v gs(th) v ds =v gs , i d = - 250 ua - 0.5 - 0.98 - 1.3 v drain - source on - state resistance r ds(on) v gs = - 4.5 v, i d = - 1.1 a - 293 3 70 m gs = - 2.5 v, i d = - 0.5 a - 387 5 40 v gs = - 1.8 v , i d = - 0.1 a - 750 9 7 0 zero gate voltage drain current i dss v ds = - 30 v, v gs =0v - - 0.01 - 1 u a gate - source leakage current i gss v gs = + 8 v, v ds =0v - + 3.4 + 10 u a dynamic (note 5 ) total gate charge q g v ds = - 15 v, i d = - 1.1 a, v gs = - 4.5v (note 1 , 2 ) - 1.6 - nc gate - sour ce charge q gs - 0.5 - gate - drain charge q gd - 0.3 - input capacitance ciss v ds = - 1 5v, v gs = 0 v, f=1.0mhz - 125 - pf output capacitance coss - 22 - reverse transfer capacitance crss - 6 - turn - on delay time t d (on) v dd = - 15 v, i d = - 1.1 a, v g s = - 4.5v, r g = 6 (note 1 , 2 ) - 11 - ns turn - on rise time tr - 51 - turn - o ff delay time t d (off) - 65 - turn - o ff fall time tf - 46 - drain - source diode maximum continuous drain - source diode forward current i s --- - - - 1.0 a diode forward voltage v sd i s = - 1.0 a, v gs = 0 v - - 0.9 - 1.2 v notes : 1. pulse width < 300us, duty cycle < 2% 2. essentially independent of operating temperature typical characteristics . 3. r ? ja is the sum of the junction - to - case and case - to - ambient thermal resistance where the case thermal reference is defi ned as the solder mounting surface of the drain pins m ounted on a 1 inch fr - 4 with 2oz . square pad of copper . 4. the maximum current rating is package limited. 5. guaranteed by design, not subject to product ion testing.
p p j s68 3 3 january 22,2015 - rev.01 page 3 t ypical characteristic curves fig.1 on - region characteristics fig. 2 transfer characteristics fig. 3 on - resistance vs. drain current fig. 4 on - resistance vs. junction temperature fig. 5 on - resistance variation with vgs. fig. 6 body d i ode characteristics
p p j s68 3 3 january 22,2015 - rev.01 page 4 t ypica l characteristic curves fig. 7 gate - charge characteristics fig. 8 threshold voltage variation with temperature . fig. 9 capacitance vs. drain - source voltage.
p p j s68 3 3 january 22,2015 - rev.01 page 5 part no packing code version mounting pad layout p art n o packing code package type pack ing type marking ver sion PJS6833 _s1_00001 sot - 23 6l 3k pcs / 7 0.024 (0.60) 0 . 0 2 6 ( 0 . 6 7 ) 0 . 0 9 6 ( 2 . 4 3 ) 0.037 (0.95) 0.037 (0.95)
p p j s68 3 3 january 22,2015 - rev.01 page 6 disclaimer
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