general description the max3634 burst-mode clock phase aligner (cpa) isdesigned specifically for 622mbps or 1244mbps gpon (itu g.984) optical line terminal (olt) receiver applica- tions. the max3634 provides clock and clock-aligned resynchronized upstream data through differential lvpecl outputs. using the olt system clock as a ref- erence, the max3634 aligns to the input data and acquires within the first 13 bits of the burst. the cpa operates with received data that is frequency locked to the olt reference. the acquisition time, bit-error ratio, and jitter tolerance all support gpon pmd specifica- tions. lvpecl high-speed clock and data outputs pro- vide compatibility with fpgas at 622mbps and with the max3885 deserializer at 1244mbps. the max3634 is available in a low-profile, 7mm x 7mm, 48-lead tqfn package. the max3634 operates from a single +3.3v supply, over the -40 c to +85 c tempera- ture range. applications 622mbps gpon olt receivers1244mbps gpon olt receivers features ? dc-coupled clock phase aligner for burst-modegpon applications ? 13-bit burst acquisition time ? 0.85ui high-frequency jitter tolerance ? continuous clock output ? byte rate (1/8th data rate) reference clock input ? lock detect output ? lvpecl serial data input and output ? lvpecl reset input max3634 622mbps/1244mbps burst-mode clock phase aligner for gpon olt applications ________________________________________________________________ maxim integrated products 1 ordering information 19-3818; rev 0; 9/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package pkg code max3634etm -40? to +85? 48 tqfn (7mm x 7mm) t4877-6 max3634 max3738 burst-mode tia/la max3656 burst-mode laser driver max3864 max3748a tia/la max3872 sonet cdr max3892 data serializer data clockolt clock data burst reset ratesel divide by 16 divide by 8 continuous laser driver gpon optical line termination gpon optical network termination data data burst enable clock clock 4 upstream 1244mbps downstream 2488mbps burst-mode clock phase aligner t ypical application circuit pin configuration appears at end of data sheet. downloaded from: http:///
max3634 622mbps/1244mbps burst-mode clock phase aligner for gpon olt applications 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v cc = +3.0v to +3.6v, t a = -40 c to +85 c. typical values are at v cc = +3.3v, t a = +25 c, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc , v cc i, v cc o, v cc v ........................................-0.5v to +4.0v sdi? rst , refclk? ratesel, filt, test.............................-0.5v to (v cc + 0.5v) lvpecl output current (sdo? sclk? lock ) .............50ma continuous power dissipation (t a = +85 c) 48-lead tqfn package (derate 27.8mw/ c above +85 c) .............................1800mw storage temperature range .............................-55 c to +150 c operating ambient temperature range .............-40 c to +85 c lead temperature (soldering, 10s) .................................+400 c parameter symbol conditions min typ max units supply current i cc not including lvpecl output current 315 390 ma ratesel = low 1244.16 data rate ratesel = high 622.08 mbps ratesel = low 155.52 reference clock input frequency ratesel = high 77.76 mhz sdi, rst, refclk differentialinput v in 200 1600 mv p-p sdi? rst , refclk?input current -180 +180 ? rate = 1244mbps 200 rst input rise/fall times t r , t f rate = 622mbps 200 ps sdi? rst , refclk?common- mode input v cc - 1.49 v cc - v in /4 v t a = 0 c to +85 c (note 1) v cc - 1.81 v cc - 1.62 sdo? sclk? lock output voltage low v ol t a = -40 c to 0 c (note 1) v cc - 1.83 v cc - 1.555 v t a = 0 c to +85 c (note 1) v cc - 1.025 v cc - 0.88 sdo , sclk , lock output voltage high v oh t a = -40 c to 0 c (note 1) v cc - 1.085 v cc - 0.88 v 622mbps (notes 2, 5, 6) 0.73 0.83 jitter tolerance 1244mbps (notes 2, 5, 6) 0.73 0.81 ui p-p acquisition time (notes 2, 3) 13 bits bit-error ratio after acquisition (notes 2, 4) 10 -10 sdo? lock transition time t r , t f 20% to 80% (note 1) 265 ps sclk?transition time t r , t f 20% to 80% (note 1) 200 ps downloaded from: http:///
max3634 622mbps/1244mbps burst-mode clock phase aligner for gpon olt applications _______________________________________________________________________________________ 3 electrical characteristics (continued)(v cc = +3.0v to +3.6v, t a = -40 c to +85 c. typical values are at v cc = +3.3v, t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units 622mbps (notes 1, 2) 500 serial data output clock-to-qdelay (figure 1) t clk-q 1244mbps (notes 1, 2) 250 ps 622mbps (notes 1, 2) 500 serial data output q-to-clockdelay (figure 1) t q-clk 1244mbps (notes 1, 2) 250 ps ratesel input high v ih 2v ratesel input low v il 0.8 v ratesel input current v in = 0v or v cc -100 +100 ? note 1: pecl output must have external termination of 50 to v cc - 2v (thevenin equivalent). note 2: ac parameters are guaranteed by design and characterization. note 3: from start of pon burst, 101010101010 preamble sequence. note 4: ber, acquisition time requirements are met with 100mv p-p sinusoidal noise on v cc , 0 < f noise 10mhz. note 5: measured with 20ps rms input random jitter (1.244mbps), 30ps rms (622mbps) note 6: jitter tolerance refers to the variation in phase between refclk and sdi after acquisition. t ypical operating characteristics (v cc = +3.3v and t a = +25 c, unless otherwise noted) 1.244gbps input and output eye diagrams max3634 toc01 200ps/div sdi sdo 622mbps input and output eye diagrams max3634 toc02 400ps/div sdi sdo burst capture at 1.244gbps max3634 toc03 1ns/div rst sdi sdo lock (sclk+) - (sclk-) (sdo+) - (sdo-) t clk-q t q-clk figure 1. definition of clock-to-q and q-to-clock delay downloaded from: http:///
max3634 622mbps/1244mbps burst-mode clock phase aligner for gpon olt applications 4 _______________________________________________________________________________________ pin name function 1, 2, 12, 25, 36, 37, 48 gnd supply ground 3, 6, 7, 10 v cc i +3.3v supply for input buffers 4 sdi+ positive serial data input, lvpecl 5 sdi- negative serial data input, lvpecl 8 rst + positive reset input, lvpecl. reset (= rst + - rst-) is falling edge triggered. 9 rst- negative reset input, lvpecl 11, 38, 39, 44, 47 v cc +3.3v supply for digital circuitry 13?0, 22, 23 test production test pins, reserved. leave open for normal operation. 21, 24, 26, 29, 32, 35 v cc o +3.3v supply for output buffers 27 lock- negative lock status output, lvpecl 28 lock+ positive lock status output, lvpecl. lock (= ( lock + ) - (lock-)) high indicates that the max3634 has acquired the correct phase. 30 sdo- negative serial data output, lvpecl 31 sdo+ positive serial data output, lvpecl 33 sclk- negative serial clock output, lvpecl 34 sclk+ positive serial clock output, lvpecl 40 ratesel rate select input, ttl. high selects 622.08mbps operation. 41, 43 v cc v +3.3v supply for vco 42 filt pll filter capacitor. connect a 0.1? x7r capacitor from pin 42 to v cc v. 45 refclk- negative reference clock input, lvpecl (1/8th data rate) 46 refclk+ positive reference clock input, lvpecl ep exposed pad the exposed pad must be connected to the ground plane for proper thermal performance. pin description t ypical operating characteristics (continued) (v cc = +3.3v and t a = +25 c, unless otherwise noted) jitter tolerance vs. sdi-to-refclk phase (1.244gbps) max3634 toc04 sdi-to-refclk phase (ps) jitter tolerance (ui p-p ) 600 400 200 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0 800 limited by test equipment jitter tolerance vs. sdi-to-refclk phase (622mbps) max3634 toc05 sdi-to-refclk phase (ps) jitter tolerance (ui p-p ) 600 400 200 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 08 0 0 limited by test equipment supply current vs. temperature max3634 toc06 ambient temperature ( c) supply current (ma) 50 0 220 240 260 280 300 320 340200 -50 100 excludes pecl output current downloaded from: http:///
general description theory of operation the max3634 cpa provides serial clock and data out-puts for gpon upstream bursts. the burst-mode cpa operates on the principle that the recovered clock from the ont cdr is used at each ont to clock upstream data bursts out of the ont con- troller. the burst-mode cpa has logic that determines the correct phase relationship between the upstream data and the olt reference clock at the beginning of each ont? burst, and resamples the upstream data at each bit using that clock. the burst-mode cpa contains a phase-locked loop (pll) that synchronizes its oscillator to the reference clock input. this oscillator drives a phase splitter, which generates eight evenly spaced phases of the serial clock, which are used to sample the input data at 1/8th bit intervals in eight flip-flops. combinatorial and sequential logic measures the preamble, and based on the phase of the preamble, determines which one of the eight clock phases is at the center of the input data bits. the data from the flip-flop associated with this phase is then steered through a multiplexer to the cpa output, which requires four or five additional clock peri- ods until valid data is output. the cpa serial output clock is continuous, without any phase jumps or dis- continuities from burst to burst. the burst-mode cpa requires a preamble sequence of 1010101010101 (13 bits) for correct phase alignment. typically, output begins after the 12th bit, although for certain data/phase relationships, 13 bits are required. an lvpecl-compatible lock status output is provided, which indicates when the correct phase has been acquired and valid serial output data is available. this output remains low until reset by the burst reset input (rst). the output data is disabled (held low) during the period between reset and lock. reference clock input the max3634 includes a pll, which multiplies the ref-erence clock by eight for use in the retiming circuitry. for correct operation, the refclk input must be con- nected to the olt byte-rate reference clock, which must be equal to 1/8th the serial data rate, and must have a 40% to 60% duty cycle. this must be the same clock source used to time the downstream data, and the upstream data must be frequency locked to this source. the ratesel input is used to configure 622mbps or 1244mbps operation; when ratesel is high, the max3634 operates at 622mbps. max3634 622mbps/1244mbps burst-mode clock phase aligner for gpon olt applications _______________________________________________________________________________________ 5 max3634 lvpecl refclk+ refclk- lvpecl lvpecl lvpecl sdi+ sdi- ttl ratesel 622mbps/1244mbps pll/phase splitter dq dq dq mux synchronizer phase-acquisition logic rst+ rst- sdo+ sdo- lvpecl sclk+ sclk- lvpecl lock+ lock- burst-mode cpa 0 7 figure 2. functional block diagram downloaded from: http:///
max3634 input stage the lvpecl serial data input, sdi? and burst-mode reset input, rst , provide 200mv p-p sensitivity. the rst input rise and fall times (20% to 80%) must not exceed 200ps. lvpecl inputs must be dc-coupled withexternal termination for correct operation with burst data (see maxim application note hfan 1.0 for termination configuration). lock detect after the first 12 or 13 bits of the preamble, plus 4 or 5bits of synchronizer delay, lock asserts to indicate the beginning of valid data output. applications information gpon burst-mode timing internally, the max3634 requires five internal clockcycles (8x refclk) to initialize itself after receiving the rest (brst) signal. it then uses the next 8 bits of pream- ble (10101010) to measure the phase relationship between the reference clock and upstream data (after the internal logic has been reset), and 3 to 5 bits later begins outputting data. the time interval from brst to the end of the preamble must be no less than 18 bits long. if the 8 bits of preamble that it uses to measure phase have been excessive pulse-width distortion, the phase measurement is in error. the active edge of the reset input (brst) must arrive at the max3634 after the tia has finished its level recovery, but no sooner than 18 bits prior to the end of the (repeat- ing 10 pattern) preamble, in order to provide adequate time for the max3634 to initialize, measure the phase, and load the output pipelines. this timing is shown in figure 3. 622mbps/1244mbps burst-mode clock phase aligner for gpon olt applications 6 _______________________________________________________________________________________ data input to max3634 reset t dsr : burst-to-burst separation time t lr : tia/la level recovery time t cr : cpa reset and acquisition time, 19 bits t dsr data valid guard time tia/la acquisition cpa reset (5 bits) cpa acquisition (12 or 13 bits) output data valid t lr t cr figure 3. clock phase aligner operation timing diagram downloaded from: http:///
max3634 622mbps/1244mbps burst-mode clock phase aligner for gpon olt applications _______________________________________________________________________________________ 7 3738 39 40 41 42 43 44 45 46 47 48 2423 22 21 20 19 18 17 16 15 14 13 123456789101112 36 ep* *ep must be connected to ground. 35 34 33 32 31 30 29 28 27 26 25 v cc o test10test9 v cc o test8test7 test6 test5 test4 test3 test2 test1 gnd v cc v cc ratesel v cc v filt v cc v v cc refclk- refclk+ v cc gnd gndv cc o sclk+sclk- v cc o sdo+sdo- v cc o lock+lock- v cc o gnd gndgnd v cc i sdi+ sdi- v cc i v cc i rst+ rst- v cc i v cc gnd max3634 tqfn pin configuration chip information transistor count: 10,805process: silicon germanium bicmos downloaded from: http:///
max3634 622mbps/1244mbps burst-mode clock phase aligner for gpon olt applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) 32, 44, 48l qfn .eps e l e l a1 a a2 e/ 2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k package outline 21-0144 2 1 f 32, 44, 48, 56l thin qfn, 7x7x0.8m m package outline 21-0144 2 2 f 32, 44, 48, 56l thin qfn, 7x7x0.8m m downloaded from: http:///
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