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? 2013 - 2016 microchip technology inc. ds00001588b-page 1 highlights usb 2.0 compatible 4-port hub with two upstream host port connections - provides electronic reconfiguration and re- assignment of any of its 4 downstream ports to either of two upstream host ports (on-the- fly) - allows multiple usb hosts to share peripher- als and enables a user to dynamically assign host ownership - embedded mode - 8 (predefined, oem programmable) configurations for port assignment are selectable via three external control signals - peripheral mode - dedicated select pin for every downstream port (total of 4), selectable edge or level triggered in order to support a wide range of possible switch configurations and styles - each host has a dedicated single transac- tion translator (single-tt) for supporting fs/ ls devices, or can also operate in multi-tt mode where each downstream port has a dedicated transaction translator. downstream ports can be disabled or defined as non-removable switching hub can be configured as compound device for support of embedded usb peripherals multiple led modes for maximum implementation flexibility - usb mode - 2 single-color leds for each downstream port (total of 8 leds) - host ownership mode - 8 single-color leds indicate which upstream host each of the downstream ports are assigned to. - host ownership & port speed mode - 8 dual- color leds are used to indicate which upstream host each of the downstream ports are assigned to, while simultaneously indicat- ing downstream port connection speed. enhanced configuration options available through either a single serial i 2 c eeprom, or smbus slave port - vid/pid/did - port configuration - string descriptors (each can support a maxi- mum length of 31 characters) - custom manufacturer string - custom product string - custom serial string - assignment of downstream ports to upstream hosts - switching mechanism selection hardware strapping options allow for configura- tion without an external eeprom or smbus host - default vid/pid/did, allows functionality when configuratio n eeprom is absent complete usb specification 2.0 compatibility - includes usb 2.0 hi-speed transceivers - high-speed (480mbits/s), full-speed (12mbits/s) and low-speed (1.5mbits/s) compatible - full power management with choice of indi- vidual or ganged power control on-board 24mhz crystal driver circuit or 24 mhz external clock driver internal pll for 480mhz usb 2.0 sampling internal 1.8v linear voltage regulator integrated usb terminatio n and pull-up/pull-down resistors internal short circuit protection of usb differential signal pins 1.8 volt low power core operation 3.3 volt i/o with 5v input tolerance 56-pin qfn rohs compliant package usb2524 usb multiswitch hub downloaded from: http:///
usb2524 ds00001588b-page 2 ? 2013 - 2016 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 3 usb2524 table of contents 1.0 general description ........................................................................................................................................................................ 4 2.0 pin layout ................................................................................................................ ....................................................................... 6 3.0 pin configuration ............................................................................................................................................................................ 7 4.0 switching hub pin descriptions ............................................................................................ .......................................................... 8 5.0 switching hub block diagram ....................................................................................................................................................... 13 6.0 assigning ports ........................................................................................................... .................................................................. 14 7.0 configuration options ..................................................................................................... .............................................................. 16 8.0 led interface description ................................................................................................. ............................................................ 40 9.0 reset ............................................................................................................................................................................................. 4 3 10.0 xnor test .................................................................................................................................................................................. 47 11.0 dc parameters ........................................................................................................................................................................... 48 12.0 ac specifications ........................................................................................................................................................................ 51 13.0 package outline .......................................................................................................... ................................................................ 52 appendix a: data sheet revision history ........................................................................................................................................... 54 the microchip web site ........................................................................................................ .............................................................. 55 customer change notification service ............................................................................................................................................... 55 customer support ............................................................................................................................................................................... 55 product identification system ................................................................................................. ............................................................ 56 downloaded from: http:///
usb2524 ds00001588b-page 4 ? 2013 - 2016 microchip technology inc. 1.0 general description the microchip 4-port usb 2.0 switching hub controller acts as two independently controllable usb 2.0 hubs in a single package with the ability to electronically reassign and reconf igure any of its 4 downstream ports to either of its two upstream usb ports. this allows two usb hosts to share peripherals and to dynamically reconfigure them. any configuration of the downstream port s is possible except simultaneous connection to both upstream ports. up to 8 different configurations can be selected by a dedicated 3-pin interface, or the 4-pin interface can be used to directly assign each port to either of the upstream hosts. an exte rnal serial eeprom (or smbus ho st) is used to store the 8 different configuration parameters. howe ver, 8 predefined configurations, as well as generic vid/pid/did information, are provided as defaults if no external serial eeprom is detected at power up. the smbu s interface can be used to configure the hub as well as dynamically re-assigning down stream ports to upstream ho sts. the smbus interface can be live while the hub is operational, and allows an exte rnal smbus host to have full access to re-assign ports on an as-needed basis. the microchip 4-port switching hub is fully compliant with the usb 2.0 specification and will attach to either or both upstream usb hosts as a full-speed hub or as a full-/ high-speed hub. the 4 downstream hub ports support low- speed, full-speed, and high-speed (if operating as a high- speed hub) downstream devices on all of the enabled downstream ports. a usb peripheral or usb hub that is atta ched to one of the downstream usb2524 ports will be available to one or the other of the upstream usb host contro llers, but can never be simultaneously s hared with both host controllers. the user can switch a peripheral from one host to the other (on-the-fly), and the peripheral will automatically detach from one host and attach to the other host. each host will only configure and control the downstream ports that are assigned to it, including full usb power management and suspend/resume operations. the usb2524 works with an external usb power distribution switch device to control v bus switching to downstream ports, and to limit current and sense over-current conditions. all required resistors on the usb ports are integrated into t he hub. this includes all series termination resistors on d+ and dC pins and all required pull-down and pull-up resistor s on d+ and dC pins. the over-current sense inputs for the downstream facing ports have internal pull-up resistors. throughout this document the upstream facing port of the hub will be referr ed to as the upstream port, and the down- stream facing ports will be called the downstream ports. for performance reasons, the hub provides 1 transaction translator (tt) per port (defined as multi-tt configuration), and each tt has 1512 bytes of periodic buffer space and 272 by tes of non- periodic buffer space (divided into 4 non- periodic buffers per tt), for a total of 1784 bytes of buffer space for each transaction translator. when configured as a single-tt hub (required by usb 2.0 specification), the single transaction translator will have 1512 bytes of periodic buffer space and 272 bytes of non-per iodic buffer space (divided into 4 non-periodic buffers per tt), for a total of 1784 bytes of buffer space for the entire transaction translator. 1.1 oem selectable features a default configuration is available in the usb2524 following a reset. this configuration may be sufficient for some appli- cations. strapping option pins make it possible to modi fy a limited sub-set of t he configuration options. the usb2524 may also be conf igured by an external eeprom or a microcon troller. when using the microcontroller interface, the hub appears as an smbus slave device. if the hub is pin-strapped for external eeprom configuration but no external eeprom is pres ent, then a value of 0 will be written to a ll configuration data bit fields (the hub will attach to the host with all 0 values). the usb2524 supports several oem selectable features: optional oem configuration via i 2 c eeprom or via the industry standard smbus interface from an external smbus host or microcontroller. compound device support (port is permanently ha rdwired to a downstream usb peripheral device). hardware strapping options enable co nfiguration of the follo wing features (when not configured via an eeprom or smbus host). - non-removable ports - port power polarity (active high or active low logic) selection of single (stt) or multi-transaction translator (mtt) capability. selection of over-current sensing and port power cont rol on a individual (port-by-port) or ganged (all ports together) to match the oems choice of circuit board component selection. downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 5 usb2524 selection of end-user method of switching ports between hosts - embedded mode: 8 default configuratio ns that are controlled by oem pr ogrammable registers (or internal default settings). - peripheral mode: each wire directly controls one of the 4 downstream ports. the interface is selectable between edge triggered operation or level triggered operation for compatibility with many different mechanical switch configurations or di rect control from an external microcontrollers gpio pins. enablement of string descriptor support, along with the capability to customize each of the 3 different string descriptors (up to a maximum size of 31 characters each) selection of led mode: usb mode, host ownership mode, or host ownership mode with speed indication. downloaded from: http:///
usb2524 ds00001588b-page 6 ? 2013 - 2016 microchip technology inc. 2.0 pin layout table 2-1: usb2524 56-pin qf n pin configuration table upstream usb 2.0 interfaces (6 pins) usbup_dp1 usbup_dm1 usbup_dp2 usbup_dm2 vbus_det1 vbus_det2 downstream 4-port usb 2.0 interface (30 pins) usbdn_dp1 usbdn_dm1 usbdn_dp2 ocs1_n usbdn_dp3 usbdn_dm3 usbdn_dm2 ocs2_n led_a1_n/non_rem0 led_a2_n/non_rem1 led_a3_n/prt_dis0 ocs3_n led_b1_n led_b2_n led_b3_n prt_assign0 prtpwr1 prtpwr2 prt_assign1 prtpwr_pol prtpwr3 rbias prt_assign2 led_a4_n/prt_dis1 usbdn_dm4 usbdn_dp4 prtpwr4 prt_assign3 led_b4_n ocs4_n serial port interface (4 pins) sda/smbdata scl/smbclk/ cfg_sel0 cfg_sel1 cfg_sel2 misc (5 pins) xtal1/clkin xtal2 reset_n self_pwr test analog power & ground (5 pins) vddpll18(1) vdda33(4) digital power, ground & no connect (6 pins) vdd33(3) vddcr18(2) nc total (56 pins) downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 7 usb2524 3.0 pin configuration figure 3-1: usb2524 qfn-56 thermal slug connects to vss 41 prt_assign0 40 prt_assign1 39 prt_assign2 38 prt_assign3 37 vdd33 36 self_pwr 35 cfg_sel2 34 cfg_sel1 32 sda/smbdata 31 led_b1_n 29 led_b2_n 30 led_a1_n/non_rem0 33 scl/smbclk/cfg_sel0 42 led_a4_n/prt_dis1 26 ocs1_n 25 ocs2_n 24 prtpwr2 23 prtpwr3 22 ocs3_n 21 ocs4_n 20 prtpwr4 19 prtpwr_pol 18 test 17 vdd33 16 vddcr18 15 led_b3_n 27 prtpwr1 28 led_a2_n/non_rem1 vdda33 1 usbup_dp1 2 usbup_dm1 3 usbdn_dm1 4 usbdn_dp1 5 vdda33 6 usbdn_dp2 7 usbdn_dm2 8 usbdn_dm3 9 usbdn_dp3 10 vdda33 11 usbdn_dp4 12 usbdn_dm4 13 led_a3_n/prt_dis0 14 reset_n 44 vbus_det1 45 vbus_det2 46 vdda33 47 usbup_dp2 48 usbup_dm2 49 xtal2 51 xtal1/clkin 52 vddpll18 53 rbias 56 nc 55 led_b4_n 43 vdd33 54 vddcr18 50 86% 7rs9lhz4)1 downloaded from: http:///
usb2524 ds00001588b-page 8 ? 2013 - 2016 microchip technology inc. 4.0 switching hub pin descriptions table 4-1: switching hub pin descriptions name symbol type function upstream usb 2.0 interface usb bus data usbup_dp[2:1] usbup_dm[2:1] io-u these pins connect to the upstream usb bus data signals. detect upstream vbus power vbus_det[2:1] i/o detects state of upstream vbus power. the microchip hub monitors vbus_det to determine when to assert the internal d+ pull-up resistor (signaling a connect event). when designing a detachable hub, this pin must be connected to the vbus power pin of the usb port that is upstream of the hub. (use of a weak pull-down resistor is recommended.) for self-powered applications with a permanently attached host, this pin must be pulled-up to either 3.3v or 5.0v (typically vdd33). 4-port usb 2.0 hub interface high-speed usb data usbdn_dp[4:1] usbdn_dm[4:1] io-u these pins connect to the downstream usb peripheral devices attached to the hubs ports. usb power enable prtpwr[4:1] o enables power to usb peripheral devices (downstream). the active signal level of the prtpwr[4] pin is determined by the power polarity strapping function of the prtpwr_pol pin. port 4:3 green led & port disable strapping option 0 led_a[4:3]_n/ prt_dis[1:0] i/o12 green indicator led for ports 4 and 3. will be active low when led support is enabled via eeprom or smbus. see prt_dis1 function description if the hub is configured by the internal default configuration. port disable strapping option 1 prt_dis1 i/o12 if the hub is configured by th e internal default configuration, prt_dis[1:0] will be sampled at reset_n negation to determine if ports [4:2] will be permanently disabled. also, the active state of led_a3_n will be determined as follows: prt_dis[1:0] = '00', all ports are enabled, led_a4_n is active high, led_a3_n is active high. prt_dis[1:0] = '01', port 4 is disabled, led_a4_n is active high, led_a3_n is active low. prt_dis[1:0] = '10', ports 4 & 3 are disabled, led_a4_n is active low, led_a3_n is active high. prt_dis[1:0] = '11', ports 4, 3 & 2 are disabled, led_a4_n is active low, led_a3_n is active low. downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 9 usb2524 port [2:1] green led & port non- removable strapping option led_a[2:1]_n/ non_rem[1:0] i/o12 green indicator led for ports 2 and 1. will be active low when led support is enabled via eeprom or smbus. if the hub is configured by th e internal default configuration, these pins will be sampled at reset_n negation to determine if ports [3:1] contain permanently attached (non- removable) devices. also, the active state of the led's will be determined as follows: non_rem[1:0] = '00', all ports are removable, led_a2_n is active high, led_a1_n is active high. non_rem[1:0] = '01', port 1 is non-removable, led_a2_n is active high, led_a1_n is active low. non_rem[1:0] = '10', ports 1 & 2 are non-removable, led_a2_n is active low, led_a1_n is active high. non_rem[1:0] = '11', ports 1, 2, & 3 are non-removable, led_a2_n is active low, led_a1_n is active low. enhanced port led indicators led_b[4:1]_n i/o12 these 4 pins in conjunction with the led_a[4:1]_n pins provides a total of 8 led pins which are used to indicate upstream host ownership of the downstream ports. 2 operational modes are available single color led mode: led will light to show which host owns each of the downstr eam ports. if a port is unassigned then neither led for that port will light up. dual color leds: (note; 4 possible states are displayed to the user, green, red, orange and off). port power polarity strapping prtpwr_pol i/o port power polarity strapping determination for the active signal polarity of the prtpwr[4:1] pins. while reset_n is asserted, the logic state of this pin will (through the use of internal co mbinatorial logic) determine the active state of the prtpwr[4:1] pins in order to ensure that downstream port power is not inadvertently enabled to inactive ports during a hardware reset. when reset_n is negated, the logic value wi ll be latched internally, and will retain the active signal polarity for the prtpwr[4:1] pins. 1 = prtpwr[4:1] pins have active high polarity 0 = prtpwr[4:1] pins have active low polarity warning: active low port power controllers may glitch the downstream port power when system power is first applied. care should be taken when designing with active low components! over current sense ocs[4:1]_n ipu input from external current monitor indicating an over- current condition. {note: contains internal pull-up to 3.3v supply} usb transceiver bias rbias i-r a 12.0k ? ( ???????? resistor is attached from ground to this pin to set the transceivers internal bias settings. table 4-1: switching hub pin descriptions (continued) name symbol type function downloaded from: http:///
usb2524 ds00001588b-page 10 ? 2013 - 2016 microchip technology inc. assign downstream ports to upstream host ports prt_assign [3:0] i port assign interface: operat es in either embedded mode, or peripheral mode. see section 6.0, "assigning ports" for additional details. serial port interface serial data/smb data sda/smbdata iosd12 (serial data)/(smb data) signal. serial clock/smb clock & configuration programming select scl/smbclk/ cfg_sel0 iosd12 (serial clock)/(smb clock) signal. cfg_sel0: the logic state of this multifunction pin is internally latched on the rising edge of reset_n (reset_n negation), and will determine the hub configuration method as described in table 4-2 . configuration programming select cfg_sel1 i the logic state of this pin is internally latched on the rising edge of reset_n (reset_n negation), and will determine the hub configuration method as described in ta b l e 4 - 2 . configuration programming select cfg_sel2 i the logic state of this pin is internally latched on the rising edge of reset_n (reset_n negation), and will determine the hub configuration method as described in ta b l e 4 - 2 . table 4-2: smbus or eeprom interface behavior name name name function cfg_sel2 cfg_sel1 cfg_sel0 smbus or eeprom interface behavior. 0 0 0 internal default configuration prt_assign[3:0] = embedded mode. strap options on pins led_a[4:1]_n are enabled. led mode = usb mode 0 0 1 configured as an smbus slave for external download of user-defined descriptors. smbus slave address is :0101100 strap options on pins led_a[4:1]_n are disabled led mode = see section 8.0, "led interface descrip- tion" 0 1 0 internal default configuration prt_assign[3:0] = peripheral mode (level triggered) strap options on pins led_a[4:1]_n are enabled. no support for unassigned ports. led mode = usb mode 011 2 - w i r e ( i 2 c) eeproms are supported, led mode = see section 8.0, "led interface descrip- tion" table 4-1: switching hub pin descriptions (continued) name symbol type function downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 11 usb2524 1 0 0 internal default configuration prt_assign[3:0] = peripheral mode (edge triggered) led mode = host ownership mode strap options on pins led_a[4:1]_n are enabled. supports unassigned ports 1 0 1 internal default configuration prt_assign[3:0] = peripheral mode (edge triggered) led mode = host ownership & port speed mode strap options on pins led_a[4:1]_n are disabled supports unassigned ports. 110 r e s e r v e d 111 r e s e r v e d table 4-3: miscellaneous pins name symbol type function crystal input/external clock input xtal1/ clkin iclkx 24mhz crystal or external clock input. this pin connects to either one terminal of the crystal or to an external 24mhz clock when a crystal is not used. note: see table 11-1 for the required logic voltage levels of this pad if it will be driven by an exter- nal clock source. crystal output xtal2 oclkx 24mhz crystal this is the other terminal of the crystal, or left unconnected when an external clock source is used to drive xtal1/clkin. it must not be used to drive any external circuitry other than the crystal circuit. reset input reset_n is this active low signal is used by the system to reset the chip. the minimum active low pulse is 1us. self-power / bus-power detect self_pwr i detects availability of local self-power source. low = self/local power source is not available (i.e., hub gets all power from upstream usb vbus). high = self/local power source is available. test pin test ipd used for testing the chip. user must treat as a no- connect or connect to ground. table 4-2: smbus or eeprom inte rface behavior (continued) name name name function downloaded from: http:///
usb2524 ds00001588b-page 12 ? 2013 - 2016 microchip technology inc. table 4-4: power, ground, and no connect name symbol type function vdd core vddcr18 +1.8v core power. pins 16 and 50 must have a 4.7 ? f (or greater) 20% (esr <0.1 ??? capacitor to vss vddio 3.3v vdd33 +3.3v power supply for the digital i/o. vdd pll vddpll18 +1.8v filtered analog power for internal pll. this pin must have a 4.7 ? f (or greater) 20% (esr <0.1 ??? capacitor to vss vdd analog i/o vdda33 +3.3v filtered analog phy power, shared between adjacent ports. vss vss ground nc nc no connect table 4-5: buffer type descriptions buffer description i input. ipd input, weak internal pull-down. ipu input, weak internal pull-up. is input with schmitt trigger. iosd12 open drain.12ma sink with schmitt trigger, and must meet i2c-bus spec ification version 2.1 requirements. iclkx xtal clock input oclkx xtal clock output i-r rbias io-u defined in usb specification. note: meets usb 1.1 requirements when operating as a 1.1-compliant device and meets usb 2.0 requirements when operating as a 2.0-compliant device. aio analog input/output. per phy test requirements. downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 13 usb2524 5.0 switching h ub block diagram figure 5-1: usb2524 swit ching hub block diagram upstream v bus upstream phy upstream usb data repeater controller sie serial interface switching logic downstream phy #1 port #1 oc sense switch driver led drivers downstream phy #2 port #2 oc sense switch driver led drivers downstream usb data oc sense switch/led drivers downstream usb data oc sense switch/led drivers v bus power detect internal defaults select upstream phy upstream usb data repeater controller sie pin strapping options pll 24 mhz crystal 3.3v 1.8v reg. 1.8v cap to eeprom or smbus master scl sd downstream phy #4 port #4 oc sense switch driver led drivers downstream usb data oc sense switch/led drivers downstream phy #3 port #3 oc sense sw itch driver led drivers downstream usb data oc sense switch/led drivers tt #1 tt #2 tt #3 tt #4 port controller tt #1 tt #2 tt #3 tt #4 port controller routing logic routing logic port assign [3:0] downloaded from: http:///
usb2524 ds00001588b-page 14 ? 2013 - 2016 microchip technology inc. 6.0 assigning ports there are two different (oem selectab le) methods of assigning downstream port s to upstream hosts. one method is with the prt_assign[3:0] interface through the use of mechanical switches or by electrical control of the pins via an external microcontrollers gpio interface. the second meth od is through the smbus interface, where the smbus inter- face is used to control the switching hub during operat ion and can switch downstream ports via smbus commands. 6.1 port assign interface (prt_assign[3:0] pins) assigning ports to either of the upstream host controller s can be accomplished through the 4-wire prt_assign inter- face. the prt_assign interface has three operating mo des. one is called the emb edded mode, and the other is peripheral mode (with two different electrical s ub modes; (level triggered or edge triggered). 6.1.1 embedded mode: the four-pin interface (prt_ assign[3:0]) operates with only three of the four avai lable pins (prt _assign3 is dis- abled in this mode), which enables a user to select one of 8 pre-determined port assignm ent configurations. there are 8 default configurations, or an oem can customize th e configurations through an eeprom or smbus code load. the configuration is determined by table 6-1, "usb2524 port assign interface (embedded mode)" . note 6-1 h1 = the usb host or hub that is connected to upstream port #1 note 6-2 h2 = the usb host or hub that is connected to upstream port #2 note 6-3 ua = un-assigned note 6-4 x = dont care note: any change in prt_assign pins will be igno red until the usb25 24 is out of reset. note: there is a switching delay determined by the register d0h: port interface delay timer. table 6-1: usb2524 port assign interface (embedded mode) port assign interface encoding internal default configuration host ownership of downstream ports prt_assign 3 prt_assign 2 prt_assign 1 prt_assign 0 config # port 1 port 2 port 3 port 4 x 0 0 0 0 h 1h 1h 1h 1 x 0 0 1 1 h 2h 2h 2h 2 x 0 1 0 2 h 1h 1h 2h 2 x 0 1 1 3 h 1h 1h 1h 2 x 1 0 0 4 h 2h 2h 2h 1 x 1 0 1 5 h 2h 1h 1h 1 x1106 h 1 h 1 h 2 u a x1117 h 1 h 1 h 1 u a downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 15 usb2524 6.1.2 peripheral mode: level triggered in peripheral mode (level triggered), each pin directly switches a downstream port between the two upstream host ports. each pin on the prt_assign interface is only capable of two electrical stat es (either logic low or logic high). the interface will control downstream port assignment as follows. prt_assign0 = '0', then port 1 assigned to host 1 prt_assign0 = '1', then port 1 assigned to host 2 prt_assign1 = '0', then port 2 assigned to host 1 prt_assign1 = '1', then port 2 assigned to host 2 prt_assign2 = '0', then port 3 assigned to host 1 prt_assign2 = '1', then port 3 assigned to host 2 prt_assign3 = '0', then port 4 assigned to host 1 prt_assign3 = '1', then port 4 assigned to host 2 6.1.3 peripheral mode: edge triggered each pin will respond to a positive edge transition that is part of a positive pulse that has a minimum pulse width of 100ns, and will not respond to another positive edge until after a negative pulse with minimum pulse width (that is deter- mined by the register d0h: port interface dela y timer (reset = 0x00) on page 26 ) has been detected. the combination of a 100ns positive pulse width and a programmable length ne gative width requirement provid es an effective glitch filter mechanism for a variety of mechanical switches. each positive edge transition will change the upstream host ownership of downstream ports as follows (1st transition will increment ownership from host 1 to host 2, the 2nd transition will increment ownership from host 2 to unassigned (or host 1, if not using the unassigned state), and the 3rd transition will increment ownership from unassigned to host 1 (note: this 3rd state will not occur if unassigned is not used). each subsequent transition will continue to increment the port ownership and will cycle through in similar fashion. 6.2 smbus host control of port assignment in this mode, the smbus interf ace remains live during operation of the switching hub and is used to switch/assign ports on-the-fly through smbus commands. this is accomplished through register direct writes to the port assignment reg- isters (see the usb_attach description under register ffh: status/command (reset = 0x00) on page 35 ). note: there is a switching delay determined by the register d0h: port interface delay timer. note: power-on default for edge triggered operation is: all ports assigned to host 1. downloaded from: http:///
usb2524 ds00001588b-page 16 ? 2013 - 2016 microchip technology inc. 7.0 configuration options 7.1 switching hub configuration options the microchip hub supports a large number of features (some are mutually exclus ive), and must be configured in order to correctly function when attached to a usb host controller. there are three principal ways to configure the hub: smbus, eeprom, or by internal default settings (with or without pin strapping option over-ri des). in all cases, the configuration method will be determined by the cfg_ sel2, cfg_sel1 and cfg_sel0 pins i mmediately after reset_n negation. 7.1.1 power switching polarity the selection of active state polarity for the prtpwr pins is made by a str apping option only (the prtpwr_pol pin). 7.1.2 vbus detect according to section 7.2.1 of the usb 2. 0 specification, a downstream port can ne ver provide power to its d+ or d- pull- up resistors unless the upstream ports vbus is in the asserted (powered) state. the vbus_det pin on the hub mon- itors the state of the upstream vbus sign al and will not pull-up the d+ resistor if vbus is not active. if vbus goes from an active to an inactive state (not powered), hub will remo ve power from the d+ pull-up resistor within 10 seconds. 7.1.3 port assignment configuration: the order of precedence for control of ownership of each port is as follows: 1. cfg_sel0 and cfg_sel1. 2. prt_assign_cfg register 3. prt_assign_mode register 4. prt_lck register 5. the applicable port_assign_intxx or port_assign_ xx register (based on the settings above). 7.1.4 internal register set (common to eeprom and smbus) note: the prt_lck register will primarily be used when in smbus mode, but is available for use in eeprom configuration, when the eeprom port assignment values are loaded, the prt_lck will be temporarily suspended, then after the configuration is lo aded, the prt_lck function will be enabled. table 7-1: internal eeprom & smbus register memory map reg addr r/w register name abbr default rom 00h r/w vid lsb vidl 24h 01h r/w vid msb vidm 04h 02h r/w pid lsb pidl 24h 03h r/w pid msb pidm 25h 04h r/w did lsb didl 00h 05h r/w did msb didm 00h 06h r/w config data byte 1 cfg1 9bh 07h r/w config data byte 2 cfg2 10h 08h r/w config data byte 3 cfg3 00h 09h r/w non-removable devices nrd 00h 0ah r/w port disable (self) pds 00h 0bh r/w port disable (bus) pdb 00h 0ch r/w max power (self) maxps 01h downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 17 usb2524 0dh r/w max power (bus) maxpb 64h 0eh r/w hub controller max current (self) hcmcs 01h 0fh r/w hub controller max current (bus) hcmcb 64h 10h r/w power-on time pwrt 32h 11h r/w lang_id_h langidh 00h 12h r/w lang_id_l langidl 00h 13h r/w mfr_str_len mfrsl 00h 14h r/w prd_str_len prdsl 00h 15h r/w ser_str_len sersl 00h 16h-53h r/w mfr_str manstr 00h 54h-91h r/w prod_str prdstr 00h 92h-cfh r/w ser_str serstr 00h d0h r/w prt_dly_time prtdt 2fh d1h r/w port assign int0a prtif0a 11h d2h r/w port assign int0b prtif0b 11h d3h r/w port assign int0c prtif0c 00h d4h r/w port assign int0d prtif0d 00h d5h r/w port assign int1a prtif1a 22h d6h r/w port assign int1b prtif1b 22h d7h r/w port assign int1c prtif1c 00h d8h r/w port assign int1d prtif1d 00h d9h r/w port assign int2a prtif2a 11h dah r/w port assign int2b prtif2b 22h dbh r/w port assign int2c prtif2c 00h dch r/w port assign int2d prtif2d 00h ddh r/w port assign int3a prtif3a 11h deh r/w port assign int3b prtif3b 21h dfh r/w port assign int3c prtif3c 00h e0h r/w port assign int3d prtif3d 00h e1h r/w port assign int4a prtif4a 22h e2h r/w port assign int4b prtif4b 12h e3h r/w port assign int4c prtif4c 00h e4h r/w port assign int4d prtif4d 00h e5h r/w port assign int5a prtif5a 12h e6h r/w port assign int5b prtif5b 11h e7h r/w port assign int5c prtif5c 00h table 7-1: internal eeprom & smbus register memory map (continued) reg addr r/w register name abbr default rom downloaded from: http:///
usb2524 ds00001588b-page 18 ? 2013 - 2016 microchip technology inc. 7.1.4.1 register 00h: vendor id (lsb) (reset = 0x00) 7.1.4.2 register 01h: vendor id (msb) (reset = 0x00) 7.1.4.3 register 02h: product id (lsb) (reset = 0x00) e8h r/w port assign int5d prtif5d 00h e9h r/w port assign int6a prtif6a 11h eah r/w port assign int6b prtif6b 02h ebh r/w port assign int6c prtif6c 00h ech r/w port assign int6d prtif6d 00h edh r/w port assign int7a prtif7a 11h eeh r/w port assign int7b prtif7b 01h efh r/w port assign int7c prtif7c 00h f0h r/w port assign int7d prtif7d 00h f1h r/w port assign 12 prta12 00h f2h r/w port assign 34 prta34 00h f3h r/w port assign 56 prta56 00h f4h r/w port assign 7 prta7 00h f5h r/w port lockout prt_lk 00h f6h-feh r/w reserved n/a 00h ffh r/w status/command note: smbus register only! stcd 00h bit number bit name description 7:0 vid_lsb least significant byte of the vendo r id. this is a 16-bit value that uniquely identifies the vendor of the user device (assigned by usb-interface forum). this field is set by the oem using ei ther the smbus or eeprom interface options. bit number bit name description 7:0 vid_msb most significant byte of the vendor id. this is a 16-bit value that uniquely identifies the vendor of the user devi ce (assigned by usb-interface forum). this field is set by the oem using either the smbus or eeprom interface options. bit number bit name description 7:0 pid_lsb least significant byte of the produc t id. this is a 16-bit value that the vendor can assign that uniquely identifies this particular product (assigned by oem). this field is set by the oem using either the smbus or eeprom interface options. table 7-1: internal eeprom & smbus register memory map (continued) reg addr r/w register name abbr default rom downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 19 usb2524 7.1.4.4 register 03h: product id (msb) (reset = 0x00) 7.1.4.5 register 04h: device id (lsb) (reset = 0x00) 7.1.4.6 register 05h: device id (msb) (reset = 0x00) 7.1.4.7 register 06h: config_byte_1 (reset = 0x00) bit number bit name description 7:0 pid_msb most significant byte of the produc t id. this is a 16-bit value that the vendor can assign that uniquely identifies th is particular product (assigned by oem). this field is set by the oem using either the smbus or eeprom interface options. bit number bit name description 7:0 did_lsb least significant byte of the device id. this is a 16-bit device release number in bcd format (assigned by oem). this field is set by the oem using either the smbus or eeprom interface options. bit number bit name description 7:0 did_msb most significant byte of the device id. this is a 16-bit device release number in bcd format (assigned by oem). this field is set by the oem using either the smbus or eeprom interface options. bit number bit name description 7 self_bus_pwr self or bus power: select s between self- and bus-powered operation. the hub is either self-powered (draws less than 2ma of upstream bus power) or bus-powered (limited to a 100ma maximum of upstream power prior to being configured by the host controller). when configured as a bus-powered device, the microchip hub consumes less than 100ma of current prior to being c onfigured. after conf iguration, the bus- powered microchip hub (along with all associated hub circuitry, any embedded devices if part of a compound device, and 100ma per externally available downstream port) must cons ume no more than 500ma of upstream vbus current. the current consumptio n is system dependent, and the oem must ensure that the usb 2.0 specifications are not violated. when configured as a self-powered dev ice, <1ma of upstream vbus current is consumed and all ports are available, with each port being capable of sourcing 500ma of current. this field is set by the oem using ei ther the smbus or eeprom interface options. please see the description under dynamic power for the self/bus power functionality when dynamic power switching is enabled. 0 = bus-powered operation. 1 = self-powered operation. note: if dynamic power switching is enabled, this bit is ignored and the self_pwr pin is used to determine if the hub is operating from self or bus power. 6 reserved reserved, always = 0. 5 hs_disable high speed disable: disables the capability to attach as either a high/full- speed device, and forces attachment as full-speed only i.e. (no high-speed support). 0 = high-/full-speed. 1 = full-speed-only (high-speed disabled!) downloaded from: http:///
usb2524 ds00001588b-page 20 ? 2013 - 2016 microchip technology inc. 7.1.4.8 register 07h: configuration data byte 2 (reset = 0x00) 4 mtt_enable multi-tt enable: enables one tr ansaction translator per port operation. selects between a mode where only one transaction translator is available for all ports (single-tt), or each port gets a dedicated transaction translator (multi-tt) {note: the host may force single-tt mode only}. when using the internal default option, the mtt_en pin enables/disables mtt support. 0 = single tt for all ports. 1 = one tt per port (multiple tts supported) 3 eop_disable eop disable: disables eop gene ration of eof1 when in full-speed mode. during fs operation only, this permits the hub to send eop if no downstream traffic is detected at eof1 . see section 11.3.1 of the usb 2.0 specification for additional details. note: generati on of an eop at t he eof1 point may prevent a host controller (operating in fs mode) from placing the usb bus in suspend. 0 = an eop is generated at the eof1 point if no traffic is detected. 1 = eop generation at eof1 is disabled (note: this is normal usb operation). 2:1 current_sns over current sense: selects current sensing on a port-by-port basis, all ports ganged, or none (only for bus-powered h ubs) the ability to support current sensing on a port or ganged basis is hardware implementation dependent. 00 = ganged sensing (all ports together). 01 = individual port-by-port. 1x = over current sensing not suppor ted. (must only be used with bus- powered configurations!) 0 port_pwr port power switching: enables power switching on all ports simultaneously (ganged), or port power is individually switched on and off on a port- by-port basis (individual). the ability to support power enabling on a port or ganged basis is hardware implementation dependent. 0 = ganged switching (all ports together) 1 = individual port-by-port switching. bit number bit name description 7 dynamic dynamic power enable: controls t he ability of the hub to automatically change from self-powered operation to bus- powered operation if the local power source is removed or is unavai lable (and from bus-powered to self- powered if the local power source is restored). {note: if the local power source is available, the hub will always switch to self-powered operation.} when dynamic power switching is enabl ed, the hub detects the availability of a local power source by monitoring the external self_pwr pin. if the hub detects a change in power source availability, the hub immediately disconnects and removes power from all downstream devices and disconnects the upstream port. the hub will then re-attach to the upstream port as either a bus-powered hub (if local-power in unavailable) or a self- powered hub (if local power is available). 0 = no dynamic auto-switching. 1 = dynamic auto-switching capable. 6 reserved reserved, always = 0. 5:4 oc_timer overcurrent timer: over current timer delay. 00 = 0.1ms 01 = 2ms 10 = 4ms 11 = 6ms bit number bit name description downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 21 usb2524 7.1.4.9 register 08h: configuration data byte 3 (reset = 0x00) 3 compound compound device: allows the oem to indicate that the hub is part of a compound (see the usb specification for definition) device. the applicable port(s) must also be defined as having a non-removable device. note: when configured via strapping options, declaring a port as non- removable automatically causes the hub c ontroller to report that it is part of a compound device. 0 = no. 1 = yes, hub is part of a compound device. 2:1 reserved reserved, always = 0. 0 boost_iout upstream usb electrical signaling drive strength boost bit. note: this is used for long-trace length designs where additional electri- cal signal boost may be required to support standard usb signal levels at the far end of a cable. 0 = normal electrical drive strength. 1 = elevated electrical drive strength. bit number bit name description 7:6 prt_assign_mod e port assignment interface mode: 00 = port assign interface is configured for programmable mode (8 configurations) (3-wire) 01 = port assign interface is configur ed for direct port control. (4-wire), level sensitive. 10 = port assign interface is configur ed for direct port control. (4-wire), edge sensitive, and unassigned state is not supported. 11 = port assign interface is configur ed for direct port control. (4-wire), edge sensitive, and the una ssigned state is supported. 5 prt_assign_cfg port a ssignment configuration: 0 = port assignment is contro lled by hardware interface pins 1 = port assignment is controlled by: port_assign_12 port_assign_34 port_assign_56 port_assign_73333 4:3 reserved reserved, always = 0.3 2:1 led_mode led mode selection: the led_a[ 4:1]_n and led_b[4:1]_n pins support several different modes of operation (depending upon oem implementation of the led circuit). 00 = usb mode, (see usb mode on page 40 for description) 01 = host ownership and port speed led indicator, (see host ownership and port speed led indication on page 40 for description) 10 = basic host ownership led indicator, (see basic host owner led indication on page 40 for description) 11 = same as "00", usb mode warning: do not enable an led mode th at requires led pins that are not available in the specific package being used in the implementation! bit number bit name description downloaded from: http:///
usb2524 ds00001588b-page 22 ? 2013 - 2016 microchip technology inc. 7.1.4.10 register 09h: non-removable device (reset = 0x00) 7.1.4.11 register 0ah: port disable for self powered operation (reset = 0x00) 0 string_en enables string descriptor support 0 = string support disabled 1 = string support enabled bit number bit name description 7:0 nr_device non-removable device: indicates which port(s) include non- removable devices. 0 = port is removable, 1 = port is non- removable. informs the host if one of the active ports has a permanent device that is un- detachable from the hub. (note: the de vice must provide its own descriptor data.) when using the internal default option, the non_rem[1:0] pins will designate the appropriate ports as being non- removable. bit 7= reserved, always = 0. bit 6= reserved, always = 0. bit 5= reserved, always = 0. bit 4= 1; port 4 is disabled. bit 3= 1; port 3 non-removable. bit 2= 1; port 2 non-removable. bit 1= 1; port 1 non-removable. bit 0 is reserved, always = 0. bit number bit name description 7:0 port_dis_sp port disable self-powered: disabl es 1 or more contiguous ports. 0 = port is available, 1 = port is disabled. during self-powered operation, th is selects the ports which will be permanently disabled, and are not avail able to be enabled or enumerated by a host controller. the disabled ports must be contiguous, and must be in decreasing order starting with port 4. when using the internal default option, the prt_dis[1:0] pins will disable the appropriate ports. bit 7= reserved, always = 0. bit 6= reserved, always = 0. bit 5= reserved, always = 0. bit 4= 1; port 4 is disabled. bit 3= 1; port 3 is disabled. bit 2= 1; port 2 is disabled. bit 1= 1; port 1 is disabled. bit 0 is reserved, always = 0 bit number bit name description downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 23 usb2524 7.1.4.12 register 0bh: port disable fo r bus powered operation (reset = 0x00) 7.1.4.13 register 0ch: max power for se lf powered operation (reset = 0x00) 7.1.4.14 register 0dh: max power for bus powered operation (reset = 0x00) 7.1.4.15 register 0eh: hub controller max curr ent for self powered operation (reset = 0x00) bit number bit name description 7:0 port_dis_bp port disable bus-powered: disabl es 1 or more contiguous ports. 0 = port is available, 1 = port is disabled. during bus-powered operation, this selects the ports which will be permanently disabled, and are not available to be enabled or enumerated by a host controller. the disabled ports must be contiguous, and must be in decreasing order starting with port 4. when using the internal default option, the prt_dis[1:0] pins will disable the appropriate ports. bit 7= reserved, always = 0. bit 6= reserved, always = 0. bit 5= reserved, always = 0. bit 4= 1; port 4 is disabled. bit 3= 1; port 3 is disabled. bit 2= 1; port 2 is disabled. bit 1= 1; port 1 is disabled. bit 0 is reserved, always = 0 bit number bit name description 7:0 max_pwr_sp max power self_powered: value in 2ma increments that the hub consumes from an upstream port (vbus) when o perating as a self-powered hub. this value includes the hub silicon along with the combined power consumption (from vbus) of all associated circuitry on the board. this value also includes the power consumption of a permanently attached peripheral if the hub is configured as a compound device, and the embedded peripheral reports 0ma in its descriptors. note: the usb 2.0 specification does not permit this value to exceed 100ma bit number bit name description 7:0 max_pwr_bp max power bus_powered: value in 2ma increments that the hub consumes from an upstream port (vbus) when op erating as a bus-powered hub. this value includes the hub silicon along with the combined power consumption (from vbus) of all associated circuitry on the board. this value also includes the power consumption of a permanently attached peripheral if the hub is configured as a compound device, and the embedded peripheral reports 0ma in its descriptors. bit number bit name description 7:0 hc_max_c_sp hub controller max current self -powered: value in 2ma increments that the hub consumes from an upstream po rt (vbus) when operating as a self- powered hub. this value includes the hub silicon along with the combined power consumption (from vbus) of all associated circuitry on the board. this value does not include the power co nsumption of a permanently attached peripheral if the hub is c onfigured as a compound device. note: the usb 2.0 specification does not permit this value to exceed 100ma downloaded from: http:///
usb2524 ds00001588b-page 24 ? 2013 - 2016 microchip technology inc. 7.1.4.16 register 0fh: hub controller max current for bus powered operation (reset = 0x00) 7.1.4.17 register 10h: power-on time (reset = 0x00) 7.1.4.18 register 11h: language id high (reset = 0x00) 7.1.4.19 register 12h: language id low (reset = 0x00) 7.1.4.20 register 13h: manufacturer string length (reset = 0x00) 7.1.4.21 register 14h: product string length (reset = 0x00) 7.1.4.22 register 15h: serial string length (reset = 0x00) bit number bit name description 7:0 hc_max_c_bp hub controller max current bus- powered: value in 2ma increments that the hub consumes from an upstream po rt (vbus) when operating as a bus- powered hub. this value will include the hub silicon along with the combined power consumption (from vbus) of all associated circuitry on the board. this value will not include the power cons umption of a permanently attached peripheral if the hub is c onfigured as a compound device. bit number bit name description 7:0 power_on_time power on time: the length of time that is takes (in 2 ms intervals) from the time the host initiated power-on sequence begins on a port until power is good on that port. system software uses this value to determine how long to wait before accessing a powered-on port. bit number bit name description 7:0 lang_id_h usb language id (upper 8 bits of a 16 bit id field) bit number bit name description 7:0 lang_id_l usb language id (lower 8 bits of a 16 bit id field) bit number bit name description 7:0 mfr_str_len manufacturer string length maximum string length is 31 characters. bit number bit name description 7:0 prd_str_len product string length maximum string length is 31 characters bit number bit name description 7:0 ser_str_len serial string length maximum string length is 31 characters downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 25 usb2524 7.1.4.23 register 16h-53h: manufacturer string (reset = 0x00) 7.1.4.24 register 54h-91h: product string (reset = 0x00) 7.1.4.25 register 92h-cfh: seri al string (reset = 0x00) bit number bit name description 7:0 mfr_str manufacturer string, unicod e utf-16le per usb 2.0 specification maximum string length is 31 characters (62 bytes) note: the string consists of individua l 16 bit unicode utf-16le char- acters. the characters will be stored starting with the lsb at the least significant address and the m sb at the next 8-bit location (sub- sequent characters must be st ored in sequential contiguous address in the same lsb, msb manner). some eeprom program- mers may transpose the msb and lsb, thus reversing the byte order. please pay careful attention to the byte ordering or your selected programming tools. bit number bit name description 7:0 prd_str product string, unicode ut f-16le per usb 2.0 specification maximum string length is 31 characters (62 bytes) note: the string consists of individua l 16 bit unicode utf-16le char- acters. the characters will be stored starting with the lsb at the least significant address and the m sb at the next 8-bit location (sub- sequent characters must be st ored in sequential contiguous address in the same lsb, msb manner). some eeprom program- mers may transpose the msb and lsb, thus reversing the byte order. please pay careful attention to the byte ordering or your selected programming tools. bit number bit name description 7:0 ser_str serial string, unicode utf-16le per usb 2.0 specification maximum string length is 31 characters (62 bytes) note: the string consists of individua l 16 bit unicode utf-16le char- acters. the characters will be stored starting with the lsb at the least significant address and the m sb at the next 8-bit location (sub- sequent characters must be st ored in sequential contiguous address in the same lsb, msb manner). some eeprom program- mers may transpose the msb and lsb, thus reversing the byte order. please pay careful attention to the byte ordering or your selected programming tools. downloaded from: http:///
usb2524 ds00001588b-page 26 ? 2013 - 2016 microchip technology inc. 7.1.4.26 register d0h: port interface delay timer (reset = 0x00) 7.1.4.27 register d1h: port assign in terface configuration 0a (reset = 0x00) 7.1.4.28 register d2h: port assign in terface configuration 0b (reset = 0x00) bit number bit name description 7:0 prtdt port delay timer: a 0-255 bit value that represents a delay of 0-255ms from the time a state change is detected on the prt_assign[3:0] pins until the internal logic begins the port switching process for the affected port (or ports) to a different upstream host. note: this register effectively creates a programmable debounce circuit for mechanical switches that may be connected to the prt_as- sign[3:0] interface pins. bit number bit name description 7:0 port_int_0a port assign interface 0a: dete rmines the configuration of the hardware interface configuration for the assignmen t of ports 1 & 2 to upstream hosts. bit [7:4] = 0000 port 2 is unassigned 0001 port 2 owned by up1 0010 port 2 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 1 is unassigned 0001 port 1 owned by up1 0010 port 1 owned by up2 0011 to 1111 reserved, will default to 0001 value bit number bit name description 7:0 port_int_0b port assign interface 0b: dete rmines the configuration of the hardware interface configuration for the assignmen t of ports 3 & 4 to upstream hosts. bit [7:4] = 0000 port 4 is unassigned 0001 port 4 owned by up1 0010 port 4 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 3 is unassigned 0001 port 3 owned by up1 0010 port 3 owned by up2 0011 to 1111 reserved, will default to 0001 value downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 27 usb2524 7.1.4.29 register d3h: port assign inte rface configuration 0c (reset = 0x00) 7.1.4.30 register d4h: port assign inte rface configuration 0d (reset = 0x00) 7.1.4.31 register d5h: port assign in terface configuration 1a (reset = 0x00) 7.1.4.32 register d6h: port assign in terface configuration 1b (reset = 0x00) bit number bit name description 7:0 port_int_0c reserved, always = 0. bit number bit name description 7:0 port_int_0d reserved, always = 0. bit number bit name description 7:0 port_int_1a port assign interface 1a: determines the configuration of the hardware interface configuration for the assignmen t of ports 1 & 2 to upstream hosts. bit [7:4] = 0000 port 2 is unassigned 0001 port 2 owned by up1 0010 port 2 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 1 is unassigned 0001 port 1 owned by up1 0010 port 1 owned by up2 0011 to 1111 reserved, will default to 0001 value bit number bit name description 7:0 port_int_1b port assign interface 1b: determines the configuration of the hardware interface configuration for the assignmen t of ports 3 & 4 to upstream hosts. bit [7:4] = 0000 port 4 is unassigned 0001 port 4 owned by up1 0010 port 4 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 3 is unassigned 0001 port 3 owned by up1 0010 port 3 owned by up2 0011 to 1111 reserved, will default to 0001 value downloaded from: http:///
usb2524 ds00001588b-page 28 ? 2013 - 2016 microchip technology inc. 7.1.4.33 register d7h: port assign inte rface configuration 1c (reset = 0x00) 7.1.4.34 register d8h: port assign inte rface configuration 1d (reset = 0x00) 7.1.4.35 register d9h: port assign in terface configuration 2a (reset = 0x00) 7.1.4.36 register dah: port assign inte rface configuration 2b (reset = 0x00) bit number bit name description 7:0 port_int_1c reserved, always = 0. bit number bit name description 7:0 port_int_1d reserved, always = 0. bit number bit name description 7:0 port_int_2a port assign interface 2a: dete rmines the configuration of the hardware interface configuration for the assignmen t of ports 1 & 2 to upstream hosts. bit [7:4] = 0000 port 2 is unassigned 0001 port 2 owned by up1 0010 port 2 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 1 is unassigned 0001 port 1 owned by up1 0010 port 1 owned by up2 0011 to 1111 reserved, will default to 0001 value bit number bit name description 7:0 port_int_2b port assign interface 2b: dete rmines the configuration of the hardware interface configuration for the assignmen t of ports 3 & 4 to upstream hosts. bit [7:4] = 0000 port 4 is unassigned 0001 port 4 owned by up1 0010 port 4 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 3 is unassigned 0001 port 3 owned by up1 0010 port 3 owned by up2 0011 to 1111 reserved, will default to 0001 value downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 29 usb2524 7.1.4.37 register dbh: port assign inte rface configuration 2c (reset = 0x00) 7.1.4.38 register dch: port assign interface configuration 2d (reset = 0x00) 7.1.4.39 register ddh: port assign interface configuration 3a (reset = 0x00) 7.1.4.40 register deh: port assign inte rface configuration 3b (reset = 0x00) bit number bit name description 7:0 port_int_2c reserved, always = 0. bit number bit name description 7:0 port_int_2d reserved, always = 0. bit number bit name description 7:0 port_int_3a port assign interface 3a: determines the configuration of the hardware interface configuration for the assignmen t of ports 1 & 2 to upstream hosts. bit [7:4] = 0000 port 2 is unassigned 0001 port 2 owned by up1 0010 port 2 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 1 is unassigned 0001 port 1 owned by up1 0010 port 1 owned by up2 0011 to 1111 reserved, will default to 0001 value bit number bit name description 7:0 port_int_3b port assign interface 3b: determines the configuration of the hardware interface configuration for the assignmen t of ports 3 & 4 to upstream hosts. bit [7:4] = 0000 port 4 is unassigned 0001 port 4 owned by up1 0010 port 4 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 3 is unassigned 0001 port 3 owned by up1 0010 port 3 owned by up2 0011 to 1111 reserved, will default to 0001 value downloaded from: http:///
usb2524 ds00001588b-page 30 ? 2013 - 2016 microchip technology inc. 7.1.4.41 register dfh: port assign inte rface configuration 3c (reset = 0x00) 7.1.4.42 register e0h: port assign interface configuration 3d (reset = 0x00) 7.1.4.43 register e1h: port assign interface configuration 4a (reset = 0x00) 7.1.4.44 register e2h: port assign interface configuration 4b (reset = 0x00) bit number bit name description 7:0 port_int_3c reserved, always = 0. bit number bit name description 7:0 port_int_3d reserved, always = 0. bit number bit name description 7:0 port_int_4a port assign interface 4a: dete rmines the configuration of the hardware interface configuration for the assignmen t of ports 1 & 2 to upstream hosts. bit [7:4] = 0000 port 2 is unassigned 0001 port 2 owned by up1 0010 port 2 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 1 is unassigned 0001 port 1 owned by up1 0010 port 1 owned by up2 0011 to 1111 reserved, will default to 0001 value bit number bit name description 7:0 port_int_4b port assign interface 4b: dete rmines the configuration of the hardware interface configuration for the assignmen t of ports 3 & 4 to upstream hosts. bit [7:4] = 0000 port 4 is unassigned 0001 port 4 owned by up1 0010 port 4 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 3 is unassigned 0001 port 3 owned by up1 0010 port 3 owned by up2 0011 to 1111 reserved, will default to 0001 value downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 31 usb2524 7.1.4.45 register e3h: port assign interface configuration 4c (reset = 0x00) 7.1.4.46 register e4h: port assign interface configuration 4d (reset = 0x00) 7.1.4.47 register e5h: port assign interface configuration 5a (reset = 0x00) 7.1.4.48 register e6h: port assign interface configuration 5b (reset = 0x00) bit number bit name description 7:0 port_int_4c reserved, always = 0. bit number bit name description 7:0 port_int_4d reserved, always = 0. bit number bit name description 7:0 port_int_5a port assign interface 5a: determines the configuration of the hardware interface configuration for the assignmen t of ports 1 & 2 to upstream hosts. bit [7:4] = 0000 port 2 is unassigned 0001 port 2 owned by up1 0010 port 2 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 1 is unassigned 0001 port 1 owned by up1 0010 port 1 owned by up2 0011 to 1111 reserved, will default to 0001 value bit number bit name description 7:0 port_int_5b port assign interface 5b: determines the configuration of the hardware interface configuration for the assignmen t of ports 3 & 4 to upstream hosts. bit [7:4] = 0000 port 4 is unassigned 0001 port 4 owned by up1 0010 port 4 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 3 is unassigned 0001 port 3 owned by up1 0010 port 3 owned by up2 0011 to 1111 reserved, will default to 0001 value downloaded from: http:///
usb2524 ds00001588b-page 32 ? 2013 - 2016 microchip technology inc. 7.1.4.49 register e7h: port assign interface configuration 5c (reset = 0x00) 7.1.4.50 register e8h: port assign interface configuration 5d (reset = 0x00) 7.1.4.51 register e9h: port assign interface configuration 6a (reset = 0x00) 7.1.4.52 register eah: port assign interface configuration 6b (reset = 0x00) bit number bit name description 7:0 port_int_5c reserved, always = 0. bit number bit name description 7:0 port_int_5d reserved, always = 0. bit number bit name description 7:0 port_int_6a port assign interface 6a: dete rmines the configuration of the hardware interface configuration for the assignmen t of ports 1 & 2 to upstream hosts. bit [7:4] = 0000 port 2 is unassigned 0001 port 2 owned by up1 0010 port 2 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 1 is unassigned 0001 port 1 owned by up1 0010 port 1 owned by up2 0011 to 1111 reserved, will default to 0001 value bit number bit name description 7:0 port_int_6b port assign interface 6b: dete rmines the configuration of the hardware interface configuration for the assignmen t of ports 3 & 4 to upstream hosts. bit [7:4] = 0000 port 4 is unassigned 0001 port 4 owned by up1 0010 port 4 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 3 is unassigned 0001 port 3 owned by up1 0010 port 3 owned by up2 0011 to 1111 reserved, will default to 0001 value downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 33 usb2524 7.1.4.53 register ebh: port assign inte rface configuration 6c (reset = 0x00) 7.1.4.54 register ech: port assign inte rface configuration 6d (reset = 0x00) 7.1.4.55 register edh: port assign inte rface configuration 7a (reset = 0x00) 7.1.4.56 register eeh: port assign interface configuration 7b (reset = 0x00) bit number bit name description 7:0 port_int_6c reserved, always = 0. bit number bit name description 7:0 port_int_6d reserved, always = 0. bit number bit name description 7:0 port_int_7a port assign interface 7a: determines the configuration of the hardware interface configuration for the assignmen t of ports 1 & 2 to upstream hosts. bit [7:4] = 0000 port 2 is unassigned 0001 port 2 owned by up1 0010 port 2 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 1 is unassigned 0001 port 1 owned by up1 0010 port 1 owned by up2 0011 to 1111 reserved, will default to 0001 value bit number bit name description 7:0 port_int_7b port assign interface 7b: determines the configuration of the hardware interface configuration for the assignmen t of ports 3 & 4 to upstream hosts. bit [7:4] = 0000 port 4 is unassigned 0001 port 4 owned by up1 0010 port 4 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 3 is unassigned 0001 port 3 owned by up1 0010 port 3 owned by up2 0011 to 1111 reserved, will default to 0001 value downloaded from: http:///
usb2524 ds00001588b-page 34 ? 2013 - 2016 microchip technology inc. 7.1.4.57 register efh: port assign inte rface configuration 7c (reset = 0x00) 7.1.4.58 register f0h: port assign inte rface configuration 7d (reset = 0x00) 7.1.4.59 register f1h: port assignment 1 & 2 (reset = 0x00) 7.1.4.60 register f2h: port assignment 3 & 4 (reset = 0x00) bit number bit name description 7:0 port_int_7c reserved, always = 0. bit number bit name description 7:0 port_int_7d reserved, always = 0. bit number bit name description 7:0 port_assign_12 port 1 & 2 assignment to upstr eam host port. determines which upstream port owns each of the downstream ports bit [7:4] = 0000 port 2 is unassigned 0001 port 2 owned by up1 0010 port 2 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 1 is unassigned 0001 port 1 owned by up1 0010 port 1 owned by up2 0011 to 1111 reserved, will default to 0001 value bit number bit name description 7:0 port_assign_34 port 3 & 4 assignment to upstr eam host port. determines which upstream port owns each of the downstream ports bit [7:4] = 0000 port 4 is unassigned 0001 port 4 owned by up1 0010 port 4 owned by up2 0011 to 1111 reserved, will default to 0001 value bit [3:0] = 0000 port 3 is unassigned 0001 port 3 owned by up1 0010 port 3 owned by up2 0011 to 1111 reserved, will default to 0001 value downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 35 usb2524 7.1.4.61 register f3h: port assignment 5 & 6 (reset = 0x00) 7.1.4.62 register f4h: port assignment 7 (reset = 0x00) 7.1.4.63 register f5h: port lockout (reset = 0x00) 7.1.4.64 register ffh: status/command (reset = 0x00) bit number bit name description 7:0 port_assign_56 reserv ed, always = 0. bit number bit name description 7:0 port_assign_7 reserved, always = 0. bit number bit name description 7:0 port_lockout port lockout: locks a port to the currently assigned upstream port, and doesnt allow the port to be re-assigned. 0 = port is available to be switched 1 = port is locked to the assigned port. bit 7= reserved, always = 0. bit 6= reserved, always = 0. bit 5= reserved, always = 0. bit 4= 1; port 4 is locked. bit 3= 1; port 3 is locked. bit 2= 1; port 2 is locked. bit 1= 1; port 1 is locked. bit 0 is reserved, always = 0 bit number bit name description 7:3 reserved reserved. {note: software must never write a 1 to these bits} 2 intf_pw_dn smbus interface power down 0 = interface is active 1 = interface power down after ack has completed. {note: this bit is write once and is on ly cleared by assertion of the external reset_n pin.} 1 reset reset the smbus interface and internal memory back to reset_n assertion default settings. {note: during this reset, this bit is automatically cleared to its default value of 0.} 0 = normal run/idle state. 1 = force a reset of the registers to their default state. if the usb_attch bit is set, then this bit will only reset the non write- protected registers! downloaded from: http:///
usb2524 ds00001588b-page 36 ? 2013 - 2016 microchip technology inc. 7.2 eeprom interface the microchip hub can be configured via a 2-wire (i 2 c) eeprom (256x8). (please see table 4-2, "smbus or eeprom interface behavior" for specific details on how to enable configuration via an i 2 c eeprom). the internal state-machine will, (when configured for eeprom support) read the external eeprom for configuration data. the hub will then attach to the upstream usb port. please see internal register set (common to eeprom and smbus) for a list of data fields available. 7.2.1 i 2 c master the i 2 c eeprom interface implem ents a subset of the i 2 c master specification (please refer to the philips semicon- ductor standard i 2 c-bus specification for details on i 2 c bus protocols). the hubs i 2 c eeprom interface is designed to attach to a single dedicated i 2 c eeprom, and it conforms to the standard-mode i 2 c specification (100kbit/s trans- fer rate and 7-bit addressing) for protocol and electrical compatibility. the hub acts as the master and generates the serial clock scl, controls the bus access (determines which device acts as the transmitter and which device acts as the receiver), and generates the start and stop conditions. 7.2.1.1 implementation characteristics the hub will only access an eeprom usin g the sequential read protocol. 7.2.1.2 pull-up resistor the circuit board designer is required to place external pull-up resistors (10k ? recommended) on the sda/smbdata & scl/smbclk/cfg_selo lines (per smbus 1.0 specificat ion, and eeprom manufactur er guidelines) to vcc in order to assure proper operation. 7.2.1.3 i 2 c eeprom slave address slave address is 1010000. 7.2.2 in-circuit eeprom programming the eeprom can be programmed via ate by pulling reset_n low (which tri-states the hubs eeprom interface and allows an external source to program the eeprom). 0 usb_attach usb attach (and write protect). 0 = smbus slave interface is active. 1 = hub will signal a usb attach event to an upstream device, and the internal memory (address range 00h-f0h) is write-protected to prevent unintentional data corruption.} {note 1: this bit is write once and is only cleared by assertion of the external reset_n pin.} {note 2: if the smbus interface is kept active after this bit is set, the port_assign_12, port_assi gn_34 port_assign_56, port_assign_7 and port_lockout re gisters may be continuously written to reconfigure port ownership. note: the hub does not have the capability to write, or program, an external eeprom. the hub only has the capability to read external eeproms. the external eeprom will be read (even if it is blank or non-popu- lated), and the hub will be configured with the values that are read. note: extensions to the i 2 c specification are not supported. note: 10-bit addressing is not supported. bit number bit name description downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 37 usb2524 7.3 smbus slave interface instead of loading user-defined descriptor data from an external eeprom, the microchip hub can be configured to receive a code load from an external processor via an smbu s interface. the smbus interface shares the same pins as the eeprom interface, if cfg_sel2, cfg_sel1 & cfg_sel0 activates the sm bus interface, external eeprom sup- port is no longer available (and the user-defined descripto r data must be downloaded via the smbus). due to system issues, the microchip hub waits indefinitely for the smbus code load to complete and only appears as a newly con- nected device on usb after the code load is complete. the hubs smbus implementation is a subset of t he smbus interface to the host. the device is a slave-only smbus device. the implementation in the device is a subset of sm bus since it only supports tw o protocols. the write block and read block protocols are the only valid smbus protocol s for the hub. the hub responds to other protocols as described in invalid protocol response behavior on page 38 . reference the system management bus specification, rev 1.0. the smbus interface is used to read and write the r egisters in the device. the register set is shown in , internal register set (common to eeprom and smbus) on page 16 . 7.3.1 bus protocols typical write block and read block protocols are shown be low. register accesses are performed using 7-bit slave addressing, an 8-bit register address field, and an 8-bit data field. the shading indicates the hub driving data on the smbdata line; otherwise, host data is on the sda/smbdata line. the slave address is the unique smbus interface address for t he hub that identifies it on smbus. the register address field is the internal address of the regist er to be accessed. the register data fiel d is the data that the host is attempting to write to the register or the contents of the register that the host is attempting to read. data bytes are transferre d msb first (msb first). 7.3.1.1 block read/write the block write begins with a slave address and a write condition. after the command code the host issues a byte count which describes how many more bytes will follow in the message. if a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. the by te count may not be 0. a block read or write is allowed to transfer a maximum of 32 data bytes. for the following smbus tables: table 7-2: smbus block write denotes master-to-slave denotes slave-to-master 1 81 s slave address register address wr a 171 18 a 1 ... byte count = n a data byte 1 a data byte 2 8 111 88 data byte n a p block write a downloaded from: http:///
usb2524 ds00001588b-page 38 ? 2013 - 2016 microchip technology inc. a block read differs from a block write in that th e repeated start condition exists to satisfy the i 2 c specification's require- ment for a change in the transfer direction. table 7-3: smbus block read 7.3.2 invalid protocol response behavior registers that are accessed with an invalid protocol are not u pdated. a register is only updated following a valid protocol. the only valid protocols are write block and read block, which are described above. the hub only responds to the hardware selected slave addr ess. attempting to communic ate with the hub over smbus with an invalid slave address or invalid protocol results in no response, and the smbus sl ave interface returns to the idle state. the only valid registers that are accessible by the smbus slave address are the registers defined in the reg- isters section. see undefined registers for the response to undefined registers. 7.3.3 general call address response the hub does not respond to a general call address of 0000_000b. 7.3.4 slave device time-out according to the smbus specification, v1.0 devices in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds 25ms (t timeout, min ). devices that have detect ed this condition must reset their communication and be able to receive a new start condition no later than 35ms (t timeout, max ). 7.3.5 stretching the sclk signal the hub supports stretching of the sclk by other de vices on the smbus. the hub does not stretch the sclk. 7.3.6 smbus timing the smbus slave interface complies with the smbus ac timi ng specification. see the smbus timing in the timing diagram section. 7.3.7 bus reset sequence the smbus slave interface resets and returns to the idle state upon a start field followed immediately by a stop field. 7.3.8 smbus aler t response address the smbalert# signal is not supported by the hub. 7.3.8.1 undefined registers reads to undefined registers return 00h. writes to undefined registers have no effect and do not return an error. note: some simple devices do not contain a clock low drive circuit; this simple kind of de vice typically resets its communications port after a start or stop condition. the slave device time-out must be implemented. block read 1 s s slave address register address wr a 17 1 18 a 1 slave address rd a 71 1 81 1 1 88 p 1 81 a a a a byte count = n data byte 1 data byte 2 data byte n ... downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 39 usb2524 7.3.8.2 reserved registers unless otherwise instructed, only a 0 may be wr itten to all reserved registers or bits. 7.4 default strapping option the usb2524 can be configured via a combination of internal default values and pin strap options. the strapping option pins only cover a lim ited sub-set of the configuration options. the internal default values will be used for the bits & registers that are no t controlled by a strapping option pin. the led_a[4:1]_n pins are sampled after reset_n negation, and the logic values are used to configure the hub if the internal default configuration mode is selected. the implementation shown in figure 7-1, "led strapping option" shows a recommended passive scheme. when a pin is configured with a strap high configuration, the led functions with active low signaling, and the pad will sink the current from the external supply . when a pin is configured with a strap low configuration, the led functions with active high signalin g, and the pad will source the current to the external led. 7.5 default configuration when configured for internal defaults only, the default rom values in table 7-1, "internal eepr om & smbus register memory map" lists the values which will be used to configure the various hub features. figure 7-1: led strapping option hub 100k strap low led pin 100k strap high led pin +v led led downloaded from: http:///
usb2524 ds00001588b-page 40 ? 2013 - 2016 microchip technology inc. 8.0 led interface description the usb2524 supports 3 different (mutually exclusive) led modes. usb mode provides 8 leds, which conform to the usb 2.0 specification functional requirements for green and amber leds. basic host owner led indication mode uses 8 single color leds to provide user indication of upst ream host ownership of the 4 downstream ports. host owner and downstream port speed led indication mode uses 8 dual color leds to provide both a user indication of down- stream port ownership, while simultaneously displaying an indication of the speed of the downstream device which is attached to each of the downstream ports. 8.1 usb mode the led_a[4:1]_n pins are used to pr ovide green led, and led_b[4:1]_n pins are used to provide amber led sup- port as defined in the usb 2.0 specification. the usb specif ication defines the leds as port and error status indicators for the downstream ports. please note that no indication of upstream host ownership is possible in this mode. the pins are utilized as follows: led_a1_n = port 1 green led_b1_n = port 1 amber led_a2_n = port 2 green led_b2_n = port 2 amber led_a3_n = port 3 green led_b3_n = port 3 amber led_a4_n = port 4 green led_b4_n = port 4 amber 8.2 basic host owner led indication all 8 led pins are used in this mode in conjunction with sing le-color leds to indicate wh ich upstream host owns each specific downstream port. the usage and assignment is as follows: led_a1_n = port 1 owned by host a led_b1_n = port 1 owned by host b led_a2_n = port 2 owned by host a led_b2_n = port 2 owned by host b led_a3_n = port 3 owned by host a led_b3_n = port 3 owned by host b led_a4_n = port 4 owned by host a led_b4_n = port 4 owned by host b if a port is disabled, or is unassigned, then neither the a or b led associated with that port will be asserted. since these leds are provided to give an end-user a clear in dication of host ownership of downstream ports, they will function when the hub is in suspend, and will indicate ho st ownership even if the applic able assigned host is discon- nected, powered off, etc. 8.3 host ownership and port speed led indication all 8 led pins are used in this mode in conjunction with 8 du al-color leds (each led pair in a single package) to indi- cate which upstream host owns each specific downstream port, as well as th e speed that the downstream device is operating at. each dual-color led provides two separate colors (commo nly green and red). if each of these separate colors are pulsed on and off at a rapid rate, a user will see a third color (i n this example, orange). by this means, 4 different color states are possible (gre en, red, orange, and off). downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 41 usb2524 figure 8-1 shows a simple example of how this led circuit will be implemented. the circuit will need to be replicated for each of the 8 led pins on the usb2524. in this circuit, when the led pin is driven to a logic low state, the green led will light up. when the led pin is driven to a logic high state the red led will light up. when a 1khz square wave is driven out on the led pin, the gr een and red leds will both alternately li ght up giving the effect of the color orange. when nothing is driven out on the led pin (i.e. the pi n floats to a tri-state condition), neither the green or red led will light up, this is the off state. the assignment is as follows: led_a1_n = port 1 owned by host a led_b1_n = port 1 owned by host b led_a2_n = port 2 owned by host a led_b2_n = port 2 owned by host b led_a3_n = port 3 owned by host a led_b3_n = port 3 owned by host b led_a4_n = port 4 owned by host a led_b4_n = port 4 owned by host b the usage is as follows: led_ax_n driven to logic low = port owned by host a and is operating at usb ls/fs speed led_ax_n driven to logic high = port owned by host a and is operating at usb hs speed led_ax_n pulsed @ 1khz= port owned by host a and has nothing attached. led_ax_n is tri-state= led a is off. table 8-1: dual color led implementation example led pin green led red led 3.3v general purpose diode current limiting resistor connect to other dual color diodes. downloaded from: http:///
usb2524 ds00001588b-page 42 ? 2013 - 2016 microchip technology inc. led_bx_n driven to logic low = port owned by host b and is operating at usb ls/fs speed led_bx_n driven to logic high = port owned by host b and is operating at usb hs speed led_bx_n pulsed @ 1khz= port owned by host b and has nothing attached. led_bx_n is tri-state= led b is off. if a port is disabled, or is unassigned, then neither the a or b led associated with that port will be asserted (i.e. both led's will be off/tri-stated). since these leds are provided to give an end-user a clear in dication of host ownership of downstream ports, they will function when the hub is in suspend, and will indicate ho st ownership even if the applic able assigned host is discon- nected, powered off, etc. when a downstream device is in suspend (or the hub is in suspend), connected devices will continue to reflect the proper led color for the operational speed the device is enumerated at (i.e, hs will remain hs, and fs/ls will remain fs/ls) what will change is the 3rd color which represents an assigned port with no connection, when in suspend the corresponding led will be off (giving the same indication as unassigned, while the hub is suspended). this disables the 1khz toggle while the hub is suspended. downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 43 usb2524 9.0 reset 9.1 reset there are two different resets that the hub experiences. one is a hardware reset (via the reset_n pin) and the second is a usb bus reset. 9.1.1 external hardware reset_n a valid hardware reset is defined as, assertion of reset_n for a minimum of 1us after all power supplies are within operating range. while reset is asserted, the hub (and it s associated external circuitry) consumes less than 500 ? a of current from the upstream usb power source (300 ? a for the hub and 200 ? a for the external circuitry). assertion of reset_n (external pin) causes the following: all downstream ports are disabled, and prtpwr power to downstream devices is removed. the phys are disabled, and the differential pairs will be in a high-impedance state. all transactions immediately te rminate; no states are saved. all internal registers return to the default state (in most cases, 00(h)). the external crystal oscillator is halted. the pll is halted. led indicators are disabled. the hub is operational 500 ? s after reset_n is negated. once operational, the hub immediately reads oem-specific dat a from the external eeprom (if the smbus option is not disabled) or the internal rom. 9.1.1.1 reset_n for strapping option configuration figure 9-1: reset_n timing fo r default/strap option mode t1 t4 t5 t6 t7 t8 valid dont care dont care driven by hub if strap is an output. reset_n vss strap pins vss hardware reset asserted read strap options drive strap outputs to inactive levels attach usb upstream usb reset recovery idle start completion request response t2 t3 downloaded from: http:///
usb2524 ds00001588b-page 44 ? 2013 - 2016 microchip technology inc. note 9-1 when in bus-powered mode, the hub and its asso ciated circuitry must not consume more than 100ma from the upstream u sb power source during t1+t5. 9.1.1.2 reset_n for eeprom configuration table 9-1: reset_n timing for default/strap option mode name description min typ max units t1 reset_n asserted. 1 ? sec t2 strap setup time 16.7 nsec t3 strap hold time. 16.7 1400 nsec t4 hub outputs driven to inactive logic states 1.5 2.0 ? sec t5 usb attach (see note 9-1 ) 100 msec t6 host acknowledges attach and signals usb reset. 100 msec t7 usb idle. undefined msec t8 completion time for requests (with or without data stage). 5 msec figure 9-2: reset_n timing for eeprom mode table 9-2: reset_n timing for eeprom mode name description min typ max units t1 reset_n asserted. 1 ? sec t2 hub recovery/stabilization. 500 ? sec t3 eeprom read / hub config. 2.0 99.5 msec t4 usb attach (see note 9-2 ) 100 msec t1 t2 t4 t5 t6 t7 reset_n vss hardware reset asserted read strap options read eeprom + set options attach usb upstream usb reset recovery idle start completion request response t3 downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 45 usb2524 note 9-2 when in bus-powered mode, the hub and its associated circuitry must not consume more than 100ma from the upstream usb po wer source during t4+t5+t6+t7. 9.1.1.3 reset_n for smbus slave configuration t5 host acknowledges attach and signals usb reset. 100 msec t6 usb idle. undefined msec t7 completion time for requests (with or without data stage). 5 msec figure 9-3: reset_n ti ming for smbus mode table 9-3: reset_n timing for smbus mode name description min typ max units t1 reset_n asserted. 1 ? sec t2 hub recovery/stabilization. 500 ? sec t3 smbus code load (see note 9-3 ) 250 300 msec t4 hub configuration and usb attach. 100 msec t5 host acknowledges attach and signals usb reset. 100 msec t6 usb idle. undefined msec t7 completion time for requests (with or without data stage). 5 msec table 9-2: reset_n timing for eeprom mode (continued) name description min typ max units t1 t2 t4 t5 t6 t7 reset_n vss hardware reset asserted reset negation smbus code load attach usb upstream usb reset recovery idle start completion request response t3 hub phy stabilization downloaded from: http:///
usb2524 ds00001588b-page 46 ? 2013 - 2016 microchip technology inc. note 9-3 for self-powered configurations, t3 max is not app licable and the time to load the configuration is determined by the external smbus host. 9.1.2 usb bus reset in response to the upstream port signaling a reset to the hub, the hub does the following: sets default address to 0. sets configuration to: unconfigured. negates prtpwr[4:1] to all downstream ports. clears all tt buffers. moves device from suspended to active (if suspended). complies with section 11.10 of the usb 2.0 specificati on for behavior after completion of the reset sequence. the host then configures the hub and the hubs downstream port devices in accordance with the usb specification. note: for bus-powered configurations, the hub and its asso ciated circuitry will consume more than 100ma from the upstream usb power sour ce during t2+t3+t4+t5+t6+t7. note: the hub does not propagate the upstream usb reset to downstream devices. downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 47 usb2524 10.0 xnor test please contact your microchip representative for a detailed description of how this test mode is enabled and utilized. downloaded from: http:///
usb2524 ds00001588b-page 48 ? 2013 - 2016 microchip technology inc. 11.0 dc parameters 11.1 maximum ratings operating temperature range.................................................................................................... .................0 o c to +70 o c storage temperature range ...................................................................................................... ............... -55 o to +150 o c lead temperature range (soldering, 10 seconds) ........... ...................................................................... ..............+325 o c positive voltage on any i/o pin, with respect to groun d ............................ ............ ...................... .......... ....................5.5v negative voltage on any i/o pin, with respect to ground ............. .............. ............ ................................. ................... -0.v positive voltage on xtal1, with respect to ground..... ................................................................ ......... .....................4.0v positive voltage on xtal2, with respect to ground..... ................................................................ ......... .....................3.6v negative voltage on xtal1 and xtal2, with respect to ground ................. ....................................... ............ .......... -0.v maximum v dda33 &v dd33 ............................................................................................................................... .........+4.0v * stresses above the specified parameters could cause perm anent damage to the device. this is a stress rating only and functional operation of the device at any other conditi on above those indicated in the operation sections of this specification is not implied. 11.1.1 dc electrical characteristics (t a = 0c - 70c, v dd33 , v dda33 , = +3.3 v tolerance -5% to ? 10%) note: when powering this device from laboratory or system power supplies, it is important that the absolute max- imum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. when this possibility ex ists, it is suggested that a clamp circuit be used. table 11-1: dc electrical characteristics parameter symbol min typ max units comments i, is type input buffer low input level high input level input leakage hysteresis (is only) v ili v ihi i il v hysi 2.0 -10 250 300 0.8 +10 350 vv ua mv ttl levels v in = 0 to v dd33 input buffer with pull-up (ipu) low input level high input level low input leakage high input leakage v ili v ihi i ill i ihl 2.0 0.8 1030 vv uaua ttl levels v in = 0 v in = v dd33 downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 49 usb2524 input buffer with pull- down (ipd ) low input level high input level low input leakage high input leakage v ili v ihi i ill i ihl 2.0 0.8 3010 vv uaua ttl levels v in = 0 v in = v dd33 iclk input buffer low input level high input level input leakage v ilck v ihck i il 1.4 -10 0.5 +10 vv ua ttl levels v in = 0 to v dd33 i/osd12 type buffe r low output level output leakage hysteresis v ol i ol v hysi -10 250 300 0.4 +10 350 v a mv i ol = 12 ma @ v dd33 = 3.3v v in = 0 to v dd33 ( note 11-1 ) io-u ( note 11-2 ) i-r( note 11-3 ) supply current unconfigured 1high-speed hosts 1full-speed hosts i ccinit i ccinit 119 117 mama note: 1 upstream port is in suspend, and the other upstream port is in the process of being enumerated by an external host con- troller (all downstream ports assigned to the upstream port under enumeration). supply current unconfigured 2 high-speed hosts 2 full-speed hosts i ccinit i ccinit 199 174 mama note: both upstream ports are in the process of being enumerated by external host control- lers. supply current configured (2 upstream high-speed hosts) 2 ports @ fs/ls 2 ports @ hs 1 port hs, 1 port fs/ls 3 ports hs 4 ports hs i hcc2 i hch2 i hch1c1 i hch3 i hch4 198 260 240 310 340 mama ma ma ma total from all supplies table 11-1: dc electrical characteristics (continued) parameter symbol min typ max units comments downloaded from: http:///
usb2524 ds00001588b-page 50 ? 2013 - 2016 microchip technology inc. note 11-1 output leakage is measured with th e current pins in high impedance. note 11-2 see usb 2.0 specification for usb dc electrical characteristics. note 11-3 rbias is a 3.3v tolerant analog pin. capacitance t a = 25c; fc = 1mhz; v ddio = 3.3 v power sequencing there are no power supply sequence restrictions for the hub. the order in which power supplies power-up and power- down is implementation dependent. supply current configured (2 upstream full-speed hosts) 1 port 2 ports 3 ports 4 ports i fcc1 i fcc2 i fcc3 i fcc4 182 182 182 182 mama ma ma total from all supplies supply current suspend i csby 272 ? a total from all supplies. supply current reset i crst 73 ? a total from all supplies. limits parameter symbol min typ max unit test condition clock input capacitance c in 2 pf all pins except usb pins (and pins under test tied to ac ground) input capacitance c in 8p f output capacitance c out 12 pf table 11-1: dc electrical characteristics (continued) parameter symbol min typ max units comments downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 51 usb2524 12.0 ac specifications 12.1 oscillator/clock crystal: parallel resonant, fundamental mode, 24 mhz ? 100ppm. external clock: 50% duty cycle ? 10%, 24 mhz ? 100ppm, jitter < 100 ps rms. 12.1.1 smbus interface the microchip switching hub conforms to all voltage, power, and timing characteristics and specifications as set forth in the smbus 1.0 specification for sl ave-only devices (except as noted in section 7.3, "smbus slave interface" ). 12.1.2 i 2 c eeprom frequency is fixed at 58.6 khz ?????? 12.1.3 usb 2.0 the hub conforms to all voltage, power, and timing characteri stics and specifications as set forth in the usb 2.0 spec- ification which is available at the www.usb.org web site. please refer to the usb specification for more information. downloaded from: http:///
usb2524 ds00001588b-page 52 ? 2013 - 2016 microchip technology inc. 13.0 package outline figure 13-1: usb2524 56-pin qfn, 8 x 8 x 0.9mm body, 0.5mm pitch note: for the most current package draings, see the microchip packaging specification at http://.microchip.com/packaging downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 53 usb2524 figure 13-1: usb2524 56-pin qfn, 8 x 8 x 0.9mm body, 0.5mm pitch (continued) note: for the most current package draings, see the microchip packaging specification at http://.microchip.com/packaging downloaded from: http:///
usb2524 ds00001588b-page 54 ? 2013 - 2016 microchip technology inc. appendix a: data sheet revision history table a-1: revision history revision section/figure/entry correction ds00001588b (03-15-16) document is converted to microchip template usb2524 revision a replaces the previous smsc version, revision 1.91 downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 55 usb2524 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microc hip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notifi- cation and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://www.microchip.com/support downloaded from: http:///
usb2524 ds00001588b-page 56 ? 2013 - 2016 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . part no. xxx package device device: usb2524 package: abzj = 56-pin qfn tape and reel option: blank = tray packaging tr = tape and reel (1) example: a) USB2524-ABZJ = 56-pin qfn rohs compliant package tray [x] tape and reel option - note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the dev ice package. check with your microchip sale s office for package availability with the tape and reel option. - downloaded from: http:///
? 2013 - 2016 microchip technology inc. ds00001588b-page 57 usb2524 information contained in this publication regarding device applica tions and the like is provided only for your convenience and may be super- seded by updates. it is your responsibility to ensure that your application meets wi th your specifications. microchip makes no rep- resentations or warranties of an y kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entire ly at the buyers risk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, cl aims, suits, or expenses resulting from such use. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, klee r, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, body com, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit se rial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technol ogy incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2013 - 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978152240394 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner out side the operating specifications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can gu arantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips code protection feature ma y be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrigh ted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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